DM74LS83AN - Fairchild Semiconductor

August 1986

Revised March 2000

DM74LS83A 4-Bit Binary Adder with Fast Carry

DM74LS83A

4-Bit Binary Adder with Fast Carry

General Descript ion

These full adders perform the addition of two 4-bit binary

numbers. The sum (∑) outputs are provided for each bit

and the r esult ant car ry (C4 ) is obt aine d from the f ourth bit.

These adders feature full internal look ahead across all four

bits. This provides the system designer with partial look-

ahead per formance at the eco nomy and reduced packa ge

count of a ripple-carry implementation.

The adder logic, including the carry, is implemented in its

true form meaning that the end-around carry can be

accomplished without the need for logic or level inversion.

Features

■Full-carry look-ahead across the four bits

■Systems achieve partial look-ahead performance with

the economy of ripple carry

■Typical add times

Two 8-bit words 25 ns

Two 16-bit words 45 ns

■Typical power dissipation per 4-bit adder 95 mW

Ordering Code:

Connection Diagram

Order Number Package Number Package Description

DM74LS83AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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DM74LS83A

Truth Table

H = HIGH Level, L = LOW Level

Input conditions at A1, B1, A2, B2, and C0 are used to determine outputs ∑1 and ∑2 and the value of the internal carry C2. The values at C2, A3, B3, A4, and

B4 are t hen use d t o determin e outpu ts ∑3, ∑4, and C4 .

Logic Diagram

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DM74LS83A

Absolute Maximum Ratings(Note 1) Note 1: The “Abso lute Maximum Ratings” ar e those value s beyond which

the safety of the device cannot be guaranteed. The device should not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum ratings.

The “Re comm ended Operat ing Co ndition s” table will de fine the cond itions

for actu al device operation.

Recommended Operating Conditions

Electri cal Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Note 2: All typicals are at VCC = 5V, TA = 25°C.

Note 3: N ot m ore than one output sh ould be sh orted at a tim e, and the duration sh ould not ex c eed one sec ond.

Note 4: ICC1 is measur ed w it h all outp ut s open, all B inputs LOW and all other inputs at 4.5 V, or all inputs at 4.5 V.

Note 5: ICC2 is measur ed w it h all outp ut s OPEN and all input s grounde d.

Supply Voltage 7V

Input Voltage 7V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

VCC Supply Voltage 4.75 5 5.25 V

VIH HIGH Level Input Voltage 2 V

VIL LOW Level Input Voltage 0.8 V

IOH HIGH Level Output Current −0.4 mA

IOL LOW Level Output Current 8 mA

TAFree Air Operatin g Temperature 0 70 °C

Symbol Parameter Conditions Min Typ Max Units

(Note 2)

VIInput Clamp Voltage VCC = Min, II = −18 mA −1.5 V

VOH HIGH Level VCC = Min, IOH = Max 2.7 3.4 V

Output Voltage VIL = Max, VIH = Min

VOL LOW Level VCC = Min, I OL = Max 0.35 0.5

Output Voltage VIL = Max, VIH = Min V

IOL = 4 mA, VCC = Min 0.25 0.4

IIInput Current @ Max VCC = Max A or B 0.2 mA

Input V oltag e VI = 7V C0 0.1

IIH HIGH Level VCC = Max A or B 40 µA

Input Current VI = 2.7V C0 20

IIL LOW Level VCC = Max A or B −0.8 mA

Input Current VI = 0.4V C0 −0.4

IOS Short Circuit Output Current VCC = Max (Note 3) −20 −100 mA

ICC1 Supply Cur rent VCC = Max (Note 4) 19 34 mA

ICC2 Supply Cur rent VCC = Max (Note 5) 22 39 mA

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DM74LS83A

Switching Characteri stics

at VCC = 5V and TA = 25°C From (Inp ut) RL = 2 kΩ

Symbol Parameter To (Output) CL = 15 pF CL = 50 pF Units

Min Max Min Max

tPLH Propagation Delay Time C0 to ∑1 or ∑22428ns

LOW-to-HIGH Level Output

tPHL Propagation Delay Time C0 to ∑1 or ∑22430ns

HIGH-to-LOW Level Output

tPLH Propagation Delay Time C0 to ∑32428ns

LOW-to-HIGH Level Output

tPHL Propagation Delay Time C0 to ∑32430ns

HIGH-to-LOW Level Output

tPLH Propagation Delay Time C0 to ∑42428ns

LOW-to-HIGH Level Output

tPHL Propagation Delay Time C0 to ∑42430ns

HIGH-to-LOW Level Output

tPLH Propagation Delay Time Ai, Bi to ∑i24 28 ns

LOW-to-HIGH Level Output

tPHL Propagation Delay Time Ai, Bi to ∑i24 30 ns

HIGH-to-LOW Level Output

tPLH Propagation Delay Time C0 to C4 17 24 ns

LOW-to-HIGH Level Output

tPHL Propagation Delay Time C0 to C4 17 25 ns

HIGH-to-LOW Level Output

tPLH Propagation Delay Time Ai, Bi to C4 17 24 ns

LOW-to-HIGH Level Output

tPHL Propagation Delay Time Ai, Bi to C4 17 26 ns

HIGH-to-LOW Level Output

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DM74LS83A 4-Bit Binary Adder with Fast Carry

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circu itry descr ibed, no circuit patent licenses ar e implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the labe l ing, can be re a-

sonably expected to result in a significant injury to the

user.

2. A criti cal com ponen t in any compo nent o f a l ife supp ort

device or system whose failure to perform can be rea-

sonabl y e xpec ted to c ause th e fa i lure of the li fe s upp or t

device or system, or to affect its safety or effectiveness.