X5043/X5045 4K 512 x 8 Bit CPU Supervisor with 4K SPI EEPROM FEATURES DESCRIPTION * Selectable time out watchdog timer * Low VCC detection and reset assertion --Five standard reset threshold voltages --Re-program low VCC reset threshold voltage using special programming sequence. --Reset signal valid to VCC = 1V * Long battery life with low power consumption --<50A max standby current, watchdog on --<10A max standby current, watchdog off --<2mA max active current during read * 2.7V to 5.5V and 4.5V to 5.5V power supply versions * 4Kbits of EEPROM-1M write cycle endurance * Save critical data with Block LockTM memory --Protect 1/4, 1/2, all or none of EEPROM array * Built-in inadvertent write protection --Write enable latch --Write protect pin * 3.3MHz clock rate * Minimize programming time --16-byte page write mode --Self-timed write cycle --5ms write cycle time (typical) * SPI modes (0,0 & 1,1) * Available packages --8-lead MSOP, 8-lead SOIC, 8-pin PDIP --14-lead TSSOP These devices combine four popular functions, Poweron Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor executes code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET/ RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device's low VCC detection circuitry protects the user's system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Five industry standard VTRIP thresholds are available, however, Xicor's unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. BLOCK DIAGRAM Watchdog Transition Detector WP SO SCK CS/WDI Protect Logic RESET/RESET Data Register Status Register Command Decode & Control Logic 1Kbits VCC Threshold Reset Logic 2Kbits 1Kbits VCC + VTRIP REV 1.1.2 5/29/01 EEPROM Array SI Watchdog Timer Reset - www.xicor.com Reset & Watchdog Timebase X5043 = RESET X5045 = RESET Power on and Low Voltage Reset Generation Characteristics subject to change without notice. 1 of 20 X5043/X5045 The memory portion of the device is a CMOS Serial EEPROM array with Xicor's block lock protection. The array is internally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Xicor's proprietary Direct WriteTM cell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years. PIN CONFIGURATION 8-Lead SOIC/PDIP/MSOP CS/WDI 1 SO 2 WP 3 VSS 4 X5043/45 8 VCC 7 RESET/RESET 6 SCK 5 SI 14-Lead TSSOP CS 1 14 VCC SO 2 13 RESET/RESET NC 3 12 NC 11 NC NC NC 4 X5043/45 NC 5 10 WP 6 9 SCK VSS 7 8 SI Chip Select (CS) When CS is high, the X5043/45 is deselected and the SO output pin is at high impedance and, unless an internal write operation is underway, the X5043/45 will be in the standby power mode. CS low enables the X5043/45, placing it in the active power mode. It should be noted that after power-up, a high to low transition on CS is required prior to the start of any operation. Write Protect (WP) When WP is low, nonvolatile writes to the X5043/45 are disabled, but the part otherwise functions normally. When WP is held high, all functions, including non volatile writes operate normally. WP going low while CS is still low will interrupt a write to the X5043/45. If the internal write cycle has already been initiated, WP going low will have no affect on a write. Reset (RESET, RESET) X5043/45, RESET/RESET is an active low/HIGH, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 200ms. RESET/RESET also goes active if the Watchdog timer is enabled and CS remains either high or low longer than the Watchdog time out period. A falling edge of CS will reset the watchdog timer. PIN NAMES PIN DESCRIPTIONS Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Symbol Description CS Chip Select Input SO Serial Output SI Serial Input SCK Serial Clock Input WP Write Protect Input VSS Ground VCC Supply Voltage RESET/RESET Reset Output Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin is latched on the rising edge of the clock input, while data on the SO pin changes after the falling edge of the clock input. REV 1.1.2 5/29/01 www.xicor.com Characteristics subject to change without notice. 2 of 20 X5043/X5045 PRINCIPLES OF OPERATION Power On Reset Application of power to the X5043/X5045 activates a Power On Reset Circuit. This circuit pulls the RESET/ RESET pin active. RESET/RESET prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. When VCC exceeds the device VTRIP value for 200ms (nominal) the circuit releases RESET/RESET, allowing the processor to begin executing code. Low Voltage Monitoring During operation, the X5043/X5045 monitors the VCC level and asserts RESET/RESET if supply voltage falls below a preset minimum VTRIP. The RESET/RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET/RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms. Watchdog Timer The Watchdog Timer circuit monitors the microprocessor activity by monitoring the WDI input. The microprocessor must toggle the CS/WDI pin periodically to prevent an active RESET/RESET signal. The CS/WDI pin must be toggled from HIGH to LOW prior to the expiration of the watchdog time out period. The state of two nonvolatile control bits in the Status Register determines the watchdog timer period. The microprocessor can change these watchdog bits. With no microprocessor action, the watchdog timer control bits remain unchanged, even during total power failure. VCC Threshold Reset Procedure The X5043/X5045 is shipped with a standard VCC threshold (VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or if higher precision is needed in the VTRIP value, the X5043/X5045 threshold may be adjusted. The procedure is described below, and uses the application of a high voltage control signal. Setting the VTRIP Voltage This procedure is used to set the VTRIP to a higher voltage value. For example, if the current VTRIP is 4.4V and the new VTRIP is 4.6V, this procedure will directly make the change. If the new setting is to be lower than the current setting, then it is necessary to reset the trip point before setting the new value. To set the new VTRIP voltage, apply the desired VTRIP threshold voltage to the VCC pin and tie the WP pin to the programming voltage VP. Then send a WREN command, followed by a write of Data 00h to address 01h. CS going HIGH on the write operation initiates the VTRIP programming sequence. Bring WP LOW to complete the operation. Note: This operation also writes 00h to array address 01h. Figure 1. Set VTRIP Level Sequence (VCC = desired VTRIP value.) VPE = 15-18V WP CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK 8 Bits SI 06h WREN REV 1.1.2 5/29/01 02h Write www.xicor.com 01h Address 00h Data Characteristics subject to change without notice. 3 of 20 X5043/X5045 Resetting the VTRIP Voltage This procedure is used to set the VTRIP to a "native" voltage level. For example, if the current VTRIP is 4.4V and the new VTRIP must be 4.0V, then the VTRIP must be reset. When VTRIP is reset, the new VTRIP is something less than 1.7V. This procedure must be used to set the voltage to a lower value. To reset the VTRIP voltage, apply at least 3V to the VCC pin and tie the WP pin to the programming voltage VP. Then send a WREN command, followed by a write of Data 00h to address 03h. CS going HIGH on the write operation initiates the VTRIP programming sequence. Bring WP LOW to complete the operation. Note: This operation also writes 00h to array address 03h. Figure 2. Reset VTRIP Level Sequence (VCC > 3V. WP = 15-18V) VPE = 15-18V WP CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK 8 Bits SI 06h 02h WREN Write 00h 03h Address Data Figure 3. Sample VTRIP Reset Circuit 4.7K VP Adjust VTRIP Adj. Run 1 2 3 4 8 X5043 X5045 C RESET 7 6 SCK 5 SI SO CS REV 1.1.2 5/29/01 www.xicor.com Characteristics subject to change without notice. 4 of 20 X5043/X5045 Figure 4. VTRIP Programming Sequence SPI Serial Memory The memory portion of the device is a CMOS Serial EEPROM array with Xicor's block lock protection. The array is internally organized as x8 bits. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. VTRIP Programming Execute Reset VTRIP Sequence The device utilizes Xicor's proprietary Direct WriteTM cell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years. Set VCC = VCC Applied = Desired VTRIP New VCC Applied = Old VCC Applied - Error Execute Set VTRIP Sequence Apply 5V to VCC New VCC Applied = Old VCC Applied - Error Execute Reset VTRIP Sequence Decrement VCC (VCC = VCC-10mV) NO RESET pin goes active? YES Error -Emax Measured VTRIP -Desired VTRIP Error Emax -Emax < Error < Emax DONE The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. The device contains an 8-bit instruction register that controls the operation of the device. The instruction code is written to the device via the SI input. There are two write operations that requires only the instruction byte. There are two read operations that use the instruction byte to initiate the output of data. The remainder of the operations require an instruction byte, an 8-bit address, then data bytes. All instruction, address and data bits are clocked by the SCK input. All instructions (Table 1), addresses and data are transferred MSB first. Clock and Data Timing Data input on the SI line is latched on the first rising edge of SCK after CS goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off. CS must be LOW during the entire operation. Emax = Maximum Desired Error Table 1. Instruction Set Instruction Name Instruction Format* WREN 0000 0110 Note: Operation Set the Write Enable Latch (Enable Write Operations) WRDI 0000 0100 Reset the Write Enable Latch (Disable Write Operations) RSDR 0000 0101 Read Status Register WRSR 0000 0001 Write Status Register (Watchdog and Block Lock) READ 0000 A8011 Read Data from Memory Array Beginning at Selected Address WRITE 0000 A8010 Write Data to Memory Array Beginning at Selected Address (1 to 16 bytes) *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first. REV 1.1.2 5/29/01 www.xicor.com Characteristics subject to change without notice. 5 of 20 X5043/X5045 Write Enable Latch The device contains a Write Enable Latch. This latch must be SET before a Write Operation is initiated. The WREN instruction will set the latch and the WRDI instruction will reset the latch (Figure 3). This latch is automatically reset upon a power-up condition and after the completion of a valid byte, page, or status register write cycle. The latch is also reset if WP is brought LOW. When issuing a WREN, WRDI or RDSR commands, it is not necessary to send a byte address or data. Figure 5. Write Enable/Disable Latch Sequence CS 0 1 2 3 4 5 6 7 Status Reg Bits Array Addresses Protected BL1 BL0 X5043/X5045 0 0 None 0 1 $180-$1FF 1 0 $100-$1FF 1 1 $000-$1FF The Watchdog Timer bits, WD0 and WD1, select the Watchdog Time-out Period. These nonvolatile bits are programmed with the WRSR instruction. SCK Status Register Bits SI SO The block lock bits, BL0 and BL1, set the level of block lock protection. These nonvolatile bits are programmed using the WRSR instruction and allow the user to protect one quarter, one half, all or none of the EEPROM array. Any portion of the array that is block lock protected can be read but not written. It will remain protected until the BL bits are altered to disable block lock protection of that portion of memory. WD0 0 0 1.4 seconds 0 1 600 milliseconds 1 0 200 milliseconds 1 1 disabled (factory default) High Impedance Status Register The Status Register contains four nonvolatile control bits and two volatile status bits. The control bits set the operation of the watchdog timer and the memory block lock protection. The Status Register is formatted as shown in "Status Register". Status Register: (Default = 30H) 7 6 0 0 5 4 WD1 WD0 3 2 1 0 BL1 BL0 WEL WIP The Write-In-Progress (WIP) bit is a volatile, read only bit and indicates whether the device is busy with an internal nonvolatile write operation. The WIP bit is read using the RDSR instruction. When set to a "1", a nonvolatile write operation is in progress. When set to a "0", no write is in progress. The Write Enable Latch (WEL) bit indicates the status of the "write enable" latch. When WEL = 1, the latch is set and when WEL = 0 the latch is reset. The WEL bit is a volatile, read only bit. The WREN instruction sets the WEL bit and the WRDS instruction resets the WEL bit. REV 1.1.2 5/29/01 Watchdog Time Out (Typical) WD1 Read Status Register To read the Status Register, pull CS low to select the device, then send the 8-bit RDSR instruction. Then the contents of the Status Register are shifted out on the SO line, clocked by CLK. Refer to the Read Status Register Sequence (Figure 6). The Status Register may be read at any time, even during a Write Cycle. Write Status Register Prior to any attempt to write data into the status register, the "Write Enable" Latch (WEL) must be set by issuing the WREN instruction (Figure 5). First pull CS LOW, then clock the WREN instruction into the device and pull CS HIGH. Then bring CS LOW again and enter the WRSR instruction followed by 8 bits of data. These 8 bits of data correspond to the contents of the status register. The operation ends with CS going HIGH. If CS does not go HIGH between WREN and WRSR, the WRSR instruction is ignored. www.xicor.com Characteristics subject to change without notice. 6 of 20 X5043/X5045 Table 2. Device Protect Matrix Memory Block Status Register WREN CMD (WEL) Device Pin (WP) Protected Area Unprotected Area (BL0, BL1, WD0, WD1) 0 x Protected Protected Protected x 0 Protected Protected Protected 1 1 Protected Writable Writable Figure 6. Read Status Register Sequence CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction SI SO Data Out High Impedance 7 6 5 4 3 2 1 0 MSB Figure 7. Write Status Register Sequence CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Data Byte Instruction 7 SI SO 5 4 3 2 1 0 High Impedance Read Memory Array When reading from the EEPROM memory array, CS is first pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 8-bit address. Bit 3 of the READ instruction selects the upper or lower half of the device. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next REV 1.1.2 5/29/01 6 address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to address $000 allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS high. Refer to the Read EEPROM Array Sequence (Figure 8). www.xicor.com Characteristics subject to change without notice. 7 of 20 X5043/X5045 Figure 8. Read EEPROM Array Sequence CS 0 1 2 3 4 5 6 7 8 9 7 6 10 12 13 14 15 16 17 18 19 20 21 22 SCK Instruction 8 Bit Address 8 SI 5 3 2 1 0 9th Bit of Address Data Out High Impedance 7 SO 6 5 4 3 2 1 0 MSB Write Memory Array Prior to any attempt to write data into the memory array, the "Write Enable" Latch (WEL) must be set by issuing the WREN instruction (Figure 5). First pull CS LOW, then clock the WREN instruction into the device and pull CS HIGH. Then bring CS LOW again and enter the WRITE instruction followed by the 8-bit address and then the data to be written. Bit 3 of the WRITE instruction contains address bit A8, which selects the upper or lower half of the array. If CS does not go HIGH between WREN and WRITE, the WRITE instruction is ignored. The WRITE operation requires at least 16 clocks. CS must go low and remain low for the duration of the operation. The host may continue to write up to 16 bytes of data. The only restriction is that the 16 bytes REV 1.1.2 5/29/01 must reside within the same page. A page address begins with address [x xxxx 0000] and ends with [x xxxx 1111]. If the byte address reaches the last byte on the page and the clock continues, the counter will roll back to the first address of the page and overwrite any data that has been previously written. For the write operation (byte or page write) to be completed, CS must be brought HIGH after bit 0 of the last complete data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed (Figure 9). While the write is in progress following a status register or memory array write sequence, the Status Register may be read to check the WIP bit. WIP is HIGH while the nonvolatile write is in progress. www.xicor.com Characteristics subject to change without notice. 8 of 20 X5043/X5045 Figure 9. Write Memory Sequence CS 0 1 2 3 4 5 6 7 8 9 10 7 6 8 Bit Address 5 3 2 12 13 14 15 16 17 18 19 20 21 22 23 SCK Instruction 8 SI 1 0 7 6 5 Data Byte 1 4 3 2 1 0 9th Bit of Address CS 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCK SI 7 6 Data Byte 2 5 4 3 2 1 0 7 6 Data Byte 3 5 4 3 2 OPERATIONAL NOTES - The device is in the low power standby state. - A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. - The Write Enable Latch is reset. 0 6 5 Data Byte N 4 3 2 1 0 Data Protection The following circuitry has been included to prevent inadvertent writes: The device powers-up in the following state: - SO pin is high impedance. 1 - A WREN instruction must be issued to set the Write Enable Latch. - CS must come HIGH at the proper clock count in order to start a nonvolatile write cycle. - The Flag Bit is reset. - Block Protect bits provide additional level of write protection for the memory array. - Reset Signal is active for tPURST. - The WP pin LOW blocks nonvolatile write operations. REV 1.1.2 5/29/01 www.xicor.com Characteristics subject to change without notice. 9 of 20 X5043/X5045 ABSOLUTE MAXIMUM RATINGS COMMENT Temperature under bias ....................-65C to +135C Storage temperature ........................-65C to +150C Voltage on any pin with respect to VSS ...................................... -1.0V to +7V D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds).........300C Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Option Supply Voltage Limits Commercial 0C 70C -2.7, -2.7A 2.7V to 5.5V Industrial -40C +85C Blank, -4.5A 4.5V to 5.5V D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol Parameter ICC1 Typ.(2) Min. Max. Unit Test Conditions/Comments VCC Write Current (Active) 3 mA SCK = 3.3MHz(3); SO, RESET, RESET = Open ICC2 VCC Read Current (Active) 2 mA SCK = 3.3MHz(3); SI = VSS, RESET, RESET = Open ISB1 VCC Standby Current WDT = OFF 10 A CS = VCC, SCK, SI = VSS, VCC = 5.5V ISB2 VCC Standby Current WDT = ON 50 A CS = VCC, SCK, SI = VSS, VCC = 5.5V ILI Input Leakage Current 0.1 10 A SCK, SI, WP = VSS to VCC ILO Output Leakage Current 0.1 10 A SO, RESET, RESET = VSS to VCC (1) Input LOW Voltage -0.5 VCC x 0.3 V SCK, SI, WP, CS (1) VIH Input HIGH Voltage VCC x 0.7 VCC + 0.5 V SCK, SI, WP, CS VOL Output LOW Voltage (SO) 0.4 V IOL = 2mA @ VCC = 2.7V IOL = 0.5mA @ VCC = 1.8V VOH1 Output HIGH Voltage (SO) VCC - 0.8 V VCC > 3.3V, IOH = -1.0mA VOH2 Output HIGH Voltage (SO) VCC - 0.4 V 2V < VCC 3.3V, IOH = -0.4mA VOH3 Output HIGH Voltage (SO) VCC - 0.2 V VCC 2V, IOH = -0.25mA VOLRS Output LOW Voltage (RESET, RESET) V IOL = 1mA VIL 0.4 CAPACITANCE TA = +25C, f = 1MHz, VCC = 5V Symbol (2) COUT (2) CIN Test Max. Unit Conditions Output Capacitance (SO, RESET, RESET) 8 pF VOUT = 0V Input Capacitance (SCK, SI, CS, WP) 6 pF VIN = 0V Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. (3) SCK frequency measured from VCC x 0.1/VCC x 0.9 REV 1.1.2 5/29/01 www.xicor.com Characteristics subject to change without notice. 10 of 20 X5043/X5045 Equivalent A.C. Load Circuit at 5V VCC 5V A.C. Test Conditions 5V 4.6K 1.64K Output Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level VCC x0.5 RESET/RESET 1.64K 30pF 30pF A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Data Input Timing 2.7V-5.5V Symbol Parameter fSCK Clock Frequency Min. Max. Unit 0 3.3 MHz tCYC Cycle Time 300 ns tLEAD CS Lead Time 150 ns tLAG CS Lag Time 150 ns tWH Clock HIGH Time 130 ns tWL Clock LOW Time 130 ns tSU Data Setup Time 30 ns tH Data Hold Time 30 ns (3) Input Rise Time (3) tFI Input Fall Time tCS CS Deselect Time tWC(4) Write Cycle Time tRI 2 s 2 s 100 ns 10 ms Max. Unit Data Output Timing 2.7-5.5V Symbol Parameter Min. fSCK Clock Frequency 3.3 MHz tDIS Output Disable Time 150 ns Output Valid from Clock Low 120 ns tV tHO 0 Output Hold Time 0 ns (3) Output Rise Time 50 ns (3) Output Fall Time 50 ns tRO tFO Notes: (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. REV 1.1.2 5/29/01 www.xicor.com Characteristics subject to change without notice. 11 of 20 X5043/X5045 Serial Output Timing CS tCYC tWH tLAG SCK tV tHO MSB Out SO tWL tDIS MSB-1 Out LSB Out ADDR LSB IN SI Serial Input Timing tCS CS tLEAD tLAG SCK tSU tH tRI MSB In SI tFI LSB In High Impedance SO SYMBOL TABLE WAVEFORM REV 1.1.2 5/29/01 INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don't Care: Changes Allowed N/A Changing: State Not Known Center Line is High Impedance www.xicor.com Characteristics subject to change without notice. 12 of 20 X5043/X5045 Power-Up and Power-Down Timing VCC VTRIP VTRIP tPURST 0 Volts tPURST tF tR tRPD RESET (X5043) RESET (X5045) RESET Output Timing Symbol VTRIP tPURST (5) tRPD (5) Min. Typ. Max. Unit Reset Trip Point Voltage, (-4.5A) Reset Trip Point Voltage, (Blank) Reset Trip Point Voltage, (-2.7A) Reset Trip Point Voltage, (-2.7) 4.5 4.25 2.85 2.55 4.62 4.38 2.92 2.62 4.75 4.5 3.0 2.7 V Power-up Reset Time Out 100 200 400 ms 500 ns VCC Detect to Reset/Output tF VCC Fall Time 10 s tR(5) VCC Rise Time 0.1 ns 1 V VRVALID Note: Parameter Reset Valid VCC (5) This parameter is periodically sampled and not 100% tested. CS/WDI vs. RESET/RESET Timing CS/WDI tCST RESET tWDO tRST tWDO tRST RESET RESET/RESET Output Timing Symbol tWDO Parameter Watchdog Time Out Period, WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 Min. Typ. Max. Unit 100 450 1 200 600 1.4 300 800 2 ms ms sec 200 400 ms tCST CS Pulse Width to Reset the Watchdog 400 tRST Reset Time Out 100 REV 1.1.2 5/29/01 www.xicor.com ns Characteristics subject to change without notice. 13 of 20 X5043/X5045 VTRIP Programming Timing Diagram VCC (VTRIP) VTRIP tTSU tTHD VP WP tVPS tVPH tPCS tVPO CS tRP SCK SI 06h 02h 01h or 03h VTRIP Programming Parameters Parameter Description Min Max Unit tVPS VTRIP Program Enable Voltage Setup time 1 s tVPH VTRIP Program Enable Voltage Hold time 1 s tPCS VTRIP Programming CS inactive time 1 s tTSU VTRIP Setup time 1 s tTHD VTRIP Hold (stable) time 10 ms tWC VTRIP Write Cycle Time tVPO VTRIP Program Enable Voltage Off time (Between successive adjustments) 10 0 ms s tRP VTRIP Program Recovery Period (Between successive adjustments) 10 VP Programming Voltage 15 18 V VTRIP Programmed Voltage Range 1.7 5.0 V Vta1 Initial VTRIP Program Voltage accuracy (VCC applied-VTRIP) (Programmed at 25C.) -0.1 +0.4 V Vta2 Subsequent VTRIP Program Voltage accuracy [(VCC applied-Vta1)-VTRIP. Programmed at 25C.) -25 +25 mV Vtr VTRIP Program Voltage repeatability (Successive program operations. Programmed at 25C.) -25 +25 mV Vtv VTRIP Program variation after programming (0-75C). (Programmed at 25C.) -25 +25 mV VTRAN ms VTRIP programming parameters are periodically sampled and are not 100% tested. REV 1.1.2 5/29/01 www.xicor.com Characteristics subject to change without notice. 14 of 20 X5043/X5045 PACKAGING INFORMATION 8-Lead Miniature Small Outline Gull Wing Package Type M 0.118 0.002 (3.00 0.05) 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.0256 (0.65) Typ. R 0.014 (0.36) 0.118 0.002 (3.00 0.05) 0.030 (0.76) 0.0216 (0.55) 0.036 (0.91) 0.032 (0.81) 0.040 0.002 (1.02 0.05) 7 Typ. 0.008 (0.20) 0.004 (0.10) 0.0256" Typical 0.007 (0.18) 0.005 (0.13) 0.025" Typical 0.150 (3.81) Ref. 0.193 (4.90) Ref. 0.220" FOOTPRINT 0.020" Typical 8 Places NOTE: 1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS) REV 1.1.2 5/29/01 www.xicor.com Characteristics subject to change without notice. 15 of 20 X5043/X5045 PACKAGING INFORMATION 8-Lead Plastic Dual In-Line Package Type P 0.430 (10.92) 0.360 (9.14) 0.260 (6.60) 0.240 (6.10) Pin 1 Index Pin 1 0.300 (7.62) Ref. Half Shoulder Width On All End Pins Optional 0.145 (3.68) 0.128 (3.25) Seating Plane 0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) .073 (1.84) Max. 0.060 (1.52) 0.020 (0.51) 0.020 (0.51) 0.016 (0.41) 0.325 (8.25) 0.300 (7.62) 0 15 Typ. 0.010 (0.25) NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH REV 1.1.2 5/29/01 www.xicor.com Characteristics subject to change without notice. 16 of 20 X5043/X5045 PACKAGING INFORMATION 8-Lead Plastic Small Outline Gull Wing Package Type S 0.150 (3.80) 0.228 (5.80) 0.158 (4.00) 0.244 (6.20) Pin 1 Index Pin 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7 0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25) 0.050 (1.27) 0.010 (0.25) X 45 0.020 (0.50) 0.050"Typical 0.050" Typical 0 - 8 0.0075 (0.19) 0.010 (0.25) 0.250" 0.016 (0.410) 0.037 (0.937) 0.030" Typical 8 Places FOOTPRINT NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.1.2 5/29/01 www.xicor.com Characteristics subject to change without notice. 17 of 20 X5043/X5045 PACKAGING INFORMATION 14-Lead Plastic, TSSOP, Package Type V .025 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .193 (4.9) .200 (5.1) .047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15) .010 (.25) Gage Plane 0 - 8 Seating Plane .019 (.50) .029 (.75) Detail A (20X) .031 (.80) .041 (1.05) See Detail "A" NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.1.2 5/29/01 www.xicor.com Characteristics subject to change without notice. 18 of 20 X5043/X5045 Ordering Information VCC Range VTRIP Range Package 4.5-5.5V 4.5-4.75 8-Pin PDIP -40C-85C X5043PI-4.5A X5045PI-4.5A 8L SOIC -40C-85C X5043S8I-4.5A X5045S8I-4.5A 8L MSOP -40C-85C X5043M8I-4.5A X5045M8I-4.5A 14L TSSOP -40C-85C X5043V14I-4.5A X5045V14I-4.5A 8-Pin PDIP -40C-85C X5043PI X5045PI 8L SOIC 0C-70C X5043S8 X5045S8 -40C-85C X5043S8I X5045S8I 8L MSOP -40C-85C X5043M8I X5045M8I 14L TSSOP -40C-85C X5043V14I X5045V14I 8L PDIP -40C-85C X5043PI-2.7A X5045PI-2.7A 8L SOIC -40C-85C X5043S8I-2.7A X5045S8I-2.7A 8L MSOP -40C-85C X5043M8I-2.7A X5045M8I-2.7A 14L TSSOP -40C-85C X5043V14I-2.7A X5045V14I-2.7A 8-Pin PDIP -40C-85C X5043PI-2.7 X5045PI-2.7 8L SOIC 0C-70C X5043S8-2.7 X5045S8-2.7 -40C-85C X5043S8I-2.7 X5045S8I-2.7 4.25-4.5 2.7-5.5V 2.85-3.0 2.55-2.7 REV 1.1.2 5/29/01 Operating Temperature Range Part Number RESET (Active LOW) Part Number RESET (Active HIGH) 8L MSOP -40C-85C X5043M8I-2.7 X5045M8I-2.7 14L TSSOP -40C-85C X5043V14I-2.7 X5045V14I-2.7 www.xicor.com Characteristics subject to change without notice. 19 of 20 X5043/X5045 Part Mark Information PDIP/SOIC X5043/45 X X MSOP YWW XXX Blank = 8-Lead SOIC P= 8 Pin Plastic DIP Blank = No suffix, 0C to +70C I = No Suffix; -40C to +85C A = -4,5A; 0C to +70C, IA = -4.5A; -40C to +85C F = -2.7; 0C to +70C G = -2.7; -40C to +85C FA = -2.7A; 0C to +70C GA = -2.7A; -40C to +85C AEP/AEY = No Suffix; -40C to +85C AEN/AEW = -4.5A; -40C to +85C AET/AFC = -2.7; -40C to +85C AER/AFA = -2.7A; -40C to +85C X5043/X5045 TSSOP X5043/45 W X V = 14 Lead TSSOP Blank = 5V 10%, 0C to +70C, VTRIP = 4.25-4.5 AL = 5V10%, 0C to +70C, VTRIP = 4.5-4.75 I = 5V 10%, -40C to +85C, VTRIP = 4.25-4.5 AM = 5V 10%, -40C to +85C, VTRIP = 4.5-4.75 F = 2.7V to 5.5V, 0C to +70C, VTRIP = 2.55-2.7 AN = 2.7V to 5.5V, 0C to +70C, VTRIP = 2.85-3.0 G = 2.7V to 5.5V, -40C to +85C, VTRIP = 2.55-2.7 AP = 2.7V to 5.5V, -40C to +85C, VTRIP = 2.85-3.0 LIMITED WARRANTY (c)Xicor, Inc. 2001 Patents Pending Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. COPYRIGHTS AND TRADEMARKS Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM, E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are used for identification purposes only, and are trademarks or registered trademarks of their respective holders. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. REV 1.1.2 5/29/01 www.xicor.com Characteristics subject to change without notice. 20 of 20