REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
A Add device type 02. Add device class V criteria. Add case outline X and table
III, delta limits. Update the boilerplate to include radiation hardness assured
requirements and to reflect the changes in accordance with MIL-PRF-38535
requirements. Editorial changes throughout - jak.
04-12-14
Thomas M. Hess
B
Add appendix A, microcircuit die. Update the boilerplate to MIL-PRF-38535
requirements and to include radiation hardness assurance paragraphs. - LTG
08-06-11
Thomas M. Hess
REV
SHEET
REV
B
B
B
B
B
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B
B
SHEET
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16
17
18
19
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21
22
23
24
25
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28
REV STATUS
REV
B
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OF SHEETS
SHEET
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PMIC N/A
PREPARED BY
Monica L. Poelking
STANDARD
MICROCIRCUIT
DRAWING
CHECKED BY
Monica L. Poelking
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
APPROVED BY
Michael A. Frye
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
DRAWING APPROVAL DATE
90-03-13
MICROCIRCUITS, DIGITAL, ADVANCED
CMOS, UP/DOWN BINARY COUNTER WITH
PRESET AND RIPPLE CLOCK, MONOLITHIC
SILICON
AMSC N/A
REVISION LEVEL
B
SIZE
A
CAGE CODE
67268
5962-89749
SHEET
1 OF
21
DSCC FORM 2233
APR 97 5962-E406-08
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89749
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
B
SHEET 2
DSCC FORM 2234
APR 97
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)
and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or
Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.
1.2 PIN. The PIN is as shown in the following examples.
For device classes M and Q:
5962 - 89749 01 E A
Federal RHA Device Case Lead
stock class designator type outline finish
designator (see 1.2.1) (see 1.2.2) (see 1.2.4) (see 1.2.5)
\ /
\/
Drawing number
For device class V:
5962 F 89749 01 V E A
Federal RHA Device Device Case Lead
stock class designator type class outline finish
designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5)
\ / (see 1.2.3)
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type Generic number Circuit function
01 54AC191 Up/down counter with preset and ripple clock
02 54AC191 Up/down counter with preset and ripple clock
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as listed
below. Since the device class designator has been added after the original issuance of this drawing, device classes M and Q
designators will not be included in the PIN and will not be marked on the device.
Device class Device requirements documentation
M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN
class level B microcircuits in accordance with MIL-PRF-38535, appendix A
Q or V Certification and qualification to MIL-PRF-38535
STANDARD
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A
5962-89749
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
B
SHEET 3
DSCC FORM 2234
APR 97
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter Descriptive designator Terminals Package style
E GDIP1-T16 or CDIP2-T16 16 Dual-in-line
F GDFP2-F16 or CDFP3-F16 16 Flat pack
X CDFP4-F16 16 Flat pack
2 CQCC1-N20 20 Square leadless chip carrier
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
1.3 Absolute maximum ratings. 1/ 2/ 3/
Supply voltage range (VCC) .................................................................................. -0.5 V dc to +6.0 V dc
DC input voltage range (VIN) ................................................................................ -0.5 V dc to VCC + 0.5 V dc
DC output voltage range (VOUT) ........................................................................... -0.5 V dc to VCC + 0.5 V dc
Clamp diode current (IIK, IOK)................................................................................ ±20 mA
DC output current (IOUT) (per pin)......................................................................... ±50 mA
DC VCC or GND current (ICC, IGND) (per pin) ......................................................... ±100 mA
Maximum power dissipation (PD) ......................................................................... 500 mW
Storage temperature range (TSTG) ....................................................................... -65°C to +150°C
Lead temperature (soldering, 10 seconds):
Case outline X.................................................................................................... +260°C
All other case outlines except case X ................................................................ +300°C
Thermal resistance, junction-to-case (θJC) ........................................................... See MIL-STD-1835
Junction temperature (TJ) .................................................................................... +175°C 4/
1.4 Recommended operating conditions. 2/ 3/ 5/
Supply voltage range (VCC) .................................................................................. +3.0 V dc to +5.5 V dc
Input voltage range (VIN) ...................................................................................... +0.0 V dc to VCC
Output voltage range (VOUT)................................................................................. +0.0 V dc to VCC
Case operating temperature range (TC) ............................................................... -55°C to +125°C
Input rise or fall time rate at (Δt/ΔV) (VCC = 3.6 V to 5.5 V) .................................. 0 to 8 ns/V
1.5 Radiation features.
Device type 02:
Maximum total dose available (dose rate = 50 – 300 rads (Si)/s) ...................... 300 krads (Si)
Single Event Latch-up (SEL) ............................................................................. ≥ 93 MeV-cm2/mg 6/
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ Unless otherwise noted, all voltages are referenced to GND.
3/ The limits for the parameters specified herein shall apply over the full specified VCC range and case temperature range
of -55°C to +125°C.
4/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in
accordance with method 5004 of MIL-STD-883.
5/ Operation from 2.0 V dc to 3.0 V dc is provided for compatibility with data retention and battery backup systems. Data
retention implies no input transitions and no stored data loss with the following conditions: VIH ≥ 70% VCC, VIL ≤ 30% VCC,
VOH ≥ 70% VCC at -20 μA, VOL ≤ 30% VCC at 20 μA.
6/ Limits are guaranteed by design or process, but not production tested unless specified by the customer through the
purchase order or contract.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89749
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
B
SHEET 4
DSCC FORM 2234
APR 97
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of
this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 - Test Method Standard Microcircuits.
MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract.
ELECTRONIC INDUSTRIES ALLIANCE (EIA)
JEDEC Standard No. 20 - Standard for Description of 54/74ACXXXX and 54/74ACTXXXX Advanced High-Speed
CMOS Devices
(Copies of these documents are available online at http://www.jedec.org or from the Electronic Industries Alliance, 2500 Wilson
Boulevard, Arlington, VA 22201-3834.)
AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM)
ASTM F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion
Irradiation of semiconductor Devices.
(Copies of these documents are available online at http://www.astm.org or from ASTM International, 100 Barr Harbor Drive, P.O.
Box C700, West Conshohocken, PA, 19428-2959).
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of
this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific
exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein.
3.1.1 Microcircuit die. For the requirements of microcircuit die, see appendix A to this document.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in
MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89749
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
B
SHEET 5
DSCC FORM 2234
APR 97
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Truth table. The truth table shall be as specified on figure 2.
3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3.
3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4.
3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document
revision level control and shall be made available to the preparing and acquiring activity upon request.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical
performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full case
operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table IA.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in
accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103
(see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and
herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product
(see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the
option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit
group number 40 (see MIL-PRF-38535, appendix A).
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89749
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
B
SHEET 6
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics.
Limits 4/ Test and
MIL-STD-883
test method 1/
Symbol Test conditions 2/ 3/
-55°C ≤ TC ≤ +125°C
+3.0 V ≤ VCC ≤ +5.5 V
Unless otherwise specified
Device
type
and
device
class
VCC Group A
subgroups
Min Max
Unit
Positive input
clamp voltage
3022
VIC+ For input under test, IIN = 1.0 mA All
and
V
0.0 V 1 0.4 1.5 V
Negative input
clamp voltage
3022
VIC- For input under test, IIN = -1.0 mA All
and
V
Open 1 -0.4 -1.5 V
3.0 V 2.9
4.5 V 4.4
VIN = VIH minimum or VIL maximum
IOH = -50 μA
All
and
All
5.5 V
1, 2, 3
5.4
VIN = VIH minimum or VIL maximum
IOH = -12 mA
All
and
All
3.0 V 1, 2, 3 2.4
4.5 V 1, 2, 3 3.70 VIN = VIH minimum or VIL maximum
IOH = -24 mA
All
and
All 5.5 V 1, 2, 3 4.70
High level output
voltage
3006
VOH
5/
VIN = VIH minimum or VIL maximum
IOH = -50 mA
All
and
All
5.5 V 1, 2, 3 3.85
V
3.0 V 0.1
4.5 V 0.1
VIN = VIH minimum or VIL maximum
IOL = 50 μA
All
and
All
5.5 V
1, 2, 3
0.1
VIN = VIH minimum or VIL maximum
IOL = 12 mA
All
and
All
3.0 V 1, 2, 3 0.50
4.5 V 1, 2, 3 0.50 VIN = VIH minimum or VIL maximum
IOL = 24 mA
All
and
All 5.5 V 1, 2, 3 0.50
Low level output
voltage
3007
VOL
5/
VIN = VIH minimum or VIL maximum
IOL = 50 mA
All
and
All
5.5 V 1, 2, 3 1.65
V
3.0 V 2.1
4.5 V 3.15
High level input
voltage
VIH
6/
All
and
All
5.5 V
1, 2, 3
3.85
V
3.0 V 0.9
4.5 V 1.35
Low level input
voltage
VIL
6/
All
and
All
5.5 V
1, 2, 3
1.65
V
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89749
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
B
SHEET 7
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics – Continued.
Limits 4/ Test and
MIL-STD-883
test method 1/
Symbol Test conditions 2/ 3/
-55°C ≤ TC ≤ +125°C
+3.0 V ≤ VCC ≤ +5.5 V
Unless otherwise specified
Device
type
and
device
class
VCC Group A
subgroups
Min Max
Unit
Input leakage
current low
3009
IIL V
IN = 0.0 V All
and
All
5.5 V 1, 2, 3 -1.0 μA
Input leakage
current high
3010
IIH V
IN = 5.5 V All
and
All
5.5 V 1, 2, 3 1.0 μA
01
and
All
5.5 V 1, 2, 3 160 μA
1 4.0
VIN = VCC or GND
02
and
All 2, 3 80
Quiescent supply
current, output high
3005
ICCH
M, D, P, L, R, F
7/
02
and
Q, V
5.5 V
1 50
μA
01
and
All
5.5 V 1, 2, 3 160 μA
1 4.0
VIN = VCC or GND
02
and
All 2, 3 80
Quiescent supply
current, output low
3005
ICCL
M, D, P, L, R, F
7/
02
and
Q, V
5.5 V
1 50
μA
Input capacitance
3012
CIN See 4.4.1c All
and
All
GND 4 8.0 pF
Power dissipation
capacitance
CPD
8/
See 4.4.1c All
and
All
5.0 V 4 85 pF
3.0 V 7, 8 L H Functional tests
3014
9/
VIN = VIH or VIL
Verify output VOUT
See 4.4.1b
All
and
All 5.5 V 7, 8 L H
9 1.0 13.0
All
and
All
3.0 V
10, 11 1.0 16.0
9 1.5 10.0
tPHL1
10/
All
and
All
4.5 V
10, 11 1.5 12.0
ns
9 1.0 13.0
All
and
All
3.0 V
10, 11 1.0 16.5
9 1.5 10.0
Propagation delay
time, CP to Qn
3003
tPLH1
10/
CL = 50 pF minimum
RL = 500Ω
See figure 4
All
and
All
4.5 V
10, 11 1.5 12.0
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89749
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
B
SHEET 8
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics – Continued.
Limits 4/ Test and
MIL-STD-883
test method 1/
Symbol Test conditions 2/ 3/
-55°C ≤ TC ≤ +125°C
+3.0 V ≤ VCC ≤ +5.5 V
Unless otherwise specified
Device
type
and
device
class
VCC Group A
subgroups
Min Max
Unit
9 1.0 15.5
All
and
All
3.0 V
10, 11 1.0 19.0
9 1.5 11.5
tPHL2
10/
All
and
All
4.5 V
10, 11 1.5 14.5
ns
9 1.0 15.0
All
and
All
3.0 V
10, 11 1.0 19.5
9 1.5 11.0
Propagation delay
time, CP to TC
3003
tPLH2
10/
CL = 50 pF minimum
RL = 500Ω
See figure 4
All
and
All
4.5 V
10, 11 1.5 14.0
ns
9 1.0 10.0
All
and
All
3.0 V
10, 11 1.0 12.5
9 1.5 8.0
tPHL3
10/
All
and
All
4.5 V
10, 11 1.5 9.5
ns
9 1.0 11.5
All
and
All
3.0 V
10, 11 1.0 14.0
9 1.5 9.0
Propagation delay
time, CP to RC
3003
tPLH3
10/
CL = 50 pF minimum
RL = 500Ω
See figure 4
All
and
All
4.5 V
10, 11 1.5 10.5
ns
9 1.0 10.5
All
and
All
3.0 V
10, 11 1.0 12.5
9 1.5 7.5
tPHL4
10/
All
and
All
4.5 V
10, 11 1.5 9.5
ns
9 1.0 11.5
All
and
All
3.0 V
10, 11 1.0 14.0
9 1.5 8.0
Propagation delay
time, CE to RC
3003
tPLH4
10/
CL = 50 pF minimum
RL = 500Ω
See figure 4
All
and
All
4.5 V
10, 11 1.5 10.0
ns
9 1.0 12.5
All
and
All
3.0 V
10, 11 1.0 15.0
9 1.5 9.0
tPHL5
10/
All
and
All
4.5 V
10, 11 1.5 11.0
ns
9 1.0 12.5
All
and
All
3.0 V
10, 11 1.0 14.5
9 1.5 9.0
Propagation delay
time, U/D to RC
3003
tPLH5
10/
CL = 50 pF minimum
RL = 500Ω
See figure 4
All
and
All
4.5 V
10, 11 1.5 11.0
ns
See footnotes at end of table.
STANDARD
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SIZE
A
5962-89749
DEFENSE SUPPLY CENTER COLUMBUS
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REVISION LEVEL
B
SHEET 9
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics – Continued.
Limits 4/ Test and
MIL-STD-883
test method 1/
Symbol Test conditions 2/ 3/
-55°C ≤ TC ≤ +125°C
+3.0 V ≤ VCC ≤ +5.5 V
Unless otherwise specified
Device
type
and
device
class
VCC Group A
subgroups
Min Max
Unit
9 1.0 11.0
All
and
All
3.0 V
10, 11 1.0 13.5
9 1.5 8.5
tPHL6
10/
All
and
All
4.5 V
10, 11 1.5 10.0
ns
9 1.0 11.0
All
and
All
3.0 V
10, 11 1.0 14.0
9 1.5 8.5
Propagation delay
time, U/D to TC
3003
tPLH6
10/
CL = 50 pF minimum
RL = 500Ω
See figure 4
All
and
All
4.5 V
10, 11 1.5 10.5
ns
9 1.0 12.0
All
and
All
3.0 V
10, 11 1.0 15.5
9 1.5 9.0
tPHL7
10/
All
and
All
4.5 V
10, 11 1.5 10.5
ns
9 1.0 13.5
All
and
All
3.0 V
10, 11 1.0 16.5
9 1.5 9.0
Propagation delay
time, Pn to Qn
3003
tPLH7
10/
CL = 50 pF minimum
RL = 500Ω
See figure 4
All
and
All
4.5 V
10, 11 1.5 11.5
ns
9 1.0 12.5
All
and
All
3.0 V
10, 11 1.0 15.5
9 1.5 9.5
tPHL8
10/
All
and
All
4.5 V
10, 11 1.5 11.5
ns
9 1.0 14.0
All
and
All
3.0 V
10, 11 1.0 18.0
9 1.5 10.0
Propagation delay
time, PL to Qn
3003
tPLH8
10/
CL = 50 pF minimum
RL = 500Ω
See figure 4
All
and
All
4.5 V
10, 11 1.5 12.5
ns
9 70
All
All 3.0 V
10, 11 55
9 90
Maximum clock
frequency, CP
fMAX
11/
All
and
All
4.5 V
10, 11 80
MHz
9 3.5
All
and
All
3.0 V
10, 11 4.0
9 2.5
Setup time, Pn to PL
(high or low)
ts1
11/ All
and
All
4.5 V
10, 11 3.0
ns
9 7.0
All
and
All
3.0 V
10, 11 9.0
9 5.0
Setup time, CE to CP
(low)
ts2
11/
CL = 50 pF minimum
RL = 500Ω
See figure 4
All
and
All
4.5 V
10, 11 6.0
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89749
DEFENSE SUPPLY CENTER COLUMBUS
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SHEET 10
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics – Continued.
Limits 4/ Test and
MIL-STD-883
test method 1/
Symbol Test conditions 2/ 3/
-55°C ≤ TC ≤ +125°C
+3.0 V ≤ VCC ≤ +5.5 V
Unless otherwise specified
Device
type
and
device
class
VCC Group A
subgroups
Min Max
Unit
9 9.0
All
and
All
3.0 V
10, 11 10.5
9 6.0
Setup time U/D to CP
(high or low)
ts3
11/ All
and
All
4.5 V
10, 11 7.5
ns
9 1.0
All
and
All
3.0 V
10, 11 1.5
9 2.0
Hold time, Pn to PL
(high or low)
th1
11/
All
and
All
4.5 V
10, 11 2.0
ns
9 0.0
All
and
All
3.0 V
10, 11 0.0
9 0.5
Hold time, CE to CP
(low)
th2
11/ All
and
All
4.5 V
10, 11 0.5
ns
9 0.0
All
and
All
3.0 V
10, 11 0.0
9 1.0
Hold time, U/D to CP
(high or low)
th3
11/ All
and
All
4.5 V
10, 11 1.0
ns
9 5.0
All
and
All
3.0 V
10, 11 5.0
9 5.0
CP pulse width
(high)
tw1
11/ All
and
All
4.5 V
10, 11 5.0
ns
9 5.0
All
and
All
3.0 V
10, 11 6.0
9 6.0
CP pulse width
(low)
tw2
11/ All
and
All
4.5 V
10, 11 6.0
ns
9 5.0
All
and
All
3.0 V
10, 11 5.0
9 5.0
PL pulse width
(low)
tw3
11/ All
and
All
4.5 V
10, 11 5.0
ns
9 1.0
All
and
All
3.0 V
10, 11 1.5
9 1.0
Recovery time
PL to CP
trec
11/
CL = 50 pF minimum
RL = 500Ω
See figure 4
All
and
All
4.5 V
10, 11 1.0
ns
See footnotes on next sheet.
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TABLE IA. Electrical performance characteristics - Continued.
1/ For tests not listed in the referenced MIL-STD-883 (e.g. VIH, VIL), utilize the general test procedure under the conditions listed
herein. All inputs and outputs shall be tested, as applicable, to the tests in table IA herein.
2/ Each input/output, as applicable shall be tested at the specified temperature for the specified limits. Output terminals not
designated shall be high level logic, low level logic, or open, except as follows:
a. VIC (pos) tests, the GND terminal can be open. TC = +25°C.
b. VIC (neg) tests, the VCC terminal shall be open. TC = +25°C.
c. All ICC tests, the output terminal shall be open. When performing these tests, the current meter shall be placed in the
circuit such that all current flows through the meter.
3/ RHA parts for device type 02 supplied to this drawing have been characterized through all levels M, D, P, L, R, and F of
irradiation. However, this device is only tested at the 'F' level. Pre and Post irradiation values are identical unless otherwise
specified in table IA. When performing post irradiation electrical measurements for any RHA level, TA = +25°C.
4/ For negative and positive voltage and current values, the sign designates the potential difference in reference to GND and the
direction of current flow, respectively; and the absolute value of the magnitude, not the sign, is relative to the minimum and
maximum limits, as applicable, listed herein.
5/ The VOH and VOL tests shall be tested at VCC = 3.0 V and 4.5 V. The VOH and VOL tests are guaranteed, if not tested, for other
values of VCC. Limits shown apply to operation at VCC = 3.3 V ±0.3 V and VCC = 5.0 V ±0.5 V. Tests with input current at
+50 mA or -50 mA are performed on only one input at a time with duration not to exceed 2 ms. Transmission driving tests
may be performed using VIN = VCC or GND. When VIN = VCC or GND is used, the test is guaranteed for VIN = VIH minimum
and VIL maximum.
6/ The VIH and VIL tests are not required if applied as forcing functions for VOH and VOL tests.
7/ The maximum limit for this parameter at 100 krads (Si) is 4 μA.
8/ Power dissipation capacitance (CPD) determines both the power consumption (PD) and dynamic current consumption (IS).
Where:
P
D = (CPD + CL) (VCC x VCC)f + (ICC x VCC)
I
S = (CPD + CL) VCCf + ICC
f is the frequency of the input signal and CL is the external output load capacitance.
9/ Tests shall be performed in sequence, attributes data only. Functional tests shall include the truth table and other logic
patterns used for fault detection. The test vectors used to verify the truth table shall, at a minimum, test all functions of each
input and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the truth table in
figure 2 herein. Functional tests shall be performed in sequence as approved by the qualifying activity on qualified devices.
Allowable tolerances in accordance with MIL-STD-883 for the input voltage levels may be incorporated.
For VOUT measurements, L ≤ 0.3VCC and H ≥ 0.7VCC.
10/ AC limits at VCC = 5.5 V are equal to the limits at VCC = 4.5 V and guaranteed by testing at VCC = 4.5 V. AC limits at
VCC = 3.6 V are equal to limits at VCC = 3.0 V and guaranteed by testing at VCC = 3.0 V. Minimum AC limits for VCC = 5.5 V
are 1.0 ns and guaranteed by guardbanding the VCC = 4.5 V minimum limits to 1.5 ns. For propagation delay tests, all paths
must be tested.
11/ This parameter is guaranteed if not tested.
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TABLE IB. SEP test limits. 1/ 2/
Device
type
SEP TC = temperature ±10°C VCC
Effective LET
02 SEL +25°C 3.6 V and 5.5 V ≥ 93 MeV-cm2/mg
1/ For SEP test conditions, see 4.4.4.2 herein.
2/ Technology characterization and model verification supplemented by in-line data may be used in lieu of
end-of-line testing. Test plan must be approved by TRB and qualifying activity.
Device types
01, 02
Case outlines
E, F, and X
2
Terminal
number
Terminal symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
P1
Q1
Q0
CE
U/D
Q2
Q3
GND
P3
P2
PL
TC
RC
CP
P0
VCC
---
---
---
---
NC
P1
Q1
Q0
CE
NC
U/D
Q2
Q3
GND
NC
P3
P2
PL
TC
NC
RC
CP
P0
VCC
NC = no connection
FIGURE 1. Terminal connections.
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Mode select table
Inputs
PL CE U/D CP
Mode
H L L ↑ Count up
H L H ↑ Count down
L X X X Preset
(asynchronous)
H H X X No change (hold)
RC truth table
Inputs Outputs
CE TC * CP RC
L H
H X X H
X L X H
* = TC is generated internally
H = High voltage level
L = Low voltage level
X = Irrelevant
↑ = Low-to-high clock transition
= Low clock pulse
FIGURE 2. Truth table.
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FIGURE 3. Logic diagram.
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FIGURE 4. Switching waveforms and test circuit.
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FIGURE 4. Switching waveforms and test circuit – Continued.
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NOTES:
1. CL = 50 pF minimum or equivalent (includes test jig and probe capacitance).
2. RT = 50Ω or equivalent, RL = 500Ω or equivalent.
3. Input signal from pulse generator: VIN = 0.0 V to VCC; PRR ≤ 10 MHz; tr ≤ 3.0 ns; tf ≤ 3.0 ns; tr and tf shall be
measured from 10% VCC to 90% VCC and from 90% VCC to 10% VCC, respectively; duty cycle = 50 percent.
4. Timing parameters shall be tested at a minimum input frequency of 1 MHz.
5. The outputs are measured one at a time with one transition per measurement.
FIGURE 4. Switching waveforms and test circuit - Continued.
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4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in
accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a. Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision
level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
(2) TA = +125°C, minimum.
b. Interim and final electrical test parameters shall be as specified in table IIA herein.
4.2.2 Additional criteria for device classes Q and V.
a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b. Interim and final electrical test parameters shall be as specified in table IIA herein.
c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for
device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see
4.4.1 through 4.4.4).
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TABLE IIA. Electrical test requirements.
Test requirements Subgroups
(in accordance with
MIL-STD-883,
method 5005, table I)
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Device
class M
Device
class Q
Device
class V
Interim electrical
parameters (see 4.2)
1
Final electrical
parameters (see 4.2)
1/ 1, 2, 3, 7,
8, 9
1/ 1, 2, 3, 7,
8, 9
2/ 3/ 1, 2, 3, 7,
8, 9, 10, 11
Group A test
requirements (see 4.4)
1, 2, 3, 4, 7,
8, 9, 10, 11
1, 2, 3, 4, 7,
8, 9, 10, 11
1, 2, 3, 4, 7,
8, 9, 10, 11
Group C end-point electrical
parameters (see 4.4)
1, 2, 3 1, 2, 3 3/ 1, 2, 3, 7,
8, 9, 10, 11
Group D end-point electrical
parameters (see 4.4)
1, 2, 3 1, 2, 3 1, 2, 3
Group E end-point electrical
parameters (see 4.4)
1, 7, 9 1, 7, 9 1, 7, 9
1/ PDA applies to subgroup 1.
2/ PDA applies to subgroups 1, 7, and deltas.
3/ Delta limits, as specified in table IIB, shall be required where specified, and the delta limits shall
be completed with reference to the zero hour electrical parameters.
TABLE IIB. Burn-in and operating life test, delta parameters (+25°C).
Parameter 1/ Symbol Device type Delta limits
01 ±100 nA 2/
Quiescent supply current ICCH, ICCL 02 ±300 nA
Supply current delta ΔICC 02 ±0.4 mA
Input current low level IIL 02 ±20 nA
Input current high level IIH 02 ±20 nA
Output voltage low level
(IOL = 24 mA, VCC = 5.5 V) VOL 02 ±0.04 V
Output voltage high level
(IOH = -24 mA, VCC = 5.5 V) VOH 02 ±0.20 V
1
/ These parameters shall be recorded before and after the required burn-in
and life tests to determine delta limits.
2/ Guaranteed if not tested.
4.4.1 Group A inspection
a. Tests shall be as specified in table IIA herein.
b. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table in figure 2 herein. The test
vectors used to verify the truth table shall, at a minimum, test all functions of each input and output. All possible input to
output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 2, herein. For device
classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device.
c. CIN and CPD shall be measured only for initial qualification and after process or design changes which may affect
capacitance. CIN shall be measured between the designated terminal and GND at a frequency of 1 MHz. CPD shall be
tested in accordance with the latest revision of JEDEC Standard No. 20 and table IA herein. For CIN and CPD, test all
applicable pins on five devices with zero failures.
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4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a. Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
b. TA = +125°C, minimum.
c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature, or
approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The test
circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a. End-point electrical parameters shall be as specified in table II herein.
b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device
classes must meet the postirradiation end-point electrical parameter limits as defined in table IA at TA = +25°C ±5°C, after
exposure, to the subgroups specified in table IIA herein.
4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883 method
1019, condition A and as specified herein. Prior to and during total dose irradiation characterization and testing, the devices for
characterization shall be biased so that 50 percent are at inputs high and 50 percent are at inputs low, and the devices for testing
shall be biased to the worst case condition established during characterization. Devices shall be biased as follows:
Device type 02:
Inputs tested high, VCC = 5.5 V dc ±5%, VIN = 5.0 V dc +10%, RIN = 1 kΩ ±20%, and all outputs are open.
Inputs tested low, VCC = 5.5 V dc ±5%, VIN = 0.0 V dc, RIN = 1 kΩ ±20%, and all outputs are open.
4.4.4.1.1 Accelerated annealing test. Accelerated annealing tests shall be performed on all devices requiring a RHA level
greater than 5k rads (Si). The post-anneal end-point electrical parameter limits shall be as specified in table IA herein and shall be
the pre-irradiation end-point electrical parameter limit at 25°C ±5°C. Testing shall be performed at initial qualification and after any
design or process changes which may affect the RHA response of the device.
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4.4.4.2 Single event phenomena (SEP). When specified in the purchase order or contract, SEP testing shall be required on
class V devices. SEP testing shall be performed on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as
approved by the qualifying activity at initial qualification and after any design or process changes which may affect the upset or
latchup characteristics. Test four devices with zero failures. ASTM F1192 may be used as a guideline when performing SEP
testing. The test conditions for SEP are as follows:
a. The ion beam angle of incidence shall be between normal to the die surface and 60° to the normal, inclusive
(i.e. 0° ≤ angle ≤ 60°). No shadowing of the ion beam due to fixturing or package related effects is allowed.
b. The fluence shall be ≥ 100 errors or ≥ 107 ions/cm2.
c. The flux shall be between 102 and 105 ions/cm2/s. The cross-section shall be verified to be flux independent by measuring
the cross-section at two flux rates which differ by at least an order of magnitude.
d. The particle range shall be ≥ 20 microns in silicon.
e. The upset test temperature shall be +25°C and the latchup test temperature is maximum rated operating temperature
±10°C.
f. Bias conditions shall be defined by the manufacturer for latchup measurements.
g. For SEP test limits, see table IB herein.
4.5 Methods of inspection. Methods of inspection shall be specified as follows:
4.5.1 Voltage and current. Unless otherwise specified, all voltages given are referenced to the microcircuit GND terminal.
Currents given are conventional current and positive when flowing into the referenced terminal.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes Q
and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-
prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the
individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone
(614) 692-0547.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
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6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to this
drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103. The
vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted
to and accepted by DSCC-VA.
6.7 Additional information. When specified in the purchase order or contract, a copy of the following additional data shall be
supplied.
a. RHA upset levels.
b. Test conditions (SEP).
c. Number of upsets (SEP).
d. Number of transients (SEP).
e. Occurrence of latch-up (SEP).
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-89749
A.1 SCOPE
A.1.1 Scope. This appendix establishes minimum requirements for microcircuit die to be supplied under the Qualified
Manufacturers List (QML) Program. QML microcircuit die meeting the requirements of MIL-PRF-38535 and the manufacturers
approved QM plan for use in monolithic microcircuits, multi-chip modules (MCMs), hybrids, electronic modules, or devices using
chip and wire designs in accordance with MIL-PRF-38534 are specified herein. Two product assurance classes consisting of
military high reliability (device class Q) and space application (device class V) are reflected in the Part or Identification Number
(PIN). When available, a choice of Radiation Hardiness Assurance (RHA) levels are reflected in the PIN.
A.1.2 PIN. The PIN is as shown in the following example:
5962 F 89749 02 V 9 A
Federal RHA Device Device Die Die
stock class designator type class code details
designator (see A.1.2.1) (see A.1.2.2) designator (see A.1.2.4)
\ / (see A.1.2.3)
\/
Drawing number
A.1.2.1 RHA designator. Device classes Q and V RHA identified die meet the MIL-PRF-38535 specified RHA levels. A dash (-)
indicates a non-RHA die.
A.1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type Generic number Circuit function
02 54AC191 Up/down counter with preset and ripple clock
A.1.2.3 Device class designator. Device class Q designator will not be included in the PIN and will not be marked on the device
since the device class designator has been added after the original issuance of this drawing.
Device class Device requirements documentation
Q or V Certification and qualification to the die requirements of MIL-PRF-38535
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-89749
A.1.2.4 Die details. The die details designation is a unique letter which designates the die's physical dimensions, bonding pad
location(s) and related electrical function(s), interface materials, and other assembly related information, for each product and
variant supplied to this appendix.
A.1.2.4.1 Die physical dimensions.
Die type Figure number
02 A-1
A.1.2.4.2 Die bonding pad locations and electrical functions.
Die type Figure number
02 A-1
A.1.2.4.3 Interface materials.
Die type Figure number
02 A-1
A.1.2.4.4 Assembly related information.
Die type Figure number
02 A-1
A.1.3 Absolute maximum ratings. See paragraph 1.3 herein for details.
A.1.4 Recommended operating conditions. See paragraph 1.4 herein for details.
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-89749
A.2. APPLICABLE DOCUMENTS
A.2.1 Government specification, standards, and handbooks. The following specification, standard, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARD
MIL-STD-883 - Test Method Standard Microcircuits.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or from the Standardization Document
Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
A.2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
A.3 REQUIREMENTS
A.3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer’s Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein.
A.3.2 Design, construction and physical dimensions. The design, construction, and physical dimensions shall be as specified in
MIL-PRF-38535 and herein and the manufacturer’s QM plan for device classes Q and V.
A.3.2.1 Die physical dimensions. The die physical dimensions shall be as specified in A.1.2.4.1 and on figure A-1.
A.3.2.2 Die bonding pad locations and electrical functions. The die bonding pad locations and electrical functions shall be as
specified in A.1.2.4.2 and on figure A-1.
A.3.2.3 Interface materials. The interface materials for the die shall be as specified in A.1.2.4.3 and on figure A-1.
A.3.2.4 Assembly related information. The assembly related information shall be as specified in A.1.2.4.4 and on figure A-1.
A.3.2.5 Truth table. The truth table shall be as defined in paragraph 3.2.3 herein.
A.3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be as defined in paragraph 3.2.6 herein.
A.3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and post-irradiation parameter limits are as specified in table IA of the body of this
document.
A.3.4 Electrical test requirements. The wafer probe test requirements shall include functional and parametric testing sufficient
to make the packaged die capable of meeting the electrical performance requirements in table IA.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89749
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
B
SHEET 26
DSCC FORM 2234
APR 97
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-89749
A.3.5 Marking. As a minimum, each unique lot of die, loaded in single or multiple stack of carriers, for shipment to a customer,
shall be identified with the wafer lot number, the certification mark, the manufacturer’s identification and the PIN listed in A.1.2
herein. The certification mark shall be a “QML” or “Q” as required by MIL-PRF-38535.
A.3.6 Certification of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see A.6.4 herein). The certificate of compliance
submitted to DSCC-VA prior to listing as an approved source of supply for this appendix shall affirm that the manufacturer’s
product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and the requirements herein.
A.3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall
be provided with each lot of microcircuit die delivered to this drawing.
A.4 VERIFICATION
A.4.1 Sampling and inspection. For device classes Q and V, die sampling and inspection procedures shall be in accordance
with MIL-PRF-38535 or as modified in the device manufacturer’s Quality Management (QM) plan. The modifications in the QM
plan shall not affect the form, fit, or function as described herein.
A.4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and as defined in the
manufacturer’s QM plan. As a minimum, it shall consist of:
a. Wafer lot acceptance for class V product using the criteria defined in MIL-STD-883, method 5007.
b. 100% wafer probe (see paragraph A.3.4 herein).
c. 100% internal visual inspection to the applicable class Q or V criteria defined in MIL-STD-883, method 2010 or the
alternate procedures allowed in MIL-STD-883, method 5004.
A.4.3 Conformance inspection.
A.4.3.1 Group E inspection. Group E inspection is required only for parts intended to be identified as radiation assured (see
A.3.5 herein). RHA levels for device classes Q and V shall be as specified in MIL-PRF-38535. End point electrical testing of
packaged die shall be as specified in table II herein. Group E tests and conditions are as specified in paragraphs 4.4.4 herein.
A.5 DIE CARRIER
A.5.1 Die carrier requirements. The requirements for the die carrier shall be accordance with the manufacturer’s QM plan or as
specified in the purchase order by the acquiring activity. The die carrier shall provide adequate physical, mechanical and
electrostatic protection.
A.6 NOTES
A.6.1 Intended use. Microcircuit die conforming to this drawing are intended for use in microcircuits built in accordance with
MIL-PRF-38535 or MIL-PRF-38534 for government microcircuit applications (original equipment), design applications, and
logistics purposes.
A.6.2 Comments. Comments on this appendix should be directed to DSCC-VA, Columbus, Ohio, 43218-3990 or telephone
(614) 692-0547.
A.6.3 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
A.6.4 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed within QML-38535 have submitted a certificate of compliance (see A.3.6 herein) to DSCC-VA and have agreed
to this drawing.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89749
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
B
SHEET 27
DSCC FORM 2234
APR 97
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-89749
Die physical dimensions.
Die size: 2090 x 1876 μm
Die thickness: 285 ±25 μm
Die bonding pad locations and electrical functions.
Optional manufacturer's logo
Pad size: Pad numbers 1 to 7 and 9 to 15: 100 x 100 μm
Pad numbers 8 (GND) and 16 (VCC): 100 x 280 μm
NOTE: Pad numbers reflect terminal numbers when placed in case outline X (see figure 1).
FIGURE A-1
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89749
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
B
SHEET 28
DSCC FORM 2234
APR 97
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-89749
Interface materials.
Top metallization: Al Si Cu 0.85 μm
Backside metallization: None
Glassivation.
Type: P. Vapox + Nitride
Thickness: 0.5 μm – 0.7 μm
Substrate: Silicon
Assembly related information.
Substrate potential: Floating or tied to GND
Special assembly instructions: Bond pad #16 (VCC) first
FIGURE A-1 – Continued.
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 08-06-11
Approved sources of supply for SMD 5962-89749 are listed below for immediate acquisition information only and shall
be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised
to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate
of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next
dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of
supply at http://www.dscc.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-8974901EA 0C7V7 54AC191DMQB
5962-8974901FA 0C7V7 54AC191FMQB
5962-89749012A 0C7V7 54AC191LMQB
5962-8974902XA 3/ 54AC191K02Q
5962-8974902XC 3/ 54AC191K01Q
5962-8974902VXA 3/ 54AC191K02V
5962-8974902VXC 3/ 54AC191K01V
5962F8974902EA F8859 RHFAC191D04Q
5962F8974902EC F8859 RHFAC191D03Q
5962F8974902XA F8859 RHFAC191K02Q
5962F8974902XC F8859 RHFAC191K01Q
5962F8974902VEA F8859 RHFAC191D04V
5962F8974902VEC F8859 RHFAC191D03V
5962F8974902VXA F8859 RHFAC191K02V
5962F8974902VXC F8859 RHFAC191K01V
5962F8974902V9A F8859 AC191DIE2V
1/ The lead finish shown for each PIN representing a hermetic
package is the most readily available from the manufacturer
listed for that part. If the desired lead finish is not listed
contact the Vendor to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
3/ Not available from an approved source of supply.
Vendor CAGE Vendor name
number and address
F8859 ST Microelectronics
3 rue de Suisse
CS 60816
35208 RENNES cedex2-FRANCE
0C7V7 QP Semiconductor
2945 Oakmead Village Court
Santa Clara, CA 95051
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
