Si860x Data Sheet Bidirectional I2C Isolators with Unidirectional Digital Channels The Si860x series of isolators are single-package galvanic isolation solutions for I2C and SMBus serial port applications. These products are based on Silicon Labs proprietary RF isolation technology and offer shorter propagation delays, lower power consumption, smaller installed size, and more stable operation with temperature and age versus opto couplers or other digital isolators. All devices in this family include hot-swap, bidirectional SDA and/or SCL isolation channels with open-drain, 35 mA sink capability that operate to a maximum frequency of 1.7 MHz. The 8-pin version (Si8600) supports bidirectional SDA and SCL isolation; the Si8602 supports bidirectional SDA and unidirectional SCL isolation, and the 16-pin versions (Si8605, Si8606) feature two unidirectional isolation channels to support additional system signals, such as interrupts or resets. All versions contain protection circuits to guard against data errors when an unpowered device is inserted into a powered system. Small size, low installed cost, low power consumption, and short propagation delays make the Si860x family the optimum solution for isolating I2C and SMBus serial ports. Applications * Isolated I2C, PMBus, SMBus * * * * * Power over Ethernet Motor Control Systems Hot-swap applications Intelligent Power systems Isolated SMPS systems with PMBus interfaces KEY FEATURES * Independent, bidirectional SDA and SCL isolation channels * Open drain outputs with 35 mA sink current * Supports I2C clocks up to 1.7 MHz * Unidirectional isolation channels support additional system signals (Si8605, Si8606) * Up to 5000 VRMS isolation * UL, CSA, VDE, CQC recognition * 60-year life at rated working voltage * High electromagnetic immunity * Wide operating supply voltage * 3.0 to 5.5 V * Wide temperature range * -40 to +125 C * Transient immunity 50 kV/s * AEC-Q100 qualification * RoHS-compliant packages * SOIC-8 narrow body * SOIC-16 wide body * SOIC-16 narrow body Safety Regulatory Approvals * UL 1577 recognized * Up to 5000 VRMS for 1 minute * CSA component notice 5A approval * IEC 60950-1, 61010-1, 60601-1 (reinforced insulation) * VDE certification conformity * Si863xxT options certified to reinforced VDE 0884-10 * All other options certified to IEC 60747-5-5 and reinforced 60950-1 * CQC certification approval * GB4943.1 silabs.com | Building a more connected world. Rev. 1.7 Table of Contents 1. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3. Typical Application Overview . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.1 I2C Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.2 I2C Isolator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.3 I2C Isolator Design Constraints . . . . . . . . . . . . . . . . . . . . . . . . 4 3.4 I2C Isolator Design Considerations . . . . . . . . . . . . . . . . . . . . . . . 4 3.5 Typical Application Schematics . . . . . . . . . . . . . . . . . . . . . . . 5 . 4. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.3 Input and Output Characteristics for Non-I2C Digital Channels . . . . . . . . . . . . . 8 4.4 Layout Recommendations. 4.4.1 Supply Bypass . . . . 4.4.2 Output Pin Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 . 8 . 8 4.5 Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . 9 5. Electrical Specifications 5.1 Test Circuits 6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 . . . . . . . . . . . . . . . . . . . . . . . . . . .15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 Si8600/02 SOIC-8 Package . . . . . . . . . . . . . . . . . . . . . . . . .20 6.2 Si8600/02 SOIC-16 Package . . . . . . . . . . . . . . . . . . . . . . . . .21 6.3 Si8605/06 SOIC-16 Package . . . . . . . . . . . . . . . . . . . . . . . . .22 7. Package Outline: 16-Pin Wide Body SOIC. . . . . . . . . . . . . . . . . . . . 23 8. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . 25 9. Package Outline: 8-Pin Narrow Body SOIC 10. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . 26 . . . . . . . . . . . . . . . . . . . . 27 11. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . 28 12. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . 30 13. Si860x Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 13.1 Top Marking: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . .31 13.2 Top Marking: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . .32 13.3 Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . .33 silabs.com | Building a more connected world. Rev. 1.7 14. Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . 34 14.1 Revision 0.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 14.2 Revision 0.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 14.3 Revision 0.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 14.4 Revision 1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 14.5 Revision 1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 14.6 Revision 1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 14.7 Revision 1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 14.8 Revision 1.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 14.9 Revision 1.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 14.10 Revision 1.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 silabs.com | Building a more connected world. Rev. 1.7 Si860x Data Sheet Ordering Guide 1. Ordering Guide Table 1.1. Ordering Guide1, 2 Ordering Part Number (OPN) Number of Bidirectional 2 I C Channels Max I2C Bus Speed (MHz) Number of Unidirectional Non-I2C Channels Max Data Rate of Non-I2C Unidirectional Channels (Mbps) Isolation Ratings (kVrms) Temp Range (C) Package Si8600AB-B-IS 2 1.7 0 -- 2.5 -40 to 125 NB SOIC-8 Si8600AC-B-IS 2 1.7 0 -- 3.75 -40 to 125 NB SOIC-8 Si8600AD-B-IS 2 1.7 0 -- 5.0 -40 to 125 WB SOIC-16 Si8602AB-B-IS 1 1.7 1 10 2.5 -40 to 125 NB SOIC-8 Si8602AC-B-IS 1 1.7 1 10 3.75 -40 to 125 NB SOIC-8 Si8602AD-B-IS 1 1.7 1 10 5.0 -40 to 125 WB SOIC-16 Si8605AB-B-IS1 2 1.7 1 Forward 10 2.5 -40 to 125 NB SOIC-16 10 3.75 -40 to 125 NB SOIC-16 10 5.0 -40 to 125 WB SOIC-16 1 Reverse Si8605AC-B-IS1 2 1.7 1 Forward 1 Reverse Si8605AD-B-IS 2 1.7 1 Forward 1 Reverse Si8606AC-B-IS1 2 1.7 2 Forward 10 3.75 -40 to 125 NB SOIC-16 Si8606AD-B-IS 2 1.7 2 Forward 10 5.0 -40 to 125 WB SOIC-16 Note: 1. All packages are RoHS-compliant with peak reflow temperature of 260 C according to the JEDEC industry standard classifications and peak solder temperature. 2. "Si" and "SI" are used interchangeably. 3. An "R" at the end of the part number denotes tape and reel packaging option. silabs.com | Building a more connected world. Rev. 1.7 | 1 Si860x Data Sheet System Overview 2. System Overview 2.1 Theory of Operation The operation of an Si86xx channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified block diagram for a single unidirectional Si86xx channel is shown in the figure below. Transmitter Receiver RF OSCILLATOR A MODULATOR SemiconductorBased Isolation Barrier DEMODULATOR B Figure 2.1. Simplified Channel Diagram A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See the following figure for more details. Input Signal Modulation Signal Output Signal Figure 2.2. Modulation Scheme silabs.com | Building a more connected world. Rev. 1.7 | 2 Si860x Data Sheet Typical Application Overview 3. Typical Application Overview 3.1 I2C Background In many applications, I2C, SMBus, and PMBus interfaces require galvanic isolation for safety or ground loop elimination. For example, Power over Ethernet (PoE) applications typically use an I2C interface for communication between the PoE power sourcing device (PSE), and the earth ground referenced system controller. Galvanic isolation is required both by standard and also as a practical matter to prevent ground loops in Ethernet connected equipment. The physical interface consists of two wires: serial data (SDA) and serial clock (SCL). These wires are connected to open collector drivers that serve as both inputs and outputs. At first glance, it appears that SDA and SCL can be isolated simply by placing two unidirectional isolators in parallel, and in opposite directions. However, this technique creates feedback that latches the bus line low when a logic low asserted by either master or slave. This problem can be remedied by adding anti-latch circuits, but results in a larger and more expensive solution. The Si860x products offer a single-chip, anti-latch solution to the problem of isolating I2C/SMBus applications and require no external components except the I2C/SMBus pull-up resistors. In addition, they provide isolation to a maximum of 5.0 kVRMS, support I2C clock stretching, and operate to a maximum I2C bus speed of 1.7 Mbps. 3.2 I2C Isolator Operation Without anti-latch protection, bidirectional I2C isolators latch when an isolator output logic low propagates back through an adjacent isolator channel creating a stable latched low condition on both sides. Anti-latch protection is typically added to one side of the isolator to avoid this condition (the "A" side for the Si8600/02/05/06). The following examples illustrate typical circuit configurations using the Si8600/02/05/06. Si8600/02/05/06 I2C/SMBus Unit 1 + - VIL I2C/SMBus Unit 2 ISO1 VOL VIL VOL B Side A Side ISO2 Figure 3.1. Isolated Bus Overview (I2C Channels Only) The "A side" output low (VOL) and input low (VIL) levels are designed such that the isolator VOL is greater than the isolator VIL to prevent the latch condition. silabs.com | Building a more connected world. Rev. 1.7 | 3 Si860x Data Sheet Typical Application Overview 3.3 I2C Isolator Design Constraints The table below lists the I2C isolator design constraints. Table 3.1. Design Constraints Design Constraint To prevent the latch condition, the isolator output low level must be greater than the isolator input low level. Data Sheet Values Effect of Bus Pull-up Strength and Temperature Isolator VOL 0.7 V typical This is normally guaranteed by the isolator data sheet. However, if the pull up strength is too weak, the output low voltage will fall and can get too close to the input low logic level. These track over temperature. Isolator VIL 0.5 V typical Input/Output Logic Low Level Difference VSDA1, VSCL1 = 50 mV minimum The bus output low must be less than the isolator input low logic level. The isolator output low must be less than the bus input low. Bus VOL = 0.4 V maximum Isolator VIL = 0.41 V minimum Bus VIL 0.3 x VDD = 1.0 V minimum for VDD = 3.3 V Isolator VOL = 0.8 V maximum If the pull up strength is too large, the devices on the bus might not pull the voltage below the input low range. These have opposite temperature coefficients. Worst case is hot temperature. If the pull up strength is too large, the isolator might not pull below the bus input low voltage. Si8600/02/05/06 Vol: -1.8 mV/C CMOS buffer: -0.6 mV/C This provides some temperature tracking, but worst case is cold temperature. 3.4 I2C Isolator Design Considerations The first step in applying an I2C isolator is to choose which side of the bus will be connected to the isolator A side. Ideally, it should be the side which: Is compatible with the range of bus pull up specified by the manufacturer. For example, the Si8600/02/05/06 isolators are normally used with a pull up of 0.5 mA to 3 mA. Has the highest input low level for devices on the bus. Some devices may specify an input low of 0.9 V and other devices might require an input low of 0.3 x Vdd. Assuming a 3.3 V minimum power supply, the side with an input low of 0.3 x Vdd is the better side because this side has an input low level of 1.0 V. Have devices on the bus that can pull down below the isolator input low level. For example, the Si860x input level is 0.41 V. As most CMOS devices can pull to within 0.4 V of GND this is generally not an issue. Has the lowest noise. Due to the special logic levels, noise margins can be as low as 50 mV. silabs.com | Building a more connected world. Rev. 1.7 | 4 Si860x Data Sheet Typical Application Overview 3.5 Typical Application Schematics The figures below illustrate typical circuit configurations using the Si8600, Si8602, Si8605, and Si8606. AVDD 3k 3k 0.1 F 0.1 F ASDA BVDD 8 1 2 3k 7 ASCL 3 6 AGND 4 5 3k BSDA BSCL I2C Bus BGND Si8600 Figure 3.2. Typical Si8600 Application Diagram AVDD 3k 0.1 F 0.1 F ASDA BVDD 8 1 2 3k BSDA 7 ASCL 3 6 AGND 4 5 BSCL I2C Bus BGND Si8602 Figure 3.3. Typical Si8602 Application Diagram BGND 1 16 2 15 33 14 4 13 ASDA 5 12 BSDA ASCL 6 11 BSCL AGND 7 10 AGND AVDD 0.1 F 3k 3k 8 Si8600 BVDD 0.1 F 9 3k 3k I2C Bus BGND Figure 3.4. Typical Si8600 Application Diagram silabs.com | Building a more connected world. Rev. 1.7 | 5 Si860x Data Sheet Typical Application Overview BGND 1 16 2 15 33 14 4 13 ASDA 5 12 BSDA ASCL 6 11 BSCL AGND 7 10 AGND AVDD 0.1 F 3k 8 Si8602 BVDD 0.1 F 3k I2C Bus BGND 9 Figure 3.5. Typical Si8602 Application Diagram AVDD 0.1 F 3k 3k ASDA RESET Microcontroller ASCL 1 16 2 15 33 14 4 13 5 12 6 11 7 10 8 AGND Si8605 BVDD 0.1 F 3k 3k BSDA Microcontroller INT I2C Bus BSCL BGND 9 Figure 3.6. Typical Si8605 Application Diagram 1 16 2 15 ASDA 33 14 RESET 4 13 INT 5 12 ASCL 6 11 7 10 AVDD 0.1 F 3k 3k AGND 8 Si8606 BVDD 0.1 F 3k 3k BSDA Microcontroller 9 I2C Bus BSCL BGND Figure 3.7. Typical Si8606 Application Diagram silabs.com | Building a more connected world. Rev. 1.7 | 6 Si860x Data Sheet Device Operation 4. Device Operation Device behavior during start-up, normal operation, and shutdown is shown in Figure 4.1 Device Behavior during Normal Operation on page 7, where UVLO+ and UVLO- are the positive-going and negative-going thresholds respectively. Refer to Table 4.1 Si86xx Operation Table on page 8 to determine outputs when power supply (VDD) is not present. 4.1 Device Startup Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following this, the outputs follow the states of inputs. 4.2 Undervoltage Lockout Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its specified operating circuits range. Both Side A and Side B each have their own undervoltage lockout monitors. Each side can enter or exit UVLO independently. For example, Side A unconditionally enters UVLO when AVDD falls below AVDDUVLO- and exits UVLO when AVDD rises above AVDDUVLO+. Side B operates the same as Side A with respect to its BVDD supply. UVLO+ UVLO- AVDD UVLO+ UVLO- BVDD INPUT tSD tSTART tSTART tSTART tPHL tPLH OUTPUT Figure 4.1. Device Behavior during Normal Operation silabs.com | Building a more connected world. Rev. 1.7 | 7 Si860x Data Sheet Device Operation 4.3 Input and Output Characteristics for Non-I2C Digital Channels The unidirectional Si86xx inputs and outputs are standard CMOS drivers/receivers. The nominal output impedance of an isolator driver channel is approximately 50 , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. Table 4.1 Si86xx Operation Table on page 8 details powered and unpowered operation of the Si86xx's non-I2C digital channels. Table 4.1. Si86xx Operation Table Comments VI Input1, 4 VDDI State11,2,3 VDDO State1,2,3 VO Output1, 4 H P P H L P P L X UP P L Upon transition of VDDI from unpowered to powered, VO returns to the same state as VI in less than 1 s. X P UP Undetermined Upon transition of VDDO from unpowered to powered, VO returns to the same state as VI within 1 s. Normal operation. Note: 1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. 2. Powered (P) state is defined as 3.0 V < VDD < 5.5 V. 3. Unpowered (UP) state is defined as VDD = 0 V. 4. X = not applicable; H = Logic High; L = Logic Low. 5. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current. 6. For I2C channels, the outputs for a given side go to Hi-Z when power is lost on the opposite side. 4.4 Layout Recommendations To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the safety extra-low voltage circuits (SELV is a circuit with <30 VAC) by a certain distance (creepage/clearance). If a component, such as a digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating (commonly referred to as working voltage protection). Table 5.6 Regulatory Information1 on page 15 and Table 5.7 Insulation and Safety-Related Specifications on page 16 detail the working voltage and creepage/clearance capabilities of the Si86xx. These tables also detail the component standards (UL1577, IEC60747, CSA 5A), which are readily accepted by certification bodies to provide proof for end-system specifications requirements. Refer to the end-system specification (61010-1, 60950-1, 60601-1, etc.) requirements before starting any design that uses a digital isolator. 4.4.1 Supply Bypass The Si860x family requires a 0.1 F bypass capacitor between AVDD and AGND and BVDD and BGND. The capacitor should be placed as close as possible to the package. To enhance the robustness of a design, the user may also include resistors (50-300 ) in series with the inputs and outputs if the system is excessively noisy. 4.4.2 Output Pin Termination The nominal output impedance of an non-I2C isolator channel is approximately 50 , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. silabs.com | Building a more connected world. Rev. 1.7 | 8 Si860x Data Sheet Device Operation 4.5 Typical Performance Characteristics The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer to Tables Table 5.2 Si860x Power Characteristics1 on page 10, Table 5.3 Si8600/02/05/06 Electrical Characteristics for Bidirectional I2C Channels1 on page 11, Table 5.4 Electrical Characteristics for Unidirectional Non-I2C Digital Channels (Si8602/05/06) on page 13, and Table 5.5 Electrical Characteristics for All I2C and Non-I2C Channels on page 14 for actual specification limits. Figure 4.2. I2C Side A Pulling Down (1100 Pull-Up) Figure 4.3. I2C Side A Pulling Up, Side B Following Figure 4.5. Non I2C Channel Propagation Delay vs. Temperature Figure 4.4. I2C Side B Pulling Down Figure 4.6. I2C Side B Pulling Up, Side A Following silabs.com | Building a more connected world. Rev. 1.7 | 9 Si860x Data Sheet Electrical Specifications 5. Electrical Specifications Table 5.1. Recommended Operating Conditions Parameter Ambient Operating Temperature1 Supply Voltage Symbol Min Typ Max Unit TA -40 25 125* C AVDD 3.0 -- 5.5 V BVDD 3.0 -- 5.5 V Note: 1. The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels, and supply voltage. Table 5.2. Si860x Power Characteristics1 3.0 V < VDD < 5.5 V. TA = -40 to +125 C. Typical specs at 25 C (See Figure 5.2 Simplified Timing Test Diagram on page 15 and Figure 3.2 Typical Si8600 Application Diagram on page 5 for test diagrams.) Parameter Symbol Test Condition Min Typ Max Unit -- 5.4 7.6 mA -- 4.3 6.5 mA -- 2.6 3.9 mA -- 1.9 2.9 mA -- 3.3 5.0 mA -- 2.6 3.9 mA -- 1.8 2.7 mA -- 1.8 2.7 mA -- 4.7 7.1 mA -- 3.1 4.7 mA -- 2.5 3.8 mA -- 2.1 3.2 mA Si8600 Supply Current AVDD Current Idda BVDD Current Iddb AVDD Current Idda BVDD Current Iddb AVDD Current Idda BVDD Current Iddb All channels = 0 dc All channels = 1 dc All channels = 1.7 MHz Si8602 Supply Current AVDD Current Idda BVDD Current Iddb AVDD Current Idda BVDD Current Iddb AVDD Current Idda BVDD Current Iddb All channels = 0 dc All channels = 1 dc All channels = 1.7 MHz Si8605 Supply Current AVDD Current Idda All non-I2C channels = 0 -- 3.4 5.1 mA BVDD Current Iddb All I2C channels = 1 -- 2.7 4.1 mA AVDD Current Idda All non-I2C channels = 1 -- 7.2 10.1 mA BVDD Current Iddb All I2C channels = 0 -- 6.2 8.7 mA AVDD Current Idda All non-I2C channels = 5 MHz -- 4.2 6.3 mA BVDD Current Iddb All I2C channels = 1.7 MHz -- 3.6 5.4 mA silabs.com | Building a more connected world. Rev. 1.7 | 10 Si860x Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit AVDD Current Idda All non-I2C channels = 0 -- 2.8 4.2 mA BVDD Current Iddb All I2C channels = 1 -- 3.0 4.5 mA AVDD Current Idda All non-I2C channels = 1 -- 8.3 11.6 mA BVDD Current Iddb All I2C channels = 0 -- 5.5 7.7 mA AVDD Current Idda All non-I2C channels = 5 MHz -- 4.1 6.2 mA BVDD Current Iddb All I2C channels = 1.7 MHz -- 3.5 5.3 mA Si8606 Supply Current Note: 1. All voltages are relative to respective ground. Table 5.3. Si8600/02/05/06 Electrical Characteristics for Bidirectional I2C Channels1 3.0 V < VDD < 5.5 V. TA = -40 to +125 C. Typical specs at 25 C unless otherwise noted. Parameter Symbol Test Condition Min Typ Max Unit 410 -- 540 mV 540 -- 800 mV Logic Levels Side A Logic Input Threshold2 I2CVT (Side A) Logic Low Output Voltages I2CVOL (Side A) Input/Output Logic Low Level Difference3 I2CV (Side A) 50 -- -- mV I2CVIL (Side B) -- -- 0.8 V 2.0 -- -- V -- -- 500 mV -- 2.0 10 A CA -- 10 -- pF CB -- 10 -- pF Logic Levels Side B Logic Low Input Voltage ISDAA, ISCLA (>0.5 mA, <3.0 mA) ISCLB = 35 mA Logic High Input Voltage I2CVIH (Side B) Logic Low Output Voltage I2CVOL (Side B) SCL and SDA Logic High Leakage Isdaa, Isdab SDAA, SCLA = VSSA Iscla, Isclb SDAB, SCLB = VSSB Pin Capacitance SDAA, SCLA, SDAB, SDBB silabs.com | Building a more connected world. Rev. 1.7 | 11 Si860x Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit -- -- 1.7 MHz Timing Specifications (Measured at 1.40 V Unless Otherwise Specified) Maximum I2C Bus Frequency Fmax Propagation Delay 5 V Operation Side A to Side B Rising 4 Tphab No bus capacitance, -- 38 45 ns Side A to Side B Falling 4 Tplab R1 = 1400 -- 15 26 ns Tphba R2 = 499 -- 33 46 ns Tplba -- 11 22 ns -- 44 55 ns Side B to Side A Rising 3.3 V Operation Tphab See Figure 5.2 Simplified Timing Test Diagram on page 15 Side A to Side B Rising 4 Tplab R1 = 806 -- 17 29 ns Side A to Side B Falling 4 Tphba R2 = 499 -- 30 40 ns Side B to Side A Rising Tplba -- 14 27 ns -- 22 32 ns -- 21 32 ns -- 27 35 ns -- 15 25 ns Side B to Side A Falling Side B to Side A Falling Pulse Width Distortion No bus capacitance 5V R1 = 1400 Side A Low to Side B Low 4 PWDBA Side B Low to Side A Low 3.3 V Side A Low to Side B Low PWDAB 4 R2 = 499 PWDAB See Figure 5.2 Simplified Timing Test Diagram on page 15 PWDBA R1 = 806 Side B Low to Side A Low R2 = 499 Note: 1. All voltages are relative to respective ground. 2. VIL < 0.410 V, VIH > 0.540 V. 3. I2CV (Side A) = I2CVOL (Side A) - I2CVT (Side A). To ensure no latch-up on a given bus, I2CV (Side A) is the minimum difference between the output logic low level of the driving device and the input logic threshold. 4. Side A measured at 0.6 V. silabs.com | Building a more connected world. Rev. 1.7 | 12 Si860x Data Sheet Electrical Specifications Table 5.4. Electrical Characteristics for Unidirectional Non-I2C Digital Channels (Si8602/05/06) 3.0 V < VDD < 5.5 V. TA = -40 to +125 C. Typical specs at 25 C Parameter Symbol Test Condition Min Typ Max Unit Positive-Going Input Threshold VT+ All inputs rising 1.4 1.67 1.9 V Negative-Going Input Threshold VT- All inputs falling 1.0 1.23 1.4 V Input Hysteresis VHYS 0.38 0.44 0.50 V High Level Input Voltage VIH 2.0 -- -- V Low Level Input Voltage VIL -- -- 0.8 V High Level Output Voltage VOH loh = -4 mA AVDD, BVDD -0.4 4.8 -- V Low Level Output Voltage VOL lol = 4 mA -- 0.2 0.4 V Input Leakage Current IL -- -- 10 A Output Impedance1 ZO -- 50 -- Maximum Data Rate 0 -- 10 Mbps Minimum Pulse Width -- -- 40 ns Timing Characteristics Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew2 Channel-Channel Skew tPHL, tPLH See Figure 5.1 Propagation Delay Timing (Non-I2C Channels) on page 14 -- -- 20 ns PWD See Figure 5.1 Propagation Delay Timing (Non-I2C Channels) on page 14 -- -- 12 ns tPSK(P-P) -- -- 20 ns tPSK -- -- 10 ns -- 2.5 4.0 ns -- 2.5 4.0 ns -- 350 -- ps C3 = 15 pF Output Rise Time tr See Figure 5.1 Propagation Delay Timing (Non-I2C Channels) on page 14 and Figure 5.2 Simplified Timing Test Diagram on page 15 C3 = 15 pF Output Fall Time Peak Eye Diagram Jitter tf tJIT(PK) See Figure 5.1 Propagation Delay Timing (Non-I2C Channels) on page 14 and Figure 5.2 Simplified Timing Test Diagram on page 15 Note: 1. The nominal output impedance of a non-I2C isolator driver channel is approximately 50 , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. silabs.com | Building a more connected world. Rev. 1.7 | 13 Si860x Data Sheet Electrical Specifications Table 5.5. Electrical Characteristics for All I2C and Non-I2C Channels 3.0 V < VDD < 5.5 V. TA = -40 to +125 C. Typical specs at 25 C Parameter Symbol Test Condition Min Typ Max Unit VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 1.95 2.24 2.375 V VDD Undervoltage Threshold VDDUV- VDD1, VDD2 falling 1.88 2.16 2.325 V VDD Undervoltage Hysteresis VDDHYS 50 70 95 mV 35 50 -- kV/s tSD -- 3.0 -- s tSTART -- 15 40 s VI = VDD or 0 V Common Mode Transient Immunity CMTI Shut Down Time from UVLO Start-up Time1 VCM = 1500 V (see Figure 5.3 Common Mode Transient Immunity Test Circuit on page 15) Note: 1. Start-up time is the time period from the application of power to valid data at the output. 1.4 V Typical Input tPLH 1.4 V Typical Output tPHL 90% 90% 10% 10% tr tf Figure 5.1. Propagation Delay Timing (Non-I2C Channels) silabs.com | Building a more connected world. Rev. 1.7 | 14 Si860x Data Sheet Electrical Specifications 5.1 Test Circuits Figure 5.2 Simplified Timing Test Diagram on page 15 depicts the timing test diagram; Figure 5.3 Common Mode Transient Immunity Test Circuit on page 15 depicts the CMTI test diagram. AVDD R1 R1 NC ASDA BSDA ADIN BDOUT ASCL C1 NC C3 R2 NC ADOUT C1 BVDD R2 BDIN BSCL NC AGND BGND Si8605 C2 C3 C2 Figure 5.2. Simplified Timing Test Diagram 3 to 5 V Supply Si86xx Input Signal Switch 3 to 5 V Isolated Supply AVDD BVDD INPUT OUTPUT Oscilloscope AGND BGND Isolated Ground Input High Voltage Differential Probe Output Vcm Surge Output High Voltage Surge Generator Figure 5.3. Common Mode Transient Immunity Test Circuit Table 5.6. Regulatory Information1 CSA The Si860x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873. 61010-1: Up to 600 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage. 60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. 60601-1: Up to 125 VRMS reinforced insulation working voltage; up to 380 VRMS basic insulation working voltage. silabs.com | Building a more connected world. Rev. 1.7 | 15 Si860x Data Sheet Electrical Specifications VDE The Si860x is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001. 60747-5-2: Up to 1200 Vpeak for basic insulation working voltage. 60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. UL The Si860x is certified under UL1577 component recognition program. For more details, see File E257455. Rated up to 5000 VRMS isolation voltage for basic protection. CQC The Si860x is certified under GB4943.1-2011. For more details, see certificates CQC13001096110 and CQC13001096239. Rated up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. Note: 1. Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec. Regulatory Certifications apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1 sec. Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec. For more information, see 1. Ordering Guide. Table 5.7. Insulation and Safety-Related Specifications Parameter Symbol Test Condition Value Unit NB SOIC-8 NB SOIC-16 WB SOIC-16 Nominal Air Gap (Clearance) L(1O1) 4.9 4.9 8.0 mm Nominal External Tracking (Creepage)1 L(1O2) 4.01 4.01 8.0 mm 0.014 0.014 0.014 mm 600 600 600 VRMS Minimum Internal Gap (Internal Clearance) Tracking Resistance (Proof Tracking Index) PTI Erosion Depth ED 0.040 0.019 0.019 mm Resistance (Input-Output)2 RIO 1012 1012 1012 Capacitance (Input-Output)2 CIO f = 1 z 1.0 2.0 2.0 pF CI on-2C Channel 4.0 4.0 4.0 pF I2C Channel 10 10 10 pF Input Capacitance3 IEC60112 Note: 1. VDE certifies the clearance and creepage limits as 4.7 mm minimum for the NB SOIC-8 and SOIC-16 packages and 8.5 mm minimum for the WB SOIC-16 package. UL does not impose a clearance and creepage minimum for component level certifications. CSA certifies the clearance and creepage limits as 3.9 mm minimum for the NB SOIC-8 and SOIC-16 packages and 7.6 mm minimum for the WB SOIC-16 package. 2. To determine resistance and capacitance, the Si860x, SO-16, is converted into a 2-terminal device. Pins 1-8 (1-4, SO-8) are shorted together to form the first terminal and pins 9-16 (5-8, SO-8) are shorted together to form the second terminal. The parameters are then measured between these two terminals. 3. Measured from input pin to ground. silabs.com | Building a more connected world. Rev. 1.7 | 16 Si860x Data Sheet Electrical Specifications Table 5.8. IEC 60664-1 (VDE 0844 Part 2) Ratings Parameter Test Conditions NB SOIC-8 SOIC-16 WB SOIC-16 Material Group I I Rated Mains Voltages < 150 VRMS I-IV I-IV Rated Mains Voltages < 300 VRMS I-III I-IV Rated Mains Voltages < 400 VRMS I-II I-III Rated Mains Voltages < 600 VRMS I-II I-III Basic Isolation Group Installation Classification Specification Table 5.9. IEC 60747-5-2 Insulation Characteristics for Si86xxxx1 Parameter Symbol Maximum Working Insulation Voltage Input to Output Test Voltage Transient Overvoltage Test Condition Characteristic VIORM WB SOIC-16 NB SOIC-8 SOIC-16 1200 630 Vpeak VPR Method b1 (VIORM x 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC) 2250 1182 Vpeak VIOTM t = 60 sec 6000 6000 Vpeak 2 2 >109 >109 Pollution Degree (DIN VDE 0110, Table 1) Insulation Resistance at TS, VIO = 500 V Unit RS Note: 1. Maintenance of the safety data is ensured by protective circuits. The Si86xxxx provides a climate classification of 40/125/21. Table 5.10. IEC Safety Limiting Values1 Parameter Symbol Case Temperature TS Safety Input Current S Test Condition JA = 100 C/W (WB SOIC-16), 105 C/W (NB SOIC-16), 140 C/W (NB SOIC-8) AVDD, BVDD = 5.5 V, TJ = 150 C, NB SOIC-8 NB SOIC-16 WB SOIC-16 Unit 150 150 150 C 160 210 220 mA 220 275 275 mW TA = 25 C Device Power Dissipation2 PD silabs.com | Building a more connected world. Rev. 1.7 | 17 Si860x Data Sheet Electrical Specifications Parameter Symbol Test Condition NB SOIC-8 NB SOIC-16 WB SOIC-16 Unit Note: 1. Maximum value allowed in the event of a failure. Refer to the thermal derating curve in the three figures below. 2. The Si86xx is tested with AVDD, BVDD = 5.5 V; TJ = 150 C; C1, C2 = 0.1 F; C3 = 15 pF; R1, R2 = 3 k; input 1 MHz 50% duty cycle square wave. Table 5.11. Thermal Characteristics Parameter IC Junction-to-Air Thermal Resistance Symbol NB SOIC-8 NB SOIC-16 WB SOIC-16 Unit JA 140 105 100 C/W Safety-Limiting Values (mA) 400 300 270 AVDD, BVDD = 3.6 V 200 160 AVDD, BVDD = 5.5 V 100 0 0 50 100 150 Case Temperature (C) 200 Figure 5.4. NB SOIC-8 Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 Safety-Limiting Current (mA) 500 400 350 300 AVDD , BVDD = 3.6 V 210 200 AVDD , BVDD = 5.5 V 100 0 0 50 100 Temperature (C) 150 200 Figure 5.5. NB SOIC-16 Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 silabs.com | Building a more connected world. Rev. 1.7 | 18 Si860x Data Sheet Electrical Specifications Safety-Limiting Current (mA) 500 400 350 300 AVDD , BVDD = 3.6 V 220 200 AVDD , BVDD = 5.5 V 100 0 0 50 100 Temperature (C) 150 200 Figure 5.6. WB SOIC-16 Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 Table 5.12. Absolute Maximum Ratings1 Parameter Symbol Min Max Unit TSTG -65 150 C Ambient Temperature Under Bias TA -40 125 C Junction Temperature TJ -- 150 C VDD -0.5 7.0 V Input Voltage VI -0.5 VDD + 0.5 V Output Voltage VO -0.5 VDD + 0.5 V Output Current Drive (non-I2C channels) IO -- 10 mA Side A output current drive (I2C channels) IO -- 15 mA Side B output current drive (I2C channels) IO -- 75 mA Lead Solder Temperature (10 s) -- 260 C Maximum Isolation (Input to Output) (1 sec) NB SOIC-8, SOIC-16 -- 4500 VRMS Maximum Isolation (Input to Output) (1 sec) WB SOIC-16 -- 6500 VRMS Storage Temperature 2 Supply Voltage Note: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to conditions as specified in the operational sections of this data sheet. 2. VDE certifies storage temperature from -40 to 150 C. silabs.com | Building a more connected world. Rev. 1.7 | 19 Si860x Data Sheet Pin Descriptions 6. Pin Descriptions 6.1 Si8600/02 SOIC-8 Package AVDD 1 8 BVDD AVDD 1 8 BVDD ASDA 2 Bidirectional Isolator Channel 7 BSDA ASDA 2 Bidirectional Isolator Channel 7 BSDA ASCL 3 Bidirectional Isolator Channel 6 BSCL ASCL 3 Unidirectional Isolator Channel 6 BSCL 5 BGND AGND 4 AGND 4 Si8600 Si8602 5 BGND Table 6.1. Si8600/02 in SOIC-8 Package Pin Name Description 1 AVDD Side A power supply terminal; connect to a source of 3.0 to 5.5 V. 2 ASDA Side A data (open drain) input or output. 3 ASCL Side A clock input or output. Open drain I/O for Si8600. Standard CMOS input for Si8602. 4 AGND Side A ground terminal. 5 BGND Side B ground terminal. 6 BSCL Side B clock input or output. Open drain I/O for Si8600. Push-pull output for Si8602. 7 BSDA Side B data (open drain) input or output. 8 BVDD Side B power supply terminal; connect to a source of 3.0 to 5.5 V. silabs.com | Building a more connected world. Rev. 1.7 | 20 Si860x Data Sheet Pin Descriptions 6.2 Si8600/02 SOIC-16 Package 16 BGND AGND 1 NC 2 15 NC AVDD 3 14 BVDD NC 4 13 NC NC 2 12 BSDA ASDA 5 ASCL 6 Bidirectional Isolator Channel 11 BSCL ASCL 6 NC 8 Si8600 9 BGND 14 BVDD NC 4 ASDA 5 10 NC 15 NC AVDD 3 Bidirectional Isolator Channel AGND 7 16 BGND AGND 1 13 NC Bidirectional Isolator Channel Unidirectional Isolator Channel AGND 7 NC 8 12 BSDA 11 BSCL 10 NC Si8602 9 BGND Table 6.2. Si8600/02 in Narrow and Wide-Body SOIC-16 Packages Pin Name Description 1 AGND Side A Ground Terminal. 2 NC 3 AVDD 4 NC 5 ASDA Side A data open drain input or output. 6 ASCL Side A data open drain input or output. 7 AGND Side A Ground Terminal. 8 NC 9 BGND 10 NC 11 BSCL Side B data open drain input or output. 12 BSDA Side B data open drain input or output. 13 NC 14 BVDD 15 NC 16 BGND silabs.com | Building a more connected world. No connection. Side A power supply terminal. Connect to a source of 3.0 to 5.5 V. No connection. No connection. Side B Ground Terminal. No connection. No connection. Side B power supply terminal. Connect to a source of 3.0 to 5.5 V. No connection. Side B Ground Terminal. Rev. 1.7 | 21 Si860x Data Sheet Pin Descriptions 6.3 Si8605/06 SOIC-16 Package 16 BVDD AVDD 1 NC 2 ASDA 3 ADIN 4 ADOUT 5 ASCL 6 15 NC Bidirectional Isolator Channel Unidirectional Isolator Channel Unidirectional Isolator Channel Bidirectional Isolator Channel NC 7 AGND 8 14 BSDA Si8605 NC 2 ASDA 3 13 BDOUT ADIN1 4 12 BDIN ADIN2 5 11 BSCL ASCL 6 10 NC 9 BGND 16 BVDD AVDD 1 15 NC Bidirectional Isolator Channel Unidirectional Isolator Channel Unidirectional Isolator Channel Bidirectional Isolator Channel NC 7 14 BSDA 13 BDOUT1 12 BDOUT2 11 BSCL 10 NC AGND 8 Si8606 9 BGND Table 6.3. Si8605/06 in Narrow and Wide-Body SOIC-16 Packages Pin Name Description 1 AVDD Side A power supply terminal. Connect to a source of 3.0 to 5.5 V. 2 NC 3 ASDA 4 ADIN/ADIN1 5 ADOUT/ADIN2 No connection. Side A data (open drain) input or output. Side A standard CMOS digital input (non I2C). Side A digital input/output (non I2C) Standard CMOS digital input for Si8606. Push-Pull output for Si8605. 6 ASCL Side A clock input or output. Open drain I/O for Si8605/06. 7 NC No connection. 8 AGND Side A Ground Terminal. 9 BGND Side B Ground Terminal. 10 NC 11 BSCL No connection. Side B clock input or output. Open drain I/O for Si8605/06. 12 BDIN/BDOUT2 Side B digital input/output (non I2C) Standard CMOS digital input for Si8605. Push-Pull output for Si8606. 13 BDOUT/BDOUT1 14 BSDA 15 NC 16 BVDD silabs.com | Building a more connected world. Side B digital push-pull output (non I2C). Side B data open drain input or output. No connection. Side B power supply terminal. Connect to a source of 3.0 to 5.5 V. Rev. 1.7 | 22 Si860x Data Sheet Package Outline: 16-Pin Wide Body SOIC 7. Package Outline: 16-Pin Wide Body SOIC Figure 7.1 16-Pin Wide Body SOIC on page 23 illustrates the package details for the Si860x Digital Isolator. Table 7.1 Package Diagram Dimensions on page 23 lists the values for the dimensions shown in the illustration. Figure 7.1. 16-Pin Wide Body SOIC Table 7.1. Package Diagram Dimensions Dimension Min Max A -- 2.65 A1 0.10 0.30 A2 2.05 -- b 0.31 0.51 c 0.20 0.33 D 10.30 BSC E 10.30 BSC E1 7.50 BSC e 1.27 BSC L 0.40 1.27 h 0.25 0.75 0 8 aaa -- 0.10 bbb -- 0.33 ccc -- 0.10 ddd -- 0.25 eee -- 0.10 fff -- 0.20 silabs.com | Building a more connected world. Rev. 1.7 | 23 Si860x Data Sheet Package Outline: 16-Pin Wide Body SOIC Dimension Min Max Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC Outline MS-013, Variation AA. 4. Recommended reflow profile per JEDEC J-STD-020C specification for small body, lead-free components. silabs.com | Building a more connected world. Rev. 1.7 | 24 Si860x Data Sheet Land Pattern: 16-Pin Wide-Body SOIC 8. Land Pattern: 16-Pin Wide-Body SOIC Figure 8.1 16-Pin SOIC Land Pattern on page 25 illustrates the recommended land pattern details for the Si860x in a 16-pin widebody SOIC. Table 8.1 16-Pin Wide Body SOIC Land Pattern Dimensions on page 25 lists the values for the dimensions shown in the illustration. Figure 8.1. 16-Pin SOIC Land Pattern Table 8.1. 16-Pin Wide Body SOIC Land Pattern Dimensions Dimension Feature (mm) C1 Pad Column Spacing 9.40 E Pad Row Pitch 1.27 X1 Pad Width 0.60 Y1 Pad Length 1.90 Note: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. silabs.com | Building a more connected world. Rev. 1.7 | 25 Si860x Data Sheet Package Outline: 8-Pin Narrow Body SOIC 9. Package Outline: 8-Pin Narrow Body SOIC Figure 9.1 8-pin Small Outline Integrated Circuit (SOIC) Package on page 26 illustrates the package details for the Si860x in an 8-pin SOIC (SO-8). Table 9.1 Package Diagram Dimensions on page 26 lists the values for the dimensions shown in the illustration. Figure 9.1. 8-pin Small Outline Integrated Circuit (SOIC) Package Table 9.1. Package Diagram Dimensions Symbol Millimeters Min Max A 1.35 1.75 A1 0.10 0.25 A2 1.40 REF 1.55 REF B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 BSC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 0 8 silabs.com | Building a more connected world. Rev. 1.7 | 26 Si860x Data Sheet Land Pattern: 8-Pin Narrow Body SOIC 10. Land Pattern: 8-Pin Narrow Body SOIC Figure 10.1 PCB Land Pattern: 8-Pin Narrow Body SOIC on page 27 illustrates the recommended land pattern details for the Si860x in an 8-pin narrow-body SOIC. Table 10.1 PCM Land Pattern Dimensions (8-Pin Narrow Body SOIC) on page 27 lists the values for the dimensions shown in the illustration. Figure 10.1. PCB Land Pattern: 8-Pin Narrow Body SOIC Table 10.1. PCM Land Pattern Dimensions (8-Pin Narrow Body SOIC) Dimension Feature (mm) C1 Pad Column Spacing 5.40 E Pad Row Pitch 1.27 X1 Pad Width 0.60 Y1 Pad Length 1.55 Note: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8N for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. silabs.com | Building a more connected world. Rev. 1.7 | 27 Si860x Data Sheet Package Outline: 16-Pin Narrow Body SOIC 11. Package Outline: 16-Pin Narrow Body SOIC Figure 11.1 16-pin Small Outline Integrated Circuit (SOIC) Package on page 28 illustrates the package details for the Si860x in a 16pin narrow-body SOIC (SO-16). Table 11.1 Package Diagram Dimensions on page 28 lists the values for the dimensions shown in the illustration. Figure 11.1. 16-pin Small Outline Integrated Circuit (SOIC) Package Table 11.1. Package Diagram Dimensions Dimension Min Max A -- 1.75 A1 0.10 0.25 A2 1.25 -- b 0.31 0.51 c 0.17 0.25 D 9.90 BSC E 6.00 BSC E1 3.90 BSC e 1.27 BSC L 0.40 L2 1.27 0.25 BSC h 0.25 0.50 0 8 aaa 0.10 bbb 0.20 ccc 0.10 silabs.com | Building a more connected world. Rev. 1.7 | 28 Si860x Data Sheet Package Outline: 16-Pin Narrow Body SOIC Dimension ddd Min Max 0.25 Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. silabs.com | Building a more connected world. Rev. 1.7 | 29 Si860x Data Sheet Land Pattern: 16-Pin Narrow Body SOIC 12. Land Pattern: 16-Pin Narrow Body SOIC Figure 12.1 16-Pin Narrow Body SOIC PCB Land Pattern on page 30 illustrates the recommended land pattern details for the Si860x in a 16-pin narrow-body SOIC. Table 12.1 16-Pin Narrow Body SOIC Land Pattern Dimensions on page 30 lists the values for the dimensions shown in the illustration. Figure 12.1. 16-Pin Narrow Body SOIC PCB Land Pattern Table 12.1. 16-Pin Narrow Body SOIC Land Pattern Dimensions Dimension Feature (mm) C1 Pad Column Spacing 5.40 E Pad Row Pitch 1.27 X1 Pad Width 0.60 Y1 Pad Length 1.55 Note: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. silabs.com | Building a more connected world. Rev. 1.7 | 30 Si860x Data Sheet Si860x Top Markings 13. Si860x Top Markings 13.1 Top Marking: 16-Pin Wide Body SOIC Si86XYSV YYWWRTTTTT e4 TW Figure 13.1. 16-Pin Wide Body SOIC Top Marking Table 13.1. 16-Pin Wide Body SOIC Top Marking Explanation Line 1 Marking: Base Part Number Si86 = Isolator product series Ordering Options XY = Channel Configuration (See Ordering Guide for more in- 05 = Bidirectional SCL, SDA; 1- forward and formation). 1-reverse unidirectional channel 06 = Bidirectional SCL, SDA; 2- forward unidirectional channels S = Speed Grade A = 1.7 Mbps V = Isolation rating A = 1 kV; B = 2.5 kV; C = 3.75 kV; D = 5.0 kV Line 2 Marking: YY = Year WW = Workweek RTTTTT = Mfg Code Assigned by assembly subcontractor. Corresponds to the year and workweek of the mold date. Manufacturing code from assembly house "R" indicates revision Line 3 Marking: Circle = 1.7 mm Diameter "e4" Pb-Free Symbol (Center-Justified) Country of Origin ISO Code Abbreviation silabs.com | Building a more connected world. TW = Taiwan Rev. 1.7 | 31 Si860x Data Sheet Si860x Top Markings 13.2 Top Marking: 8-Pin Narrow Body SOIC Si86XYSV YYWWRF e3 AIXX Figure 13.2. 8-Pin Narrow Body SOIC Top Marking Table 13.2. 8-Pin Narrow Body SOIC Top Marking Explanation Line 1 Marking: Base Part Number Si86 = Isolator I2C Product Series: Ordering Options XY = Channel Configuration (See Ordering Guide for more infor- 00 = Bidirectional SCL and SDA channels mation). 02 = Bidirectional SDA channel; Unidirectional SCL channel S = Speed Grade A = 1.7 Mbps V = Isolation rating A = 1 kV; B = 2.5 kV; C = 3.75 kV Line 2 Marking: YY = Year WW = Work week R = Product Rev F = Wafer Fab Line 3 Marking: Circle = 1.1 mm Diameter Assigned by assembly contractor. Corresponds to the year and work week of the mold date. First two characters of the manufacturing code from Assembly. "e3" Pb-Free Symbol Left-Justified A = Assembly Site I = Internal Code Last four characters of the manufacturing code from assembly. XX = Serial Lot Number silabs.com | Building a more connected world. Rev. 1.7 | 32 Si860x Data Sheet Si860x Top Markings 13.3 Top Marking: 16-Pin Narrow Body SOIC Figure 13.3. 16-Pin Narrow Body SOIC Top Marking Table 13.3. 16-Pin Narrow Body SOIC Top Marking Explanation Line 1 Marking: Base Part Number Si86 = Isolator product series Ordering Options XY = Channel Configuration 05 = Bidirectional SCL, SDA; 1- forward and 1-reverse unidirectional channel 06 = Bidirectional SCL, SDA; 2- forward unidirectional channels S = Speed Grade A = 1.7 Mbps V = Isolation rating A = 1 kV; B = 2.5 kV; C = 3.75 kV Line 2 Marking: Circle = 1.2 mm Diameter "e3" Pb-Free Symbol YY = Year Assigned by the Assembly House. Corresponds to the year and work week of the mold date. WW = Work Week TTTTTT = Mfg Code silabs.com | Building a more connected world. Manufacturing code from assembly house Rev. 1.7 | 33 Si860x Data Sheet Document Change List 14. Document Change List 14.1 Revision 0.1 * Initial release. 14.2 Revision 0.2 * * * * * * * * * * Si8601 replaced by Si8602 throughout. Added chip graphics. Moved Table 12. Updated Table 3, "Si8600/02/05/06 Electrical Characteristics for Bidirectional I2C Channels1". Updated Table 7, "Insulation and Safety-Related Specifications". Updated Table 9, "IEC 60747-5-2 Insulation Characteristics for Si86xxxx*," on page 12. Moved "3. Typical Application Overview" to page 16. Moved "Typical Performance Characteristics" to page 23. Updated "5.Pin Descriptions" on page 24. Updated "6.Ordering Guide" on page 27. 14.3 Revision 0.3 * * * * * * * * Added chip graphics on page 1. Moved Tables 1 and 2 to page 4. Updated Table 7, "Insulation and Safety-Related Specifications". Updated Table 9, "IEC 60747-5-2 Insulation Characteristics for Si86xxxx*" . Moved Table 13 to page 17. Moved Table 14 to page 21. Updated "Pin Descriptions" . Updated "Ordering Guide" . 14.4 Revision 1.1 * Updated Figures 12 and 13. * Updated Pin 7 AGND connection. * Updated "Ordering Guide" to include MSL2A. 14.5 Revision 1.2 * Updated Table 12. * Added junction temperature spec. * Updated "Supply Bypass" . * Updated "Ordering Guide". * Removed Rev A devices. * Updated "Package Outline: 16-Pin Wide Body SOIC". * Updated Top Marks. * Added revision description. 14.6 Revision 1.3 * * * * * * Added Figure 3, "Common Mode Transient Immunity Test Circuit". Added references to CQC throughout. Added references to 2.5 kVRMS devices throughout. Removed Fail-safe operating mode throughout. Updated "Ordering Guide". Updated "Si860x Top Marking (16-Pin Wide Body SOIC)". silabs.com | Building a more connected world. Rev. 1.7 | 34 Si860x Data Sheet Document Change List 14.7 Revision 1.4 * * * * * Updated Table 6. Added CQC certificate numbers. Corrected Device Power Dissipation units in Table 10 on page 12. Updated "Ordering Guide". Removed references to moisture sensitivity levels. Removed Note 2. 14.8 Revision 1.5 July 2016 * Converted data sheet to DITA. 14.9 Revision 1.6 February 2017 * Corrected Figure 13.3. 14.10 Revision 1.7 April 18, 2017 * Formatted tables in 5. Electrical Specifications. silabs.com | Building a more connected world. Rev. 1.7 | 35 Smart. Connected. Energy-Friendly. Products Quality Support and Community www.silabs.com/products www.silabs.com/quality community.silabs.com Disclaimer Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. 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