VIPER20DIP-E - STMicroelectronics

Rev 1

September 2005 1/31

VIPer20-E

VIPer20DIP-E

SMPS PRIMARY I.C.

General Features

■ADJUSTABLE SWITCHING FREQUENCY UP

TO 200 kHz

■CURRENT MODE CONTROL

■SOFT START AND SHUTDOWN CONTROL

■AUTOMATIC BURST MODE OPERATION IN

STAND - BY CONDITION ABLE TO M EET

“BLUE ANGEL” NORM (<1w TOTAL POWER

CONSUMPTION)

■INTERNALLY TRIMMED ZE NER

REFERENCE

■UNDERVOLTAGE LOCK-OUT WITH

HYSTERESIS

■INTEGRATED START-UP SUPPLY

■OVER-TEMPERATURE PROTECTION

■LOW STAND-BY CURRENT

■ADJUSTABLE CURRENT LIMITAT ION

Blo ck Diag r am

Description

VIPer20-E/DIP-E, made using VIPower M0

Technology, combines on the same silicon chip a

state-of-the-art PWM circuit together with an

optimized, high voltage, Vertical Power MOSFET

(620V/ 0.5A).

Typical applications cover offline power supplies

with a secondary power capability of 10W in wide

range condition and 20W in single range or with

doubler configuration. It is compatible from both

primary or secondary regulation loop despite

using around 50% less components when

compared with a discrete solution. Burst mode

operation is an additional feature of this device,

offering the ability to operate in stand-by mode

without extra components.

Type VDSS InRDS(on)

VIPer20-E/DIP-E 620V 0.5A 16Ω

PENTAWATT HV

PENTAWATT HV (022Y)

DIP-8

www.st.com

VDD

OSC

COMP

DRAIN

SOURCE

13 V

UVLO

LOGIC

SECURITY

LATCH PWM

LATCH

FFFF

R/S SQ

R1R2 R3 Q

OSCILLATOR

OVERTEMP.

DETECTOR

ERROR

AMPLIFIER

0.5 V +

1.7

µs

delay

250 ns

Blanking

CURRENT

AMPLIFIER

ON/OFF

0.5V

6 V/ A

4.5 V

FC00491

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Contents

1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 Drain Pin (Integrated Power MOSFET Drain): . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2 Source Pin: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.3 VDD Pin (Power Supply): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.4 Compensation Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3. 5 OSC Pin (O s c illat or Freque nc y ): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Typical Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5 Operation Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.1 Current M ode Topology: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

5.2 Stand-by Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

5.3 High Voltage Start-up Current Suorce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.4 Transconductance Erro r Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.5 External Clock Synchronization: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.6 Primary Peak Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.7 Over-Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.8 Operation Pictures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

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6 Electrical Over Stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.1 Electrical Over Stress Ruggedness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.1 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9 Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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1 E lectrical Data VIPer20-E/DIP-E

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1 Electrical Data

1.1 Maximum Rating

Table 1. Absolute Maximum Rating

Symbol Parameter Value Unit

VDS Continuous Drain-Source Voltage (TJ = 25 to 125°C) –0.3 to 620 V

IDMaximum Current Internally limited A

VDD Supply Voltage 0 to 15 V

VOSC Voltage Range Input 0 to VDD V

VCOMP Voltage Range Input 0 to 5 V

ICOMP Maximum Continuous Current ±2 mA

VESD Electrostatic Discharge (R = 1.5kΩ; C = 100pF) 4000 V

ID(AR) Aval anche Drain-Source Current, Repet it ive or Not Repetitive

(TC = 10 0°C; Pulse width li mit ed by TJ max; δ < 1 % ) 0.5 A

PTOT Power Dissipation at TC= 25ºC 57 W

TJJunction Oper ating Temp erature Internally limite d °C

TSTG St orage Temperature -65 to 150 °C

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VIPer20-E/DIP-E 1 Ele c tri c al Data

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1.2 Electrical Characteristics

TJ = 25°C; VDD = 13V, unless otherwise specified

Tabl e 2. Power Section

(1) On Inductive Load, Clamped.

Tabl e 3. Supply Section

Tabl e 4. Oscillator Section

Symbol Parameter Test Conditions Min Typ Max Unit

BVDS Drain-Source Voltage ID = 1mA; VCOMP = 0V 620 V

IDSS Of f-State Drain

Current VCOMP = 0V; Tj = 125°C

VDS = 620V 1.0 mA

RDS(on) Static Drain-Source

On Resistance ID = 0.4A

ID = 0.4A; TJ= 100°C 13.5 16

Ω

tfFa ll Time ID = 0.2A; VIN =300V (1)Figure 7 100 ns

tr Rise Time ID = 0.4A; VIN = 300V (1)Figure 7 50 ns

Coss Output Capacitance VDS = 25V 90 pF

Symbol Parameter Test Conditions Min Typ Max Unit

IDDch Start-Up Charging Current VDD = 5 V; V DS = 35V

(see Fig ure 6)(see Fig ure 11) -2 mA

IDD0 Operati ng Supply Current VDD = 12V; FSW = 0kHz

(see Fig ure 6) 12 16 mA

IDD1 Operati ng Supply Current VDD = 12V; Fsw = 100kHz 13 mA

IDD2 Operati ng Supply Current VDD = 12V; Fsw = 200kHz 14 mA

VDDoff Undervoltage Shutdown (see Fig ure 6) 7.5 8 9 V

VDDon Undervoltage Reset (see Fig ure 6) 11 12 V

VDDhyst Hys ter esis Start - up (see Fig ure 6) 2.4 3 V

Symbol Parameter Test Conditions‘ Min Typ Max Unit

FSW Oscillator Frequency Total

Variation RT=8.2KΩ; CT=2.4nF

VDD= 9 to 1 5 V;

with RT± 1%; CT± 5%

(see Fig ure 10)(see Fi gure 14)

90 100 110 KHz

VOSCIH Oscillator Peak Voltage 7.1 V

VOSCIL Oscillator Valley Voltage 3.7 V

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1 E lectrical Data VIPer20-E/DIP-E

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Table 5. Error Amplifier Section

Table 6. PWM Com parator Section

Tabl e 7. Shutd own and Ov ertempe rature Section

Symbol Parameter Test Conditions‘ Min Typ Max Unit

VDDREG VDD Regulation Point ICOMP=0m A (s ee Figure 5) 12.6 13 13.4 V

∆VDDreg Total Vari at io n TJ = 0 to 100°C 2 %

GBW Unity Gain Bandwidth From Input =VDD to

Output = VCOMP

COMP pi n is open

(see Figure 15)

150 KHz

AVOL Open Loop Voltage Gain COMP pin is open

(see Figure 15) 45 52 dB

GmDC Transconductance VCOMP=2.5V(see Figure 5) 1.1 1.5 1.9 mA/V

VCOMPLO Output Low Level ICOMP=- 400µA; VDD=14V 0.2 V

VCOMPHI Output High Level ICOMP=400µ A; VDD=12V 4.5 V

ICOMPLO Output Low Current Capability VCOMP=2.5V; VDD=14V -600 µA

ICOMPHI Output High Current

Capability VCOMP=2.5V; VDD=12V 600 µA

Symbol Parameter Test Conditions‘ Min Typ Max Unit

HID ∆VCOMP / ∆IDPEAK VCOMP = 1 to 3 V 4.2 6 7.8 V/A

VCOMPoff VCOMP Offset IDPEAK = 10mA 0.5 V

IDpeak Peak Current Li mitation VDD = 12V; COMP pin open 0.5 0.67 0.9 A

tdCurrent Se nse Delay to Turn-

Off ID = 1A 250 ns

tbBlanking Time 250 360 ns

ton(min) Minimum On Ti me 350 1200 ns

Symbol Parameter Test Conditions‘ Min Typ Max Unit

VCOMPth Restart Threshold (see Figure 8) 0.5 V

tDISsu Disable Set Up Time (see Fig ure 8) 1.7 5 µs

Ttsd Thermal Shutdown

Temperature (s ee Figure 8) 140 170 190 °C

Thyst Thermal Shutdown Hysteresis (see Figure 8) 40 °C

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VIPer20-E/DIP-E 2 Thermal Dat a

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2 Thermal Data

Ta ble 8. Thermal data

Symbol Parameter PENTAWATT HV Unit

RthJC Thermal Resistance Juncti on-case Max 1 .9 °C/W

RthJA Thermal Resistance Ambien t-case Max 60 °C/W

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3 P in Description VIPer20-E/DIP-E

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3 Pin Description

3.1 Drain Pin (Int egrated Power MOSFET Drain):

Integrated Power MOSFET drain pin. It provides internal bias current during start-up v ia an

integrated high voltage current source which is switc hed off during normal operation. The

device is able to handle an unclamped current during its normal operation, assuring self

prot ection against voltage s urges, PCB stray inductance, and allowing a snubberless operation

for low output power.

3.2 Source Pin:

Power MOSFET source pin. Primary side circuit common ground connection.

3.3 VDD Pin (Power Supply):

This pin provides two functions :

●It corresponds to the low voltage supply of t he control part of the circuit. If V DD goes below

8V, the start -up current source is activated and the output power MOSFET is switched off

until the VDD voltage reaches 11V. During this phase, the internal current consumption is

reduced, the VDD pin is sourcing a current of about 2mA and the COMP pin is shorted to

ground. After th at, the current source is shut down, and the device trie s to start up by

switching agai n.

●This pin is also c onnect ed to the error amplifier, in order to allow primary as well as

secondary regulation configuration s. In case of primary regulation, an internal 13V

trimmed referenc e voltage is u sed to maintain VDD at 13V. For secondar y regulation, a

voltage between 8.5V and 12.5 V will b e put on VDD pin by transformer design, in order to

stuck the output of the transconductance amplifier to the high state. Th e COMP pin

behave s as a constant current source, and can easily be connected to the output of an

optocoupler. Note that any overvoltage due to regulation loop failure is still detected by the

error amplifier through the VDD voltage, which cannot overpass 13V. Th e outpu t voltage

will be som ewhat higher than the nominal one, but still under control.

3.4 Compensation Pin

This pin provides two functions :

●It is the output of t he error transconductance amplifier, and allows for the connection of a

compens ation network to provide the desired transfer function of the regulation loop. Its

bandwidth can be easily adjusted to the needed value with usual components value. As

stated above, secondary regulation configuration s are also implemented throu gh the

COMP pin.

●When the COMP voltage is go ing below 0.5V, the shut-down of the circuit occurs, with a

zero duty cycle for the power MOSFET. This feature can be used to switch off the

converter, and is automatically activated by the regulation loop (no matter what the

configuration is) to provide a burst mode operation in case of negligible output p ower or

open load c ondition.

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3.5 OSC Pin (Oscillator Frequency):

An Rt-Ct network must be connec ted on that to define the switching frequency. Note that

des pite the connect ion of Rt to VDD, no significant frequency change oc curs for VDD varying

from 8V t o 15V. It provides also a synchronisation capabilit y, when connected to an external

freque ncy source.

Figure 1. Connection Diagrams (Top View)

Figure 2. Current and Voltage Convention

PENTAWATT HV PENTAWATT HV (022Y) DIP-8

OSC

Vdd

OURCE

COMP

DRAI

DRAIN

SC10540

13V

OSC

COMP SOURCE

DRAINVDD

VCOMP

VOSC

VDD VDS

ICOMP

IOSC

IDD ID

FC00020

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4 Typical Cir cuit VIPer20-E/DIP-E

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4 Typical Circuit

Figure 3. Offline Power Supply With Auxiliary Supply Feedback

Figure 4. Offline Power Supply With Optocoupler Feedback

AC I N +Vcc

GND

BR1

TR2

C10

TR1

C9C7

VIPer20

13V

OSC

COMP SOURCE

DRAINVDD

FC00401

C11

AC IN

BR1

TR2

C10

TR1

L2 +Vcc

GND

VIPer20

ISO1 R6

13V

OSC

COMP SOURCE

DRAINVDD

FC00411

C11

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VIPer20-E/DIP-E 5 Op eration Descr iption

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5 Operation Description

5.1 Current Mode Topology:

The curre nt mode control method, like the one integrated in the VIPer20-E, uses two control

loops - an inner current c ontrol loop and an outer loop for voltage control. When the Power

MO SFE T output transistor is o n, the inductor current (primary si de of the transformer) is

moni tored with a SenseFET technique and conv ert ed into a voltage VS proportional to this

current. When VS reaches VCOMP (the amplified output voltage error) the power switch is

swi tched off. Thus, the outer voltage control lo op defi nes the level at which the inner loop

regulat es peak current through the power switch and the primary winding of the transformer.

Excellent open loop D.C. and dynamic line regulation is ensured due to the inherent input

voltage feedforward characteristic of the current mode control. This results in improved line

regulat ion, instantaneous correction to line changes, and better stability for the voltage

regulat ion loop.

Curr ent mode topology also ensures good limitation in case there is a short circuit. During the

first phase the output current increases slowly following the dynamic of the regulation loop.

Then it reache s the maximum limitation current internally set and finally stops because the

powe r supply on VDD is no longer correct. For specific applications the maximum peak current

inte rnally set can be overridden by externally limiting the voltage excursion on the COMP pin.

An integrated blanki ng filter inhibits the PW M com parator output for a short time after the

inte grated Power MOS FET is switched on. This function prevents anomalous or premature

terminat ion of the switching pulse in case there are current spikes caused by primary side

capacitance or secondary side rectifier reverse recovery time.

5.2 Stand-by Mode

Stand-by operation in nearly open load conditions automatically leads to a burst mode

operat ion allow ing voltage regulation on the secondary side. Th e transition from norm al

operat ion to burst mode operation hap pens for a power PSTBY given by :

Where:

LP is the prima ry inductance of the transformer. FSW is the normal switching frequency.

ISTBY is the minimum controllable current, corresponding to the minimum on time that the

dev ice is able to provide in normal operation. This current can be computed as :

tb + td is the sum of the blanking time and of the propagation time of the internal current sense

and comparator, and r epresents roughly the minimum on time of the device. Note: that PSTBY

may be affected by the efficie nc y of the converter at lo w load, and must include the power

drawn on the primary auxiliary voltage.

PSTBY 1

---LPI2STBYFSW=

ISTBY tbtd

+()VIN

-----------------------------=

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5 Op eration Descr iption VIPer20-E/DIP-E

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As soon as the power goes below this limit, the auxiliary secondary voltage starts to increase

abov e the 13V regulation level , forcin g the output voltage of the transconductance amplifier to

low state (VCOMP < VCOMPth). This s ituation leads to the shutdown mode where the power

switch is maintained in the Of f state, resulti ng in missing cycles and zero duty cycle. As soon as

VDD gets back to the regulation level and the VCOMPth threshold is reached, the device

operates again. The above cycle repeats indefinitely, providing a burst mode of which the

effective duty cycle is much lower than the minimum one when in normal operation. The

equivalent switching frequenc y is also lower than t he norm al one, leading to a reduced

consumption on the input main supply lines. This mode of operation allows the VIPer20-E to

meet the new Ge rman "B lue Angel" Norm with less than 1W total power con su mption for the

system when working in stand-by mode. The output voltage remains regulated around the

normal level, wit h a low frequency ri pple corresponding to the burst mode. The amplitude of this

ripple is low, because of the output capa citors and low output current drawn in such

con ditions. The normal operat ion resum es automat ically when the power gets back to higher

levels than PSTBY.

5.3 High Voltage Start-up Curren t Suorce

An integrated high voltage current source provide s a bias current from the DRAIN pin during

the start -up phase. This current is partially absorbed by internal control circuits which are

placed into a standby mode with reduced consumption and also provided to the external

capacitor connec ted to t he VDD pin. As soon as t he volt age on t his pi n reaches the high v oltage

threshold VDDon of the UVLO logic, the device becomes active mode and start s switching. The

start-up current generator is switched off, and the converter should normally provide the

needed c urrent on the VDD pin through t he auxiliary winding of the transformer, as shown on

(see Figure 11).

In case there are abnormal conditions where the auxiliary winding is unable to provide the low

vol tage supply current to the VDD pin (i.e. short circuit on the output of the converter), the

external capacitor discharges to the low threshold voltage VDDoff of the UVLO logic, and the

device goes back to the inactive state where the internal circuits are in standby mode and the

start-up current source is activated. The converter enters a endless start- up cycle, with a start-

up duty cycle defined by t he ratio of charging c urrent towards discharging when the VIPer20-E

tries to start. This rati o is fixed by design to 2A to 15A, which gives a 12 % start-up duty cycle

w hile the power dissipation at start-up is approxima tely 0.6W, for a 230Vrms input vol tage.

This low value start-up duty cycle prevents the application of stress to the ou tput rectifiers as

well as the transformer when a short circuit occurs.

The exter nal capacitor C VDD on the VDD pin must be sized according t o the time needed by the

con verter to start up, when the device starts swit ching. This time tSS depends on many

parameters, amo ng which transforme r desig n, output capacitors, soft start feature, and

compensation network implemented on the COMP pin. The following formula c an be used for

defi ning the minimu m capacitor needed:

where:

IDD is the consumption current on the VDD pin when switching. Refer to specified IDD1 and IDD2

val ues.

tSS is the start up time of the converter when the device begins to switch. Worst case is

generally at full load.

CVDD

IDDtSS

VDDhyst

-------------------->

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VIPer20-E/DIP-E 5 Op eration Descr iption

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VDDhyst is the voltage hysteresis of the UVLO logic (refer to the minimum specified value).

The soft start fe atu re can be implement ed on the COMP pin throu gh a simple capacitor which

w ill b e a ls o u s ed as the co mp ens ation ne two rk . In thi s ca s e, the re g ula t io n loop ba n dw id th is

rather low, becaus e of the large value of this cap acitor. In case a large regulation loop

bandwidt h is mandatory, the schemat ics of (see Figure 17) can be used. It mixes a high

performanc e comp ens ation netw ork together with a separate high value soft start capac itor.

Both s oft start time and regulation loop bandwidth ca n be adjuste d separately.

If the device is intention ally shut down by tying the COMP pin to ground, the device is also

performing start-up cycles, and the VDD voltage is oscillating between VDDon and VDDoff.

This voltage c an be used for supplying external functions, provided that their consumption does

not exc eed 0.5mA. (see Figure 18) shows a typical application of this function, with a latched

shu tdown. Once the "Shutdown" signal has been ac tivated, the device rem ains in the Off state

unti l the input voltage is removed.

5.4 Transconductance Error Amplifier

The VIPer20-E includes a transconducta nc e error amplifier. Transconductance Gm is the

cha nge in output current (ICOMP) versus change in input voltage (VDD). Thus:

The output impedance ZCOMP at the output of this amplifier (COMP pin) can be defined as:

This last equ ation sho ws that the open loop gai n AVOL can be related to Gm and ZCOMP:

AVOL = Gm x ZCOMP

where Gm value for VIPer20-E is 1.5 mA/V typically.

Gm is def ined by spec ificatio n, but ZCOMP and therefore AVOL are subject to large to lerances.

An impedance Z can be connected betw een the COMP pin and ground in order to define the

transf er function F of the e rror amplifier more accurately, according to the following equation

(very similar to the one above):

F(S) = Gm x Z(S)

The error amplifier frequency response is reported in Figure 10. for different values of a simple

resistance connected on the COMP pin. The unloaded transconductance error amplifier shows

an internal ZCOMP of about 330KΩ. More complex impedance can be connected on the COMP

pin to achieve different compensation level. A capacitor will provide an integrator function, thus

eliminat ing the DC static error, and a resistance in series leads to a flat gain at hi gher

frequency, ins uring a correct phas e margin. This configur at ion is illustrat ed in Figure 20

As shown in Figure 19 an additio nal noise filtering capacitor of 2.2nF is generally needed to

avo id any high freque ncy interference.

Is also possible to implement a slope compensation when working in continuous mode with

duty cycle higher than 50%. Figure 21 shows such a configuration. Note: R1 and C2 build the

classical compensation network, and Q1 is injecting the slope compensation with the correct

polarity from the oscillator sawtooth.

∂lCOMP

∂VDD

-------------------=

ZCOMP ∂VCOMP

∂ICOMP

---------------------1

--------∂VCOMP

∂VDD

-------------------------×==

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5 Op eration Descr iption VIPer20-E/DIP-E

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5.5 External Clock Synchronization:

The OS C pin provides a synchroni satio n capability when connected to an exte rnal frequ ency

source. Figure 21 shows one possible schematic to be adapted, depending the specific needs.

If the proposed sch ema tic is used, the pulse duration must be kept at a low va lue (500ns is

sufficient) for minimizing consumption. The optocoupler must be able to provide 20mA through

the optot rans istor.

5.6 Primary Peak Current Limitation

The primary IDPEAK current and, consequentl y, the output power can be limited using the

simpl e circuit shown in Figure 22 . The circuit based on Q1, R1 and R2 clam ps the voltage on

the COMP pin in order to limit the primary peak current of the device to a value:

where:

The sugges t ed value for R1+R2 is in the range of 220KΩ.

5.7 Over-Temperature Protection

Ov er-temperature prote ction is based on chip temperature sensing. The minim um junction

temperat ure at which over-temperature c ut-out occurs is 140ºC, while the typical value is

170ºC. The device is automatically restarted when the junction tempe rature decreases to the

restart temperature threshold that is typically 40ºC below the shutdown value (see Figure 13)

IDPEAK VCOMP 0.5–

HID

--------------------------------=

VCOMP 0.6 R1R2

-------------------×=

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5.8 Operation Pictures

Figure 5. VDD Regul ation Poin t Fi gur e 6 . Undervoltage Lockout

Fi gur e 7. Tr ansi t ion Time Fi gur e 8 . S hutdo wn Action

Figure 9. Brea kdo wn Voltage vs. Tem per ature Figure 10. Typica l Freque ncy Variation

ICOMP

ICOMPHI

COMPLO VDDreg

Slope =

Gm in mA/V

FC00150

VDDon

DDch

IDD0

VDDoff

VDS= 35 V

Fsw = 0

IDD

VDDhyst

FC00170

tf tr

10% Ipe ak

10% V D

90% V D

FC00160

VCOMP

VOSC

tDISsu

ENABLE DISABLEENABLE

COMPth

FC0006

Temperature (°C)

FC00180

0 20406080100120

0.95

1.05

1.1

1.15

BVDSS

(

Normalized)

Temperat ure (°C)

0 20406080100120

140

-5

-4

-3

-2

-1

1FC00190

(

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5 Op erati on D escr iption VIPer20-E/DIP-E

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Figure 11. Behavio ur of the high voltage curr ent sou rce at star t-up

Figure 12. Start-Up W aveforms

Ref.

UNDERVOLTAGE

LOCK OUT LOGIC

15 mA1 mA

3 mA

2 mA

15 mA

VDD DRAIN

SOURCE

VIPer20

Auxiliary primary

winding

VDD

DDoff

VDDon

Start up duty cycle ~ 12%

CVDD

FC00101

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Figure 13. Over- temperature Protection

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SC 101 91

tsd

-T

h yst

ts c

dd on

dd off

com p

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Figure 14. Oscillator

OSC

VDD

~360Ω

CLK

FC00050

40kHz

15nF

22nF

Forbidden are a

Forbidden area

Ct(nF) = Fsw(kHz)

880

1 2 3 5 10 20 30 50

100

200

300

500

1,000

Rt (kΩ)

Frequency (kHz)

Oscillator frequency vs Rt and Ct

Ct = 1.5 nF

Ct = 2.7 nF

Ct = 4.7 nF

Ct = 10 nF

FC00030FC00030

For Rt > 1. 2k Ω and Ct ≤ 40KHz

FSW 2.3

RtCt

-----------1 550

Rt150–

--------------------–

⎝⎠

⎛⎞

⋅=

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Figure 15. Error Amplifier frequency Response

Figure 16. Error Amplifier Phase Response

0.001 0.01 0.1 1 10 100 1,00

(20)

Frequency (kHz)

Volta ge Gain (dB )

RCOMP = +∞

RCOMP = 270k

RCOMP = 82k

RCOMP = 27k

RCOMP = 12k

FC00200

0.001 0.01 0.1 1 10 100 1,00

(50)

100

150

200

Fre que n c y ( kH z )

Phase (°)

RCOMP = +∞

RCOMP = 270k

RCOMP = 82k

RCOMP = 27k

RCOMP = 12k

FC00210

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Figure 17. Mixed Soft Start and Compen sati on Figure 18. Latched Shut Down

Figure 19. Typical Com pensation Netwo rk Figure 20. Slope Compensa tion

Figu re 21 . Ext ernal Cl ock S in chronis at i on F ig ure 22. Current Li m itation C i rc u it Exampl e

13V

OSC

COMP SOURCE

DRAINVDD

VIPer20

C1 +C2

+C3

AUXILIAR

WINDING

FC00431

13V

OSC

COMP SOURCE

DRAINVDD

VIPer20

Shutdown Q1

R2R3

R4 D1

FC00440

13V

OSC

COMP SOURCE

DRAINVDD

VIPer20

FC00451

13V

OSC

COMP SOURCE

DRAINVDD

VIPer20

R1R2

C1 R3

FC00461

13V

OSC

COMP SOURCE

DRAINVDD

VIPer20

10 kΩ

FC00470

13V

OSC

COMP SOURCE

DRAINVDD

VIPer20

FC00480

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6 Electrical Over Stress

6.1 Electrical Over Stress Ruggedness

The VIPer m ay be submitted to electrical over-stress , caused by violent input voltage surges or

lightning. Following the Layout Considerations is sufficient to prevent catastr ophic damages

most of the time. However in some cases, the vol tage surges coupled through the transformer

auxiliary winding can exceed the VDD pin absolute maximum rating voltage value. Such events

may trig ger the VDD interna l protection circuitry which could be damaged by the strong

disch arge curren t of the VDD bulk capacitor. The simple RC filter shown in Figure 23 can b e

imp lem ented to improve the appl ication immuni ty to such surges.

Figure 23. In pu t Voltage Surges Pr otecti on

ulk capacitor

(Optional)

22nF

Auxilliary windin

13V

OSC

COMPSOURCE

DRAIN

VDD

VIPerXX0

39R

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7 Layout

7.1 Layout Considerations

Some simple rules insure a correct running of switching power supplies. They may be

classifi ed int o two categories:

– Minimizing power loops: The switched power current must be carefully analysed and

the corresponding paths must be as s mall an inner l oop area as possible. This avoids

radiated EMC noises, conducted EMC noises by magnetic coupling, and pr ovides a

better efficiency by eliminating parasitic inductances, especially on secondary side.

– Using diffe rent tracks for low level and power signals: Interference due to mixing of

signal and power may result in instabilities and/or anomalous behaviour of t he device

in case of violent power surge (Input overvolt ages, output short circuit s...).

In case of VIPer, the se rules apply as shown on (see Figure 24).

– Loops C1-T1-U1, C5-D2-T1, and C7-D1-T1 m ust be minimized.

– C6 must be as close as possible to T1.

– Signal components C2, ISO1, C3, and C4 ar e using a dedicated track connected

directly to the power source of the device.

Figure 24. Recommended Layout

VIPerXX0

13V

OSC

COMP SOURCE

DRAINVDD

ISO1

From input

iodes bridge

To se con dary

filtering and loa

FC00500

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8 Package M echanica l Data

In order to meet environ men tal requirements, ST offe rs these devi ces in ECOPAC K®

packages. These packages have a Lead-free second level interconn ect . The category of

second Level Interconnect is marked on the package and on the inner box label, in compliance

w ith JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also

marked on the inner box label. ECOPACK is an ST trademark. ECOPACK spec ifications are

available at: www.st.com.

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Pentawatt HV Mechanical Data

Dim mm. inch

Min. Typ. Maw. Min. Typ. Max.

A 4.30 4.80 0.169 0.189

C 1.17 1.37 0.046 0.054

D 2.40 2.80 0.094 0.11

E 0.35 0.55 0.014 0.022

F 0.60 0.80 0.024 0.031

G1 4.91 5.21 0.193 0.205

G2 7.49 7.80 0.295 0.307

H1 9.30 9.70 0.366 0.382

H2 10.40 0.409

H3 10.05 10.40 0.396 0.409

L 15.60 17.30 6.14 0.681

L1 14.60 15.22 0.575 0.599

L2 21.20 21.85 0.835 0.860

L3 22.20 22.82 0.874 0.898

L5 2.60 3 0.102 0.118

L6 15.10 15.80 0.594 0.622

L7 6 6.60 0.236 0.260

M 2.50 3.10 0.098 0.122

M1 4.50 5.60 0.177 0.220

R0.50 0.02

V4 90°

Diam 3.65 3.85 0.144 0.152

P023H3

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Pentawatt HV 022Y ( Vertical High P itch ) Mechanical Data

Dim mm. inch

Min. Typ. Maw. Min. Typ. Max.

A 4.30 4.80 0.169 0.189

C 1.17 1.37 0.046 0.054

D 2.40 2.80 0.094 0.110

E 0.35 0.55 0.014 0.022

F 0.60 0.80 0.024 0.031

G1 4.91 5.21 0.193 0.205

G2 7.49 7.80 0.295 0.307

H1 9.30 9.70 0.366 0.382

H2 10.40 0.409

H3 10.05 10.40 0.396 0.409

L 16.42 17.42 0.646 0.686

L1 14.60 15.22 0.575 0.599

L3 20.52 21.52 0.808 0.847

L5 2.60 3.00 0.102 0.118

L6 15.10 15.80 0.594 0.622

L7 6.00 6.60 0.236 0.260

M 2.50 3.10 0.098 0.122

M1 5.00 5.70 0.197 0.224

R 0.50 0.02 0.020

V4 90°90°

Diam 3.65 3.85 0.144 0.154

DIA

LL1

Resin between

leads

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A ll di m e ns i o ns ar e in mm.

Base Q.ty 50

Bulk Q.ty 1000

Tube lengt h ( ± 0.5 )532

A18

B33.1

C ( ± 0.1)1

Penta watt HV Tube Shipment ( no suffix )

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VIPer20-E/DIP-E 9 Order Codes

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9 Order Codes

PENTAWATT HV PENTAWATT HV (022Y) DIP-8

VIPer20-E VIPer20-22-E VIPer20DIP-E

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10 Revision history

Date Revision Changes

27-Sep- 2005 1 Initi al release.

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