© Semiconductor Components Industries, LLC, 2016
November, 2016 − Rev. 4 1Publication Order Number:
NCP45524/D
NCP45524, NCP45525
ecoSWITCHt
Advanced Load Management
Controlled Load Switch with Low RON
The NCP4552x series of load switches provide a component and
area-reducing solution for efficient power domain switching with
inrush current limit via soft start. These devices are designed to
integrate control and driver functionality with a high performance low
on−resistance power MOSFET in a single package. This cost effective
solution is ideal for power management and hot-swap applications
requiring low power consumption in a small footprint.
Features
•Advanced Controller with Charge Pump
•Integrated N-Channel MOSFET with Low RON
•Input Voltage Range 0.5 V to 13.5 V
•Soft-Start via Controlled Slew Rate
•Adjustable Slew Rate Control (NCP45525)
•Power Good Signal (NCP45524)
•Extremely Low Standby Current
•Load Bleed (Quick Discharge)
•This is a Pb−Free Device
Typical Applications
•Portable Electronics and Systems
•Notebook and Tablet Computers
•Telecom, Networking, Medical, and Industrial Equipment
•Set−Top Boxes, Servers, and Gateways
•Hot Swap Devices and Peripheral Ports
Figure 1. Block Diagram
(*Note: either PG or SR available for each part)
EN
Bandgap
&
Biases
Charge
Pump Delay and
Slew Rate
Control
GND BLEED
SR*
Control
Logic
PG*
VOUT
VIN
VCC
DFN8, 2x2
CASE 506CC
MARKING DIAGRAM
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RON TYP VCC IMAX
18.0 mW3.3 V
6 A
3.3 V
18.8 mW
VIN
1.8 V
5.0 V
PIN CONFIGURATION
(Top View)
See detailed ordering and shipping information on page 13 o
f
this data sheet.
ORDERING INFORMATION
1
XX = 4H for NCP45524−H
= 4L for NCP45524−L
= 5H for NCP45525−H
= 5L for NCP45525−L
M = Date Code
G= Pb−Free Package
XX MG
G
1
(Note: Microdot may be in either location)
21.9 mW3.3 V 12 V
1
PG or SR
EN
GND BLEED
4
2
3
8
7
6
5
9: VIN
VOUT
VOUT
VCC
VIN
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Table 1. PIN DESCRIPTION
Pin Name Function
1, 9 VIN Drain of MOSFET (0.5 V – 13.5 V), Pin 1 must be connected to Pin 9
2 EN NCP45524−H & NCP45525−H − Active−high digital input used to turn on the MOSFET, pin
has an internal pull down resistor to GND
NCP45524−L & NCP45525−L − Active−low digital input used to turn on the MOSFET, pin has
an internal pull up resistor to VCC
3 VCC Supply voltage to controller (3.0 V − 5.5 V)
4 GND Controller ground
5 BLEED Load bleed connection; must be tied to VOUT either directly or through a resistor ≤ 100 MW.
6PG NCP45524 − Active−high, open−drain output that indicates when the gate of the MOSFET is
fully charged, external pull up resistor ≥ 1 kW to an external voltage source required; tie to
GND if not used
SR NCP45525 − Slew rate adjustment; float if not used
7, 8 VOUT Source of MOSFET connected to load
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage Range VCC −0.3 to 6 V
Input Voltage Range VIN −0.3 to 18 V
Output Voltage Range VOUT −0.3 to 18 V
EN Digital Input Range VEN −0.3 to (VCC + 0.3) V
PG Output Voltage Range (Note 1) VPG −0.3 to 6 V
Thermal Resistance, Junction−to−Ambient, Steady State (Note 2) RθJA 40.0 °C/W
Thermal Resistance, Junction−to−Ambient, Steady State (Note 3) RθJA 72.7 °C/W
Thermal Resistance, Junction−to−Case (VIN Paddle) RθJC 5.3 °C/W
Continuous MOSFET Current @ TA = 25°C IMAX 6.0 A
Total Power Dissipation @ TA = 25°C (Notes 2 and 4)
Derate above TA = 25°CPD2.50
24.9 W
mW/°C
Total Power Dissipation @ TA = 25°C (Notes 3 and 4)
Derate above TA = 25°CPD1.37
13.8 W
mW/°C
Storage Temperature Range TSTG −40 to 150 °C
Lead Temperature, Soldering (10 sec.) TSLD 260 °C
ESD Capability, Human Body Model (Notes 5 and 6) ESDHBM 3.0 kV
ESD Capability, Machine Model (Note 5) ESDMM 200 V
ESD Capability, Charged Device Model (Note 5) ESDCDM 1.0 kV
Latch−up Current Immunity (Notes 5 and 6) LU 100 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
1. NCP45524 only. PG is an open−drain output that requires an external pull up resistor ≥ 1 kW to an external voltage source.
2. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
3. Surface−mounted on FR4 board using the minimum recommended pad size, 1 oz Cu.
4. Specified for derating purposes only, ensure that IMAX is never exceeded.
5. Tested by the following methods @ TA = 25°C:
ESD Human Body Model tested per JESD22−A114
ESD Machine Model tested per JESD22−A115
ESD Charged Device Model tested per JESD22−C101
Latch−up Current tested per JESD78
6. Rating i s for all pins except for VIN and VOUT which are tied to the internal MOSFET’ s Drain and Source. Typical MOSFET ESD performance
for VIN and VOUT should be expected and these devices should be treated as ESD sensitive.
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Table 3. RECOMMENDED OPERATING RANGES
Rating Symbol Min Max Unit
Supply Voltage VCC 3 5.5 V
Input Voltage VIN 0.5 13.5 V
Ground GND 0 V
Ambient Temperature TA−40 85 °C
Junction Temperature TJ−40 125 °C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 4. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter Conditions (Note 7) Symbol Min Typ Max Unit
MOSFET
On−Resistance VCC = 3.3 V; VIN = 1.8 V RON 18.0 24.0 mW
VCC = 3.3 V; VIN = 5 V 18.8 25.0
VCC = 3.3 V; VIN = 12 V 21.9 31.7
Leakage Current (Note 8) VEN = 0 V; VIN = 13.5 V ILEAK 0.1 1 mA
CONTROLLER
Supply Standby Current (Note 9) VEN = 0 V; VCC = 3 V ISTBY 0.65 2 mA
VEN = 0 V; VCC = 5.5 V 3.2 4.5
Supply Dynamic Current (Note 10) VEN = VCC = 3 V; VIN = 12 V IDYN 180 300 mA
VEN = VCC = 5.5 V; VIN = 1.8 V 475 680
Bleed Resistance VEN = 0 V; VCC = 3 V RBLEED 86 115 144 W
VEN = 0 V; VCC = 5.5 V 72 97 121
EN Input High Voltage VCC = 3 V − 5.5 V VIH 2 V
EN Input Low Voltage VCC = 3 V − 5.5 V VIL 0.8 V
EN Input Leakage Current NCP45524−H; NCP45525−H; VEN = 0 V IIL 90 500 nA
NCP45524−L; NCP45525−L; VEN = 5.5 V IIH 90 500
EN Pull Down Resistance NCP45524−H; NCP45525−H RPD 76 100 124 kW
EN Pull Up Resistance NCP45524−L; NCP45525−L RPU 76 100 124 kW
PG Output Low Voltage (Note 11) NCP45524; VCC = 3 V; ISINK = 5 mA VOL 0.2 V
PG Output Leakage Current (Note 12) NCP45524; VCC = 3 V; VTERM = 3.3 V IOH 5 100 nA
Slew Rate Control Constant (Note 13) NCP45525; VCC = 3 V KSR 24 31 38 mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. VEN shown only for NCP45524−H, NCP45525−H (EN Active−High) unless otherwise specified.
8. Average current from VIN to VOUT with MOSFET turned off.
9. Average current from VCC to GND with MOSFET turned off.
10.Average current from VCC to GND after charge up time of MOSFET.
11.PG is an open-drain output that is pulled low when the MOSFET is disabled.
12.PG is an open-drain output that is not driven when the gate of the MOSFET is fully charged, requires an external pull up resistor ≥ 1 kW to
an external voltage source, VTERM.
13.See Applications Information section for details on how to adjust the slew rate.
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Table 5. SWITCHING CHARACTERISTICS (TJ = 25°C unless otherwise specified) (Notes 14 and 15)
Parameter Conditions Symbol Min Typ Max Unit
Output Slew Rate (Note 16)
VCC = 3.3 V; VIN = 1.8 V
SR
11.9
kV/s
VCC = 5.0 V; VIN = 1.8 V 12.1
VCC = 3.3 V; VIN = 12 V 13.5
VCC = 5.0 V; VIN = 12 V 13.9
Output Turn−on Delay (Note 16)
VCC = 3.3 V; VIN = 1.8 V
TON
220
ms
VCC = 5.0 V; VIN = 1.8 V 185
VCC = 3.3 V; VIN = 12 V 270
VCC = 5.0 V; VIN = 12 V 260
Output Turn−off Delay (Note 16)
VCC = 3.3 V; VIN = 1.8 V
TOFF
1.2
ms
VCC = 5.0 V; VIN = 1.8 V 0.9
VCC = 3.3 V; VIN = 12 V 0.4
VCC = 5.0 V; VIN = 12 V 0.2
Power Good T urn−on Time (Note 17)
VCC = 3.3 V; VIN = 1.8 V
TPG,ON
0.91
ms
VCC = 5.0 V; VIN = 1.8 V 0.93
VCC = 3.3 V; VIN = 12 V 1.33
VCC = 5.0 V; VIN = 12 V 1.21
Power Good Turn−off Time (Note 17)
VCC = 3.3 V; VIN = 1.8 V
TPG,OFF
21
ns
VCC = 5.0 V; VIN = 1.8 V 15
VCC = 3.3 V; VIN = 12 V 21
VCC = 5.0 V; VIN = 12 V 15
14.See below figure for Test Circuit and Timing Diagram.
15.Tested with the following conditions: VTERM = VCC; RPG = 100 kW; RL = 10 W; CL = 0.1 mF.
16.Applies to NCP45524 and NCP45525.
17.Applies only to NCP45524.
EN
NCP4552x−H
PG
GND
BLEED
OFF ON
SR
10%
90% DV
Dt
SR = DV
Dt
50% 50%
90%
50% 50%
Figure 2. Switching Characteristics Test Circuit and Timing Diagram
VOUT
VIN
VCC CL
RL
VTERM
RPG
TPG,OFF
TOFF
TPG,ON
TON
VOUT
VPG
VEN
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TYPICAL CHARACTERISTICS
(TJ = 25°C unless otherwise specified)
Figure 3. On−Resistance vs. Input Voltage Figure 4. On−Resistance vs. Temperature
VIN, INPUT VOLTAGE (V) TJ, JUNCTION TEMPERATURE (°C)
12.510.58.56.54.52.50.5
17
18
19
20
22
23
24
105754515−15−45
10
15
20
25
30
35
Figure 5. Supply Standby Current vs. Supply
Voltage Figure 6. Supply Standby Current vs.
Temperature
VCC, SUPPLY VOLTAGE (V) TJ, JUNCTION TEMPERATURE (°C)
5.55.04.54.03.53.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
105906030150−30−45
0
1
2
3
4
5
6
7
Figure 7. Supply Dynamic Current vs. Input
Voltage Figure 8. Supply Dynamic Current vs. Supply
Voltage
VIN, INPUT VOLTAGE (V) VCC, SUPPLY VOLTAGE (V)
12.510.58.56.54.52.50.5
100
150
250
300
350
450
500
5.55.04.54.03.53.0
100
200
300
350
400
500
RON, ON−RESISTANCE (mW)
RON, ON−RESISTANCE (mW)
ISTBY, SUPPLY STANDBY CURRENT (mA)
21
VCC = 3 V
VCC = 5.5 V
VIN = 1.8 V
VCC = 3.3 V
VIN = 5.0 V
VIN = 12 V
1200−30 30 60 90
−15 45 75 120
VCC = 3 V
VCC = 5.5 V
ISTBY, SUPPLY STANDBY CURRENT (mA)
VCC = 3 V
VCC = 5.5 V
400
IDYN, SUPPLY DYNAMIC CURRENT (mA)
VIN = 12 V
IDYN, SUPPLY DYNAMIC CURRENT (mA)
250
450 VIN = 1.8 V
200
150
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TYPICAL CHARACTERISTICS
(TJ = 25°C unless otherwise specified)
Figure 9. Supply Dynamic Current vs.
Temperature Figure 10. Bleed Resistance vs. Supply
Voltage
TJ, JUNCTION TEMPERATURE (°C) VCC, SUPPLY VOLTAGE (V)
105754515−15−45
100
400
500
700
5.55.04.54.03.53.0
95
100
105
110
115
Figure 11. Bleed Resistance vs. Temperature
TJ, JUNCTION TEMPERATURE (°C)
105754515−15−45
85
95
105
115
125
135
145
Figure 12. EN Pull Down/Up Resistance vs.
Temperature
TJ, JUNCTION TEMPERATURE (°C)
105754515−15−45
85
90
95
100
105
110
115
120
IDYN, SUPPLY DYNAMIC CURRENT (mA)
RBLEED, BLEED RESISTANCE (W)
RBLEED, BLEED RESISTANCE (W)
IPD/PU, EN PULL DOWN/UP RESISTANCE (kW)
300
600
VCC = 3.0 V, VIN = 12 V
VCC = 5.5 V, VIN = 1.8 V
VCC = 3 V
VCC = 5.5 V
200
Figure 13. PG Output Low Voltage vs. Supply
Voltage Figure 14. PG Output Low Voltage vs.
Temperature
VCC, SUPPLY VOLTAGE (V) TJ, JUNCTION TEMPERATURE (°C)
5.55.04.54.03.53.0
0.110
0.115
0.120
0.125
0.130
0.135
0.140
105754515−15−45
0.08
0.10
0.12
0.14
0.16
0.18
0.20
VOL, PG OUTPUT LOW VOLTAGE (V)
VOL, PG OUTPUT LOW VOLTAGE (V)
ISINK = 5 mA
VCC = 3 V
VCC = 5.5 V
ISINK = 5 mA
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TYPICAL CHARACTERISTICS
(TJ = 25°C unless otherwise specified)
Figure 15. Slew Rate Control Constant vs.
Input Voltage Figure 16. Slew Rate Control Constant vs.
Temperature
VIN, INPUT VOLTAGE (V) TJ, JUNCTION TEMPERATURE (°C)
12.510.58.56.54.52.50.5
29
31
32
34
105754515−15−45
28
29
30
31
32
33
34
35
Figure 17. Output Slew Rate vs. Input Voltage
VIN, INPUT VOLTAGE (V)
12.510.58.56.54.52.50.5
8
9
10
11
12
13
14
15
KSR, SLEW RATE CONTROL CONSTANT (mA)
SR, OUTPUT SLEW RATE (kV/s)
30
33
VCC = 3 V
VCC = 5.5 V
VCC = 3 V
VCC = 5.5 V
KSR, SLEW RATE CONTROL CONSTANT (mA)
VCC = 3 V
VCC = 5.5 V
Figure 18. Output Slew Rate vs. Temperature
TJ, JUNCTION TEMPERATURE (°C)
100806040200−20−40
10.5
11.0
11.5
12.0
12.5
13.0
13.5
14.0
SR, OUTPUT SLEW RATE (kV/s)
120
VCC = 3.3 V, VIN = 12 V
VCC = 5 V, VIN = 1.8 V
Figure 19. Output Turn−on Delay vs. Input
Voltage
VIN, INPUT VOLTAGE (V)
12.510.58.56.54.52.50.5
150
170
190
210
230
270
290
310
Figure 20. Output Turn−on Delay vs.
Temperature
TJ, JUNCTION TEMPERATURE (°C)
100806040200−20−40
150
175
200
225
250
275
300
TON, OUTPUT TURN−ON DELAY (ms)
TON, OUTPUT TURN−ON DELAY (ms)
250
VCC = 3 V
VCC = 5.5 V
VCC = 3.3 V, VIN = 12 V
VCC = 5 V, VIN = 1.8 V
120
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TYPICAL CHARACTERISTICS
(TJ = 25°C unless otherwise specified)
Figure 21. Output Turn−off Delay vs. Input
Voltage
VIN, INPUT VOLTAGE (V)
12.510.58.56.54.52.50.5
0
0.2
0.4
0.8
1.0
1.2
1.6
1.8
Figure 22. Output Turn−off Delay vs.
Temperature
Figure 23. Power Good Turn−on Time vs. Input
Voltage
TJ, JUNCTION TEMPERATURE (°C)
VIN, INPUT VOLTAGE (V)
100806040200−20−40
0.2
0.4
0.6
0.8
1.0
1.2
12.510.58.56.54.52.50.5
0.8
0.9
1.1
1.2
1.3
1.5
1.7
1.8
TOFF, OUTPUT TURN−OFF DELAY (ms)
TOFF, OUTPUT TURN−OFF DELAY (ms)
TPG,ON, PG TURN−ON TIME (ms)
0.6
1.4
VCC = 3 V
VCC = 5.5 V
VCC = 3.3 V, VIN = 12 V
VCC = 5 V, VIN = 1.8 V
120
VCC = 3 V
VCC = 5.5 V
1.0
1.4
1.6
Figure 24. Power Good Turn−on Time vs.
Temperature
TJ, JUNCTION TEMPERATURE (°C)
100806040200−20−40
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
TPG,ON, PG TURN−ON TIME (ms)
VCC = 3.3 V, VIN = 12 V
VCC = 5 V, VIN = 1.8 V
120
Figure 25. Power Good Turn−off Time vs.
Supply Voltage
VCC, SUPPLY VOLTAGE (V)
5.55.04.54.03.53.0
12
14
16
18
20
22
24
Figure 26. Power Good Turn−off Time vs.
Temperature
TJ, JUNCTION TEMPERATURE (°C)
100806040200−20−40
10.0
12.5
15.0
17.5
20.0
22.5
25.0
27.5
TPG,OFF, PG TURN−OFF TIME (ns)
TPG,OFF, PG TURN−OFF TIME (ns)
VIN = 0.5 V
VIN = 13.5 V
120
VCC = 3.3 V, VIN = 12 V
VCC = 5 V, VIN = 1.8 V
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TYPICAL CHARACTERISTICS
(TJ = 25°C unless otherwise specified)
Figure 27. Maximum Rated Forward Biased
Safe Operating Area
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
100 ms
1 ms
10 ms
1 10 1000.01
100
10
1
0.1 0.1
100 ms
10 ms
RDS(on) Limit
Thermal Limit
Package Limit
TA = 85°C
TJ = 125°C
0 V ≤ VGS ≤ 6 V
Single Pulse
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APPLICATIONS INFORMATION
Enable Control
Both the NCP45524 and the NCP45525 have two part
numbers, NCP4552x-H and NCP4552x-L, that only differ
in the polarity of the enable control.
The NCP4552x-H devices allow for enabling the
MOSFET in an active-high configuration. When the VCC
supply pin has an adequate voltage applied and the EN pin
is at a logic high level, the MOSFET will be enabled.
Similarly, when the EN pin is at a logic low level, the
MOSFET will be disabled. An internal pull down resistor to
ground on the EN pin ensures that the MOSFET will be
disabled when not being driven.
The NCP4552x-L devices allow for enabling the
MOSFET in an active-low configuration. When the VCC
supply pin has an adequate voltage applied and the EN pin
is at a logic low level, the MOSFET will be enabled.
Similarly, when the EN pin is at a logic high level, the
MOSFET will be disabled. An internal pull up resistor to
VCC on the EN pin ensures that the MOSFET will be
disabled when not being driven.
Power Sequencing
The NCP4552x devices will function with any power
sequence, but the output turn−on delay performance may
vary from what is specified. To achieve the specified
performance, there are two recommended power sequences:
1) VCC → VIN → VEN
2) VIN → VCC → VEN
Load Bleed (Quick Discharge)
The NCP4552x devices have an internal bleed resistor,
RBLEED, which is used to bleed the charge of f of the load to
ground after the MOSFET has been disabled. In series with
the bleed resistor is a bleed switch that is enabled whenever
the MOSFET is disabled. The MOSFET and the bleed
switch are never concurrently active.
Is it required that the BLEED pin be connected to VOUT
either directly (as shown in Figures 29 and 32) or through an
external resistor, REXT (as shown in Figures 28 and 31).
REXT should not exceed 100 MW and can be used to increase
the total bleed resistance and decrease the load bleed rate.
Care must be taken to ensure that the power dissipated
across RBLEED is kept at a safe level. The maximum
continuous power that can be dissipated across RBLEED is
0.4 W. REXT can be used to decrease the amount of power
dissipated across RBLEED.
Power Good
The NCP45524 devices have a power good output (PG)
that can be used to indicate when the gate of the MOSFET
is fully charged. The PG pin is an active-high, open-drain
output that requires an external pull up resistor, R PG, greater
than or equal to 1 kW to an external voltage source, VTERM,
that is compatible with input levels of all devices connected
to this pin (as shown in Figures 28 and 29).
The power good output can be used as the enable signal for
other active−high devices in the system (as shown in
Figure 30). This allows for guaranteed by design power
sequencing and reduces the number of enable signals needed
from the system controller. If the power good feature is not
used in the application, the PG pin should be tied to GND.
Slew Rate Control
The NCP4552x devices are equipped with controlled
output slew rate which provides soft start functionality. This
limits the inrush current caused by capacitor charging and
enables these devices to be used in hot swap applications.
The slew rate of the NCP45525 can be decreased with an
external capacitor added between the SR pin and ground (as
shown in Figures 31 and 32). With an external capacitor
present, the slew rate can be determined by the following
equation:
Slew Rate +KSR
CSR [Vńs] (eq. 1)
where K SR is the specified slew rate control constant, found
in Table 4, and CSR is the slew rate control capacitor added
between the SR pin and ground. The slew rate of the device
will always be the lower of the default slew rate and the
adjusted slew rate. Therefore, i f the CSR is not large enough
to decrease the slew rate more than the specified default
value, the slew rate of the device will be the default value.
The SR pin can be left floating if the slew rate does not need
to be decreased.
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Figure 28. NCP45524 Typical Application Diagram − Load Switch
Bandgap
&
Biases
Charge
Pump Delay and
Slew Rate
Control
Control
Logic
Load
Controller
3.0 V − 5.5 V
Power Supply
or Battery
0.5 V − 13.5 V
GND BLEED VOUT
VIN
PGEN
VCC
RPG
100 kW
VTERM = 3.3 V
REXT
Figure 29. NCP45524 Typical Application Diagram − Hot Swap
Bandgap
&
Biases
Charge
Pump Delay and
Slew Rate
Control
Control
Logic
Load
EN PG GND
BACKPLANE
REMOVABLE
CARD
GND BLEED VOUT
PGEN
VCC VIN
RPG
VTERM VIN
0.5 V − 13.5 V
VCC
3.0 V − 5.5 V
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Figure 30. NCP45524 Simplified Application Diagram − Power Sequencing with PG Output
PG
NCP45524−H
EN
Controller
PG
NCP45524−H
EN
PG
RPD
100 kWPG
RPD
100 kW
RPG
10 kW
VTERM = 3.3 V
Figure 31. NCP45525 Typical Application Diagram − Load Switch
Bandgap
&
Biases
Charge
Pump Delay and
Slew Rate
Control
Control
Logic
Load
Controller
3.0 V − 5.5 V
Power Supply
or Battery
0.5 V − 13.5 V
SR GND
CSR
BLEED VOUT
REXT
VIN
VCC EN
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Bandgap
&
Biases
Charge
Pump Delay and
Slew Rate
Control
Control
Logic
Load
3.0 V − 5.5 V EN GND
BACKPLANE
REMOVABLE
CARD
Figure 32. NCP45525 Typical Application Diagram − Hot Swap
VCC EN VIN
VCC
SR GND BLEED
CSR
VOUT
0.5 V − 13.5 V
VIN
ORDERING INFORMATION
Device Pin 6 Functionality EN Polarity Package Shipping†
NCP45524IMNTWG−H PG Active−High
DFN8
(Pb−Free) 3000 / Tape & Reel
NCP45524IMNTWG−L PG Active−Low
NCP45525IMNTWG−H SR Active−High
NCP45525IMNTWG−L SR Active−Low
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCP45524, NCP45525
www.onsemi.com
14
PACKAGE DIMENSIONS
DFN8 2x2, 0.5P
CASE 506CC
ISSUE A
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.50
PITCH
1.00 2.30
1
DIMENSIONS: MILLIMETERS
0.50
8X
0.30
8X
OUTLINE
PACKAGE
RECOMMENDED
1.70
0.20
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
ÇÇ
A
D
E
B
C0.10
PIN ONE
2X
REFERENCE
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
L
D2
E2
C
C0.10
C0.10
C0.08 A1 SEATING
PLANE
8X
NOTE 3
b
8X
0.10 C
0.05 C
ABB
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 0.00 0.05
b0.20 0.30
D2.00 BSC
D2 1.50 1.70
E2.00 BSC
E2 0.80 1.00
e0.50 BSC
L0.18 0.38
14
8
NOTE 4
DET AIL A
A3 0.20 REF
A3
A
DETAIL B
A1 A3
ÇÇ
ÉÉ
DETAIL B
MOLD CMPD
EXPOSED Cu
L1 −−− 0.15
e
K0.20 REF
5
M
ALTERNATE
CONSTRUCTION
L1
DETAIL A
L
ALTERNATE
CONSTRUCTIONS
L
e/2
M0.14 REF
K
P
UBLICATION ORDERING INFORMATION
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
NCP45524/D
ecoSWITCH is a trademark of Semiconductor Components Industries, LLC (SCILLC).
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