Chip Card & Security ICs
SLE 5538
Intelligent 1024 Byte EEPROM
with Write- and Read Out Protection
and Programmable Security Code
Short Product Information May 2007
SLE 5538 Short Product Information
Revision History: Current Version 2007-05-03
Previous Releases: 2006-11-24
Page Subjects (changes since last revision)
Preliminary removed, editorial updates
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Chip Card & Security ICs,
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SLE 5538
Short Product Information 3 / 6 2007-05-03
Intelligent 1024 Byte EEPROM
with Write- and Read Out Protection and
Programmable Security Code (PSC)
Features
Downward compatibility to SLE 4428 & SLE 5528
1024 x 8 bit EEPROM organization of Data Memory
1024 x 1 bit Protection Memory
Byte-wise write protection of Data Memory (one time programmable)
Not alterable Manufacturer Code (chip coding and unique coding by application identifier
RID according to ISO/IEC 7816-5)
Sector-wise read-out protection of Data Memory
Data Memory alterable only after verification of 2 Byte PSC
Read-protected Data Memory readable after verification of 2 Byte PSC only
PSC verification trials limited by Error Counter
Serial synchronous three-wire link protocol according to ISO/IEC 7816
– Byte-wise addressing
End of processing indicated at data output
Contact configuration and Answer-to-Reset (synchronous transmission) in accordance
to standard ISO/IEC 7816
Electrical characteristics
Ambient temperature range -40 … +100°C for chip, -25 … +80°C for module
– Supply voltage 5V ± 10%
Supply current < 1 mA
EEPROM erase / write time 5 ms / 5 ms
ESD protection typically 4,000 V
EEPROM Endurance minimum 100,000 erase / write cycles1)
Data retention for minimum of 10 years1)
Advanced CMOS-technology optimized for security layout
EEPROM-cells protected by shield
Shielding of deeper layers via metal
Sensory- and logical security functions
No insulation of backside necessary
1) Values are temperature dependent.
M3
SLE 5538
Short Product Information 4 / 6 2007-05-03
1 Ordering and Packaging information
Table 1 Ordering Information
Type Package1) Remark Ordering Code
SLE 5538 C Die (on Wafer) not sawn on request
SLE 5538 D Die (on Wafer) sawn on request
SLE 5538 M3 T-M3.2-6 on request
SLE 5538 MFC3 S-MFC3.1-6-1 FCoS™ on request
Pin Description
Figure 1 Pin Configuration Wire-bonded Module M3.2 (top view)
Figure 2 Pin Configuration Module Flip Chip MFC3.1 (top view)
1) Available as a Module Flip Chip (MFC3), wire-bonded module (M2 and M3) for embedding in plastic cards or as a die
on non-sawn (C) / sawn wafer (D) for customer packaging
SLE 5538
Short Product Information 5 / 6 2007-05-03
SLE 5538
GND
I/O
VCC
RST
CLK
Figure 1 Pad Configuration Die
Table 2 Pin Definitions and Functions M3 / MFC3
Card Contact Symbol Function
C1 VCC Supply voltage
C2 RST Reset (Chip Enable)
C3 CLK Clock input
C5 GND Ground
C6 N.C. Not connected
C7 I/O Bi-directional data line (open drain)
SLE 5538
Short Product Information 6 / 6 2007-05-03
2 Circuit Description
Memory Organization
The memory is organized in a Data Memory of 1024 byte.
Write and Read-Out Protection of Data Memory
Write Protection Bits: Each byte of the Data Memory can be irreversibly protected against
data change by writing the corresponding bit in the Write Protection Memory. Dependent on
the state of the protection bit the Data Memory is read only (ROM) or may be erased and
written again (EEPROM). The manufacturer code (Application ID and Chip Coding) is
programmed unalterable by the chip manufacturer.
Read-Out Protection Bits: Three sectors of the Data Memory can be irreversibly protected
against read-out by writing the corresponding bit in the Read Protection Memory.
Programmable Security Code
Altering data in the Data Memory as well as setting a Write Protection Bit is only possible after
verification of the 2-Byte Programmable Security Code (PSC).
Read-out of read-protected Data Memory sector only after verification of the 2-Byte
Programmable Security Code (PSC).
Figure 2 Memory Configuration SLE 5538