1
2
3
4
5
6
7
14
13
12
11
10
9
8
1 OUT
1 IN−
1 IN+
VCC−
N/C
REF
N/C
VCC+
2 OUT
2 IN−
2 IN+
N/C
SHUTDOWN
N/C
1
10
100
0.01 0.1 1 10 100
f − Frequency − kHz
In−
In+
Vn
VOLTAGE NOISE AND CURRENT NOISE
vs
FREQUENCY
V Voltage Noise nV/
I Current Noise pA/
- -
- -
n
n
Hz
Hz
?
?
V = 5 V to 15 V
T = +25 C
CC
A
± ±
°
1
2
3
4
8
7
6
5
1 OUT
1 IN−
1 IN+
VCC−
VCC+
2 OUT
2 IN−
2 IN+
THS3122
SOIC (D) AND
SOIC PowerPAD (DDA) PACKAGE
(TOP VIEW)
?
THS3125
SOIC (D) AND
TSSOP PowerPAD (PWP) PACKAGE
(TOP VIEW)
?
THS3122
THS3125
www.ti.com
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
LOW-NOISE, HIGH-SPEED, 450-mA CURRENT FEEDBACK AMPLIFIERS
Check for Samples: THS3122,THS3125
1FEATURES APPLICATIONS
•Video Distribution
23•Low Noise: •Instrumentation
–2.9-pA/√Hz Noninverting Current Noise •Line Drivers
–10.8-pA/√Hz Inverting Current Noise •Motor Drivers
–2.2-nV/√Hz Voltage Noise •Piezo Drivers
–128-MHz , –3-dB BW (RL= 50 Ω, RF= 470 Ω)
–1550-V/µs Slew Rate (G = 2, RL= 50Ω)DESCRIPTION
•High Output Current: 450 mA The THS3122/5 are low-noise, high-speed current
•High Speed: feedback amplifiers, with high output current drive.
–128-MHz , –3-dB BW (RL= 50 Ω, RF= 470 Ω)This makes them ideal for any application that
requires low distortion over a wide frequency with
–1550-V/µs Slew Rate (G = 2, RL= 50Ω)heavy loads. The THS3122/5 can drive four
–26-VPP Output Voltage, RL= 50 Ωserially-terminated video lines while maintaining a
– –80 dBc (1 MHz, 2 VPP,G=2) differential gain error less than 0.03%.
•Wide Output Swing: The high output drive capability of the THS3122/5
–26-VPP Output Voltage, RL= 50 Ωenables the devices to drive 50-Ωloads with low
distortion over a wide range of output voltages:
– –80 dBc (1 MHz, 2 VPP,G=2) • –80-dBc THD at 2 VPP
–370-µA Shutdown Supply Current •-75-dBc THD at 8 VPP
•Low Distortion: The THS3122/5 can operate from ±5-V to ±15-V
– –80 dBc (1 MHz, 2 VPP,G=2) supply voltages while drawing as little as 7.2 mA of
–370-µA Shutdown Supply Current supply current per channel. The THS3125 offers a
•Low-Power Shutdown Mode (THS3125) low-power shutdown mode, reducing the supply
current to only 370 µA. The THS3122/5 are packaged
–370-µA Shutdown Supply Current in a standard SOIC, SOIC PowerPAD™, and TSSOP
•Standard SOIC, SOIC PowerPAD™, and PowerPAD packages.
TSSOP PowerPAD Packages
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. ©2001–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
THS3122
THS3125
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE OPTIONS(1)
PACKAGED DEVICE EVALUATION
TASOIC-8 SOIC-8 PowerPAD SOIC-14 TSSOP-14 MODULES
(D) (DDA) (D) (PWP)
0°C to +70°C THS3122CD THS3122CDDA THS3125CD THS3125CPWP THS3122EVM
THS3125EVM
40°C to +85°C THS3122ID THS3122IDDA THS3125ID THS3125IPWP
(1) For the most current specification and package information, refer to the Package Option Addendum located at the end of this data sheet
or see the TI web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature (unless otherwise noted). UNIT
Supply voltage, VCC+ to VCC–33 V
Input voltage ±VCC
Output current (see (2)) 550 mA
Differential input voltage ±4 V
Maximum junction temperature +150°C
Total power dissipation at (or below) +25°C free-air temperature See Dissipation Ratings Table
Commercial 0°C to +70°C
Operating free-air temperature, TAIndustrial –40°C to +85°C
Commercial –65°C to +125°C
Storage temperature, Tstg Industrial –65°C to +125°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The THS3122 and THS3125 may incorporate a PowerPAD™on the underside of the chip. This pad acts as a heatsink and must be
connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction
temperature which could permanently damage the device. See TI Technical Brief SLMA002 for more information about utilizing the
PowerPAD™thermally-enhanced package.
DISSIPATION RATING TABLE
TA= +25°C
PACKAGE θJA POWER RATING
D-8 95°C/W(1) 1.32 W
DDA 67°C/W 1.87 W
D-14 66.6°C/W(1) 1.88 W
PWP 37.5°C/W 3.3 W
(1) These data were taken using the JEDEC proposed high-K test PCB.
For the JEDEC low-K test PCB, the θJA is 168°C/W for the D-8
package and 122.3°C/W for the D-14 package.
2Submit Documentation Feedback ©2001–2011, Texas Instruments Incorporated
Product Folder Link(s): THS3122 THS3125
THS3122
THS3125
www.ti.com
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT
Dual supply ±5±15
Supply voltage, VCC+ to VCC–V
Single supply 10 30
C-suffix 0 +70
Operating free-air temperature, TA°C
I-suffix –40 +85
ELECTRICAL CHARACTERISTICS
Over operating free-air temperature range, TA= +25°C, VCC =±15 V, RF= 750 Ω, and RL= 100 Ω(unless otherwise noted).
DYNAMIC PERFORMANCE
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC =±5 V 138
RL= 50ΩRF= 50 Ω, G = 1 VCC=±15 V 160
Small-signal bandwidth (–3 dB) VCC =±5 V 126
RF= 470 Ω,G=
RL= 50 ΩMHz
2VCC=±15 V 128
BW VCC =±5 V 20
Bandwidth (0.1 dB) RF= 470 Ω, G = 2 VCC=±15 V 30
VO(PP) = 4 V VCC =±5 V 47
Full power bandwidth G = -1 MHz
VO(pp)= 20 V VCC=±15 V 64
VO= 10 VPP VCC =±15 V 1550
SR Slew rate(1), G = 8 G = 2, RF= 680ΩVCC =±5 V 500 V/µs
VO= 5 VPP VCC=±15 V 1000
VO= 2 VPP VCC =±5 V 53
tsSettling time to 0.1% G = -1 ns
VO= 5 VPP VCC =±15 V 64
(1) Slew rate is defined from the 25% to the 75% output levels.
NOISE/DISTORTION PERFORMANCE
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VO(PP) = 2 V –80
G = 2, RF= 470 Ω, VCC=±15 V,
f = 1 MHz VO(PP) = 8 V –75
THD Total harmonic distortion dBc
VO(PP)= 2 V –77
G = 2, RF= 470 Ω, VCC=±5 V,
f = 1 MHz VO(PP)= 5 V –76
VnInput voltage noise VCC =±5 V, ±15 V f = 10 kHz 2.2 nV/√Hz
Noninverting Input 2.9
InInput current noise VCC =±5 V, ±15 V f = 10 kHz pA/√Hz
Inverting Input 10.8
VCC =±5 V –67
Crosstalk G = 2, f = 1 MHz, VO= 2 VPP dBc
VCC=±15 V –67
VCC =±5 V 0.01
G = 2, RL= 150 Ω
Differential gain error %
VCC=±15 V 0.01
40 IRE modulation
±100 IRE Ramp VCC =±5 V 0.011
Differential phase error degrees
NTSC and PAL VCC=±15 V 0.011
©2001–2011, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): THS3122 THS3125
THS3122
THS3125
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Over operating free-air temperature range, TA= +25°C, VCC =±15 V, RF= 750 Ω, and RL= 100 Ω(unless otherwise noted).
DC PERFORMANCE
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TA= +25°C 6 10
Input offset voltage TA= full range 13 mV
VIC = 0 V, VO= 0 V,
VIO TA= +25°C 1 3
VCC =±5 V, VCC =±15 V
Channel offset voltage matching TA= full range 4
Offset drift TA= full range 10 µV/°C
TA= +25°C 6 23
IN- Input bias current TA= full range 30
VIC = 0 V, VO= 0 V,
IIB µA
VCC =±5 V, VCC =±15 V TA= +25°C 0.33 2
IN+ Input bias current TA= full range 3
TA= +25°C 5.4 22
VIC = 0 V, VO= 0 V,
IIO Input offset current µA
VCC =±5 V, VCC =±15 V TA= full range 30
ZOL Open-loop transimpedance VCC =±5 V, VCC =±15 V RL= 1 kΩ1 MΩ
INPUT CHARACTERISTICS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC =±5 V ±2.5 ±2.7
VICR Input common-mode voltage range TA= full range V
±12. ±12.
VCC=±15 V 5 7
TA= +25°C 58 62
VCC =±5 V,
VI= -2.5 V to 2.5 V TA= full range 56
CMRR Common-mode rejection ratio dB
TA= +25°C 63 67
VCC =±15 V,
VI=–12.5 V to 12.5 V TA= full range 60
IN+ 1.5 MΩ
RIInput resistance IN–15 Ω
CIInput capacitance 2 pF
OUTPUT CHARACTERISTICS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
G = 4, VI= 1.06 V, VCC =±5 V RL= 1 kΩTA= +25°C 4.1 V
TA= +25°C 3.8 4
G = 4, VI= 1.025 V, VCC=±5 V, RL= 50ΩTA= full 3.7 V
range
VOOutput voltage swing G = 4, VI= 3.6 V, VCC=±15 V, RL= 1 kΩTA= +25°C 14.2
TA= +25°C 12 13.3
G = 4, VI= 3.325 V, VCC=±15 V, RL= 50ΩV
TA= full 11.5
range
G = 4, VI= 1.025 V, VCC=±5 V, RL= 10 ΩTA= +25°C 200 280 mA
IOOutput current drive VI= 3.325 V, VCC =±15
G = 4, RL= 25 ΩTA= +25°C 360 440 mA
V,
roOutput resistance Open loop TA= +25°C 14 Ω
4Submit Documentation Feedback ©2001–2011, Texas Instruments Incorporated
Product Folder Link(s): THS3122 THS3125
THS3122
THS3125
www.ti.com
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
ELECTRICAL CHARACTERISTICS (continued)
Over operating free-air temperature range, TA= +25°C, VCC =±15 V, RF= 750 Ω, and RL= 100 Ω(unless otherwise noted).
POWER SUPPLY
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TA= +25°C 7.2 9
VCC =±5 V TA= full range 10
ICC Quiescent current (per channel) mA
TA= +25°C 8.4 10.5
VCC =±15 V TA= full range 11.5
TA= +25°C 53 60
VCC =±5 V ±1 V TA= full range 50
PSRR Power-supply rejection ratio dB
TA= +25°C 60 69
VCC =±15 V ±1 V TA= full range 55
SHUTDOWN CHARACTERISTICS (THS3125 Only)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Shutdown quiescent current (per
ICC(SHDN) VSHDN = 3.3 V 370 500 µA
channel)
tDIS Disable time (1) 500 µs
REF = 0 V,
tEN Enable time(1) VCC=±5 V to ±15 V 200 µs
IIL(SHDN) Shutdown pin low level leakage current VSHDN = 0 V 18 25 µA
IIH(SHDN) Shutdown pin high level leakage current VSHDN = 3.3 V 110 130 µA
VREF REF pin voltage level VCC–VCC+ –4 V
Enable REF+0.8
VSHDN SHUTDOWN pin voltage level V
Disable REF+2
(1) Disable/enable time is defined as the time from when the shutdown signal is applied to the SHDN pin to when the supply current has
reached half of its final value.
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
Small-signal closed-loop gain vs Frequency Figure 1 to Figure 10
Small- and large-signal output vs Frequency Figure 11,Figure 12
vs Frequency Figure 13 to Figure 15
Harmonic distortion vs Peak-to-peak output voltage Figure 16,Figure 17
Vn, InVoltage noise and current noise vs Frequency Figure 18
CMRR Common-mode rejection ratio vs Frequency Figure 19
Crosstalk vs Frequency Figure 20
ZoOutput impedance vs Frequency Figure 21
SR Slew rate vs Output voltage step Figure 22
vs Free-air temperature Figure 24
VIO Input offset voltage vs Common-mode input voltage Figure 24
IBInput bias current vs Free-air temperature Figure 25
VOOutput voltage vs Load current Figure 26
vs Free-air temperature Figure 27
Quiescent current vs Supply voltage Figure 28
ICC Shutdown supply current vs Free-air temperature Figure 29
Differential gain and phase error vs 75-Ωserially terminated loads Figure 30,Figure 31
Shutdown response Figure 32
Small-signal pulse response Figure 33,Figure 34
Large-signal pulse response Figure 35,Figure 36
©2001–2011, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): THS3122 THS3125
−30
−27
−24
−21
−18
−15
−12
−9
−6
−3
0
3
0.1 1 10 100 1000
RF = 500 Ω
RF = 680 Ω
G = −1,
VCC = ±15 V,
RL = 50 Ω
f − Frequency − MHz
Small Signal Closed Loop Gain − dB
RF = 330 Ω
−6
−5
−4
−3
−2
−1
0
1
2
0.1 1 10 100 1000
RF = 560 Ω
RF = 750 Ω
RF = 470 Ω
G = 1,
VCC = ±5 V,
RL = 50 Ω
f − Frequency − MHz
Small Signal Closed Loop Gain − dB
−30
−27
−24
−21
−18
−15
−12
−9
−6
−3
0
3
6
0.1 1 10 100 1000
RF = 500 Ω
RF = 680 Ω
RF = 330 Ω
G = −1,
VCC = ±5 V,
RL = 50 Ω
f − Frequency − MHz
Small Signal Closed Loop Gain − dB
−6
−3
0
3
6
9
0.1 1 10 100 1000
RF = 470 Ω
RF = 500 Ω
RF = 430 Ω
G = 2,
VCC = ±15 V,
RL = 50 Ω
f − Frequency − MHz
Small Signal Closed Loop Gain − dB
−12
−9
−6
−3
0
3
0.1 1 10 100 1000
RF = 560 Ω
RF = 470 Ω
G = 1,
VCC = ±15 V,
RL = 50 Ω
f − Frequency − MHz
Small Signal Closed Loop Gain − dB
RF = 750 Ω
−6
−3
0
3
6
9
0.1 1 10 100 1000
RF = 470 Ω
RF = 500 Ω
RF = 430 Ω
G = 2,
VCC = ±5 V,
RL = 50 Ω
f − Frequency − MHz
Small Signal Closed Loop Gain − dB
−18
−15
−12
−9
−6
−3
0
3
6
9
12
15
0.1 1 10 100 1000
RF = 270 Ω
RF = 390 Ω
RF = 200 Ω
G = 4,
VCC = ±15 V,
RL = 50 Ω
f − Frequency − MHz
Small Signal Closed Loop Gain − dB
−18
−15
−12
−9
−6
−3
0
3
6
9
12
15
0.1 1 10 100 1000
RF = 270 Ω
RF = 390 Ω
RF = 200 Ω
G = 4,
VCC = ±5 V,
RL = 50 Ω
f − Frequency − MHz
Small Signal Closed Loop Gain − dB
−12
−9
−6
−3
0
3
6
9
12
15
0.1 1 10 100 1000
RF = 470 Ω
RF = 560 Ω
RF = 200 Ω
VCC = ±5 V,
RL = 50 Ω
f − Frequency − MHz
Small Signal Closed Loop Gain − dB
THS3122
THS3125
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
www.ti.com
TYPICAL CHARACTERISTICS
SMALL-SIGNAL CLOSED-LOOP SMALL-SIGNAL CLOSED-LOOP SMALL-SIGNAL CLOSED-LOOP
GAIN GAIN GAIN
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
Figure 1. Figure 2. Figure 3.
SMALL-SIGNAL CLOSED-LOOP SMALL-SIGNAL CLOSED-LOOP SMALL-SIGNAL CLOSED-LOOP
GAIN GAIN GAIN
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
Figure 4. Figure 5. Figure 6.
SMALL-SIGNAL CLOSED-LOOP SMALL-SIGNAL CLOSED-LOOP SMALL-SIGNAL CLOSED-LOOP
GAIN GAIN GAIN
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
Figure 7. Figure 8. Figure 9.
6Submit Documentation Feedback ©2001–2011, Texas Instruments Incorporated
Product Folder Link(s): THS3122 THS3125
−12
−9
−6
−3
0
3
6
9
12
15
0.1 1 10 100 1000
RF = 470 Ω
RF = 560 Ω
RF = 200 Ω
VCC = ±15 V,
RL = 50 Ω
f − Frequency − MHz
Small Signal Closed Loop Gain − dB
−24
−18
−12
−6
0
6
12
18
0.1 110 100 1000
4 VPP G = 2, VCC = ±5 V,
RL = 680 Ω, RL = 50 Ω
f − Frequency − MHz
Small and Large Signal Output − dB
2 VPP
1 VPP
0.5 VPP
0.25 VPP
0.125 VPP
−24
−18
−12
−6
0
6
12
18
0.1 1 10 100 1000
4 VPP G = 2, VCC = ±15 V,
RL = 680 Ω,RL = 50 Ω
f − Frequency − MHz
Small and Large Signal Output − dB
2 VPP
1 VPP
0.5 VPP
0.25 VPP
0.125 VPP
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10
3rd Harmonic
G = 2,
VCC = ±15 V,
VO(PP) = 8 V,
RF = 470 Ω,
RL = 50 Ω
f − Frequency − MHz
Harmonic Distortion − dB
5th Harmonic
2nd Harmonic
4th Harmonic
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
3rd Harmonic
G = 2,
VCC = ±5 V,
VO(PP) = 2 V,
RF = 470 Ω,
RL = 50 Ω
f − Frequency − MHz
Harmonic Distortion − dB
5th Harmonic
2nd Harmonic
4th Harmonic
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0123456789
3rd Harmonic
G = 2,
VCC = ±15 V,
f = 1 MHz,
RF = 470 Ω,
RL = 50 Ω
VPP − Peak-to-Peak Output Voltage − V
Harmonic Distortion − dB
5th Harmonic
4th Harmonic
2nd Harmonic
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
3rd Harmonic
G = 2,
VCC = ±5 V,
f = 1 MHz,
RF = 470 Ω,
RL = 50 Ω
VPP − Peak-to-Peak Output Voltage − V
Harmonic Distortion − dB
4th Harmonic
2nd Harmonic 5th Harmonic
1
10
100
0.01 0.1 1 10 100
f − Frequency − kHz
− Current Noise −
Vn
In
− Voltage Noise −
pA/ Hz
nV/ Hz
In−
In+
Vn
VCC = ±5 V to ±15 V
TA = 25°C
THS3122
THS3125
www.ti.com
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
TYPICAL CHARACTERISTICS (continued)
SMALL- AND LARGE-SIGNAL SMALL- AND LARGE-SIGNAL
SMALL-SIGNAL CLOSED-LOOP
GAIN OUTPUT OUTPUT
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
Figure 10. Figure 11. Figure 12.
HARMONIC DISTORTION HARMONIC DISTORTION HARMONIC DISTORTION
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
Figure 13. Figure 14. Figure 15.
VOLTAGE NOISE AND CURRENT
HARMONIC DISTORTION HARMONIC DISTORTION NOISE
vs vs vs
PEAK-TO-PEAK OUTPUT VOLTAGE PEAK-TO-PEAK OUTPUT VOLTAGE FREQUENCY
Figure 16. Figure 17. Figure 18.
©2001–2011, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): THS3122 THS3125
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100 1000
G = 2,
VCC = ±5 V, ±15 V
RF = 470 Ω,
RL = 50 Ω,
f − Frequency − MHz
Crosstalk − dBc
0
10
20
30
40
50
60
70
80
0.1 1 10 100 1000
G = 2,
RF = 470 Ω,
RL = 50 Ω,
TA = 25°C
f − Frequency − MHz
CMRR − Common-Mode Rejection Ratio − dB
VCC = ±15 V
VCC = ±5 V
0.01
0.1
1
10
100
0.1 1 10 100 1000
VCC = ±5 V, ±15 V
RF = 1 kΩ,
f − Frequency − MHz
− Output Impedance − ΩZO
0
200
400
600
800
1000
1200
1400
1600
1800
0 1 2 3 4 5 6 7 8 9
G = 2,
RF = 470 Ω,
RL = 50 Ω,
TA = 25°C
VO − Output Voltage Step − V
SR − Slew Rate −
VCC = ±15 V
VCC = ±5 V
sµ
V/
10
7
6
5
4
3
2
1
0
−40 −15 10 35 60 85
TA − Free-Air Temperature − °C
− Input Offset Voltage − mVVIO
VCC = ±15 V,
VCM = 0 V,
RL = 100 Ω
−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
−15 −10 −5 0 5 10 15
VCM − Common-Mode Input Voltage − V
− Input Offset Voltage − mVVIO
VCC = ±15 V,
RL = 100 Ω,
TA = 25°C
0
2
4
6
8
10
12
−40 −15 10 35 60 85
− Quiescent Current − mA/ Per ChannelICC
TA − Free-Air Temperature − °C
VCC = ±15 V
VCC = ±5 V
10
11
12
13
14
15
0 50 100 150 200 250 300 350 400 450
IL − Load Current − mA
− Output Voltage − VVO
VCC = ±15 V,
RF = 330 Ω,
TA = 25°C
−2
0
2
4
6
8
10
12
−40 −15 10 35 60 85
TA − Free-Air Temperature − °C
− Input Bias Current −
IIB Aµ
VCC = ±15 V, IIB+
VCC = ±15 V, IIB−
VCC = ±5 V, IIB+
VCC = ±5 V, IIB−
THS3122
THS3125
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
COMMON-MODE REJECTION RATIO CROSSTALK OUTPUT IMPEDANCE
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
Figure 19. Figure 20. Figure 21.
SLEW RATE INPUT OFFSET VOLTAGE INPUT OFFSET VOLTAGE
vs vs vs
OUTPUT VOLTAGE STEP FREE-AIR TEMPERATURE COMMON-MODE INPUT VOLTAGE
Figure 22. Figure 23. Figure 24.
INPUT BIAS CURRENT OUTPUT VOLTAGE QUIESCENT CURRENT
vs vs vs
FREE-AIR TEMPERATURE LOAD CURRENT FREE-AIR TEMPERATURE
Figure 25. Figure 26. Figure 27.
8Submit Documentation Feedback ©2001–2011, Texas Instruments Incorporated
Product Folder Link(s): THS3122 THS3125
0
50
100
150
200
250
300
350
400
450
−40 −15 10 35 60 85
TA − Free-Air Temperature − °C
Shutdown Supply Current − Aµ
VCC = ±15 V
VCC = ±5 V
VSD = 3.3 V
RF = 750 Ω
0
2
4
6
8
10
12
0 2.5 5 7.5 10 12.5 15
− Quiescent Current − mAICC
VCC − Supply Voltage − ±V
25 °C
−40 °C
85 °C
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0 100 200 300 400 500 600
t − Time − ns
− Output Voltage − VVO
VCC = ±5 V,
G = 2,
RF = 470 Ω,
RL = 50 Ω
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
123456780
0.05
0.1
0.15
0.2
0.25
0.3
0.35
75 Ω Serially Terminated Loads
Differenrtial Gain Error − %
Differential Phase Error − Degree °
VCC = ±5 V,
G = 2,
40 IRE Modulation
±100 IRE Ramp
NTSC
Gain Error
Phase Error
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0 100 200 300 400 500 600
t − Time − ns
− Output Voltage − VVO
VCC = ±5 V,
G = 2,
RF = 470 Ω,
RL = 50 Ω
0
1
2
3
4
5
0 1 2 3 4 5 6 7 8 9 10
0
0.5
1
1.5
2
t − Time − ns
− Output Voltage − V
Shutdown Pulse − V
VO
THS3122
THS3125
www.ti.com
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
TYPICAL CHARACTERISTICS (continued)
QUIESCENT CURRENT SHUTDOWN SUPPLY CURRENT
vs vs
SUPPLY VOLTAGE FREE-AIR TEMPERATURE
Figure 28. Figure 29.
DIFFERENTIAL PHASE AND GAIN ERROR DIFFERENTIAL PHASE AND GAIN ERROR
vs vs
75-ΩSERIALLY-TERMINATED LOADS 75-ΩSERIALLY-TERMINATED LOADS
Figure 30. Figure 31.
THS3125 THS3125
SHUTDOWN RESPONSE SHUTDOWN RESPONSE
Figure 32. Figure 33.
©2001–2011, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): THS3122 THS3125
−2
−1
0
1
2
3
0 100 200 300 400 500 600
−3
t − Time − ns
− Output Voltage − VVO
VCC = ±15 V,
G = 2,
RF = 470 Ω,
RL = 50 Ω
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0 100 200 300 400 500 600
t − Time − ns
− Output Voltage − VVO
VCC = ±15 V,
G = 2,
RF = 470 Ω,
RL = 50 Ω
−3
−2
−1
0
1
2
3
0 100 200 300 400 500 600
t − Time − ns
− Output Voltage − VVO
VCC = ±5 V,
G = 2,
RF = 470 Ω,
RL = 50 Ω
THS3122
THS3125
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
SMALL-SIGNAL PULSE RESPONSE LARGE-SIGNAL PULSE RESPONSE LARGE-SIGNAL PULSE RESPONSE
Figure 34. Figure 35. Figure 36.
10 Submit Documentation Feedback ©2001–2011, Texas Instruments Incorporated
Product Folder Link(s): THS3122 THS3125
THS3125
470 W
49.9 W
56.2
R
W
M
RG
470 W
0.1 Fm
+
6.8 Fm
0.1 Fm
+
6.8 Fm
50- LoadW
50- SourceW
RF
VI
+VS
-VS
-15V
+15V
THS3125
470 W
49.9 W
49.9 W
470
R
W
G
0.1 Fm
+
6.8 Fm
0.1 Fm
+
6.8 Fm
50- LoadW
50- SourceW
RF
VI
+VS
-VS
-15V
+15V
THS3122
THS3125
www.ti.com
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
APPLICATION INFORMATION
Current-feedback amplifiers are highly dependent on
Maximum Slew Rate for Repetitive Signals the feedback resistor RFfor maximum performance
The THS3125 and THS3122 are recommended for and stability. Table 1 shows the optimal gain setting
high slew rate pulsed applications where the internal resistors RFand RGat different gains to give
nodes of the amplifier have time to stabilize between maximum bandwidth with minimal peaking in the
pulses. It is recommended to have at least 20-ns frequency response. Higher bandwidths can be
delay between pulses. achieved, at the expense of added peaking in the
frequency response, by using even lower values for
The THS3125 and THS3122 are not recommended RF. Conversely, increasing RFdecreases the
for applications with repetitive signals (sine, square, bandwidth, but stability is improved.
sawtooth, or other) that exceed 900 V/µs. Using the
part in these applications results in excessive current Table 1. Recommended Resistor Values for
draw from the power supply and possible device Optimum Frequency Response
damage. THS3125 and THS3122 RFand RGVALUES FOR MINIMAL
For applications with high slew rate, repetitive signals, PEAKING WITH RL= 50 Ω,±5-V to ±15-V POWER SUPPLY
the THS3091 and THS3095 (single versions), or GAIN (V/V) RG(Ω) RF(Ω)
THS3092 and THS3096 (dual versions) are 1—560
recommended. 2 470 470
4 66.5 200
Wideband, Noninverting Operation
The THS3125 and THS3122 are unity gain stable Wideband, Inverting Operation
130-MHz current-feedback operational amplifiers,
designed to operate from a ±5-V to ±15-V power Figure 38 shows the THS3125 in a typical inverting
supply. gain configuration where the input and output
impedances from Figure 37 are retained in an
Figure 37 shows the THS3125 in a noninverting gain inverting circuit configuration.
of 2-V/V configuration used to generate the typical
characteristic curves. Most of the curves were
characterized using signal sources with 50-Ωsource
impedance and with measurement equipment that
presents a 50-Ωload impedance.
Figure 38. Wideband, Inverting Gain
Configuration
Figure 37. Wideband, Noninverting Gain
Configuration
©2001–2011, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): THS3122 THS3125
470 W470 W
+15V
-15V
75 W
75 W
75 W
75 W
75 W
VI
nlines
75- TransmissionLineW
VO(n)
VO(1)
THS3125
RF
470 W
49.9 W
R
49.9 W
T
RG
470 W
50- LoadW
50- SourceW
VI
+VS
+VS/2
+VS/2
THS3125
RF
470 W
49.9 W
50- LoadW
+VS
+VS/2
56.2
R
W
T
RG
470 W
50- SourceW
VI
+VS/2
60
50
40
30
20
10
0
RecommendedR Resistance( )W
ISO
10 100
C CapacitiveLoad(pF)-
L
THS3122
THS3125
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
www.ti.com
Single-Supply Operation
The THS3125 and THS3122 have the capability to
operate from a single supply voltage ranging from 10
V to 30 V. When operating from a single power
supply, biasing the input and output at mid-supply
allows for the maximum output voltage swing. The
circuits in Figure 39 show inverting and noninverting
amplifiers configured for single-supply operation.
Figure 40. Video Distribution Amplifier
Application
Driving Capacitive Loads
Applications such as FET drivers and line drivers can
be highly capacitive and cause stability problems for
high-speed amplifiers.
Figure 41 through Figure 47 show recommended
methods for driving capacitive loads. The basic idea
is to use a resistor or ferrite chip to isolate the phase
shift at high frequency caused by the capacitive load
from the amplifier feedback path. See Figure 41 for
recommended resistor values versus capacitive load.
Figure 39. DC-Coupled, Single-Supply Operation
Video Distribution
The wide bandwidth, high slew rate, and high output
drive current of the THS3125 and THS3122 match
the demands for video distribution to deliver video
signals down multiple cables. To ensure high signal
quality with minimal degradation of performance, a
0.1-dB gain flatness should be at least 7x the
passband frequency to minimize group delay Figure 41. Recommended RISO vs Capacitive
variations from the amplifier. A high slew rate Load
minimizes distortion of the video signal, and supports
component video and RGB video signals that require
fast transition times and fast settling times for high
signal quality. Figure 40 illustrates a typical video
distribution amplifier application configuration.
12 Submit Documentation Feedback ©2001–2011, Texas Instruments Incorporated
Product Folder Link(s): THS3122 THS3125
49.9 W
1 Fm
100- LoadW
+VS
+VS
RG
-VS
RF
R
5.11
ISO
W
49.9 W
1 Fm
100- LoadW
+VS
+VS
RG
-VS
RF
5.11 W
27pF
560 W
RIN
49.9 W
1 Fm
100- LoadW
+VS
+VS
RG
-VS
RF
Ferrite
Bead
49.9 W
1 Fm
100- LoadW
+VS
+VS
RG
-VS
RF
5.11 W
27pF
Ferrite
Bead
FIN
THS3122
THS3125
www.ti.com
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
Placing a small series resistor, RISO, between the Figure 44 shows another method used to maintain
amplifier output and the capacitive load, as shown in the low-frequency load independence of the amplifier
Figure 42, is an easy way of isolating the load while isolating the phase shift caused by the
capacitance. capacitance at high frequency. At low frequency,
feedback is mainly from the load side of RISO. At high
frequency, the feedback is mainly via the 27-pF
capacitor. The resistor RIN in series with the negative
input is used to stabilize the amplifier and should be
equal to the recommended value of RFat unity gain.
Replacing RIN with a ferrite of similar impedance at
about 100 MHz as shown in Figure 45 gives similar
results with reduced dc offset and low frequency
noise.
Figure 42. Resistor to Isolate Capacitive Load
Using a ferrite chip in place of RISO,asFigure 43
shows, is another approach of isolating the output of
the amplifier. The ferrite impedance characteristic
versus frequency is useful to maintain the low
frequency load independence of the amplifier while
isolating the phase shift caused by the capacitance at
high frequency. Use a ferrite with similar impedance
to RISO, 20 Ωto 50 Ω, at 100 MHz and low Figure 44. Feedback Technique with Input
impedance at dc. Resistor for Capacitive Load
Figure 43. Ferrite Bead to Isolate Capacitive Load
Figure 45. Feedback Technique with Input Ferrite
Bead for Capacitive Load
©2001–2011, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): THS3122 THS3125
1nF
+VSRG
24.9 W
+VS
-VS
5.11 W
RF
RG
24.9 W
+VS
-VS
5.11 W
RF
+VS
-VS-VS
5.11 W
RF
2RG
+VS+VS
-VS
5.11 W
RF
THS3122
THS3125
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
www.ti.com
Figure 46 shows a configuration that uses two Saving Power with Shutdown Functionality
amplifiers in parallel to double the output drive current and Setting Threshold Levels with the
to larger capacitive loads. This technique is used Reference Pin
when more output current is needed to charge and The THS3125 features a shutdown pin
discharge the load faster as when driving large FET (SHUTDOWN) that lowers the quiescent current from
transistors. 8.4 mA/amp down to 370 µA/amp, ideal for reducing
system power.
The shutdown pin of the amplifier defaults to the REF
pin voltage in the absence of an applied voltage,
putting the amplifier in the normal on mode of
operation. To turn off the amplifier in an effort to
conserve power, the shutdown pin can be driven
towards the positive rail. The threshold voltages for
power-on and power-down (or shutdown) are relative
to the supply rails and are given in the Shutdown
Characteristics (THS3125 Only) table. Below the
Enable threshold voltage, the device is on. Above the
Disable threshold voltage, the device is off. Behavior
between these threshold voltages is not specified.
Note that this shutdown functionality is self-defining:
the amplifier consumes less power in shutdown
mode. The shutdown mode is not intended to provide
a high-impedance output. In other words, the
shutdown functionality is not intended to allow use as
Figure 46. Parallel Amplifiers for Higher Output a 3-state bus driver. When in shutdown mode, the
Drive impedance looking back into the output of the
amplifier is dominated by the feedback and gain
setting resistors, but the output impedance of the
Figure 47 shows a push-pull FET driver circuit typical device itself varies depending on the voltage applied
of ultrasound applications with isolation resistors to to the outputs.
isolate the gate capacitance from the amplifier. As with most current feedback amplifiers, the internal
architecture places some limitations on the system
when in shutdown mode. Most notably is the fact that
the amplifier actually turns on if there is a ±0.7 V or
greater difference between the two input nodes (IN+
and IN–) of the amplifier. If this difference exceeds
±0.7 V, the output of the amplifier creates an output
voltage equal to approximately [(IN+ –IN–)–0.7V] ×
Gain. Also, if a voltage is applied to the output while
in shutdown mode, the IN–node voltage is equal to
VO(applied) ×RG/(RF+ RG) . For low gain configurations
and a large applied voltage at the output, the
amplifier may actually turn on because of the
behavior described here.
The time delays associated with turning the device on
and off are specified as the time it takes for the
amplifier to reach either 10% or 90% of the final
output voltage. The time delays are in the order of
microseconds because the amplifier moves in and out
Figure 47. PowerFET Drive Circuit of the linear mode of operation in these transitions.
space
space
14 Submit Documentation Feedback ©2001–2011, Texas Instruments Incorporated
Product Folder Link(s): THS3122 THS3125
THS3122
THS3125
www.ti.com
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
Power-Down Reference Pin Operation Printed-Circuit Board Layout Techniques for
Optimal Performance
In addition to the shutdown pin, the THS3125
features a reference pin (REF) which allows the user Achieving optimum performance with high-frequency
to control the enable or disable power-down voltage amplifiers such as the THS3125 and THS3122
levels applied to the SHUTDOWN pin. In most requires careful attention to board layout parasitic and
split-supply applications, the reference pin is external component types. Recommendations that
connected to ground. In either case, the user must be optimize performance include:
aware of voltage-level thresholds that apply to the •Minimize parasitic capacitance to any ac ground
shutdown pin. Table 2 shows examples and illustrate for all of the signal I/O pins. Parasitic capacitance
the relationship between the reference voltage and on the output and input pins can cause instability.
the power-down thresholds. In the table, the threshold To reduce unwanted capacitance, a window
levels are derived by the following equations: around the signal I/O pins should be opened in all
of the ground and power planes around those
SHUTDOWN ≤REF + 0.8 V for enable pins. Otherwise, ground and power planes should
SHUTDOWN ≥REF + 2V for disable be unbroken elsewhere on the board.
Where the usable range at the REF pin is: •Minimize the distance [0.25 inch, (6,4 mm)] from
the power-supply pins to high-frequency 0.1-µF
VCC–≤VREF ≤(VCC+ –4V) and 100-pF decoupling capacitors. At the device
The recommended mode of operation is to tie the pins, the ground and power plane layout should
REF pin to midrail, therefore setting the not be in close proximity to the signal I/O pins.
enable/disable thresholds to V(midrail) + 0.8 V and Avoid narrow power and ground traces to
V(midrail) = 2 V, respectively. minimize inductance between the pins and the
decoupling capacitors. The power-supply
Table 2. Shutdown Threshold Voltage Levels connections should always be decoupled with
these capacitors. Larger (6.8 µF or more)
REFERENCE tantalum decoupling capacitors, effective at lower
SUPPLY PIN ENABLE DISABLE frequencies, should also be used on the main
VOLTAGE (V) VOLTAGE (V) LEVEL (V) LEVEL (V) supply pins. These capacitors may be placed
±15, ±5 0 0.8 2.0 somewhat farther from the device and may be
±15 2.0 2.8 4.0 shared among several devices in the same area
±15 –2.0 –1.2 0 of the printed circuit board (PCB).
±5 1.0 1.8 3.0 •Careful selection and placement of external
±5–1.0 –0.2 1.0 components preserve the high-frequency
+30 15.0 15.8 17 performance of the THS3125 and THS3122.
Resistors should be a very low reactance type.
+10 5.0 5.8 7.0 Surface-mount resistors work best and allow a
tighter overall layout. Again, keep the leads and
Note that if the REF pin is left unterminated, it floats PCB trace length as short as possible. Never use
to the positive rail and falls outside of the wirebound type resistors in a high-frequency
recommended operating range given above VCC–≤application. Because the output pin and inverting
VREF ≤(VCC+ –4V). As a result, it no longer serves as input pins are the most sensitive to parasitic
a reliable reference for the SHUTDOWN pin, and the capacitance, always position the feedback and
enable/disable thresholds given above no longer series output resistors, if any, as close as possible
apply. If the SHUTDOWN pin is also left to the inverting input pins and output pins. Other
unterminated, it floats to the positive rail and the network components, such as input termination
device is disabled. If balanced, split supplies are used resistors, should be placed close to the
(±VS) and the REF and SHUTDOWN pins are gain-setting resistors. Even with a low parasitic
grounded, the device is enabled. capacitance that shunts the external resistors,
space excessively high resistor values can create
significant time constants that can degrade
space performance. Good axial metal-film or
space surface-mount resistors have approximately 0.2
pF in shunt with the resistor. For resistor values
greater than 2.0 kΩ, this parasitic capacitance can
add a pole and/or a zero that can affect circuit
operation. Keep resistor values as low as
possible, consistent with load driving
considerations.
©2001–2011, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): THS3122 THS3125
DIE
DIE
Thermal
Pad
(a) SideView
(c) BottomView
(b) EndView
THS3122
THS3125
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
www.ti.com
•
Connections to other wideband devices on the •Socketing a high-speed device such as the
board may be made with short direct traces or THS3125 and THS3122 is not recommended. The
through onboard transmission lines. For short additional lead length and pin-to-pin capacitance
connections, consider the trace and the input to introduced by the socket can create an extremely
the next device as a lumped capacitive load. troublesome parasitic network which can make it
Relatively wide traces [0.05 inch (1,3 mm) to 0.1 almost impossible to achieve a smooth, stable
inch (2,54 mm)] should be used, preferably with frequency response. Best results are obtained by
ground and power planes opened up around soldering the THS3125/THS3122 amplifiers
them. Estimate the total capacitive load and directly onto the board.
determine if isolation resistors on the outputs are
necessary. Low parasitic capacitive loads (less PowerPAD™Design Considerations
than 4 pF) may not need an RSbecause the The THS3125 and THS3122 are available in a
THS3125 and THS3122 are nominally thermally-enhanced PowerPAD family of packages.
compensated to operate with a 2-pF parasitic These packages are constructed using a downset
load. Higher parasitic capacitive loads without an leadframe upon which the die is mounted [see
RSare allowed as the signal gain increases (thus Figure 48(a) and Figure 48(b)]. This arrangement
increasing the unloaded phase margin). If a long results in the lead frame being exposed as a thermal
trace is required, and the 6-dB signal loss intrinsic pad on the underside of the package [see
to a doubly-terminated transmission line is Figure 48(c)]. Because this thermal pad has direct
acceptable, implement a matched-impedance thermal contact with the die, excellent thermal
transmission line using microstrip or stripline performance can be achieved by providing a good
techniques (consult an ECL design handbook for thermal path away from the thermal pad. Note that
microstrip and stripline layout techniques). A 50-Ωdevices such as the THS312x have no electrical
environment is not necessary onboard, and in connection between the PowerPAD and the die.
fact, a higher impedance environment improves
distortion as shown in the distortion versus load
plots. With a characteristic board trace impedance
based on board material and trace dimensions, a
matching series resistor into the trace from the
output of the THS3125/THS3122 is used as well
as a terminating shunt resistor at the input of the
destination device. Remember also that the
terminating impedance is the parallel combination
of the shunt resistor and the input impedance of Figure 48. Views of Thermally-Enhanced Package
the destination device: this total effective
impedance should be set to match the trace
impedance. If the 6-dB attenuation of a The PowerPAD package allows for both assembly
doubly-terminated transmission line is and thermal management in one manufacturing
unacceptable, a long trace can be operation. During the surface-mount solder operation
series-terminated at the source end only. Treat (when the leads are being soldered), the thermal pad
the trace as a capacitive load in this case. This can also be soldered to a copper area underneath the
configuration does not preserve signal integrity as package. Through the use of thermal paths within this
well as a doubly-terminated line. If the input copper area, heat can be conducted away from the
impedance of the destination device is low, there package into either a ground plane or other heat
is some signal attenuation as a result of the dissipating device.
voltage divider formed by the series output into The PowerPAD package represents a breakthrough
the terminating impedance. in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward
mechanical methods of heatsinking.
16 Submit Documentation Feedback ©2001–2011, Texas Instruments Incorporated
Product Folder Link(s): THS3122 THS3125
0.205
(5,21)
0.060
(1,52)
0.013
(0,33)
0.017
(0,432)
0.025
(0,64)
0.094
(2,39)
0.040
(1,01)
0.035
(0,89)
0.075
(1,91)
0.010
vias
(0,254)
0.030
(0,76)
Pin1
TopView
P =
DMax
T T-
max A
qJA
THS3122
THS3125
www.ti.com
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
PowerPAD™Layout Considerations transfer. Therefore, the holes under the
THS3125/THS3122 PowerPAD package should
make the connection to the internal ground plane
with a complete connection around the entire
circumference of the plated-through hole.
6. The top-side solder mask should leave the
terminals of the package and the thermal pad
area with its five holes exposed. The bottom-side
solder mask should cover the five holes of the
thermal pad area. This configuration prevents
solder from being pulled away from the thermal
pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
8. With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard
surface-mount component. This procedure results
Dimensions are in inches (millimeters). in a part that is properly installed.
Figure 49. DGN PowerPAD PCB Etch and Via Power Dissipation and Thermal
Pattern Considerations
Although there are many ways to properly heatsink The THS3125 and THS3122 incorporate automatic
the PowerPAD package, the following steps illustrate thermal shutoff protection. This protection circuitry
the recommended approach. shuts down the amplifier if the junction temperature
exceeds approximately +160°C. When the junction
1. PCB with a top side etch pattern as shown in temperature reduces to approximately +140°C, the
Figure 49.amplifier turns on again. However, for maximum
2. Place five holes in the area of the thermal pad. performance and reliability, the designer must take
These holes should be 0.01 inch (0,254 mm) in care to ensure that the design does not exceed a
diameter. Keep them small so that solder wicking junction temperature of +125°C. Between +125°C
through the holes is not a problem during reflow. and +150°C, damage does not occur, but the
3. Additional vias may be placed anywhere along performance of the amplifier begins to degrade and
the thermal plane outside of the thermal pad long-term reliability suffers. The thermal
area. These vias help dissipate the heat characteristics of the device are dictated by the
generated by the THS3125/THS3122 IC. These package and the PCB. Maximum power dissipation
additional vias may be larger than the 0.01-inch for a given package can be calculated using the
(0,254-mm) diameter vias directly under the following formula.
thermal pad. They can be larger because they
are not in the thermal pad area to be soldered so
that wicking is not a problem.
4. Connect all holes to the internal ground plane. where:
Note that the PowerPAD is electrically isolated •PDMax is the maximum power dissipation in the
from the silicon and all leads. Connecting the amplifier (W)
PowerPAD to any potential voltage, such as VS–,•Tmax is the absolute maximum junction
is acceptable as there is no electrical connection temperature (°C)
to the silicon. •TAis the ambient temperature (°C)
5. When connecting these holes to the ground θJA =θJC +θCA
plane, do not use the typical web or spoke via
connection methodology. Web connections have where:
a high thermal resistance connection that is • θJC is the thermal coefficient from the silicon
useful for slowing the heat transfer during junctions to the case (°C/W)
soldering operations. This resistance makes the • θCA is the thermal coefficient from the case to
soldering of vias that have plane connections ambient air (°C/W)
easier. In this application; however, low thermal
resistance is desired for the most efficient heat
©2001–2011, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): THS3122 THS3125
-40 -20 0 20 40 60 80 100
T Free-AirTemperature( C)-
A°
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
P MaximumPowerDissipation(W)
DMax -
T =+125
JC°
q=158 /W
JA C°
q=95 /W
JA C°
q=58.4 /W
JA C°
THS3122
THS3125
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
www.ti.com
For systems where heat dissipation is more critical,
the THS3125 and THS3122 are also available in an
8-pin MSOP with PowerPAD package that offers
even better thermal performance. The thermal
coefficient for the PowerPAD packages are
substantially improved over the traditional SOIC.
Maximum power dissipation levels are depicted in
Figure 50 for the available packages. The data for the
PowerPAD packages assume a board layout that
follows the PowerPAD layout guidelines discussed
above and detailed in the PowerPAD application note
(literature number SLMA002). Figure 50 also
illustrates the effect of not soldering the PowerPAD to
a PCB. The thermal impedance increases
substantially, which may cause serious heat and
performance issues. Always solder the PowerPAD to Results shown are with no air flow and PCB size of 3 in ×3 in
the PCB for optimum performance. (76,2 mm ×76,2 mm).
When determining whether or not the device satisfies • θJA = 58.4°C/W for 8-pin MSOP with PowerPAD (DGN
the maximum power dissipation requirement, it is package)
important to not only consider quiescent power • θJA = 95°C/W for 8-pin SOIC High-K test PCB (D package)
dissipation, but also dynamic power dissipation. Often • θJA = 158°C/W for 8-pin MSOP with PowerPAD without solder
times, this type of dissipation is difficult to quantify Figure 50. Maximum Power Dissipation vs
because the signal pattern is inconsistent, but an Ambient Temperature
estimate of the RMS power dissipation can provide
visibility into a possible problem.
18 Submit Documentation Feedback ©2001–2011, Texas Instruments Incorporated
Product Folder Link(s): THS3122 THS3125
THS3122
THS3125
www.ti.com
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (July, 2010) to Revision D Page
•Changed output current (absolute maximum) from 275 mA to 550 mA ............................................................................... 2
Changes from Revision B (October, 2009) to Revision C Page
•Corrected REF pin name for THS3125 shown in front-page figure ...................................................................................... 1
•Deleted Shutdown pin input levels parameters and specifications from Recommended Operating Conditions table ......... 3
•Updated Shutdown Characteristics table test conditions; changed GND to REF, corrected VSHDN notations ..................... 5
•Added VREF and VSHDN parameters and speciifications to Shutdown Characteristics table ................................................. 5
•Revised second and fourth paragraphs of Saving Power with Shutdown Functionality section ........................................ 14
•Updated equation in Power-Down Reference Pin Operation section that describes usable range at the REF pin ........... 15
•Revised paragraph in Power-Down Reference Pin Operation that discusses behavior of unterminated REF pin ............ 15
©2001–2011, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): THS3122 THS3125
PACKAGE OPTION ADDENDUM
www.ti.com 20-Aug-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
THS3122CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3122CDDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM
THS3122CDDAG3 ACTIVE SO PowerPAD DDA 8 75 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM
THS3122CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3122CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3122CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3122ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3122IDDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM
THS3122IDDAG3 ACTIVE SO PowerPAD DDA 8 75 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM
THS3122IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3125CPWP ACTIVE HTSSOP PWP 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
THS3125CPWPG4 ACTIVE HTSSOP PWP 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
THS3125ID ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3125IDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS3125IPWP ACTIVE HTSSOP PWP 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
THS3125IPWPG4 ACTIVE HTSSOP PWP 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
THS3125IPWPR ACTIVE HTSSOP PWP 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 20-Aug-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
THS3125IPWPRG4 ACTIVE HTSSOP PWP 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
THS3122CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
THS3125IPWPR HTSSOP PWP 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
THS3122CDR SOIC D 8 2500 367.0 367.0 35.0
THS3125IPWPR HTSSOP PWP 14 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated