THS3122 THS3125 SLOS382D - SEPTEMBER 2001 - REVISED FEBRUARY 2011 www.ti.com LOW-NOISE, HIGH-SPEED, 450-mA CURRENT FEEDBACK AMPLIFIERS Check for Samples: THS3122, THS3125 FEATURES APPLICATIONS * * * * * * 1 23 * * * * * * Low Noise: - 2.9-pA/Hz Noninverting Current Noise - 10.8-pA/Hz Inverting Current Noise - 2.2-nV/Hz Voltage Noise - 128-MHz , -3-dB BW (RL = 50 , RF = 470 ) - 1550-V/s Slew Rate (G = 2, RL= 50 ) High Output Current: 450 mA High Speed: - 128-MHz , -3-dB BW (RL = 50 , RF = 470 ) - 1550-V/s Slew Rate (G = 2, RL= 50 ) - 26-VPP Output Voltage, RL= 50 - -80 dBc (1 MHz, 2 VPP, G = 2) Wide Output Swing: - 26-VPP Output Voltage, RL= 50 - -80 dBc (1 MHz, 2 VPP, G = 2) - 370-A Shutdown Supply Current Low Distortion: - -80 dBc (1 MHz, 2 VPP, G = 2) - 370-A Shutdown Supply Current Low-Power Shutdown Mode (THS3125) - 370-A Shutdown Supply Current Standard SOIC, SOIC PowerPADTM, and TSSOP PowerPAD Packages VOLTAGE NOISE AND CURRENT NOISE vs FREQUENCY Vn - Voltage Noise - nV/?Hz In - Current Noise - pA/?Hz 100 VCC = 5 V to 15 V TA = +25C In+ 10 Vn DESCRIPTION The THS3122/5 are low-noise, high-speed current feedback amplifiers, with high output current drive. This makes them ideal for any application that requires low distortion over a wide frequency with heavy loads. The THS3122/5 can drive four serially-terminated video lines while maintaining a differential gain error less than 0.03%. The high output drive capability of the THS3122/5 enables the devices to drive 50- loads with low distortion over a wide range of output voltages: * -80-dBc THD at 2 VPP * -75-dBc THD at 8 VPP The THS3122/5 can operate from 5-V to 15-V supply voltages while drawing as little as 7.2 mA of supply current per channel. The THS3125 offers a low-power shutdown mode, reducing the supply current to only 370 A. The THS3122/5 are packaged in a standard SOIC, SOIC PowerPADTM, and TSSOP PowerPAD packages. THS3122 SOIC (D) AND SOIC PowerPAD? (DDA) PACKAGE (TOP VIEW) 1 OUT 1 IN- 1 IN+ VCC- In- Video Distribution Instrumentation Line Drivers Motor Drivers Piezo Drivers 1 8 2 7 3 6 4 5 VCC+ 2 OUT 2 IN- 2 IN+ THS3125 SOIC (D) AND TSSOP PowerPAD? (PWP) PACKAGE (TOP VIEW) 1 OUT 1 IN- 1 IN+ VCC- N/C REF N/C 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC+ 2 OUT 2 IN- 2 IN+ N/C SHUTDOWN N/C 1 0.01 0.1 1 10 f - Frequency - kHz 100 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. (c) 2001-2011, Texas Instruments Incorporated THS3122 THS3125 SLOS382D - SEPTEMBER 2001 - REVISED FEBRUARY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. AVAILABLE OPTIONS (1) PACKAGED DEVICE (1) EVALUATION MODULES TA SOIC-8 (D) SOIC-8 PowerPAD (DDA) SOIC-14 (D) TSSOP-14 (PWP) 0C to +70C THS3122CD THS3122CDDA THS3125CD THS3125CPWP 40C to +85C THS3122ID THS3122IDDA THS3125ID THS3125IPWP THS3122EVM THS3125EVM For the most current specification and package information, refer to the Package Option Addendum located at the end of this data sheet or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature (unless otherwise noted). UNIT Supply voltage, VCC+ to VCC- 33 V VCC Input voltage Output current (see (2) ) 550 mA 4 V Differential input voltage Maximum junction temperature +150C Total power dissipation at (or below) +25C free-air temperature Commercial Operating free-air temperature, TA Storage temperature, Tstg (1) (2) See Dissipation Ratings Table 0C to +70C Industrial -40C to +85C Commercial -65C to +125C Industrial -65C to +125C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The THS3122 and THS3125 may incorporate a PowerPADTM on the underside of the chip. This pad acts as a heatsink and must be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI Technical Brief SLMA002 for more information about utilizing the PowerPADTM thermally-enhanced package. DISSIPATION RATING TABLE (1) 2 PACKAGE JA TA = +25C POWER RATING D-8 95C/W (1) 1.32 W DDA 67C/W 1.87 W D-14 66.6C/W (1) 1.88 W PWP 37.5C/W 3.3 W These data were taken using the JEDEC proposed high-K test PCB. For the JEDEC low-K test PCB, the JA is 168C/W for the D-8 package and 122.3C/W for the D-14 package. Submit Documentation Feedback (c) 2001-2011, Texas Instruments Incorporated Product Folder Link(s): THS3122 THS3125 THS3122 THS3125 SLOS382D - SEPTEMBER 2001 - REVISED FEBRUARY 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS MIN NOM Supply voltage, VCC+ to VCC- 5 15 Single supply 10 30 0 +70 -40 +85 C-suffix Operating free-air temperature, TA MAX Dual supply I-suffix UNIT V C ELECTRICAL CHARACTERISTICS Over operating free-air temperature range, TA = +25C, VCC = 15 V, RF = 750 , and RL = 100 (unless otherwise noted). DYNAMIC PERFORMANCE PARAMETER TEST CONDITIONS VCC= 15 V 160 VCC = 5 V 126 VCC= 15 V 128 VCC = 5 V 20 VCC= 15 V 30 VO(PP) = 4 V VCC = 5 V 47 VO(pp)= 20 V VCC= 15 V 64 VO= 10 VPP VCC = 15 V 1550 RL = 50 RF = 50 , G = 1 RL = 50 RF = 470 , G = 2 BW SR Full power bandwidth G = -1 Slew rate ts (1) RF = 470 , G = 2 (1) ,G=8 Settling time to 0.1% G = 2, RF = 680 G = -1 TYP MAX 138 Small-signal bandwidth (-3 dB) Bandwidth (0.1 dB) MIN VCC = 5 V VCC = 5 V 500 VCC= 15 V 1000 VO = 2 VPP VCC = 5 V 53 VO= 5 VPP VCC = 15 V 64 VO = 5 VPP UNIT MHz MHz V/s ns Slew rate is defined from the 25% to the 75% output levels. NOISE/DISTORTION PERFORMANCE PARAMETER THD Vn In TEST CONDITIONS Input current noise Noninverting Input Inverting Input G = 2, RF = 470 , VCC= 15 V, f = 1 MHz VO(PP) = 8 V -75 G = 2, RF = 470 , VCC= 5 V, f = 1 MHz VO(PP)= 2 V -77 VO(PP)= 5 V -76 VCC = 5 V, 15 V f = 10 kHz 2.2 VCC = 5 V, 15 V Crosstalk G = 2, f = 1 MHz, VO = 2 VPP Differential gain error G = 2, RL = 150 40 IRE modulation 100 IRE Ramp NTSC and PAL Differential phase error TYP MAX -80 Total harmonic distortion Input voltage noise MIN VO(PP) = 2 V f = 10 kHz 2.9 10.8 VCC = 5 V -67 VCC= 15 V -67 VCC = 5 V 0.01 VCC= 15 V 0.01 VCC = 5 V 0.011 VCC= 15 V 0.011 UNIT dBc nV/Hz pA/Hz dBc % degrees Submit Documentation Feedback (c) 2001-2011, Texas Instruments Incorporated Product Folder Link(s): THS3122 THS3125 3 THS3122 THS3125 SLOS382D - SEPTEMBER 2001 - REVISED FEBRUARY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over operating free-air temperature range, TA = +25C, VCC = 15 V, RF = 750 , and RL = 100 (unless otherwise noted). DC PERFORMANCE PARAMETER TEST CONDITIONS Input offset voltage VIO MIN TA = +25C TYP MAX 6 10 TA = full range Channel offset voltage matching VIC = 0 V, VO = 0 V, VCC = 5 V, VCC = 15 V 13 TA = +25C 1 TA = full range Offset drift 6 TA = full range VIC = 0 V, VO = 0 V, VCC = 5 V, VCC = 15 V 0.33 TA = full range IIO Input offset current VIC = 0 V, VO = 0 V, VCC = 5 V, VCC = 15 V TA = +25C ZOL Open-loop transimpedance VCC = 5 V, VCC = 15 V RL = 1 k 23 30 TA = +25C IN+ Input bias current V/C 10 TA = +25C IN- Input bias current mV 4 TA = full range IIB 3 UNIT 2 A 3 5.4 TA = full range 22 30 1 A M INPUT CHARACTERISTICS PARAMETER TEST CONDITIONS VCC = 5 V VICR CMRR Input common-mode voltage range TA = full range VCC= 15 V Input resistance CI Input capacitance TYP 2.5 2.7 12. 5 12. 7 62 VCC = 5 V, VI = -2.5 V to 2.5 V TA = +25C 58 TA = full range 56 VCC = 15 V, VI = -12.5 V to 12.5 V TA = +25C 63 TA = full range 60 Common-mode rejection ratio RI MIN MAX UNIT V dB 67 IN+ 1.5 IN- 15 M 2 pF OUTPUT CHARACTERISTICS PARAMETER TEST CONDITIONS G = 4, VO Output voltage swing VI = 1.06 V, VCC = 5 V RL = 1 k MIN TA = +25C 3.8 3.7 VI = 1.025 V, VCC= 5 V, RL = 50 TA = full range G = 4, VI = 3.6 V, VCC= 15 V, RL = 1 k TA = +25C TA = +25C IO Output current drive ro Output resistance 4 4.1 TA = +25C G = 4, TYP MAX UNIT V 4 V 14.2 12 13.3 G = 4, VI = 3.325 V, VCC= 15 V, RL = 50 TA = full range 11.5 G = 4, VI = 1.025 V, VCC= 5 V, RL = 10 TA = +25C 200 280 mA G = 4, VI = 3.325 V, VCC = 15 V, RL = 25 TA = +25C 360 440 mA 14 Open loop TA = +25C Submit Documentation Feedback V (c) 2001-2011, Texas Instruments Incorporated Product Folder Link(s): THS3122 THS3125 THS3122 THS3125 SLOS382D - SEPTEMBER 2001 - REVISED FEBRUARY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over operating free-air temperature range, TA = +25C, VCC = 15 V, RF = 750 , and RL = 100 (unless otherwise noted). POWER SUPPLY PARAMETER TEST CONDITIONS VCC = 5 V ICC TYP MAX 7.2 9 8.4 10.5 TA = full range Quiescent current (per channel) 10 TA = +25C VCC = 15 V TA = full range VCC = 5 V 1 V PSRR MIN TA = +25C Power-supply rejection ratio VCC = 15 V 1 V UNIT mA 11.5 TA = +25C 53 TA = full range 50 TA = +25C 60 TA = full range 55 60 dB 69 SHUTDOWN CHARACTERISTICS (THS3125 Only) PARAMETER ICC(SHDN) TEST CONDITIONS Shutdown quiescent current (per channel) VSHDN = 3.3 V (1) tDIS Disable time tEN Enable time (1) IIL(SHDN) Shutdown pin low level leakage current VSHDN = 0 V IIH(SHDN) Shutdown pin high level leakage current VSHDN = 3.3 V VREF REF pin voltage level VSHDN (1) MIN SHUTDOWN pin voltage level TYP MAX UNIT 370 500 A s 500 REF = 0 V, VCC= 5 V to 15 V s 200 18 110 VCC- Enable Disable 25 A 130 A VCC+ -4 V REF+0.8 REF+2 V Disable/enable time is defined as the time from when the shutdown signal is applied to the SHDN pin to when the supply current has reached half of its final value. TYPICAL CHARACTERISTICS TABLE OF GRAPHS FIGURE Small-signal closed-loop gain vs Frequency Small- and large-signal output vs Frequency Figure 11, Figure 12 vs Frequency Figure 13 to Figure 15 Harmonic distortion vs Peak-to-peak output voltage Figure 1 to Figure 10 Figure 16, Figure 17 Vn, In Voltage noise and current noise vs Frequency Figure 18 CMRR Common-mode rejection ratio vs Frequency Figure 19 Crosstalk vs Frequency Figure 20 Zo Output impedance vs Frequency Figure 21 SR Slew rate vs Output voltage step Figure 22 vs Free-air temperature Figure 24 VIO Input offset voltage vs Common-mode input voltage Figure 24 IB Input bias current vs Free-air temperature Figure 25 VO Output voltage vs Load current Figure 26 vs Free-air temperature Figure 27 vs Supply voltage Figure 28 Quiescent current ICC Shutdown supply current vs Free-air temperature Differential gain and phase error vs 75- serially terminated loads Shutdown response Figure 29 Figure 30, Figure 31 Figure 32 Small-signal pulse response Figure 33, Figure 34 Large-signal pulse response Figure 35, Figure 36 Submit Documentation Feedback (c) 2001-2011, Texas Instruments Incorporated Product Folder Link(s): THS3122 THS3125 5 THS3122 THS3125 SLOS382D - SEPTEMBER 2001 - REVISED FEBRUARY 2011 www.ti.com TYPICAL CHARACTERISTICS SMALL-SIGNAL CLOSED-LOOP GAIN vs FREQUENCY RF = 680 -6 RF = 500 -9 -12 -15 -18 -21 G = -1, VCC = 5 V, RL = 50 -24 -27 -30 0.1 1 10 100 -12 -15 -18 -21 G = -1, VCC = 15 V, RL = 50 -24 -27 0 RF = 750 -1 RF = 560 -2 -3 -4 G = 1, VCC = 5 V, RL = 50 -5 -6 1 10 100 0.1 1000 1 10 100 1000 Figure 1. Figure 2. Figure 3. SMALL-SIGNAL CLOSED-LOOP GAIN vs FREQUENCY SMALL-SIGNAL CLOSED-LOOP GAIN vs FREQUENCY SMALL-SIGNAL CLOSED-LOOP GAIN vs FREQUENCY 9 RF = 560 -3 RF = 750 -6 -9 G = 1, VCC = 15 V, RL = 50 1 10 100 9 RF = 430 6 RF = 500 RF = 470 3 0 -3 G = 2, VCC = 5 V, RL = 50 -6 0.1 1000 Small Signal Closed Loop Gain - dB Small Signal Closed Loop Gain - dB 0 1 10 100 RF = 430 3 RF = 500 6 RF = 470 0 -3 G = 2, VCC = 15 V, RL = 50 -6 0.1 1000 1 10 100 1000 f - Frequency - MHz f - Frequency - MHz f - Frequency - MHz Figure 4. Figure 5. Figure 6. SMALL-SIGNAL CLOSED-LOOP GAIN vs FREQUENCY SMALL-SIGNAL CLOSED-LOOP GAIN vs FREQUENCY SMALL-SIGNAL CLOSED-LOOP GAIN vs FREQUENCY 15 9 RF = 270 6 RF = 390 3 0 -3 -6 -9 G = 4, VCC = 5 V, RL = 50 -18 0.1 1 10 100 1000 15 RF = 200 12 Small Signal Closed Loop Gain - dB RF = 200 12 Small Signal Closed Loop Gain - dB Small Signal Closed Loop Gain - dB RF = 330 -9 f - Frequency - MHz 15 Small Signal Closed Loop Gain - dB RF = 500 -6 f - Frequency - MHz -12 0.1 6 -3 RF = 470 1 f - Frequency - MHz RF = 470 -15 RF = 680 -30 0.1 1000 3 -12 2 0 Small Signal Closed Loop Gain - dB 0 -3 SMALL-SIGNAL CLOSED-LOOP GAIN vs FREQUENCY 3 RF = 330 3 Small Signal Closed Loop Gain - dB Small Signal Closed Loop Gain - dB 6 SMALL-SIGNAL CLOSED-LOOP GAIN vs FREQUENCY 9 RF = 270 6 RF = 390 3 0 -3 -6 -9 -12 -15 -18 0.1 G = 4, VCC = 15 V, RL = 50 1 10 100 f - Frequency - MHz f - Frequency - MHz Figure 7. Figure 8. 1000 Submit Documentation Feedback 12 RF = 200 9 6 RF = 470 3 0 RF = 560 -3 -6 VCC = 5 V, RL = 50 -9 -12 0.1 1 10 100 1000 f - Frequency - MHz Figure 9. (c) 2001-2011, Texas Instruments Incorporated Product Folder Link(s): THS3122 THS3125 THS3122 THS3125 SLOS382D - SEPTEMBER 2001 - REVISED FEBRUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) SMALL- AND LARGE-SIGNAL OUTPUT vs FREQUENCY 18 RF = 200 12 Small and Large Signal Output - dB 9 RF = 470 6 3 RF = 560 0 -3 -6 VCC = 15 V, RL = 50 -9 12 2 VPP 6 1 VPP 0 0.5 VPP -6 0.25 VPP -12 0.125 VPP -18 -24 -12 0.1 1 10 100 0.1 1000 100 2 VPP 6 1 VPP 0 0.5 VPP -6 0.25 VPP -12 0.125 VPP -18 -24 0.1 1000 100 Figure 11. Figure 12. HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs FREQUENCY 5th Harmonic -50 -60 2nd Harmonic -80 -90 1 -30 2nd Harmonic -40 3rd Harmonic -50 5th Harmonic -60 -70 -80 4th Harmonic -90 4th Harmonic -100 0.1 -20 10 -100 0.1 100 G = 2, VCC = 15 V, VO(PP) = 8 V, RF = 470 , RL = 50 -10 Harmonic Distortion - dB Harmonic Distortion - dB 3rd Harmonic 1000 0 G = 2, VCC = 15 V, VO(PP) = 2 V, RF = 470 , RL = 50 -10 -40 -70 10 Figure 10. 0 -30 1 f - Frequency - MHz G = 2, VCC = 5 V, VO(PP) = 2 V, RF = 470 , RL = 50 -20 G = 2, VCC = 15 V, RL = 680 ,RL = 50 4 VPP 12 f - Frequency - MHz 0 -10 1 10 -20 -30 -40 -50 3rd Harmonic -60 2nd Harmonic -70 5th Harmonic -80 -90 4th Harmonic -100 0.1 100 1 10 f - Frequency - MHz f - Frequency - MHz f - Frequency - MHz Figure 13. Figure 14. Figure 15. HARMONIC DISTORTION vs PEAK-TO-PEAK OUTPUT VOLTAGE HARMONIC DISTORTION vs PEAK-TO-PEAK OUTPUT VOLTAGE VOLTAGE NOISE AND CURRENT NOISE vs FREQUENCY 0 100 0 -30 Harmonic Distortion - dB -20 -40 -50 5th Harmonic 2nd Harmonic -60 3rd Harmonic -70 G = 2, VCC = 15 V, f = 1 MHz, RF = 470 , RL = 50 -10 -80 -20 -30 -40 -50 5th Harmonic -60 2nd Harmonic -70 3rd Harmonic -80 VCC = 5 V to 15 V TA = 25C In- In+ 10 Vn -90 -90 4th Harmonic 4th Harmonic -100 Hz G = 2, VCC = 5 V, f = 1 MHz, RF = 470 , RL = 50 -10 I n - Current Noise - pA/ Hz Harmonic Distortion - dB 10 1 f - Frequency - MHz Harmonic Distortion - dB 18 G = 2, VCC = 5 V, RL = 680 , RL = 50 4 VPP V n - Voltage Noise - nV/ Small Signal Closed Loop Gain - dB 15 SMALL- AND LARGE-SIGNAL OUTPUT vs FREQUENCY Small and Large Signal Output - dB SMALL-SIGNAL CLOSED-LOOP GAIN vs FREQUENCY 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 VPP - Peak-to-Peak Output Voltage - V Figure 16. 5 1 -100 0 1 2 3 4 5 6 7 8 9 VPP - Peak-to-Peak Output Voltage - V Figure 17. 0.01 0.1 1 10 Figure 18. Submit Documentation Feedback (c) 2001-2011, Texas Instruments Incorporated Product Folder Link(s): THS3122 THS3125 100 f - Frequency - kHz 7 THS3122 THS3125 SLOS382D - SEPTEMBER 2001 - REVISED FEBRUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) CROSSTALK vs FREQUENCY 80 -10 VCC = 15 V -20 60 50 VCC = 5 V 40 30 10 0 0.1 -40 -50 -60 1 10 1 0.1 100 -80 0.1 1000 1 10 100 0.01 1000 0.1 Figure 20. Figure 21. SLEW RATE vs OUTPUT VOLTAGE STEP INPUT OFFSET VOLTAGE vs FREE-AIR TEMPERATURE INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE 2 800 600 VCC = 5 V 200 1 2 3 4 5 6 7 8 VCC = 15 V, VCM = 0 V, RL = 100 1 2 3 4 5 6 VCC = 15 V, RL = 100 , TA = 25C 1.5 1 0.5 0 -0.5 -1 -1.5 7 -40 9 10 VIO - Input Offset Voltage - mV VIO - Input Offset Voltage - mV VCC = 15 V -15 10 35 60 -2 -15 85 TA - Free-Air Temperature - C VO - Output Voltage Step - V -10 -5 0 5 10 Figure 24. INPUT BIAS CURRENT vs FREE-AIR TEMPERATURE OUTPUT VOLTAGE vs LOAD CURRENT QUIESCENT CURRENT vs FREE-AIR TEMPERATURE VCC = 15 V, IIB+ 14 VO - Output Voltage - V 10 8 VCC = 15 V, IIB- 6 VCC = 5 V, IIB+ VCC = 5 V, IIB- 13 12 VCC = 15 V, RF = 330 , TA = 25C 11 0 10 -15 10 35 60 85 0 50 100 150 200 250 300 350 400 450 TA - Free-Air Temperature - C IL - Load Current - mA Figure 25. Figure 26. Submit Documentation Feedback I CC - Quiescent Current - mA/ Per Channel Figure 23. 15 15 VCM - Common-Mode Input Voltage - V Figure 22. 12 -2 -40 1000 Figure 19. 1000 2 100 f - Frequency - MHz 1200 4 10 f - Frequency - MHz 0 0 1 f - Frequency - MHz 400 I IB - Input Bias Current - A 10 -70 G = 2, RF = 470 , RL = 50 , TA = 25C 1400 0 VCC = 5 V, 15 V RF = 1 k, -30 G = 2, RF = 470 , RL = 50 , TA = 25C 20 1600 SR - Slew Rate - V/ s 100 G = 2, VCC = 5 V, 15 V RF = 470 , RL = 50 , ZO - Output Impedance - 70 1800 8 OUTPUT IMPEDANCE vs FREQUENCY 0 Crosstalk - dBc CMRR - Common-Mode Rejection Ratio - dB COMMON-MODE REJECTION RATIO vs FREQUENCY 12 VCC = 15 V 10 8 VCC = 5 V 6 4 2 0 -40 -15 10 35 60 85 TA - Free-Air Temperature - C Figure 27. (c) 2001-2011, Texas Instruments Incorporated Product Folder Link(s): THS3122 THS3125 THS3122 THS3125 SLOS382D - SEPTEMBER 2001 - REVISED FEBRUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) QUIESCENT CURRENT vs SUPPLY VOLTAGE SHUTDOWN SUPPLY CURRENT vs FREE-AIR TEMPERATURE 450 12 8 25 C 6 -40 C Shutdown Supply Current - A I CC - Quiescent Current - mA VSD = 3.3 V RF = 750 400 85 C 10 4 2 350 VCC = 15 V 300 250 VCC = 5 V 200 150 100 50 0 0 0 2.5 5 7.5 10 12.5 -40 15 10 35 60 85 Figure 28. Figure 29. DIFFERENTIAL PHASE AND GAIN ERROR vs 75- SERIALLY-TERMINATED LOADS DIFFERENTIAL PHASE AND GAIN ERROR vs 75- SERIALLY-TERMINATED LOADS 0.06 0.3 0.25 0.05 0.2 Gain Error 0.04 Phase Error 0.15 0.03 0.1 0.02 0.05 0.01 0.2 VO - Output Voltage - V 0.07 0.3 0.35 VCC = 5 V, G = 2, 40 IRE Modulation 100 IRE Ramp NTSC Differential Phase Error - Degree 0.08 Differenrtial Gain Error - % -15 TA - Free-Air Temperature - C VCC - Supply Voltage - V 1 2 3 4 5 6 7 0 -0.1 VCC = 5 V, G = 2, RF = 470 , RL = 50 -0.2 0 0 0.1 -0.3 8 0 100 200 300 400 500 600 t - Time - ns Figure 30. Figure 31. THS3125 SHUTDOWN RESPONSE THS3125 SHUTDOWN RESPONSE 5 0.3 4 2 1 0 2 1.5 1 0.5 0 0 1 2 3 4 5 6 7 8 9 10 VO - Output Voltage - V 0.2 3 Shutdown Pulse - V VO - Output Voltage - V 75 Serially Terminated Loads 0.1 0 -0.1 VCC = 5 V, G = 2, RF = 470 , RL = 50 -0.2 -0.3 0 100 200 300 400 500 600 t - Time - ns t - Time - ns Figure 32. Figure 33. Submit Documentation Feedback (c) 2001-2011, Texas Instruments Incorporated Product Folder Link(s): THS3122 THS3125 9 THS3122 THS3125 SLOS382D - SEPTEMBER 2001 - REVISED FEBRUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) LARGE-SIGNAL PULSE RESPONSE 3 3 0.2 2 2 0.1 0 -0.1 VCC = 15 V, G = 2, RF = 470 , RL = 50 -0.2 0 -1 VCC = 5 V, G = 2, RF = 470 , RL = 50 100 200 300 400 500 600 1 0 -1 -3 0 100 200 300 VCC = 15 V, G = 2, RF = 470 , RL = 50 -2 -3 0 10 1 -2 -0.3 VO - Output Voltage - V LARGE-SIGNAL PULSE RESPONSE 0.3 VO - Output Voltage - V VO - Output Voltage - V SMALL-SIGNAL PULSE RESPONSE 400 500 600 0 100 200 300 400 t - Time - ns t - Time - ns t - Time - ns Figure 34. Figure 35. Figure 36. Submit Documentation Feedback 500 600 (c) 2001-2011, Texas Instruments Incorporated Product Folder Link(s): THS3122 THS3125 THS3122 THS3125 SLOS382D - SEPTEMBER 2001 - REVISED FEBRUARY 2011 www.ti.com APPLICATION INFORMATION Maximum Slew Rate for Repetitive Signals The THS3125 and THS3122 are recommended for high slew rate pulsed applications where the internal nodes of the amplifier have time to stabilize between pulses. It is recommended to have at least 20-ns delay between pulses. The THS3125 and THS3122 are not recommended for applications with repetitive signals (sine, square, sawtooth, or other) that exceed 900 V/s. Using the part in these applications results in excessive current draw from the power supply and possible device damage. For applications with high slew rate, repetitive signals, the THS3091 and THS3095 (single versions), or THS3092 and THS3096 (dual versions) are recommended. Current-feedback amplifiers are highly dependent on the feedback resistor RF for maximum performance and stability. Table 1 shows the optimal gain setting resistors RF and RG at different gains to give maximum bandwidth with minimal peaking in the frequency response. Higher bandwidths can be achieved, at the expense of added peaking in the frequency response, by using even lower values for RF. Conversely, increasing RF decreases the bandwidth, but stability is improved. Table 1. Recommended Resistor Values for Optimum Frequency Response THS3125 and THS3122 RF and RG VALUES FOR MINIMAL PEAKING WITH RL = 50 , 5-V to 15-V POWER SUPPLY GAIN (V/V) RG () RF () 1 -- 560 2 470 470 4 66.5 200 Wideband, Noninverting Operation The THS3125 and THS3122 are unity gain stable 130-MHz current-feedback operational amplifiers, designed to operate from a 5-V to 15-V power supply. Figure 37 shows the THS3125 in a noninverting gain of 2-V/V configuration used to generate the typical characteristic curves. Most of the curves were characterized using signal sources with 50- source impedance and with measurement equipment that presents a 50- load impedance. Wideband, Inverting Operation Figure 38 shows the THS3125 in a typical inverting gain configuration where the input and output impedances from Figure 37 are retained in an inverting circuit configuration. +15 V +VS + +15 V +VS 49.9 W + 6.8 mF 0.1 mF 50-W Source VI 49.9 W 6.8 mF 0.1 mF 49.9 W 50-W Source RG 470 W THS3125 RF 56.2 W RM THS3125 50-W Load 470 W VI + 50-W Load 470 W -15 V -VS 0.1 mF 6.8 mF RF 470 W RG -15 V + -VS 0.1 mF 6.8 mF Figure 38. Wideband, Inverting Gain Configuration Figure 37. Wideband, Noninverting Gain Configuration Submit Documentation Feedback (c) 2001-2011, Texas Instruments Incorporated Product Folder Link(s): THS3122 THS3125 11 THS3122 THS3125 SLOS382D - SEPTEMBER 2001 - REVISED FEBRUARY 2011 www.ti.com Single-Supply Operation 470 W The THS3125 and THS3122 have the capability to operate from a single supply voltage ranging from 10 V to 30 V. When operating from a single power supply, biasing the input and output at mid-supply allows for the maximum output voltage swing. The circuits in Figure 39 show inverting and noninverting amplifiers configured for single-supply operation. 470 W +15 V 75-W Transmission Line VO(1) 75 W VI 75 W -15 V n lines 75 W VO(n) 75 W 75 W +VS 50-W Source VI Figure 40. Video Distribution Amplifier Application 49.9 W THS3125 RT 49.9 W 50-W Load RF 470 W +VS/2 Driving Capacitive Loads Applications such as FET drivers and line drivers can be highly capacitive and cause stability problems for high-speed amplifiers. RG 470 W +VS/2 +VS RG 470 W 50-W Source Figure 41 through Figure 47 show recommended methods for driving capacitive loads. The basic idea is to use a resistor or ferrite chip to isolate the phase shift at high frequency caused by the capacitive load from the amplifier feedback path. See Figure 41 for recommended resistor values versus capacitive load. RF 470 W VI 49.9 W THS3125 +VS/2 60 50-W Load +VS/2 Figure 39. DC-Coupled, Single-Supply Operation Video Distribution The wide bandwidth, high slew rate, and high output drive current of the THS3125 and THS3122 match the demands for video distribution to deliver video signals down multiple cables. To ensure high signal quality with minimal degradation of performance, a 0.1-dB gain flatness should be at least 7x the passband frequency to minimize group delay variations from the amplifier. A high slew rate minimizes distortion of the video signal, and supports component video and RGB video signals that require fast transition times and fast settling times for high signal quality. Figure 40 illustrates a typical video distribution amplifier application configuration. 12 Recommended RISO Resistance (W) 56.2 W RT 50 40 30 20 10 0 10 100 CL - Capacitive Load (pF) Figure 41. Recommended RISO vs Capacitive Load Submit Documentation Feedback (c) 2001-2011, Texas Instruments Incorporated Product Folder Link(s): THS3122 THS3125 THS3122 THS3125 SLOS382D - SEPTEMBER 2001 - REVISED FEBRUARY 2011 www.ti.com Placing a small series resistor, RISO, between the amplifier output and the capacitive load, as shown in Figure 42, is an easy way of isolating the load capacitance. RF +VS RG RISO 5.11 W 100-W Load Figure 44 shows another method used to maintain the low-frequency load independence of the amplifier while isolating the phase shift caused by the capacitance at high frequency. At low frequency, feedback is mainly from the load side of RISO. At high frequency, the feedback is mainly via the 27-pF capacitor. The resistor RIN in series with the negative input is used to stabilize the amplifier and should be equal to the recommended value of RF at unity gain. Replacing RIN with a ferrite of similar impedance at about 100 MHz as shown in Figure 45 gives similar results with reduced dc offset and low frequency noise. 1 mF RF -VS +VS 49.9 W 27 pF +VS RG 560 W Figure 42. Resistor to Isolate Capacitive Load 5.11 W 100-W Load RIN Using a ferrite chip in place of RISO, as Figure 43 shows, is another approach of isolating the output of the amplifier. The ferrite impedance characteristic versus frequency is useful to maintain the low frequency load independence of the amplifier while isolating the phase shift caused by the capacitance at high frequency. Use a ferrite with similar impedance to RISO, 20 to 50 , at 100 MHz and low impedance at dc. 1 mF -VS +VS 49.9 W Figure 44. Feedback Technique with Input Resistor for Capacitive Load RF RF +VS RG 27 pF Ferrite Bead 100-W Load RG Ferrite Bead +VS 5.11 W FIN 1 mF -VS +VS 100-W Load 1 mF 49.9 W +VS -VS 49.9 W Figure 43. Ferrite Bead to Isolate Capacitive Load Figure 45. Feedback Technique with Input Ferrite Bead for Capacitive Load Submit Documentation Feedback (c) 2001-2011, Texas Instruments Incorporated Product Folder Link(s): THS3122 THS3125 13 THS3122 THS3125 SLOS382D - SEPTEMBER 2001 - REVISED FEBRUARY 2011 www.ti.com Figure 46 shows a configuration that uses two amplifiers in parallel to double the output drive current to larger capacitive loads. This technique is used when more output current is needed to charge and discharge the load faster as when driving large FET transistors. RF +VS RG 5.11 W 24.9 W -VS RF +VS +VS 1 nF RG 5.11 W 24.9 W -VS Figure 46. Parallel Amplifiers for Higher Output Drive Figure 47 shows a push-pull FET driver circuit typical of ultrasound applications with isolation resistors to isolate the gate capacitance from the amplifier. +VS -VS RF RF +VS 5.11 W -VS The THS3125 features a shutdown pin (SHUTDOWN) that lowers the quiescent current from 8.4 mA/amp down to 370 A/amp, ideal for reducing system power. The shutdown pin of the amplifier defaults to the REF pin voltage in the absence of an applied voltage, putting the amplifier in the normal on mode of operation. To turn off the amplifier in an effort to conserve power, the shutdown pin can be driven towards the positive rail. The threshold voltages for power-on and power-down (or shutdown) are relative to the supply rails and are given in the Shutdown Characteristics (THS3125 Only) table. Below the Enable threshold voltage, the device is on. Above the Disable threshold voltage, the device is off. Behavior between these threshold voltages is not specified. Note that this shutdown functionality is self-defining: the amplifier consumes less power in shutdown mode. The shutdown mode is not intended to provide a high-impedance output. In other words, the shutdown functionality is not intended to allow use as a 3-state bus driver. When in shutdown mode, the impedance looking back into the output of the amplifier is dominated by the feedback and gain setting resistors, but the output impedance of the device itself varies depending on the voltage applied to the outputs. As with most current feedback amplifiers, the internal architecture places some limitations on the system when in shutdown mode. Most notably is the fact that the amplifier actually turns on if there is a 0.7 V or greater difference between the two input nodes (IN+ and IN-) of the amplifier. If this difference exceeds 0.7 V, the output of the amplifier creates an output voltage equal to approximately [(IN+ - IN-) - 0.7V] x Gain. Also, if a voltage is applied to the output while in shutdown mode, the IN- node voltage is equal to VO(applied) x RG/(RF + RG) . For low gain configurations and a large applied voltage at the output, the amplifier may actually turn on because of the behavior described here. +VS 5.11 W 2RG Saving Power with Shutdown Functionality and Setting Threshold Levels with the Reference Pin -VS Figure 47. PowerFET Drive Circuit The time delays associated with turning the device on and off are specified as the time it takes for the amplifier to reach either 10% or 90% of the final output voltage. The time delays are in the order of microseconds because the amplifier moves in and out of the linear mode of operation in these transitions. space space 14 Submit Documentation Feedback (c) 2001-2011, Texas Instruments Incorporated Product Folder Link(s): THS3122 THS3125 THS3122 THS3125 SLOS382D - SEPTEMBER 2001 - REVISED FEBRUARY 2011 www.ti.com Power-Down Reference Pin Operation In addition to the shutdown pin, the THS3125 features a reference pin (REF) which allows the user to control the enable or disable power-down voltage levels applied to the SHUTDOWN pin. In most split-supply applications, the reference pin is connected to ground. In either case, the user must be aware of voltage-level thresholds that apply to the shutdown pin. Table 2 shows examples and illustrate the relationship between the reference voltage and the power-down thresholds. In the table, the threshold levels are derived by the following equations: SHUTDOWN REF + 0.8 V for enable SHUTDOWN REF + 2V for disable Where the usable range at the REF pin is: VCC- VREF (VCC+ - 4V) The recommended mode of operation is to tie the REF pin to midrail, therefore setting the enable/disable thresholds to V(midrail) + 0.8 V and V(midrail) = 2 V, respectively. Table 2. Shutdown Threshold Voltage Levels REFERENCE PIN VOLTAGE (V) ENABLE LEVEL (V) DISABLE LEVEL (V) 15, 5 0 0.8 2.0 15 2.0 2.8 4.0 15 -2.0 -1.2 0 SUPPLY VOLTAGE (V) 5 1.0 1.8 3.0 5 -1.0 -0.2 1.0 +30 15.0 15.8 17 +10 5.0 5.8 7.0 Note that if the REF pin is left unterminated, it floats to the positive rail and falls outside of the recommended operating range given above VCC- VREF (VCC+ - 4V). As a result, it no longer serves as a reliable reference for the SHUTDOWN pin, and the enable/disable thresholds given above no longer apply. If the SHUTDOWN pin is also left unterminated, it floats to the positive rail and the device is disabled. If balanced, split supplies are used (VS) and the REF and SHUTDOWN pins are grounded, the device is enabled. space space space Printed-Circuit Board Layout Techniques for Optimal Performance Achieving optimum performance with high-frequency amplifiers such as the THS3125 and THS3122 requires careful attention to board layout parasitic and external component types. Recommendations that optimize performance include: * Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and input pins can cause instability. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. * Minimize the distance [0.25 inch, (6,4 mm)] from the power-supply pins to high-frequency 0.1-F and 100-pF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections should always be decoupled with these capacitors. Larger (6.8 F or more) tantalum decoupling capacitors, effective at lower frequencies, should also be used on the main supply pins. These capacitors may be placed somewhat farther from the device and may be shared among several devices in the same area of the printed circuit board (PCB). * Careful selection and placement of external components preserve the high-frequency performance of the THS3125 and THS3122. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Again, keep the leads and PCB trace length as short as possible. Never use wirebound type resistors in a high-frequency application. Because the output pin and inverting input pins are the most sensitive to parasitic capacitance, always position the feedback and series output resistors, if any, as close as possible to the inverting input pins and output pins. Other network components, such as input termination resistors, should be placed close to the gain-setting resistors. Even with a low parasitic capacitance that shunts the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal-film or surface-mount resistors have approximately 0.2 pF in shunt with the resistor. For resistor values greater than 2.0 k, this parasitic capacitance can add a pole and/or a zero that can affect circuit operation. Keep resistor values as low as possible, consistent with load driving considerations. Submit Documentation Feedback (c) 2001-2011, Texas Instruments Incorporated Product Folder Link(s): THS3122 THS3125 15 THS3122 THS3125 SLOS382D - SEPTEMBER 2001 - REVISED FEBRUARY 2011 * 16 Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces [0.05 inch (1,3 mm) to 0.1 inch (2,54 mm)] should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and determine if isolation resistors on the outputs are necessary. Low parasitic capacitive loads (less than 4 pF) may not need an RS because the THS3125 and THS3122 are nominally compensated to operate with a 2-pF parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (thus increasing the unloaded phase margin). If a long trace is required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched-impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50- environment is not necessary onboard, and in fact, a higher impedance environment improves distortion as shown in the distortion versus load plots. With a characteristic board trace impedance based on board material and trace dimensions, a matching series resistor into the trace from the output of the THS3125/THS3122 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. If the 6-dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case. This configuration does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there is some signal attenuation as a result of the voltage divider formed by the series output into the terminating impedance. www.ti.com * Socketing a high-speed device such as the THS3125 and THS3122 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the THS3125/THS3122 amplifiers directly onto the board. PowerPADTM Design Considerations The THS3125 and THS3122 are available in a thermally-enhanced PowerPAD family of packages. These packages are constructed using a downset leadframe upon which the die is mounted [see Figure 48(a) and Figure 48(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 48(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. Note that devices such as the THS312x have no electrical connection between the PowerPAD and the die. DIE (a) Side View Thermal Pad DIE (b) End View (c) Bottom View Figure 48. Views of Thermally-Enhanced Package The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface mount with the, heretofore, awkward mechanical methods of heatsinking. Submit Documentation Feedback (c) 2001-2011, Texas Instruments Incorporated Product Folder Link(s): THS3122 THS3125 THS3122 THS3125 SLOS382D - SEPTEMBER 2001 - REVISED FEBRUARY 2011 www.ti.com PowerPADTM Layout Considerations 0.205 (5,21) 0.060 (1,52) Pin 1 0.017 (0,432) 0.013 (0,33) 0.075 (1,91) 0.094 (2,39) 0.030 (0,76) 0.025 (0,64) 0.010 (0,254) vias 0.035 (0,89) 0.040 (1,01) Top View Dimensions are in inches (millimeters). Figure 49. DGN PowerPAD PCB Etch and Via Pattern Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the recommended approach. 1. PCB with a top side etch pattern as shown in Figure 49. 2. Place five holes in the area of the thermal pad. These holes should be 0.01 inch (0,254 mm) in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow. 3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. These vias help dissipate the heat generated by the THS3125/THS3122 IC. These additional vias may be larger than the 0.01-inch (0,254-mm) diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered so that wicking is not a problem. 4. Connect all holes to the internal ground plane. Note that the PowerPAD is electrically isolated from the silicon and all leads. Connecting the PowerPAD to any potential voltage, such as VS-, is acceptable as there is no electrical connection to the silicon. 5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This resistance makes the soldering of vias that have plane connections easier. In this application; however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the THS3125/THS3122 PowerPAD package should make the connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole. 6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This configuration prevents solder from being pulled away from the thermal pad area during the reflow process. 7. Apply solder paste to the exposed thermal pad area and all of the IC terminals. 8. With these preparatory steps in place, the IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This procedure results in a part that is properly installed. Power Dissipation and Thermal Considerations The THS3125 and THS3122 incorporate automatic thermal shutoff protection. This protection circuitry shuts down the amplifier if the junction temperature exceeds approximately +160C. When the junction temperature reduces to approximately +140C, the amplifier turns on again. However, for maximum performance and reliability, the designer must take care to ensure that the design does not exceed a junction temperature of +125C. Between +125C and +150C, damage does not occur, but the performance of the amplifier begins to degrade and long-term reliability suffers. The thermal characteristics of the device are dictated by the package and the PCB. Maximum power dissipation for a given package can be calculated using the following formula. T - TA PDMax = max qJA where: * PDMax is the maximum power dissipation in the amplifier (W) * Tmax is the absolute maximum junction temperature (C) * TA is the ambient temperature (C) JA = JC + CA where: * * JC is the thermal coefficient from the silicon junctions to the case (C/W) CA is the thermal coefficient from the case to ambient air (C/W) Submit Documentation Feedback (c) 2001-2011, Texas Instruments Incorporated Product Folder Link(s): THS3122 THS3125 17 THS3122 THS3125 SLOS382D - SEPTEMBER 2001 - REVISED FEBRUARY 2011 When determining whether or not the device satisfies the maximum power dissipation requirement, it is important to not only consider quiescent power dissipation, but also dynamic power dissipation. Often times, this type of dissipation is difficult to quantify because the signal pattern is inconsistent, but an estimate of the RMS power dissipation can provide visibility into a possible problem. 18 PDMax - Maximum Power Dissipation (W) For systems where heat dissipation is more critical, the THS3125 and THS3122 are also available in an 8-pin MSOP with PowerPAD package that offers even better thermal performance. The thermal coefficient for the PowerPAD packages are substantially improved over the traditional SOIC. Maximum power dissipation levels are depicted in Figure 50 for the available packages. The data for the PowerPAD packages assume a board layout that follows the PowerPAD layout guidelines discussed above and detailed in the PowerPAD application note (literature number SLMA002). Figure 50 also illustrates the effect of not soldering the PowerPAD to a PCB. The thermal impedance increases substantially, which may cause serious heat and performance issues. Always solder the PowerPAD to the PCB for optimum performance. www.ti.com 4.0 TJ = +125C 3.5 3.0 qJA = 58.4C/W 2.5 2.0 qJA = 95C/W 1.5 1.0 0.5 qJA = 158C/W 0 -40 -20 0 20 40 60 80 100 TA - Free-Air Temperature (C) Results shown are with no air flow and PCB size of 3 in x 3 in (76,2 mm x 76,2 mm). * JA = 58.4C/W for 8-pin MSOP with PowerPAD (DGN package) * JA = 95C/W for 8-pin SOIC High-K test PCB (D package) * JA = 158C/W for 8-pin MSOP with PowerPAD without solder Figure 50. Maximum Power Dissipation vs Ambient Temperature Submit Documentation Feedback (c) 2001-2011, Texas Instruments Incorporated Product Folder Link(s): THS3122 THS3125 THS3122 THS3125 SLOS382D - SEPTEMBER 2001 - REVISED FEBRUARY 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (July, 2010) to Revision D * Page Changed output current (absolute maximum) from 275 mA to 550 mA ............................................................................... 2 Changes from Revision B (October, 2009) to Revision C Page * Corrected REF pin name for THS3125 shown in front-page figure ...................................................................................... 1 * Deleted Shutdown pin input levels parameters and specifications from Recommended Operating Conditions table ......... 3 * Updated Shutdown Characteristics table test conditions; changed GND to REF, corrected VSHDN notations ..................... 5 * Added VREF and VSHDN parameters and speciifications to Shutdown Characteristics table ................................................. 5 * Revised second and fourth paragraphs of Saving Power with Shutdown Functionality section ........................................ 14 * Updated equation in Power-Down Reference Pin Operation section that describes usable range at the REF pin ........... 15 * Revised paragraph in Power-Down Reference Pin Operation that discusses behavior of unterminated REF pin ............ 15 Submit Documentation Feedback (c) 2001-2011, Texas Instruments Incorporated Product Folder Link(s): THS3122 THS3125 19 PACKAGE OPTION ADDENDUM www.ti.com 20-Aug-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) (Requires Login) THS3122CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) THS3122CDDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM THS3122CDDAG3 ACTIVE SO PowerPAD DDA 8 75 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM THS3122CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS3122CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS3122CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS3122ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS3122IDDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM THS3122IDDAG3 ACTIVE SO PowerPAD DDA 8 75 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM THS3122IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS3125CPWP ACTIVE HTSSOP PWP 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR THS3125CPWPG4 ACTIVE HTSSOP PWP 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR THS3125ID ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS3125IDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS3125IPWP ACTIVE HTSSOP PWP 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR THS3125IPWPG4 ACTIVE HTSSOP PWP 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR THS3125IPWPR ACTIVE HTSSOP PWP 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Addendum-Page 1 Samples CU NIPDAU Level-1-260C-UNLIM PACKAGE OPTION ADDENDUM www.ti.com Orderable Device THS3125IPWPRG4 20-Aug-2011 Status (1) ACTIVE Package Type Package Drawing HTSSOP PWP Pins 14 Package Qty 2000 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant THS3122CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 THS3125IPWPR HTSSOP PWP 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS3122CDR SOIC D 8 2500 367.0 367.0 35.0 THS3125IPWPR HTSSOP PWP 14 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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