QS74FCT162652ATPA - Integrated Device Technology, Inc.

MDSL-00077-00 QUALITY SEMICONDUCTOR, INC. 1

MARCH 10, 1998

QS74FCT16652T, 162652T PRELIMINARY

Now an Company

High-Speed CMOS

16-Bit Bus Register

Transceiver

QS74FCT16652T

QS74FCT162652T

PRELIMINARY

FEATURES/BENEFITS

• Pin and function compatible with T.I.

Widebus™ and IDT Double-Density™ families

• CMOS power levels: <1µW typical standby

• SSOP (PV) and TSSOP (PA) packages

• Low output skew: 0.5ns tSK(O)

• Flow-through pinout for easy layout

• Power off disable allows hot plugging

• Industrial temperature: –40°C to +85°C

• Input hysteresis for noise immunity

• Multiple power and ground pins for low noise

FCT16652T

• High drive standard FCT-T outputs:

IOL = +64mA, IOH = –32mA

• Incident switching for driving buses and large

loads

FCT162652T

• Balanced output drivers: ±24mA

• Reduced switching noise for point to point

signals

CLKAB

CLKBA

SBA

OEAB

SAB

A Register

B Register

1Bn

1An

TO 7 OTHER CHANNELS

OEBA

CLKAB

CLKBA

SBA

OEAB

SAB

2Bn

2An

TO 7 OTHER CHANNELS

OEBA

B Register

A Register

DESCRIPTION

The FCT16652 family of products are 16-bit bus

ideal for driving address and data buses. The

FCT16652 and FCT162652 are organized for trans-

mission of data between A bus and B bus either

directly or from the internal storage registers. Easy

board layout is facilitated by the use of flow-through

pinouts and byte enable controls provide architectural

flexibility for systems designers. All outputs have

ground bounce suppression circuitry (see QSI Appli-

cation Note AN-01) and many power and ground pins

provide low ground bounce. To accommodate hot-

plug or live insertion applications, both versions of this

product were designed not to load an active bus when

VCC is removed. In applications where bus signals are

point-to-point or driving light capacitance loads, the

balanced drive FCT162652 is recommended.

UALITY

EMICONDUCTOR,

NC.

Figure 1. Functional Block Diagram

2QUALITY SEMICONDUCTOR, INC. MDSL-00077-00

MARCH 10, 1998

QS74FCT16652T, 162652T PRELIMINARY

Now an Company

Figure 2. Pin Configuration

(All Pins Top View)

SSOP, TSSOP

Name Description

xAx Data Register A Inputs

Data Register B Outputs

xBx Data Register B Inputs

Data Register A Outputs

xCLKAB, xCLKBA Clock Inputs

xSAB, xSBA Output Source Select Inputs

X OEAB, xOEBA Output Enable Inputs

Table 1. Pin Description

Table 2. Absolute Maximum Ratings

Supply Voltage to Ground...............................................–0.5V to +7.0V

DC Output Voltage VOUT ................................................–0.5V to +7.0V

DC Input Voltage VIN.......................................................–0.5V to +7.0V

AC Input Voltage (for a pulse width ≤ 20ns) ................................. –3.0V

DC Input Diode Current with VIN < 0 ........................................... –20mA

DC Output Diode Current with VOUT < 0 ..................................... –50mA

DC Output Current Max. Sink Current/Pin.................................. 120mA

Maximum Power Dissipation ................................................... 1.0 watts

TSTG Storage Temperature............................................. –65° to +150°C

Note: Stresses greater than

those listed under ABSOLUTE

MAXIMUM RATINGS may

cause permanent damage to

this device resulting in func-

tional or reliability type failures.

Pins Typ Max Unit

All 6.0 9.0 pF

Table 3. Capacitance

TA = 25°C, f = 1MHz, VIN = 0V, VOUT = 0V

1OEAB

1CLKAB

1SAB

GND

1A1

1A2

1A3

1A4

1A5

GND

1A6

1A7

1A8

2A1

2A2

2A3

GND

2A4

2A5

2A6

2A7

2A8

GND

2SAB

2CLKAB

2OEAB

1OEBA

1CLKBA

1SBA

GND

1B1

1B2

1B3

1B4

1B5

GND

1B6

1B7

1B8

2B1

2B2

2B3

GND

2B4

2B5

2B6

2B7

2B8

GND

2SBA

2CLKBA

2OEBA

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MARCH 10, 1998

QS74FCT16652T, 162652T PRELIMINARY

Now an Company

Table 4. Function Table(2,3)

Inputs Data I/O(1)

xOEAB xOEBAOEBA

OEBAOEBA

OEBA xCLKAB xCLKBA xSAB xSBA xAx xBx Operation or Function

L H H or L H or L X X Input Input Isolation

LH ↑↑X X Store A and B Data

XH ↑H or L X X Input

Unspecified

(1) Store A, Hold B

HH ↑↑X(2) X Output Store A in both Registers

L X H or L ↑XX

Unspecified

(1) Input Hold A, Store B

LL ↑↑XX

(2) Output Store B in both Registers

L L X X X L Output Input Real Time B Data to A Bus

L L X H or L X H Stored B Data to A Bus

H H X X L X Input Output Real Time A Data to B Bus

H H H or L X H X Stored A Data to B Bus

H L H or L H or L H H Output Output Stored A Data to B Bus and

Stored B Data to A Bus

Notes:

1. The data output functions may be enabled or disabled by various signals at the xOEAB or xOEBA inputs. Data

input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on

the clock inputs.

2. Select control = L; clocks can occur simultaneously.

Select control = H; clocks must be staggered to load both registers.

3. H = HIGH Voltage Level

L = LOW Voltage Level

X = Don't Care

↑ = LOW-to-HIGH Transition

Table 5. DC Electrical Characteristics Over Operating Range

Recommended Operating Ranges apply unless otherwise noted.

Symbol Parameter Test Conditions(1) Min Typ(2) Max Unit

VIH Input HIGH Voltage Logic HIGH for All Inputs 2.0 — — V

VIL Input LOW Voltage Logic LOW for All Inputs — — 0.8 V

∆VTInput Hysteresis VTLH – VTHL for All Inputs(4) — 100 — mV

| IIH | Input Current VCC = Max., 0 ≤ VIN < VCC —— 1µA

| IIL | Input HIGH or LOW

| IOZ | Off-State Output VCC = Max., 0 ≤ VOUT ≤ VCC —— 1µA

Current (Hi-Z)

| IOFF | Power off leakage VCC = 0V, VIN/OUT ≤ 4.5V(5) —— 1µA

IOS Short Circuit Current VCC = Max., VOUT = GND(3,4) –80 –140 –225 mA

VIK Input Clamp Voltage VCC = Min., IIN = –18mA – –0.7 –1.2 V

Notes:

1. For conditions shown as Min. or Max. use appropriate value specified under Recommended Operating Conditions

for the applicable device type.

2. Typical values indicate VCC = 5.0V and TA = 25°C.

3. Not more than one output should be tested at one time. Duration of test should not exceed one second.

4. These parameters are guaranteed by design but not tested.

5. The test limit for this parameter is ± 5µA at TA = –55°C

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MARCH 10, 1998

QS74FCT16652T, 162652T PRELIMINARY

Now an Company

Symbol Parameter Min Max Unit

VCC Supply Voltage 4.5 5.5 V

VIN Input Voltage 0 VCC V

VOUT Voltage Applied to Output or I/O 0 VCC V

∆t/∆v Input Transition Slew Rate — 10 ns/V

TAOperating Free Air Tempeature –40 +85 °C

Table 6. Recommended Operating Conditions

Table 8. Output Drive Characteristics for FCT162652T

Symbol Parameter Test Conditions(1) Min Typ(2) Max Unit

IODL Output LOW Current VCC = 5V, VIN = VIH or VIL 60 115 200 mA

VOUT =1.5V(3)

IODH Output HIGH Current VCC = 5V, VIN = VIH or VIL –60 –115 –200 mA

VOUT = 1.5V(3)

VOH Output HIGH Voltage VCC = Min. IOH = –24mA 2.4 3.1 — V

VIN = VIH or VIL

VOL Output LOW Voltage VCC = Min. IOL = 24mA — 0.3 0.55 V

VIN = VIH or VIL

Notes:

1. For conditions shown as Min. or Max. use appropriate value specified under Electrical Characteristics for the

applicable device type.

2. Typical values indicate VCC = 5.0V and TA = 25°C.

3. Not more than one output should be shorted and the duration is ≤1 second.

4. Duration of the condition should not exceed one second.

Table 7. Output Drive Characteristics for FCT16652T

Symbol Parameter Test Conditions(1) Min Typ(2) Max Unit

VOH Output HIGH Voltage VCC = Min. IOH = –3mA 2.5 3.4 — V

VIN = VIH or VIL IOH = –15mA 2.4 3.2 — V

IOH = –32mA(4) 2.0 3.0 — V

VOL Output LOW Voltage VCC = Min. IOL = 64mA — 0.3 0.55 V

VIN = VIH or VIL

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MARCH 10, 1998

QS74FCT16652T, 162652T PRELIMINARY

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Symbol Parameter Test Conditions(1) Typ (2) Max Unit

ICCL Quiescent Power VCC = Max., VIN = GND or VCC 5 500 µA

ICCH Supply Current

ICCZ

∆ICC Supply Current per VCC = Max., VIN = 3.4V(3) 0.5 1.5 mA

Input @ TTL HIGH

QCCD Supply Current per VCC = Max., Outputs Open VIN = VCC 75 120 µA/

Input per MHz(4) One Bit Toggling VIN = GND MHz

@ 50% Duty Cycle

xDIR = xOE = GND

ICTotal Power VCC = Max., Outputs Open VIN = VCC 0.8 1.7(5) mA

Supply Current(6) One Bit Toggling VIN = GND

@ 50% Duty Cycle VIN = 3.4 V 1.3 3.2(5) mA

fI = 5MHz, VIN = GND

fCP = 10MHz (xCLKBA)

xOEAB = xOEBA = GND

VCC = Max., Outputs Open VIN = VCC 3.8 6.5(5) mA

Sixteen Bits Toggling VIN = GND

@ 50% Duty Cycle VIN = 3.4 V 8.3 20(5) mA

fI = 2.5MHz, VIN = GND

fCP = 10MHz (xCLKBA)

xOEAB = xOEBA = GND

Table 9. Power Supply Characteristics

Notes:

1. For conditions shown as Min. or Max., use the appropriate values specified under Recommended Operating

Conditions for applicable device type.

2. Typical values are at VCC = 5.0V, +25°C ambient.

3. Per TTL driven input (VIN = 3.4V). All Other Inputs at VCC or GND.

4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

5. Values for these conditions are examples of the ICC formula. These limits are guaranteed by design but not tested.

6. IC = IQUIESCENT + IINPUTS = IDYNAMIC.

IC = ICCQ + ∆ICC DHNT + ICCD (fCPNCP/2 + fINI).

ICCQ = Quiescent Current (ICCL, ICCH, and ICCZ).

∆ICC = Power Supply Current for a TTL-High Input (VIN = 3.4V).

DH = Duty Cycle for TTL High Inputs.

NT = Number of TTL High Inputs.

ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL).

fCP = Clock Frequency for Register devices (Zero for Non-Register Devices).

NCP = Number of Clock Inputs at fCP.

fI = Input Frequency.

NI = Number of Inputs at fI.

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MARCH 10, 1998

QS74FCT16652T, 162652T PRELIMINARY

Now an Company

FCT16652T FCT16652AT FCT16652CT

FCT162652T FCT162652AT FCT162652CT

Symbol Description(1) Min Max Min Max Min Max Unit

tPHL Propagation Delay 2.0 9.0 2.0 6.3 2.0 5.4 ns

tPLH xAx to xBx

tPHL Propagation Delay 2.0 11.0 2.0 7.7 2.0 6.2 ns

tPLH xSBA or xSAB TO xAx, xBx

tPHL Propagation Delay 2.0 9.0 2.0 6.3 2.0 5.7 ns

tPLH xCLKAB or xCLKBA to xAx, xBx

tPZH Output Enable Time 1.5 14.0 1.5 9.8 1.5 7.8 ns

tPZL xOEAB or xOEBA to xAx, xBx

tPHZ Output Disable Time(3) 1.5 9.0 1.5 6.3 1.5 6.3 ns

tPLZ xOEAB or xOEBA to xAx, xBx

tSU Setup Time HIGH or LOW 4.0 — 2.0 — 2.0 — ns

Bus to Clock

tHHold Time HIGH or LOW 2.0 — 1.5 — 1.5 — ns

Bus to Clock

tWClock Pulse Width(3) 6.0 — 5.0 — 5.0 — ns

LOW or HIGH

tSK(O) Output Skew(2) — 0.5 — 0.5 — 0.5 ns

Table 10. Switching Characteristics Over Operating Range

Recommended Operating Ranges apply unless otherwise specified.

CLOAD = 50pF, RLOAD = 500Ω unless otherwise noted.

Notes:

1. Minimums guaranteed but not tested. See Test Circuit and Waveforms.

2. Skew between any two outputs of the same package switching in the same direction. This parameter is

guaranteed by design but not tested.

3. This condition is guaranteed by characterization, but not production tested.