09/24/09
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HEXFET® Power MOSFET
Benefits
lImproved Gate, Avalanche and Dynamic dV/dt
Ruggedness
lFully Characterized Capacitance and Avalanche
SOA
lEnhanced body diode dV/dt and dI/dt Capability
l Lead-Free
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
S
D
G
GDS
Gate Drain Source
PD - 97353A
IRF1324SPbF
IRF1324LPbF
D2Pak
IRF1324SPbF
TO-262
IRF1324LPbF
GD
S
GDS
Absolute Maximum Ratings
Symbol Parameter Units
I
D
@ T
C
= 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited)
I
D
@ T
C
= 100°C Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
I
D
@ T
C
= 25°C Continuous Drain Current, V
GS
@ 10V (Wire Bond Limited)
I
DM
Pulsed Drain Current
d
P
D
@T
C
= 25°C Maximum Power Dissipation W
Linear Derating Factor W/°C
V
GS
Gate-to-Source Voltage V
dv/dt Peak Diode Recovery
f
V/ns
T
J
Operating Junction and
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Avalanche Characteristics
E
AS (Thermally limited)
Single Pulse Avalanche Energy
e
mJ
I
AR
Avalanche Current
d
A
E
AR
Repetitive Avalanche Energy
g
mJ
Thermal Resistance
Symbol Parameter Typ. Max. Units
R
θJC
Junction-to-Case
k
––– 0.50 °C/W
R
θJA
Junction-to-Ambient (PCB Mounted, steady-state)
jk
––– 40
270
See Fig. 14, 15, 22a, 22b
300
0.46
A
°C
300
-55 to + 175
± 20
2.0
Max.
340
240
1420
195
V
DSS
24V
R
DS
(
on
)
typ. 1.3mΩ
max. 1.65mΩ
I
D
(Silicon Limited)
340A
c
I
D
(Package Limited)
195A
IRF1324S/LPbF
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Notes:
Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 195A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements. (Refer to AN-1140).
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.014mH
RG = 25Ω, IAS = 195A, VGS =10V. Part not recommended for use
above this value.
S
D
G
ISD ≤ 195A, di/dt ≤ 450A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom-
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
Static @ T
J
= 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
V
(BR)DSS
Drain-to-Source Breakdown Voltage 24 ––– ––– V
∆V
(
BR
)
DSS
/∆T
J
Breakdown Voltage Temp. Coefficient ––– 22 ––– mV/°C
R
DS(on)
Static Drain-to-Source On-Resistance ––– 1.3 1.65 mΩ
V
GS(th)
Gate Threshold Voltage 2.0 ––– 4.0 V
I
DSS
Drain-to-Source Leakage Current ––– ––– 20 µA
––– ––– 250
I
GSS
Gate-to-Source Forward Leakage ––– ––– 200 nA
Gate-to-Source Reverse Leakage ––– ––– -200
R
G
Internal Gate Resistance ––– 2.3 ––– Ω
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
gfs Forward Transconductance 180 ––– ––– S
Q
g
Total Gate Charge ––– 160 240 nC
Q
gs
Gate-to-Source Charge ––– 84 –––
Q
gd
Gate-to-Drain ("Miller") Charge ––– 49 –––
Q
sync
Total Gate Charge Sync. (Q
g
- Q
gd
)––– 76 –––
t
d(on)
Turn-On Delay Time ––– 17 ––– ns
t
r
Rise Time ––– 190 –––
t
d(off)
Turn-Off Delay Time ––– 83 –––
t
f
Fall Time ––– 120 –––
C
iss
Input Capacitance ––– 7590 ––– pF
C
oss
Output Capacitance ––– 3440 –––
C
rss
Reverse Transfer Capacitance ––– 1960 –––
C
oss
eff. (ER) Effective Output Capacitance (Ener
g
y Related) ––– 4700 –––
C
oss
eff. (TR) Effective Output Capacitance (Time Related) ––– 4490 –––
Diode Characteristics
Symbol Parameter Min. Typ. Max. Units
I
S
Continuous Source Current ––– ––– 350
c
A
(Body Diode)
I
SM
Pulsed Source Current ––– ––– 1420 A
(Body Diode)
d
V
SD
Diode Forward Voltage ––– ––– 1.3 V
t
rr
Reverse Recovery Time ––– 46 ––– ns T
J
= 25°C V
R
= 20V,
––– 71 ––– T
J
= 125°C I
F
= 195A
Q
rr
Reverse Recovery Charge ––– 160 ––– nC T
J
= 25°C di/dt = 100A/µs
g
––– 430 ––– T
J
= 125°C
I
RRM
Reverse Recovery Current ––– 7.7 ––– A T
J
= 25°C
t
on
Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Conditions
V
DS
= 10V, I
D
= 195A
I
D
= 195A
V
GS
= 20V
V
GS
= -20V
MOSFET symbol
showing the
V
DS
= 12V
Conditions
V
GS
= 10V
g
V
GS
= 0V
V
DS
= 24V
ƒ = 1.0 MHz, See Fig. 5
V
GS
= 0V, V
DS
= 0V to 19V
i
, See Fig. 11
V
GS
= 0V, V
DS
= 0V to 19V
h
T
J
= 25°C, I
S
= 195A, V
GS
= 0V
g
integral reverse
p-n junction diode.
Conditions
V
GS
= 0V, I
D
= 250µA
Reference to 25°C, I
D
= 5.0mA
d
V
GS
= 10V, I
D
= 195A
g
V
DS
= V
GS
, I
D
= 250µA
V
DS
= 24V, V
GS
= 0V
V
DS
= 24V, V
GS
= 0V, T
J
= 125°C
I
D
= 195A
R
G
= 2.7Ω
V
GS
= 10V
g
V
DD
= 16V
I
D
= 195A, V
DS
=0V, V
GS
= 10V
IRF1324S/LPbF
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Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature
Fig 2. Typical Output Characteristics
Fig 6. Typical Gate Charge vs. Gate-to-Source VoltageFig 5. Typical Capacitance vs. Drain-to-Source Voltage
2 3 4 5 6 7 8 9
VGS, Gate-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
TJ = 25°C
TJ = 175°C
VDS = 15V
≤60µs PULSE WIDTH
-60 -40 -20 020 40 60 80 100120140160180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 195A
VGS = 10V
110 100
VDS, Drain-to-Source Voltage (V)
1000
10000
100000
C, Capacitance (pF)
VGS = 0V, f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0 50 100 150 200
QG, Total Gate Charge (nC)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
VGS, Gate-to-Source Voltage (V)
VDS= 19V
VDS= 12V
ID= 195A
0.1 110 100
VDS, Drain-to-Source Voltage (V)
10
100
1000
10000
ID, Drain-to-Source Current (A)
4.0V
≤60µs PULSE WIDTH
Tj = 175°C
VGS
TOP 15V
10V
8.0V
6.0V
5.5V
5.0V
4.5V
BOTTOM 4.0V
0.1 110 100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
VGS
TOP 15V
10V
8.0V
6.0V
5.5V
5.0V
4.5V
BOTTOM 4.0V
≤60µs PULSE WIDTH
Tj = 25°C
4.0V
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Fig 8. Maximum Safe Operating Area
Fig 10. Drain-to-Source Breakdown Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
Fig 11. Typical COSS Stored Energy
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
0.0 0.5 1.0 1.5
VSD, Source-to-Drain Voltage (V)
1.0
10
100
1000
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
-60 -40 -20 020 40 60 80 100120140160180
TJ , Temperature ( °C )
24
26
28
30
32
V(BR)DSS, Drain-to-Source Breakdown Voltage (V)
Id = 5mA
-5 0 5 10 15 20 25 30
VDS, Drain-to-Source Voltage (V)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Energy (µJ)
25 50 75 100 125 150 175
TC , Case Temperature (°C)
0
50
100
150
200
250
300
350
ID, Drain Current (A)
Limited By Package
1 10 100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS(on)
Tc = 25°C
Tj = 175°C
Single Pulse
100µsec
1msec
10msec
DC
Limited by
package
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
200
400
600
800
1000
1200
EAS , Single Pulse Avalanche Energy (mJ)
ID
TOP 44A
83A
BOTTOM 195A
IRF1324S/LPbF
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Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 14. Typical Avalanche Current vs.Pulsewidth
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
1
10
100
1000
Avalanche Current (A)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
0.01
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
Thermal Response ( Z thJC ) °C/W
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
τJ
τJ
τ1
τ1
τ2
τ2τ3
τ3
R1
R1R2
R2R3
R3
Ci i/Ri
Ci= τi/Ri
τ
τC
τ4
τ4
R4
R4Ri (°C/W) τi (sec)
0.0125 0.000008
0.0822 0.000078
0.2019 0.001110
0.2036 0.007197
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Fig 16. Threshold Voltage vs. Temperature
-75 -50 -25 025 50 75 100 125 150 175 200
TJ , Temperature ( °C )
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VGS(th), Gate threshold Voltage (V)
ID = 250µA
ID = 1.0mA
ID = 1.0A
Fig 15. Maximum Avalanche Energy vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
50
100
150
200
250
300
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 195A
IRF1324S/LPbF
www.irf.com 7
Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P. W .
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Inductor Current
D.U.T. VDS
ID
IG
3mA
VGS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
VDS
90%
10%
VGS
t
d(on)
t
r
t
d(off)
t
f
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10V
+
-
VDD
VGS
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D2Pak (TO-263AB) Part Marking Information
D2Pak (TO-263AB) Package Outline
'$7(&2'(
<($5
:((.
$ $66(0%/<6,7(&2'(
5(&7,),(5
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7+,6,6$1,5)6:,7+
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/2*2
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Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
IRF1324S/LPbF
www.irf.com 9
TO-262 Part Marking Information
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
/2*2
5(&7,),(5
,17(51$7,21$/
/27&2'(
$66(0%/<
/2*2
5(&7,),(5
,17(51$7,21$/
'$7(&2'(
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25
352'8&7237,21$/
3 '(6,*1$7(6/($')5((
(;$03/( 7+,6,6$1,5//
/27&2'(
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Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
IRF1324S/LPbF
10 www.irf.com
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 09/2009
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
D2Pak (TO-263AB) Tape & Reel Information
Dimensions are shown in millimeters (inches)
3
4
4
TRR
FEED DIRECTION
1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
TRL
FEED DIRECTION
10.90 (.429)
10.70 (.421)
16.10 (.634)
15.90 (.626)
1.75 (.069)
1.25 (.049)
11.60 (.457)
11.40 (.449) 15.42 (.609)
15.22 (.601)
4.72 (.136)
4.52 (.178)
24.30 (.957)
23.90 (.941)
0.368 (.0145)
0.342 (.0135)
1.60 (.063)
1.50 (.059)
13.50 (.532)
12.80 (.504)
330.00
(14.173)
MAX.
27.40 (1.079)
23.90 (.941)
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
26.40 (1.039)
24.40 (.961)
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.