To our custo mers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corpor ation took over all the business of both
companies. Therefore, althoug h the old com pany name remains in this docum ent, it is a valid
Renesas Electronics document. W e appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
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Notice
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DESCRIPTION
The 3822 group (A version) is the 8-bit microcomputer based on
the 740 family core technology.
The 3822 group (A version) has the LCD drive control circuit, an 8-
channel A-D converter, and a serial I/O as additional functions.
The various microcomputers in the 3822 group (A version) include
variations of internal memory size and packaging. For details, re-
fer to the section on part numbering.
FEATURES
●Basic machine-language instructions ...................................... 71
●The minimum instruction execution time ........................... 0.4 µs
(at f(XIN) = 10 MHz, High-speed mode)
●Memory size
ROM ............................................................... 16 K t o 4 8 K bytes
RAM ................................................................. 512 to 1024 bytes
●Programmable input/output ports ............................................ 49
●
Software pull-up/pull-down resistors (Ports P0-P7 except port P4
0
)
●Interrupts ................................................. 17 sources, 16 vectors
(includes key input interrupt)
●Timers...........................................................8-bit ✕ 3, 16-bit ✕ 2
●Serial I/O...................... 8-bit ✕ 1 (UART or Clock-synchronized)
●A-D converter ................................................. 8-bit ✕ 8 channels
●LCD drive control circuit
Bias...................................................................................1/2, 1/3
Duty ...........................................................................1/2, 1/3, 1/4
Common output.......................................................................... 4
Segment output ........................................................................ 32
●2 clock generating circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
●Power source voltage
In high-speed mode
(at f(XIN) ≤ 10 MHz)................................................... 4.5 to 5.5 V
(at f(XIN) ≤ 8 MHz)..................................................... 4.0 to 5.5 V
In middle-speed mode (at f(XIN) ≤ 6 MHz) ............... 1.8 to 5.5 V
In low-speed mode .................................................... 1.8 to 5.5 V
●Power dissipation
In high-speed mode ................................................ 15 mW (std.)
(at f(XIN) = 8 MHz, Vcc = 5 V, Ta = 25 °C)
In low-speed mode ................................................... 24 µW (std.)
(at f(XIN) stopped, f(XCIN) = 32 kHz, Vcc = 3 V, Ta = 25 °C)
●Operating temperature range..................................– 20 to 85 °C
APPLICATIONS
Camera, household appliances, consumer electronics, etc.
Fig. 1 M3822XMXA-XXXFP pin configuration
PIN CONFIGURATION (TOP VIEW)
Package type : 80P6N-A (80-pin plastic-molded QFP)
S
E
G
8
S
E
G
9
P
3
4
/
S
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1
2
P
3
5
/
S
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1
3
P
0
0
/
S
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1
6
P
0
3
/
S
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1
9
P
0
4
/
S
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2
0
P
0
5
/
S
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2
1
P
0
6
/
S
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2
2
P
0
7
/
S
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2
3
P
1
1
/
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2
5
P
1
2
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S
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2
6
P
1
3
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2
7
P
1
4
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2
8
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1
5
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2
9
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1
6
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3
0
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7
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1
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7
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A
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7
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6
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/φ
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5
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4
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6
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5
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4
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A
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4
P
6
3
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3
P
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2
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6
1
/
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1
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/
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1
2
3
4
5
6
7
8
9
1
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1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
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4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
0
5
1
5
2
5
3
5
4
5
5
5
6
5
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6
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6
1
6
2
6
3
6
4
6
5
6
6
6
7
6
8
6
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7
0
7
1
7
2
7
3
7
4
7
5
7
6
7
7
7
8
7
9
8
0
3822 Group (A ver.)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0076-0120Z
Rev.1.20
2003.12.24
Rev.1.20 Dec 24, 2003 page 1 of 57
Rev.1.20 Dec 24, 2003 page 2 of 57
3822 Group (A ver.)
Package type : 80P6Q-A
(80-pin plastic-molded QFP)
PIN CONFIGURATION (TOP VIEW)
Fig. 2 M3822XMXA-XXXHP pin configuration
1
2
3
4
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
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5
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2
1
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4
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3
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3
1
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3
3
4
3
5
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4
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Rev.1.20 Dec 24, 2003 page 3 of 57
3822 Group (A ver.)
FUNCTIONAL BLOCK DIAGRAM (Package type : 80P6Q-A)
Fig. 3 Functional block diagram
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t
VL
1
VL
2
VL
3
C
O
M0
C
O
M1
C
O
M2
C
O
M3
S
E
G0
S
E
G1
S
E
G2
S
E
G3
S
E
G4
S
E
G5
S
E
G6
S
E
G7
S
E
G8
S
E
G9
S
E
G1
0
S
E
G1
1
φ
XC
I
N
XC
O
U
T
2
82
9
Rev.1.20 Dec 24, 2003 page 4 of 57
3822 Group (A ver.)
PIN DESCRIPTION
Table 1 Pin description (1)
VCC, VSS
FunctionPin Name Function except a port function
•LCD segment output pins
Power source •Apply voltage of power source to VCC, and 0 V to VSS. (For the limits of VCC, refer to “Recom-
mended operating conditions”).
VREF
AVSS
RESET
XIN
XOUT
VL1–VL3
COM
0
–COM
3
SEG
0
–SEG
11
P00/SEG16–
P07/SEG23
P10/SEG24–
P17/SEG31
P20 – P27
P3
4
/SEG
12
–
P3
7
/SEG
15
Analog refer-
ence voltage
Analog power
source
Reset input
Clock input
Clock output
LCD power
source
Common output
Segment output
I/O port P0
I/O port P1
I/O port P2
•Reference voltage input pin for A-D converter.
•GND input pin for A-D converter.
•Connect to VSS.
•Reset input pin for active “L”.
•Input and output pins for the main clock generating circuit.
•Feedback resistor is built in between XIN pin and XOUT pin.
•Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
•This clock is used as the oscillating source of system clock.
•Input 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VCC voltage.
•Input 0 – VL3 voltage to LCD.
•LCD common output pins.
•COM2 and COM3 are not used at 1/2 duty ratio.
•COM3 is not used at 1/3 duty ratio.
•LCD segment output pins.
•8-bit I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each port to be individually
programmed as either input or output.
•Pull-down control is enabled.
•8-bit I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•4-bit input port.
•CMOS compatible input level.
•Pull-down control is enabled.
•Key input (key-on wake-up) interrupt
input pins
•LCD segment output pins
Input port P3
Rev.1.20 Dec 24, 2003 page 5 of 57
3822 Group (A ver.)
Table 2 Pin description (2)
FunctionPin Name Function except a port function
P40
P42/INT0,
P43/INT1
P44/RXD,
P45/TXD,
P46/SCLK,
P47/SRDY
P50/INT2,
P51/INT3
P52/RTP0,
P53/RTP1
P54/CNTR0,
P55/CNTR1
P56/TOUT
P57/ADT
P60/AN0–
P67/AN7
P70/XCOUT,
P71/XCIN
I/O port P4
I/O port P5
I/O port P6
I/O port P7
•1-bit Input port.
•CMOS compatible input level.
•7-bit I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•8-bit I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•8-bit I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•2-bit I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•φ clock output pin
•Interrupt input pins
•Interrupt input pins
•Real time port function pins
•Timer X, Y function pins
•Timer 2 output pins
•A-D conversion input pins
•Sub-clock generating circuit I/O pins.
(Connect a resonator. External clock
cannot be used.)
Input port P4
P41/φ
•Serial I/O function pins
•A-D trigger input pins
Rev.1.20 Dec 24, 2003 page 6 of 57
3822 Group (A ver.)
PART NUMBERING
Fig. 4 Part numbering
Package type
FP : 80P6N-A package
HP : 80P6Q-A package
ROM number
Omitted in One Time PROM version shipped in blank and EPROM version.
When electrical characteristic, or division of identification code using
Product M38224 M 6 A- XXX FP
alaphanumeric character
A– : A version
ROM/PROM size
1 : 4096 bytes
2 : 8192 bytes
3 : 12288 bytes
4 : 16384 bytes
5 : 20480 bytes
6 : 24576 bytes
7 : 28672 bytes
8 : 32768 bytes
The first 128 bites and the last 2 bytes of ROM are
reserved areas ; they cannot be used.
Memory type
M :Mask ROM version
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
9 : 36864 bytes
A : 40960 bytes
B : 45056 bytes
C : 49152 bytes
Rev.1.20 Dec 24, 2003 page 7 of 57
3822 Group (A ver.)
GROUP EXPANSION (A VERSION)
Mitsubishi plans to expand the 3822 group (A version) as follows:
Memory Type
Support for Mask ROM version.
Memory Size
ROM size ........................................................... 16 K t o 4 8 K bytes
RAM size ............................................................ 512 to 1024 bytes
Package
80P6N-A ....................................0.8 mm-pitch plastic molded QFP
80P6Q-A ....................................0.5 mm-pitch plastic molded QFP
Currently products are listed below.
Memory Expansion Plan
Remarks
Package
Part number
As of Sep. 2002
RAM size (bytes)
16384
(16254)
ROM size (bytes)
ROM
size for User in ( )
24576
(24446)
Fig. 5 Memory expansion plan for A version
Table 3 List of products for H version
M38223M4A-XXXFP
M38223M4A-XXXHP
M38224M6A-XXXFP
M38224M6A-XXXHP
M38227M8A-XXXFP
M38227M8A-XXXHP
M38227MCA-XXXFP
M38227MCA-XXXHP
512
80P6N-A
80P6Q-A
80P6N-A
80P6Q-A
80P6N-A
80P6Q-A
80P6N-A
80P6Q-A
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
640
32768
(32638)
49152
(49022)
1024
32K
28K
24K
20K
16K
12K
8K
4K
256 384 512 640 768 896 1024
192
M38223M4A
RAM size (bytes)
R
OM size (bytes)
48K
M38224M6A
M38227M8A
M38227MCA
Rev.1.20 Dec 24, 2003 page 8 of 57
3822 Group (A ver.)
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
The 3822 group uses the standard 740 family instruction set. Re-
fer to the table of 740 family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack ad-
dress are determined by the stack page selection bit. If the stack
page selection bit is “0” , the high-order 8 bits becomes “0016”. If
the stack page selection bit is “1”, the high-order 8 bits becomes
“0116”.
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 7.
Store registers other than those described in Figure 7 with pro-
gram when the user needs them during interrupts or subroutine
calls.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
Fig. 6 740 Family CPU register structure
A Accumulator
b7
b7
b7
b7 b0
b7
b
15 b0
b7 b0
b0
b0
b0
X Index register X
Y Index register Y
S Stack pointer
PCLProgram counterPCH
N V T B D I Z C Processor status register (PS
)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Rev.1.20 Dec 24, 2003 page 9 of 57
3822 Group (A ver.)
Table 4 Push and pop instructions of accumulator or processor status register
Accumulator
Processor status register
Push instruction to stack
PHA
PHP
Pop instruction from stack
PLA
PLP
Fig. 7 Register push and pop at interrupt generation and subroutine call
N
o
t
e:
C
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(
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(
S
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+
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(
S
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(
S
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(
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(
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“
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Rev.1.20 Dec 24, 2003 page 10 of 57
3822 Group (A ver.)
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch opera-
tions can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
•Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Table 5 Set and clear instructions of each bit of processor status register
Set instruction
Clear instruction
C flag
SEC
CLC
Z flag
–
–
I flag
SEI
CLI
D flag
SED
CLD
B flag
–
–
T flag
SET
CLT
V flag
–
CLV
N flag
–
–
Rev.1.20 Dec 24, 2003 page 11 of 57
3822 Group (A ver.)
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and
the internal system clock selection bit.
The CPU mode register is allocated at address 003B16.
Fig. 8 Structure of CPU mode register
Not available
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 :
1 1 :
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (returns “1” when read)
(Do not write “0” to this bit)
Port X
C
switch bit
0 : I/O port function (stop oscillating)
1 : X
CIN
–X
COUT
oscillating function
Main clock (X
IN
–X
OUT
) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bit
0 : f(X
IN
)/2 (high-speed mode)
1 : f(X
IN
)/8 (middle-speed mode)
Internal system clock selection bit
0 : X
IN
–X
OUT
selected (middle-/high-speed mode)
1 : X
CIN
–X
COUT
selected (low-speed mode)
CPU mode register
(CPUM (CM) : address 003B
16
)
b7 b0
Rev.1.20 Dec 24, 2003 page 12 of 57
3822 Group (A ver.)
MEMORY
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains con-
trol registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function regis-
ter (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area.
Access to this area with only 2 bytes is possible in the special
page addressing mode.
Fig. 9 Memory map diagram
1
9
2
2
5
6
3
8
4
5
1
2
6
4
0
7
6
8
8
9
6
1
0
2
4
0
0
F
F
1
6
0
1
3
F1
6
0
1
B
F1
6
0
2
3
F1
6
0
2
B
F1
6
0
3
3
F1
6
0
3
B
F1
6
0
4
3
F1
6
R
A
M
a
r
e
a
R
A
M
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(
b
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s
)
A
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X
X
X
X1
6
4
0
9
6
8
1
9
2
1
2
2
8
8
1
6
3
8
4
2
0
4
8
0
2
4
5
7
6
2
8
6
7
2
3
2
7
6
8
3
6
8
6
4
4
0
9
6
0
4
5
0
5
6
4
9
1
5
2
F
0
0
0
1
6
E
0
0
01
6
D
0
0
01
6
C
0
0
01
6
B
0
0
01
6
A
0
0
01
6
9
0
0
01
6
8
0
0
01
6
7
0
0
01
6
6
0
0
01
6
5
0
0
01
6
4
0
0
01
6
F
0
8
0
1
6
E
0
8
01
6
D
0
8
01
6
C
0
8
01
6
B
0
8
01
6
A
0
8
01
6
9
0
8
01
6
8
0
8
01
6
7
0
8
01
6
6
0
8
01
6
5
0
8
01
6
4
0
8
01
6
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6
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Z
Z
Z1
6
0
1
0
0
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0
0
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1
6
0
0
4
0
1
6
0
8
4
0
1
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F
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0
0
1
6
F
F
D
C
1
6
F
F
F
E
1
6
F
F
F
F
1
6
X
X
X
X
1
6
Y
Y
Y
Y
1
6
Z
Z
Z
Z
1
6
R
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M
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e
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A
M
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a
Rev.1.20 Dec 24, 2003 page 13 of 57
3822 Group (A ver.)
Fig. 10 Memory map of special function register (SFR)
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
Port P0 (P0)
Port P1 (P1)
Port P1 output control register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P6 (P6)
Port P6 direction register (P6D)
Port P7 (P7)
Port P7 direction register (P7D)
Serial I/O status register (SIOSTS)
Serial I/O control register (SIO1CON)
UART control register (UARTCON)
Baud rate generator (BRG)
Interrupt control register 2(ICON2)
Timer 3 (T3)
Timer X mode register (TXM)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1(IREQ1)
Interrupt request register 2(IREQ2)
Interrupt control register 1(ICON1)
Timer X (low) (TXL)
Timer Y (low) (TYL)
Timer 1 (T1)
Timer 2 (T2)
Timer X (high) (TXH)
Timer Y (high) (TYH)
PULL register A (PULLA)
PULL register B (PULLB)
Timer Y mode register (TYM)
Timer 123 mode register (T123M)
φ output control register (CKOUT)
Segment output enable register (SEG)
LCD mode register (LM)
A-D control register (ADCON)
A-D conversion register (AD)
Transmit/Receive buffer register(TB/RB)
Port P0 direction register (P0D)
Rev.1.20 Dec 24, 2003 page 14 of 57
3822 Group (A ver.)
I/O PORTS
Direction Registers (ports P2, P41-P47, and
P5-P7)
The 3822 group has 49 programmable I/O pins arranged in seven
I/O ports (ports P0–P2, P41–P47 and P5-P7). The I/O ports P2,
P41–P47 and P5-P7 have direction registers which determine the
input/output direction of each individual pin. Each bit in a direction
register corresponds to one pin, and each pin can be set to be in-
put port or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin be-
comes an output pin.
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are
floating. If a pin set to input is written to, only the port output latch
is written to and the pin remains floating.
Direction Registers (ports P0 and P1)
Ports P0 and P1 have direction registers which determine the in-
put/output direction of each individual port.
Each port in a direction register corresponds to one port, each port
can be set to be input or output. When “0” is written to the bit 0 of
a direction register, that port becomes an input port. When “1” is
written to that port, that port becomes an output port. Bits 1 to 7 of
ports P0 and P1 direction registers are not used.
Ports P3 and P40
These ports are only for input.
Pull-up/Pull-down Control
By setting the PULL register A (address 001616) or the PULL reg-
ister B (address 001716), ports except for port P40 can control
either pull-down or pull-up (pins that are shared with the segment
output pins for LCD are pull-down; all other pins are pull-up) with
a program.
However, the contents of PULL register A and PULL register B do
not affect ports programmed as the output ports.
Fig. 11 Structure of PULL register A and PULL register B
P
0
0
–
P
0
7
p
u
l
l
-
d
o
w
n
P
1
0
–
P
1
7
p
u
l
l
-
d
o
w
n
P
2
0
–
P
2
7
p
u
l
l
-
u
p
P
3
4
–
P
3
7
p
u
l
l
-
d
o
w
n
P
7
0
,
P
7
1
p
u
l
l
-
u
p
N
o
t
u
s
e
d
(
r
e
t
u
r
n
“
0
”
w
h
e
n
r
e
a
d
)
P
U
L
L
r
e
g
i
s
t
e
r
A
(
P
U
L
L
A
:
a
d
d
r
e
s
s
0
0
1
6
1
6
)
b
7
b
0
P
4
1
–
P
4
3
p
u
l
l
-
u
p
P
4
4
–
P
4
7
p
u
l
l
-
u
p
P
5
0
–
P
5
3
p
u
l
l
-
u
p
P
5
4
–
P
5
7
p
u
l
l
-
u
p
P
6
0
–
P
6
3
p
u
l
l
-
u
p
P
6
4
–
P
6
7
p
u
l
l
-
u
p
N
o
t
u
s
e
d
(
r
e
t
u
r
n
“
0
”
w
h
e
n
r
e
a
d
)
0
:
D
i
s
a
b
l
e
1
:
E
n
a
b
l
e
P
U
L
L
r
e
g
i
s
t
e
r
B
(
P
U
L
L
B
:
a
d
d
r
e
s
s
0
0
1
7
1
6
)
b
7
b
0
N
o
t
e:
T
h
e
c
o
n
t
e
n
t
s
o
f
P
U
L
L
r
e
g
i
s
t
e
r
A
a
n
d
P
U
L
L
r
e
g
i
s
t
e
r
B
d
o
n
o
t
a
f
f
e
c
t
p
o
r
t
s
p
r
o
g
r
a
m
m
e
d
a
s
t
h
e
o
u
t
p
u
t
p
o
r
t
.
Rev.1.20 Dec 24, 2003 page 15 of 57
3822 Group (A ver.)
Real time port
function output
A-D conversion input
A-D trigger input
Diagram No.
Related SFRs
Input/Output
Name
Pin Non-Port Function
I/O Format
Table 6 List of I/O port function
P00/SEG16–
P07/SEG23
P10/SEG24–
P17/SEG31
P20–P27
P34/SEG12–
P37/SEG15
P40
P41/φ
P42/INT0,
P43/INT1
P44/RXD
P45/TXD
P46/SCLK
P47/SRDY
P50/INT2,
P51/INT3
P52/RTP0,
P53/RTP1
P54/CNTR0
Port P0
Port P1
Port P2
Port P3
Port P4
Input/output,
individual ports
Input/output,
individual bits
Input
Input
Input/output,
individual bits
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS compatible
input level
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
LCD segment output
Key input (key-on
wake-up) interrupt
input
LCD segment output
φ clock output
External interrupt input
Serial I/O function I/O
External interrupt input
Timer X function I/O
Timer Y function input
Timer 2 function output
PULL register A
Segment output enable
register
PULL register A
Interrupt control register 2
PULL register A
Segment output enable
register
PULL register B
φ
output control register
PULL register B
Interrupt edge selection
register
PULL register B
Serial I/O control register
Serial I/O status register
UART control register
PULL register B
Interrupt edge selection
register
PULL register B
Timer X mode register
PULL register B
Timer X mode register
PULL register B
Timer Y mode register
PULL register B
Timer 123 mode register
PULL register B
A-D control register
PULL register A
CPU mode register
(1)
(2)
(3)
(4)
(6)
(5)
(2)
(8)
(7)
Port P5
(9)
(2)
Input/output,
individual bits
(10)
P55/CNTR1
(11)
(12)
(13)
(12)
(14)
P56/TOUT
P57/ADT
P60/AN0–
P67/AN7
(15)
P70/XCOUT
P71/XCIN
COM0–COM3
SEG0–SEG11
(16)
(17)
(18)
Input/output,
individual bits
Input/output,
individual bits
Output
Output
Sub-clock
generating circuit I/O
LCD common output
LCD segment output
Port P6
Port P7
Common
Segment LCD mode register
Notes 1: For details of how to use double function ports as function I/O ports, refer to the applicable sections.
2: When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
Especially, power source current may increase during execution of the STP and WIT instructions.
Fix the unused input pins to “H” or “L” through a resistor.
Rev.1.20 Dec 24, 2003 page 16 of 57
3822 Group (A ver.)
Fig. 12 Port block diagram (1)
(
3
)
P
o
r
t
s
P
3
4
–
P
37
V
L
2
/
V
L
3
V
L
1
/
V
S
S
S
e
g
m
e
n
t
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
V
L
2
/
V
L
3
V
L
1
/
V
S
S
(
N
o
t
e
)
(
2
)
P
o
r
t
s
P
2
,
P
4
2
,
P
4
3
,
P
5
0
,
P
51
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
5
)
P
o
r
t
P
41
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
6
)
P
o
r
t
P
44
R
e
c
e
i
v
e
e
n
a
b
l
e
b
i
t
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
4
)
P
o
r
t
P
40
D
a
t
a
b
u
s
P
u
l
l
-
d
o
w
n
c
o
n
t
r
o
l
S
e
g
m
e
n
t
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
D
a
t
a
b
u
s
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
l
a
t
c
h
P
u
l
l
-
d
o
w
n
c
o
n
t
r
o
l
S
e
g
m
e
n
t
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
D
a
t
a
b
u
s
P
o
r
t
l
a
t
c
h
P
u
l
l
-
u
p
c
o
n
t
r
o
l
K
e
y
i
n
p
u
t
(
K
e
y
-
o
n
w
a
k
e
-
u
p
)
i
n
t
e
r
r
u
p
t
i
n
p
u
t
I
N
T0–
I
N
T3
i
n
t
e
r
r
u
p
t
i
n
p
u
t
φ
φ
o
u
t
p
u
t
c
o
n
t
r
o
l
b
i
t
P
u
l
l
-
u
p
c
o
n
t
r
o
l
D
a
t
a
b
u
s
P
o
r
t
l
a
t
c
h
P
u
l
l
-
u
p
c
o
n
t
r
o
l
S
e
r
i
a
l
I
/
O
e
n
a
b
l
e
b
i
t
S
e
r
i
a
l
I
/
O
i
n
p
u
t
D
a
t
a
b
u
s
P
o
r
t
l
a
t
c
h
D
a
t
a
b
u
s
(
1
)
P
o
r
t
s
P
0
,
P
1
N
o
t
e
:
B
i
t
0
o
f
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
.
Rev.1.20 Dec 24, 2003 page 17 of 57
3822 Group (A ver.)
Fig. 13 Port block diagram (2)
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
l
a
t
c
h
S
e
r
i
a
l
I
/
O
e
n
a
b
l
e
b
i
t
T
r
a
n
s
m
i
t
e
n
a
b
l
e
b
i
t
P
4
5
/
T
x
D
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
P
u
l
l
-
u
p
c
o
n
t
r
o
l
(
7
)
P
o
r
t
P
45
S
e
r
i
a
l
I
/
O
o
u
t
p
u
t
D
a
t
a
b
u
s
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
l
a
t
c
h
D
a
t
a
b
u
s
S
e
r
i
a
l
I
/
O
r
e
a
d
y
o
u
t
p
u
t
S
e
r
i
a
l
I
/
O
m
o
d
e
s
e
l
e
c
t
i
o
n
b
i
t
P
u
l
l
-
u
p
c
o
n
t
r
o
l
(
9
)
P
o
r
t
P
47
(
8
)
P
o
r
t
P
46
S
e
r
i
a
l
I
/
O
c
l
o
c
k
-
s
y
n
c
h
r
o
n
i
z
e
d
s
e
l
e
c
t
i
o
n
b
i
t
S
e
r
i
a
l
I
/
O
e
n
a
b
l
e
b
i
t
S
e
r
i
a
l
I
/
O
m
o
d
e
s
e
l
e
c
t
i
o
n
b
i
t
S
e
r
i
a
l
I
/
O
e
n
a
b
l
e
b
i
t
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
l
a
t
c
h
S
e
r
i
a
l
I
/
O
c
l
o
c
k
o
u
t
p
u
t
D
a
t
a
b
u
s
S
e
r
i
a
l
I
/
O
c
l
o
c
k
i
n
p
u
t
P
u
l
l
-
u
p
c
o
n
t
r
o
l
(
1
0
)
P
o
r
t
s
P
5
2
,
P
53
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
l
a
t
c
h
D
a
t
a
b
u
s
P
u
l
l
-
u
p
c
o
n
t
r
o
l
R
e
a
l
t
i
m
e
p
o
r
t
c
o
n
t
r
o
l
b
i
t
D
a
t
a
f
o
r
r
e
a
l
t
i
m
e
p
o
r
t
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
l
a
t
c
h
D
a
t
a
b
u
s
P
u
l
l
-
u
p
c
o
n
t
r
o
l
(
1
2
)
P
o
r
t
s
P
5
5
,
P
57
C
N
T
R
1
i
n
t
e
r
r
u
p
t
i
n
p
u
t
A
-
D
t
r
i
g
g
e
r
i
n
t
e
r
r
u
p
t
i
n
p
u
t
(
1
1
)
P
o
r
t
P
54
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
l
a
t
c
h
D
a
t
a
b
u
s
P
u
l
l
-
u
p
c
o
n
t
r
o
l
T
i
m
e
r
X
o
p
e
r
a
t
i
n
g
m
o
d
e
b
i
t
T
i
m
e
r
o
u
t
p
u
t
C
N
T
R
0
i
n
t
e
r
r
u
p
t
i
n
p
u
t
S
e
r
i
a
l
I
/
O
e
n
a
b
l
e
b
i
t
S
R
D
Y
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
(
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
s
e
l
e
c
t
i
o
n
)
Rev.1.20 Dec 24, 2003 page 18 of 57
3822 Group (A ver.)
Fig. 14 Port block diagram (3)
V
L
2
/
V
L
3
V
L
1
/
V
S
S
(
1
3
)
P
o
r
t
P
56
D
a
t
a
b
u
s
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
l
a
t
c
h
P
u
l
-
u
p
c
o
n
t
r
o
l
T
O
U
T
o
u
t
p
u
t
c
o
n
t
r
o
l
b
i
t
T
i
m
e
r
o
u
t
p
u
t
(
1
4
)
P
o
r
t
P
6
D
a
t
a
b
u
s
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
l
a
t
c
h
P
u
l
l
-
u
p
c
o
n
t
r
o
l
A
-
D
c
o
n
v
e
r
s
i
o
n
i
n
p
u
t
A
n
a
l
o
g
i
n
p
u
t
p
i
n
s
e
l
e
c
t
i
o
n
b
i
t
(
1
5
)
P
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Rev.1.20 Dec 24, 2003 page 19 of 57
3822 Group (A ver.)
INTERRUPTS
Interrupts occur by seventeen sources: eight external, eight inter-
nal, and one software.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software
interrupt set by the BRK instruction. An interrupt occurs if the cor-
responding interrupt request and enable bits are “1” and the
interrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
flag disables all interrupts except the BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt Operation
Upon acceptance of an interrupt the following operations are auto-
matically performed:
1. The contents of the program counter and processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding
interrupt request bit is cleared.
3. The interrupt jump destination address is read from the vec-
tor table into the program counter.
■Notes on interrupts
When setting the followings, the interrupt request bit may be set to
“1”.
•When setting external interrupt active edge
Related register: Interrupt edge selection register (address 3A16)
Timer X mode register (address 2716)
Timer Y mode register (address 2816)
•When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: A-D control regsiter (address 3416)
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
➀Set the corresponding interrupt enable bit to “0” (disabled).
➁Set the interrupt edge select bit or the interrupt source select bit.
➂Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
➃Set the corresponding interrupt enable bit to “1” (enabled).
Notes1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Table 7 Interrupt vector addresses and priority
Remarks
Interrupt Request
Generating Conditions
At reset
At detection of either rising or
falling edge of INT0 input
At detection of either rising or
falling edge of INT1 input
At completion of serial I/O data
reception
At completion of serial I/O trans-
mit shift or when transmission
buffer is empty
Interrupt Source LowHigh
Priority V ector Addresses (Note 1)
Reset (Note 2)
INT0
INT1
Serial I/O
reception
Serial I/O
transmission
Timer X
Timer Y
Timer 2
Timer 3
CNTR0
CNTR1
Timer 1
INT2
INT3
Key input
(Key-on wake-up)
ADT
A-D conversion
BRK instruction
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
At timer 1 underflow
At detection of either rising or
falling edge of INT2 input
At detection of either rising or
falling edge of INT3 input
At falling of conjunction of input
level for port P2 (at input mode)
At falling of ADT input
At completion of A-D conversion
At BRK instruction execution
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O is selected
Valid when serial I/O is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(Valid at falling)
Valid when ADT interrupt is se-
lected, External interrupt
(Valid at falling)
Valid when A-D interrupt is se-
lected
Non-maskable software interrupt
Rev.1.20 Dec 24, 2003 page 20 of 57
3822 Group (A ver.)
Fig. 15 Interrupt control
Fig. 16 Structure of interrupt-related registers
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset Interrupt request
b7 b0 Interrupt edge selection register
INT0 interrupt edge selection bit
INT1 interrupt edge selection bit
INT2 interrupt edge selection bit
INT3 interrupt edge selection bit
Not used (return “0” when read)
(INTEDGE : address 003A16)
Interrupt request register 1
INT0 interrupt request bit
INT1 interrupt request bit
Serial I/O receive interrupt request bit
Serial I/O transmit interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
Interrupt control register 1
INT0 interrupt enable bit
INT1 interrupt enable bit
Serial I/O receive interrupt enable bit
Serial I/O transmit interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
0 : No interrupt request issued
1 : Interrupt request issued
(IREQ1 : address 003C16)
(ICON1 : address 003E16)
Interrupt request register 2
CNTR0 interrupt request bit
CNTR1 interrupt request bit
Timer 1 interrupt request bit
INT2 interrupt request bit
INT3 interrupt request bit
Key input interrupt request bit
ADT/AD conversion interrupt request bit
Not used (returns “0” when read)
(IREQ2 : address 003D16)
Interrupt control register 2
CNTR0 interrupt enable bit
CNTR1 interrupt enable bit
Timer 1 interrupt enable bit
INT2 interrupt enable bit
INT3 interrupt enable bit
Key input interrupt enable bit
ADT/AD conversion interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit.)
0 : Interrupts disabled
1 : Interrupts enabled
(ICON2 : address 003F16)
0 : Falling edge active
1 : Rising edge active
b7 b0
b7 b0
b7 b0
b7 b0
Rev.1.20 Dec 24, 2003 page 21 of 57
3822 Group (A ver.)
Key Input Interrupt (Key-on wake-up)
A Key-on wake-up interrupt request is generated by applying a
falling edge to any pin of port P2 that have been set to input mode.
In other words, it is gener1ated when AND of input level goes from
“1” to “0”. An example of using a key input interrupt is shown in
Figure 17, where an interrupt request is generated by pressing
one of the keys consisted as an active-low key matrix which inputs
to ports P20–P23.
Fig. 17 Connection example when using key input interrupt and port P2 block diagram
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Rev.1.20 Dec 24, 2003 page 22 of 57
3822 Group (A ver.)
TIMERS
The 3822 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “0016”,
an underflow occurs at the next count pulse and the correspond-
ing timer latch is reloaded into the timer and the count is
continued. When a timer underflows, the interrupt request bit cor-
responding to that timer is set to “1”.
Read and write operation on 16-bit timer must be performed for
both high and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write the
low-order byte first. The 16-bit timer cannot perform the correct
operation when reading during the write operation, or when writing
during the read operation.
Fig. 18 Timer block diagram
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/
2
Rev.1.20 Dec 24, 2003 page 23 of 57
3822 Group (A ver.)
Timer X
Timer X is a 16-bit timer that can be selected in one of four modes
and can be controlled the timer X write and the real time port by
setting the timer X mode register.
(1) Timer Mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).
(2) Pulse Output Mode
Each time the timer underflows, a signal output from the CNTR0
pin is inverted. Except for this, the operation in pulse output mode
is the same as in timer mode. When using a timer in this mode,
set the corresponding port P54 direction register to output mode.
(3) Event Counter Mode
The timer counts signals input through the CNTR0 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corre-
sponding port P54 direction register to input mode.
(4) Pulse Width Measurement Mode
The count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode). If
CNTR0 active edge switch bit is “0”, the timer counts while the in-
put signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while
the input signal of CNTR0 pin is at “L”. When using a timer in this
mode, set the corresponding port P54 direction register to input
mode.
●Timer X write control
If the timer X write control bit is “0”, when the value is written in the
address of timer X, the value is loaded in the timer X and the latch
at the same time.
If the timer X write control bit is “1”, when the value is written in the
address of timer X, the value is loaded only in the latch. The value
in the latch is loaded in timer X after timer X underflows.
If the value is written in latch only, when writing in the timer latch at
the timer underflow, the value is set in the timer and the latch at
one time. Additionally, unexpected value may be set in the high-or-
der counter when the writing in high-order latch and the underflow
of timer X are performed at the same timing.
●Real time port control
While the real time port function is valid, data for the real time port
are output from ports P52 and P53 each time the timer X
underflows. (However, after rewriting a data for real time port, if
the real time port control bit is changed from “0” to “1”, data are
output independent of the timer X operation.) If the data for the
real time port is changed while the real time port function is valid,
the changed data are output at the next underflow of timer X.
Before using this function, set the corresponding port direction
registers to output mode.
■Note on CNTR0 interrupt active edge
selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
Fig. 19 Structure of timer X mode register
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Rev.1.20 Dec 24, 2003 page 24 of 57
3822 Group (A ver.)
Timer Y
Timer Y is a 16-bit timer that can be selected in one of four modes.
(1) Timer Mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).
(2) Period Measurement Mode
CNTR1 interrupt request is generated at rising/falling edge of
CNTR1 pin input signal. Simultaneously, the value in timer Y latch
is reloaded in timer Y and timer Y continues counting down. Ex-
cept for the above-mentioned, the operation in period
measurement mode is the same as in timer mode.
The timer value just before the reloading at rising/falling of CNTR1
pin input signal is retained until the timer Y is read once after the
reload.
The rising/falling timing of CNTR1 pin input signal is found by
CNTR1 interrupt. When using a timer in this mode, set the corre-
sponding port P55 direction register to input mode.
(3) Event Counter Mode
The timer counts signals input through the CNTR1 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corre-
sponding port P55 direction register to input mode.
(4) Pulse Width HL Continuously Measurement
Mode
CNTR1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode. When using a timer in this mode, set
the corresponding port P55 direction register to input mode.
■Note on CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit. However, in pulse width HL continuously measurement
mode, CNTR1 interrupt request is generated at both rising and
falling edges of CNTR1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
Fig. 20 Structure of timer Y mode register
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Rev.1.20 Dec 24, 2003 page 25 of 57
3822 Group (A ver.)
Timer 1, Timer 2, Timer 3
Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for
each timer can be selected by timer 123 mode register. The timer
latch value is not affected by a change of the count source. How-
ever, because changing the count source may cause an
inadvertent count down of the timer, rewrite the value of timer
whenever the count source is changed.
●Timer 2 write control
If the timer 2 write control bit is “0”, when the value is written in the
address of timer 2, the value is loaded in the timer 2 and the latch
at the same time.
If the timer 2 write control bit is “1”, when the value is written in the
address of timer 2, the value is loaded only in the latch. The value
in the latch is loaded in timer 2 after timer 2 underflows.
●Timer 2 output control
When the timer 2 (TOUT) is output enabled, an inversion signal
from the TOUT pin is output each time timer 2 underflows.
In this case, set the port shared with the TOUT pin to the output
mode.
■Notes on timer 1 to timer 3
When the count source of timer 1 to 3 is changed, the timer count-
ing value may be changed large because a thin pulse is generated
in count input of timer . If timer 1 output is selected as the count
source of timer 2 or timer 3, when timer 1 is written, the counting
value of timer 2 or timer 3 may be changed large because a thin
pulse is generated in timer 1 output.
Therefore, set the value of timer in the order of timer 1, timer 2
and timer 3 after the count source selection of timer 1 to 3.
Fig. 21 Structure of timer 123 mode register
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Rev.1.20 Dec 24, 2003 page 26 of 57
3822 Group (A ver.)
SERIAL I/O
Serial I/O can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O can be selected by setting the mode
selection bit of the serial I/O control register to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the transmit/receive buffer register.
Fig. 22 Block diagram of clock synchronous serial I/O
Fig. 23 Operation of clock synchronous serial I/O function
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Rev.1.20 Dec 24, 2003 page 27 of 57
3822 Group (A ver.)
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit of the serial I/O control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer regis-
ter, but the two buffers have the same address in memory. Since
the shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer, and receive data is read from
the receive buffer.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer register can hold a character while the next
character is being received.
Fig. 24 Block diagram of UART serial I/O
Fig. 25 Operation of UART serial I/O function
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Rev.1.20 Dec 24, 2003 page 28 of 57
3822 Group (A ver.)
[Transmit Buffer/Receive Buffer Register
(TB/RB)] 001816
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer register is
write-only and the receive buffer register is read-only. If a charac-
ter bit length is 7 bits, the MSB of data stored in the receive buffer
register is “0”.
[Serial I/O Status Register (SIOSTS)] 001916
The read-only serial I/O status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O
status register clears all the error flags OE, PE, FE, and SE. Writ-
ing “0” to the serial I/O enable bit (SIOE) also clears all the status
flags, including the error flags.
All bits of the serial I/O status register are initialized to “0” at reset,
but if the transmit enable bit (bit 4) of the serial I/O control register
has been set to “1”, the transmit shift register shift completion flag
(bit 2) and the transmit buffer empty flag (bit 0) become “1”.
[Serial I/O Control Register (SIOCON)] 001A16
The serial I/O control register contains eight control bits for the se-
rial I/O function.
[UART Control Register (UARTCON) ]001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer. One bit in this register (bit 4) is
always valid and sets the output structure of the P45/TXD pin.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial trans-
fer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate genera-
tor.
■Notes on serial I/O
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission
enalbed, take the following sequence.
➀Set the serial I/O transmit interrupt enable bit to “0” (disabled).
➁Set the transmit enable bit to “1”.
➂Set the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
➃Set the serial I/O transmit interrupt enable bit to “1” (enabled).
Rev.1.20 Dec 24, 2003 page 29 of 57
3822 Group (A ver.)
Fig. 26 Structure of serial I/O control registers
B
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7
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0
Rev.1.20 Dec 24, 2003 page 30 of 57
3822 Group (A ver.)
A-D CONVERTER
[A-D Conversion Register (AD)] 003516
The A-D conversion register is a read-only register that contains
the result of an A-D conversion. When reading this register during
an A-D conversion, the previous conversion result is read.
[A-D Control Register (ADCON)] 003416
The A-D control register controls the A-D conversion process. Bits
0 to 2 of this register select specific analog input pins. Bit 3 signals
the completion of an A-D conversion. The value of this bit remains
at “0” during an A-D conversion, then changes to “1” when the
A-D conversion is completed. Writing “0” to this bit starts the A-D
conversion. Bit 4 controls the transistor which breaks the through
current of the resistor ladder. When bit 5, which is the AD external
trigger valid bit, is set to “1”, this bit enables A-D conversion even
by a falling edge of an ADT input. Set ports which share with ADT
pins to input when using an A-D external trigger.
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between
AVSS and VREF by 256, and outputs the divided voltages.
[Channel Selector]
The channel selector selects one of the input ports P67/AN7–P60/
AN0, and inputs it to the comparator.
[Comparator and Control Circuit]
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”.
Note that the comparator is constructed linked to a capacitor, so
set f(XIN) to at least 500 kHz during A-D conversion.
Use the clock divided from the main clock XIN as the internal clock φ.
Fig. 28 A-D converter block diagram
Fig. 27 Structure of A-D control register
A
-
D
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(
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w
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7
P
6
6
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6
P
6
5
/
A
N
5
P
6
4
/
A
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4
P
6
3
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3
P
6
2
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2
P
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1
P
5
7
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A
D
T
8
3
Rev.1.20 Dec 24, 2003 page 31 of 57
3822 Group (A ver.)
LCD DRIVE CONTROL CIRCUIT
The 3822 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
●LCD display RAM
●Segment output enable register
●LCD mode register
●Selector
●Timing controller
●Common driver
●Segment driver
●Bias control circuit
A maximum of 32 segment output pins and 4 common output pins
can be used.
Up to 128 pixels can be controlled for LCD display. When the LCD
Fig. 29 Structure of segment output enable register and LCD mode register
enable bit is set to “1” after data is set in the LCD mode register,
the segment output enable register and the LCD display RAM, the
LCD drive control circuit starts reading the display data automati-
cally, performs the bias control and the duty ratio control, and
displays the data on the LCD panel.
Table 8 Maximum number of display pixels at each duty ratio
Duty ratio Maximum number of display pixel
64 dots
or 8 segment LCD 8 digits
96 dots
or 8 segment LCD 12 digits
128 dots
or 8 segment LCD 16 digits
2
3
4
L
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3
9
1
6
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3
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1
N
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7
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Rev.1.20 Dec 24, 2003 page 32 of 57
3822 Group (A ver.)
Fig. 30 Block diagram of LCD controller/driver
C
O
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0
C
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1
C
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2
C
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Rev.1.20 Dec 24, 2003 page 33 of 57
3822 Group (A ver.)
Bias Control and Applied Voltage to LCD
Power Input Pins
To the LCD power input pins (VL1–VL3), apply the voltage shown
in Table 9 according to the bias value.
Select a bias value by the bias control bit (bit 2 of the LCD mode
register).
Common Pin and Duty Ratio Control
The common pins (COM0–COM3) to be used are determined by
duty ratio.
Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the
LCD mode register).
Fig. 31 Example of circuit at each bias
Table 10 Duty ratio control and common pins used
Duty
ratio
Common pins used
Notes1: COM2 and COM3 are open.
2: COM3 is open.
Bit 1 Bit 0 COM0, COM1 (Note 1)
Duty ratio selection bit
2
3
4
0
1
1
1
0
1COM0–COM2 (Note 2)
COM0–COM3
Table 9 Bias control and applied voltage to VL1–VL3
Bias value
1/3 bias
Voltage value
VL3=VLCD
VL2=2/3 VLCD
VL1=1/3 VLCD
Note 1: VLCD is the maximum value of supplied voltage for the
LCD panel.
1/2 bias VL3=VLCD
VL2=VL1=1/2 VLCD
C
o
n
t
r
a
s
t
c
o
n
t
r
o
l
1
/
2
b
i
a
s
1
/
3
b
i
a
s
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o
n
t
r
a
s
t
c
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n
t
r
o
l
V
L
3
R
4
R
5
R
4
=
R
5
R
1
R
2
R
3
R
1
=
R
2
=
R
3
V
L
2
V
L
1
V
L
3
V
L
2
V
L
1
Rev.1.20 Dec 24, 2003 page 34 of 57
3822 Group (A ver.)
LCD Display RAM
Address 004016 to 004F16 is the designated RAM for the LCD dis-
play. When “1” are written to these addresses, the corresponding
segments of the LCD display panel are turned on.
Fig. 32 LCD display RAM map
LCD Drive Timing
The LCDCK timing frequency (LCD drive timing) is generated in-
ternally and the frame frequency can be determined with the
following equation;
f(LCDCK) =
Frame frequency =
(frequency of count source for LCDCK)
(divider division ratio for LCD)
f(LCDCK)
(duty ratio)
B
i
t
A
d
d
r
e
s
s
7
0
0
4
0
1
6
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4
11
6
0
0
4
21
6
0
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4
31
6
0
0
4
41
6
0
0
4
51
6
0
0
4
61
6
0
0
4
71
6
0
0
4
81
6
0
0
4
91
6
0
0
4
A1
6
0
0
4
B1
6
0
0
4
C1
6
0
0
4
D1
6
0
0
4
E1
6
0
0
4
F1
6
C
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M
3
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1
2
3
4
5
6
C
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0
C
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1
C
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2
C
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3
C
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C
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C
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2
S
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1
S
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3
S
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5
S
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7
S
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9
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1
1
S
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1
3
S
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1
5
S
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1
7
S
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1
9
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2
1
S
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2
3
S
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2
5
S
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2
7
S
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2
9
S
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3
1
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S
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2
S
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4
S
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6
S
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8
S
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1
0
S
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1
2
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1
4
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1
6
S
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1
8
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2
0
S
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2
2
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E
G
2
4
S
E
G
2
6
S
E
G
2
8
S
E
G
3
0
Rev.1.20 Dec 24, 2003 page 35 of 57
3822 Group (A ver.)
Fig. 33 LCD drive waveform (1/2 bias)
I
n
t
e
r
n
a
l
l
o
g
i
c
L
C
D
C
K
t
i
m
i
n
g
1
/
4
d
u
t
y
V
o
l
t
a
g
e
l
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v
e
l
V
L
3
V
L
2
=
V
L
1
V
S
S
V
L
3
V
S
S
C
O
M
0
C
O
M
1
C
O
M
2
C
O
M
3
S
E
G
0
O
F
F
O
N
O
F
F
O
N
C
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M
3
C
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M
2
C
O
M
1
C
O
M
0
C
O
M
3
C
O
M
2
C
O
M
1
C
O
M
0
1
/
3
d
u
t
y
V
L
3
V
L
2
=
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L
1
V
S
S
V
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3
V
S
S
O
F
F
O
N
O
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O
F
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F
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1
/
2
d
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C
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C
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2
S
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0
C
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1
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0
V
L
3
V
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2
=
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1
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S
S
V
L
3
V
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O
F
F
O
N
O
F
F
O
N
O
F
F
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N
O
F
F
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N
C
O
M
0
C
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M
2
C
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M
1
C
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M
0
C
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M
2
C
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1
C
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0
C
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M
2
C
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1
C
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0
C
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1
C
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M
0
C
O
M
1
C
O
M
0
C
O
M
1
C
O
M
0
Rev.1.20 Dec 24, 2003 page 36 of 57
3822 Group (A ver.)
Fig. 34 LCD drive waveform (1/3 bias)
I
n
t
e
r
n
a
l
l
o
g
i
c
L
C
D
C
K
t
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m
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g
1
/
4
d
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t
y
V
o
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t
a
g
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l
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v
e
l
V
L
3
V
S
S
C
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M
0
C
O
M
1
C
O
M
2
C
O
M
3
S
E
G
0
O
F
F
O
N
O
F
F
O
N
C
O
M
3
C
O
M
2
C
O
M
1
C
O
M
0
C
O
M
3
C
O
M
2
C
O
M
1
C
O
M
0
1
/
3
d
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t
y
O
F
F
O
N
O
N
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F
F
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N
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F
F
1
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M
0
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M
2
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C
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M
1
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0
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F
F
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N
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F
F
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N
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F
F
O
N
O
F
F
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N
V
L
3
V
L
2
V
S
S
V
L
1
V
L
3
V
L
2
V
S
S
V
L
1
V
L
3
V
S
S
V
L
3
V
L
2
V
S
S
V
L
1
V
L
3
V
S
S
C
O
M
0
C
O
M
2
C
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M
1
C
O
M
0
C
O
M
2
C
O
M
1
C
O
M
0
C
O
M
2
C
O
M
1
C
O
M
0
C
O
M
1
C
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M
0
C
O
M
1
C
O
M
0
C
O
M
1
C
O
M
0
Rev.1.20 Dec 24, 2003 page 37 of 57
3822 Group (A ver.)
φφ
φφ
φ CLOCK SYSTEM OUTPUT FUNCTION
The internal system clock φ can be output from port P41 by setting
the φ output control register. Set bit 1 of the port P4 direction reg-
ister to “1” when outputting φ clock.
Fig. 35 Structure of φφ
φφ
φ output control register
φ
o
u
t
p
u
t
c
o
n
t
r
o
l
r
e
g
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r
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b
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:
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f
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n
c
t
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1
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c
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d
(
r
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n
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0
”
w
h
e
n
r
e
a
d
)
b
7
b
0
Rev.1.20 Dec 24, 2003 page 38 of 57
3822 Group (A ver.)
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an “L”
level for 2 µs or more. Then the RESET pin is returned to an “H”
level (the power source voltage should be between VCC(min.) and
5.5 V, and the quartz-crystal oscillator should be stable), reset is
released. After the reset is completed, the program starts from the
address contained in address FFFD16 (high-order byte) and ad-
dress FFFC16 (low-order byte). Make sure that the reset input
voltage meets VIL spec. when a power source voltage passes
VCC(min.).
Fig. 36 Reset Circuit Example
Fig. 37 Reset Sequence
P
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Rev.1.20 Dec 24, 2003 page 39 of 57
3822 Group (A ver.)
Fig. 38 Initial status of microcomputer after reset
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C
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D
1
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E
1
6
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1
6
(
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S
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(
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C
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C
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1
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✕✕✕✕✕ ✕✕
1
Rev.1.20 Dec 24, 2003 page 40 of 57
3822 Group (A ver.)
CLOCK GENERATING CIRCUIT
The 3822 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance
with the resonator manufacturer's recommended values. No exter-
nal resistor is needed between XIN and XOUT since a feed-back
resistor exists on-chip. However, an external feed-back resistor is
needed between XCIN and XCOUT.
To supply a clock signal externally, input it to the XIN pin and make
the XOUT pin open. The sub-clock XCIN-XCOUT oscillation circuit
cannot directly input clocks that are externally generated. Accord-
ingly, be sure to cause an external resonator to oscillate.
Immediately after poweron, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
Frequency Control
(1) Middle-speed Mode
The internal clock φ is the frequency of XIN divided by 8.
After reset, this mode is selected.
(2) High-speed Mode
The internal clock φ is half the frequency of XIN.
(3) Low-speed Mode
●The internal clock φ is half the frequency of XCIN.
●A low-power consumption operation can be realized by stopping
the main clock XIN in this mode. To stop the main clock, set bit 5
of the CPU mode register to “1”.
When the main clock XIN is restarted, set enough time for oscil-
lation to stabilize by programming.
Note: If you switch the mode between middle/high-speed and low-
speed, stabilize both XIN and XCIN oscillations. The
sufficient time is required for the sub-clock to stabilize, es-
pecially immediately after poweron and at returning from
stop mode. When switching the mode between middle/high-
speed and low-speed, set the frequency on condition that
f(XIN) > 3f(XCIN).
Fig. 39 Ceramic resonator circuit example
Fig. 40 External clock input circuit
Oscillation Control
(1) Stop Mode
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillators stop. Timer 1 is set to
“FF16” and timer 2 is set to “0116”.
Either XIN or XCIN divided by 16 is input to timer 1 as count
source, and the output of timer 1 is connected to timer 2. The bits
of the timer 123 mode register except bit 4 are cleared to “0”. Set
the timer 1 and timer 2 interrupt enable bits to disabled (“0”) be-
fore executing the STP instruction. Oscillator restarts at reset or
when an external interrupt is received, but the internal clock φ is
not supplied to the CPU until timer 2 underflows. This allows timer
for the clock circuit oscillation to stabilize.
(2) Wait Mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level. The states of XIN and XCIN are the same as the state be-
fore the executing the WIT instruction. The internal clock restarts
at reset or when an interrupt is received. Since the oscillator does
not stop, normal operation can be started immediately after the
clock is restarted.
X
I
N
E
x
t
e
r
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T
X
CIN
X
COUT
X
IN
X
OUT
C
IN
C
OU
T
C
CIN
C
COUT
Rf Rd
Rev.1.20 Dec 24, 2003 page 41 of 57
3822 Group (A ver.)
Fig.41 Clock generating circuit block diagram
W
I
T
i
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s
t
r
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c
t
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S
T
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“
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Rev.1.20 Dec 24, 2003 page 42 of 57
3822 Group (A ver.)
Fig. 42 State transitions of system clock
N
o
t
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s
1
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M
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8
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c
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m
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6
k
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=
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3
2
k
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c
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d
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=
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M
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t
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p
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M
4
=
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2
k
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c
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a
t
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n
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m
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d
e
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(
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6
k
H
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C
M
6
“
0
”
“
1
”
C
M
6
“
0
”
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1
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C
M
6
“
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”
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1
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C
M4“
0
”“
1
”
C
M7“
0
”“
1
”
C
M7“
0
”“
1
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C
M5“
0
”“
1
”
C
M5“
0
”“
1
”
C
M
4
C
M
6
“
0
”
“
1
”
“
0
”
“
1
”
C
M
4
C
M
6
“
0
”
“
1
”
“
1
”
“
0
”
C
M
5
C
M
6
“
0
”
“
1
”
“
0
”
“
1
”
C
M
5
C
M
6
“
0
”
“
1
”
“
1
”
“
0
”
Rev.1.20 Dec 24, 2003 page 43 of 57
3822 Group (A ver.)
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. Af-
ter a reset, initialize flags which affect program execution.
In particular, it is essential to initialize the index X mode (T) and
the decimal mode (D) flags because of their effect on calculations.
Interrupt
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt
request register, execute at least one instruction before perform-
ing a BBC or BBS instruction.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction be-
fore executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n + 1).
Multiplication and Division Instructions
The index mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
The execution of these instructions does not change the contents
of the processor status register.
Ports
The contents of the port direction registers cannot be read.
The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis-
ter as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a
direction register
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
Serial I/O
In clock synchronous serial I/O, if the receive side is using an ex-
ternal clock and it is to output the SRDY signal, set the transmit
enable bit, the receive enable bit, and the SRDY output enable bit
to “1”.
Serial I/O continues to output the final bit from the TXD pin after
transmission is completed.
A-D Converter
The comparator uses internal capacitors whose charge will be lost
if the clock frequency is too low.
Make sure that f(XIN) is at least 500 kHz during an A-D conver-
sion.
Do not execute the STP or WIT instruction during an A-D conver-
sion.
Instruction Execution Time
The instruction execution time is obtained by multiplying the fre-
quency of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The frequency of the internal clock φ is half of the XIN frequency.
Rev.1.20 Dec 24, 2003 page 44 of 57
3822 Group (A ver.)
NOTES ON USE
Countermeasures against noise
(1) Shortest wiring length
➀ Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin
as short as possible. Especially, connect a capacitor across the
RESET pin and the VSS pin with the shortest possible wiring
(within 20mm).
● Reason
The width of a pulse input into the RESET pin is determined by
the timing necessary conditions. If noise having a shorter pulse
width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is com-
pletely initialized. This may cause a program runaway. (2) Connection of bypass capacitor across VSS line and VCC line
In order to stabilize the system operation and avoid the latch-up,
connect an approximately 0.1
µ
F bypass capacitor across the VSS
line and the VCC line as follows:
• Connect a bypass capacitor across the VSS pin and the VCC pin
at equal length.
• Connect a bypass capacitor across the VSS pin and the VCC pin
with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS
line and VCC line.
• Connect the power source wiring via a bypass capacitor to the
VSS pin and the VCC pin.
➁ Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins
as short as possible.
• Make the length of wiring (within 20 mm) across the grounding
lead of a capacitor which is connected to an oscillator and the
VSS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS
patterns.
● Reason
If noise enters clock I/O pins, clock waveforms may be de-
formed. This may cause a program failure or program runaway.
Also, if a potential difference is caused by the noise between
the VSS level of a microcomputer and the VSS level of an oscil-
lator, the correct clock will not be input in the microcomputer.
RESET
Reset
circuit
Noise
V
SS
V
SS
Reset
circuit
V
SS
RESET
V
SS
N.G.
O.K.
Noise
XIN
XOUT
VSS
XIN
XOUT
VSS
N.G. O.K.
V
SS
V
CC






V
SS
V
CC










N.G. O.K.
Fig. 44 Wiring for clock I/O pins
Fig. 43 Wiring for the RESET pin
Fig. 45 Bypass capacitor across the VSS line and the VCC line
Rev.1.20 Dec 24, 2003 page 45 of 57
3822 Group (A ver.)
(3) Oscillator concerns
In order to obtain the stabilized operation clock on the user system
and its condition, contact the oscillator manufacturer and select
the oscillator and oscillation circuit constants. Be careful espe-
cially when range of votage and temperature is wide.
Also, take care to prevent an oscillator that generates clocks for a
microcomputer operation from being affected by other signals.
➀ Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as
possible from signal lines where a current larger than the toler-
ance of current value flows.
● Reason
In the system using a microcomputer, there are signal lines for
controlling motors, LEDs, and thermal heads or others. When a
large current flows through those signal lines, strong noise oc-
curs because of mutual inductance.
➁ Installing oscillator away from signal lines where potential levels
change frequently
Install an oscillator and a connecting pattern of an oscillator
away from signal lines where potential levels change frequently.
Also, do not cross such signal lines over the clock lines or the
signal lines which are sensitive to noise.
● Reason
Signal lines where potential levels change frequently (such as
the CNTR pin signal line) may affect other lines at signal rising
edge or falling edge. If such lines cross over a clock line, clock
waveforms may be deformed, which causes a microcomputer
failure or a program runaway.
➀ Keeping oscillator away from large current signal lines
➁ Installing oscillator away from signal lines where potential
levels change frequently
Fig. 47 Wiring for the VPP pin of One Time PROM
Fig. 46 Wiring for a large current signal line/
Wiring of signal
lines where potential levels change frequently
P4
0
/V
PP
V
SS
About 5kΩ
(4) Analog input
The analog input pin is connected to the capacitor of a voltage
comparator. Accordingly, sufficient accuracy may not be obtained
by the charge/discharge current at the time of A-D conversion
when the analog signal source of high-impedance is connected to
an analog input pin. In order to obtain the A-D conversion result
stabilized more, please lower the impedance of an analog signal
source, or add the smoothing capacitor to an analog input pin.
(5) Difference of memory type and size
When Mask ROM and PROM version and memory size differ in
one group, actual values such as an electrical characteristics, A-D
conversion accuracy, and the amount of -proof of noise incorrect
operation may differ from the ideal values.
When these products are used switching, perform system evalua-
tion for each product of every after confirming product
specification.
(6) Wiring to VPP pin of One Time PROM version
Connect an approximately 5 kΩ resistor to the VPP pin the
shortest possible in series and also to the VSS pin.
Note: Even when a circuit which included an approximately 5 kΩ
resistor is used in the Mask ROM version, the microcomputer
operates correctly.
● Reason
The VPP pin of the One Time PROM version is the power source
input pin for the built-in PROM. When programming in the built-in
PROM, the impedance of the VPP pin is low to allow the electric
current for writing flow into the built-in PROM. Because of this,
noise can enter easily. If noise enters the VPP pin, abnormal in-
struction codes or data are read from the built-in PROM, which
may cause a program runaway.
Electric Characteristic Differences Between
Mask ROM and One Time PROM Version MCUs
There are differences in electric characteristics, operation margin,
noise immunity, and noise radiation between Mask ROM and
One T ime PROM version MCUs due to the dif ference in the manufac-
turing processes.
When manufacturing an application system with the One TIme PROM
version and then switching to use of the Mask ROM version,
please perform sufficient evaluations for the commercial
samples of the Mask ROM version.
X
IN
X
OUT
V
SS
Microcompute
r
M
utual inductance
Large
current
GND
M
X
IN
X
OUT
V
SS
CNTR
Do not cross
N.G.
Rev.1.20 Dec 24, 2003 page 46 of 57
3822 Group (A ver.)
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
1.Mask ROM Order Confirmation Form✽
2.Mark Specification Form✽
3.Data to be written to ROM, in EPROM form (three identical cop-
ies) or one floppy disk
✽For the mask ROM confirmation and the mark specifications, re-
fer to the “Renesas Technology” Homepage (http://
www.renesas.com/en/rom/).
Rev.1.20 Dec 24, 2003 page 47 of 57
3822 Group (A ver.)
VO
VO
Pd
Topr
Tstg
–0.3 to 6.5 VPower source voltage
Input voltage P00–P07, P10–P17, P20–P27,
P34–P37, P40–P47, P50–P57
P60–P67, P70, P71
VCC
VI
Symbol Parameter Conditions Ratings Unit
All voltages are based on VSS.
Output transistors are cut off.
VI
VI
VI
VI
VO
VO
VO
Input voltage VL1
Input voltage VL2
Input voltage VL3
Input voltage RESET, XIN
Output voltage P00–P07, P10–P17
Output voltage P34–P37
Output voltage P20–P27, P41–P47,P50–P57,
P60–P67, P70, P71
Output voltage SEG0–SEG11
Output voltage XOUT
Power dissipation
Operating temperature
Storage temperature
At output port
At segment output
At segment output
–0.3 to VCC +0.3
–0.3 to VL2
VL1 to VL3
VL2 to 6.5
–0.3 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VL3
–0.3 to VL3
–0.3 to VCC +0.3
–0.3 to VL3
–0.3 to VCC +0.3
300
–20 to 85
–40 to 150
V
V
V
V
V
V
V
V
V
V
V
mW
°C
°C
Ta = 25°C
(VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
VCC
VCC
VCC
Symbol Parameter Limits
Min. V
V
V
V
V
V
V
V
V
V
V
V
V
Unit
4.5
4.0
3.0
2.0
3.0
2.0
1.8
1.8
0.15 ✕ f + 1.3
2.0
AVSS
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
0
0
Typ. Max.
Power source voltage
(Note 1)High-speed mode f(XIN) = 10 MHz
f(XIN) = 8 MHz
f(XIN) = 6 MHz
f(XIN) = 4 MHz
Middle-speed mode f(XIN) = 10 MHz
f(XIN) = 8 MHz
f(XIN) = 6 MHz
Low-speed mode
When oscillation starts (Note 2)
Table 11 Absolute maximum ratings (A version)
Table 12 Recommended operating conditions (A version)
Notes 1: When the A-D converter is used, refer to the recommended operating condition for A-D converter.
2: Oscillation start voltage and oscillation start time depend on the oscillator, the circuit constant and temperature. Especially high-frequency oscillator
will require some conditions of oscillation.
f : Means an oscillation frequency (MHz) of an oscillator. If it is 8, substitute 8 for “f”.
VSS
VREF
AVSS
VIA
Power source voltage
A-D conversion reference voltage
Analog power source voltage
Analog input voltage AN0–AN7
Rev.1.20 Dec 24, 2003 page 48 of 57
3822 Group (A ver.)
(VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
“H” input voltage P00–P07, P10–P17,P34–P37, P40, P41, P45, P47,
P52, P53,P56,P60–P67,P70,P71 (CM4= 0)
“H” input voltage P20–P27, P42–P44,P46,P50, P51, P54, P55, P57
“H” input voltage RESET
“H” input voltage XIN
“L” input voltage P00–P07, P10–P17,P34–P37, P40, P41, P45, P47, P52, P53,
P56,P60–P67,P70,P71 (CM4= 0)
“L” input voltage P20–P27, P42–P44,P46,P50, P51, P54, P55, P57
“L” input voltage RESET
“L” input voltage XIN
VCC
VCC
VCC
VCC
0.3 VCC
0.2 VCC
0.2 VCC
0.2 VCC
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
Symbol Parameter Limits
Min. V
V
V
V
V
V
V
V
Unit
0.7VCC
0.8VCC
0.8VCC
0.8VCC
0
0
0
0
Typ. Max.
Table 13 Recommended operating conditions (A version)
Rev.1.20 Dec 24, 2003 page 49 of 57
3822 Group (A ver.)
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17 (Note 2)
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
(Note 2)
P00–P07, P10–P17 (Note 2)
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
(Note 2)
P00–P07, P10–P17 (Note 3)
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
(Note 3)
P00–P07, P10–P17 (Note 3)
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
(Note 3)
–40
–40
40
40
–20
–20
20
20
–2
–5
(VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value
measured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is an average value measured over 100 ms.
4: When the A-D converter is used, refer to the recommended operating condition for A-D converter.
5: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
6: Oscillation start voltage and oscillation start time depend on the oscillator, the circuit constant and temperature. Especially high-frequency oscillator
will require some conditions of oscillation.
“H” total peak output current
“H” total peak output current
“L” total peak output current
“L” total peak output current
“H” total average output current
“H” total average output current
“L” total average output current
“L” total average output current
“H” peak output current
“H” peak output current
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
IOH(peak)
Symbol Parameter Limits
Min. mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Unit
Typ. Max.
IOL(peak)
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
5
10
–1.0
–2.5
mA
mA
mA
mA
mA
mA
“L” peak output current
“L” peak output current
“H” average output current
“H” average output current
“L” average output current
“L” average output current
Input frequency for timers X and Y
(duty cycle 50%)
IOL(avg)
f(CNTR0)
f(CNTR1)MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
kHz
(4.5 V ≤ VCC ≤ 5.5 V)
(4.0 V ≤ VCC ≤ 4.5 V)
(2.0 V ≤ VCC ≤ 4.0 V)
(VCC ≤ 2.0 V)
High-speed mode
(4.5 V ≤ VCC ≤ 5.5 V)
High-speed mode
(4.0 V ≤ VCC ≤ 4.5 V)
High-speed mode
(2.0 V ≤ VCC ≤ 4.0 V)
Middle-speed mode (Note 6)
(3.0 V ≤ VCC ≤ 5.5 V)
Middle-speed mode (Note 6)
(2.0 V ≤ VCC ≤ 5.5 V)
Middle-speed mode (Note 6) 32.768
Main clock input oscillation frequency
(duty cycle 50%)
(Note 4)
Sub-clock input oscillation frequency
(duty cycle 50%)
(Notes 5, 6)
f(XIN)
2.5
5.0
5.0
2 ✕ V
CC
– 4
V
CC
5 ✕ V
CC
– 8
10.0
4 ✕ V
CC
– 8
2 ✕ V
CC
10.0
8.0
6.0
50
Table 14 Recommended operating conditions (A version)
f(XCIN)
Rev.1.20 Dec 24, 2003 page 50 of 57
3822 Group (A ver.)
IOL = 10 mA
IOL = 2.5 mA
IOL = 2.5 mA
VCC = 2.5 V
IOL = 5 mA
IOL = 1.25 mA
IOL = 1.25 mA
VCC = 2.5 V
VOL
IOH = –2.5 mA
IOH = –0.6 mA
VCC = 2.5 V
IOH = –5 mA
IOH = –1.25 mA
IOH = –1.25 mA
VCC = 2.5 V
VVCC–2.0
“H” output voltage
P00–P07, P10–P17
Symbol Parameter Limits
Min. Unit
0.5
Typ. Max.
Test conditions
VOH
2.0
0.5
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
RESET : VCC = 2.2 V to 5.5 V
VI = VCC
Pull-downs “off”
VCC = 5 V, VI = VCC
Pull-downs “on”
VCC = 3 V, VI = VCC
Pull-downs “on”
VI = VCC
“H” output voltage
P20–P27, P41–P47, P50–P57, P60–P67,
P70, P71 (Note)
“L” output voltage
P00–P07, P10–P7
“L” output voltage
P20–P27, P41–P47, P50–P57, P60–P67,
P70, P71 (Note)
Hysteresis
INT0–INT3, ADT, CNTR0, CNTR1, P20–P27
Hysteresis SCLK, RXD
Hysteresis RESET
“H” input current
P00–P07, P10–P17, P34–P37
“H” input current
P20–P27, P40–P47, P50–P57, P60–P67,
P70, P71 (Note)
VOH
VOL
VT+ – VT–
VT+ – VT–
VT+ – VT–
IIH
IIH
IIH
VCC–2.0
VCC–0.5
30
6.0
–30
–6.0
0.5
0.5
70
2.0
0.5
45
140
5.0
5.0
–5.0
–5.0
–140
–45
V
V
V
V
V
V
V
V
V
IIH
IIL
VCC–1.0
VCC–1.0
V
V
V1.0
V1.0
5.0 µA
25
VI = VCC
VI = VCC
VI = VSS
VI = VSS
Pull-ups “off”
VCC = 5 V, VI = VSS
Pull-ups “on”
VCC = 3 V, VI = VSS
Pull-ups “on”
VI = VSS
VI = VSS
“H” input current RESET
“H” input current XIN
“L” input current
P00–P07, P10–P17, P34–P37,P40
“L” input current
P20–P27, P41–P47, P50–P57, P60–P67,
P70, P71 (Note)
“L” input current RESET
“L” input current XIN
4.0
–5.0
–70
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
IIL
IIL
IIL
–25
–4.0
Note: When “1” is set to the port XC switch bit (bit 4 at address 003B16) of CPU mode register, the drive ability of port P70 is different from the value above
mentioned.
Table 15 Electrical characteristics (A version)
Rev.1.20 Dec 24, 2003 page 51 of 57
3822 Group (A ver.)
(VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
V
5.5
• High-speed mode, VCC = 5 V
f(XIN) = 10 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter stopped
• Low-speed mode, VCC = 5 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 5 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
All oscillation stopped
(in STP state)
Output transistors “off”
Symbol Parameter Limits
Min. Unit
Typ. Max.
Ta = 25 °C
Ta = 85 °C
Test conditions
ICC Power source current
5.0
VRAM RAM retention voltage At clock stop mode 1.8
3.0
0.8
13
5.5
8.0
0.1
6.0
1.6
26
11
16
1.0
10
mA
mA
µA
µA
µA
µA
µA
mA10
Table 16 Electrical characteristics (A version)
4.0 8.0 µA
Rev.1.20 Dec 24, 2003 page 52 of 57
3822 Group (A ver.)
(VCC = 2.0 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, 4 MHz ≤ f(XIN) ≤ 10 MHz, in middle/high-speed mode unless otherwise noted)
Symbol Parameter Limits
Min. Unit
Typ. Max.
Test conditions
–Resolution
Absolute accuracy
(excluding quantization error) VCC = VREF = 2.2 V to 5.5 V
f(XIN) = 2 ✕ VCC MHz ≤ 10 MHz
VCC = VREF < 2.2 V
f(XIN) ≤ 12 ✕ VCC – 22 MHz
12
Bits
LSB
8
±2
Note: When an internal trigger is used in middle-speed mode, it is 14 µs.
µs
f(XIN) = 8 MHz
Conversion time
Ladder resistor
Reference power source input current
–
tCONV
RLADDER
IVREF
kΩ
µA
Analog port input currentIIA µA
35
150
VREF = 5 V
12.5
(Note)
100
200
5.0
50
Table 17 A-D converter characteristics (A version)
±3 LSB
Rev.1.20 Dec 24, 2003 page 53 of 57
3822 Group (A ver.)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Note: When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
Table 18 Timing requirements 1 (A version)
Note: When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
(VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Table 19 Timing requirements 2 (A version)
2
1000/(4 ✕ VCC–8)
100
45
40
45
40
1000/(2 ✕ VCC–4)
200
105
85
105
85
80
80
800
370
370
220
100
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
Serial I/O input hold time
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
t
su(R
X
D–S
CLK
)
th(SCLK–RXD)
Symbol Parameter Limits
Min. µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Typ. Max.
4.0 ≤ Vcc < 4.5 V
4.5 ≤ Vcc ≤ 5.5 V
4.0 ≤ Vcc < 4.5 V
4.5 ≤ Vcc ≤ 5.5 V
4.0 ≤ Vcc < 4.5 V
4.5 ≤ Vcc ≤ 5.5 V
4.0 ≤ Vcc < 4.5 V
4.5 ≤ Vcc ≤ 5.5 V
4.0 ≤ Vcc < 4.5 V
4.5 ≤ Vcc ≤ 5.5 V
4.0 ≤ Vcc < 4.5 V
4.5 ≤ Vcc ≤ 5.5 V
2
125
1000/(10 ✕ V
CC
–12)
50
70
50
70
1000/VCC
1000/(5 ✕ VCC–8)
tc(CNTR)/2–20
tc(CNTR)/2–20
230
230
2000
950
950
400
200
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
Serial I/O input hold time
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
t
su(R
X
D–S
CLK
)
th(SCLK–RXD)
Symbol Parameter Limits
Min. µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Typ. Max.
2.0 ≤ Vcc ≤ 4.0 V
Vcc < 2.0 V
2.0 ≤ Vcc ≤ 4.0 V
Vcc < 2.0 V
2.0 ≤ Vcc ≤ 4.0 V
Vcc < 2.0 V
2.0 ≤ Vcc ≤ 4.0 V
Vcc < 2.0 V
Rev.1.20 Dec 24, 2003 page 54 of 57
3822 Group (A ver.)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Notes : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note)
Serial I/O output valid time (Note)
Serial I/O clock output rising time
Serial I/O clock output falling time
140
30
30
Symbol Parameter Limits
Min. ns
ns
ns
ns
ns
ns
Unit
tC (SCLK)/2–30
tC (SCLK)/2–30
–30
Typ. Max.
twH(SCLK)
twL(SCLK)
td(SCLK–TXD)
tv(SCLK–TXD)
tr(SCLK)
tf(SCLK)
(VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
ns
ns
ns
ns
ns
ns
Unit
Notes : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note)
Serial I/O output valid time (Note)
Serial I/O clock output rising time
Serial I/O clock output falling time
350
100
100
Symbol Parameter Limits
Min.
tC (SCLK)/2–100
tC (SCLK)/2–100
–30
Max.
twH(SCLK)
twL(SCLK)
td(SCLK–TXD)
tv(SCLK–TXD)
tr(SCLK)
tf(SCLK)
Typ.
Fig. 48 Circuit for measuring output switching characteristics
Table 20 Switching characteristics 1 (A version)
Table 21 Switching characteristics 2 (A version)
M
e
a
s
u
r
e
m
e
n
t
o
u
t
p
u
t
p
i
n
1
0
0
p
F
C
M
O
S
o
u
t
p
u
t
N
o
t
e
:
W
h
e
n
b
i
t
4
o
f
t
h
e
U
A
R
T
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
a
d
d
r
e
s
s
0
0
1
B
1
6
)
i
s
“
1
”
.
(
N
-
c
h
a
n
n
e
l
o
p
e
n
-
d
r
a
i
n
o
u
t
p
u
t
m
o
d
e
)
N
-
c
h
a
n
n
e
l
o
p
e
n
-
d
r
a
i
n
o
u
t
p
u
t
(
N
o
t
e
)
1
k
Ω
1
0
0
p
F
M
e
a
s
u
r
e
m
e
n
t
o
u
t
p
u
t
p
i
n
Rev.1.20 Dec 24, 2003 page 55 of 57
3822 Group (A ver.)
Fig. 49 Timing diagram
t
W
(
R
E
S
E
T
)
0
.
8
V
C
C
0
.
2
V
C
C
R
E
S
E
T
t
C
(
XI
N
)
t
C
(
C
N
T
R
)
t
W
H
(
C
N
T
R
)
t
W
L
(
C
N
T
R
)
0
.
8
V
C
C
0
.
2
V
C
C
C
N
T
R
0
,
C
N
T
R1
t
W
H
(
I
N
T
)
t
W
L
(
I
N
T
)
0
.
8
V
C
C
0
.
2
V
C
C
I
N
T
0
–
I
N
T3
t
W
H
(
XI
N
)
t
W
L
(
XI
N
)
0
.
8
V
C
C
0
.
2
V
C
C
X
I
N
t
C
(
SC
L
K
)
t
W
L
(
SC
L
K
)
t
W
H
(
SC
L
K
)
0
.
2
V
C
C
0
.
8
V
C
C
S
C
L
K
tr
tf
t
d
(
SC
L
K-
TXD
)
t
v
(
SC
L
K-
TXD
)
T
X
D
R
X
D
0
.
2
V
C
C
0
.
8
V
C
C
t
s
u
(
RXD
-
SC
L
K
)
t
h
(
SC
L
K-
RXD
)
Rev.1.20 Dec 24, 2003 page 56 of 57
3822 Group (A ver.)
PACKAGE OUTLINE
QFP80-P-1420-0.80 1.58
Weight(g)
–
JEDEC Code
EIAJ Package Code Lead Material
Alloy 42
80P6N-A Plastic 80pin 14✕20mm body QFP
–
0.1
–
––
0.2
–
–
––
–
–––
–
Symbol Min Nom Max
A
A
2
b
c
D
E
H
E
L
L
1
y
b
2
Dimension in Millimeters
H
D
A
1
0.5 ––
I
2
1.3 ––
M
D
14.6 ––
M
E
20.6
10°0°0.1
1.4 0.80.60.4 23.122.822.5 17.116.816.5 0.8 20.220.019.8 14.214.013.8 0.20.150.13 0.450.350.3 2.8
03.05
e
e
e
E
c
H
E
1
80 65
40
64
41
25
24
H
D
D
M
D
M
E
A
F
A
1
A
2
L
1
L
y
b
2
I
2
Recommended Mount Pad
Detail F
x– –0.2
b
x
M
MMP
Rev.1.20 Dec 24, 2003 page 57 of 57
3822 Group (A ver.)
LQFP80-P-1212-0.5 Weight(g)
–0.47
JEDEC Code
EIAJ Package Code Lead Material
Cu Alloy
80P6Q-A
Plastic 80pin 12✕12mm body LQFP
–
0.1
–
––
0.2
–
–
––
–
–––
–
Symbol Min Nom Max
A
A
2
b
c
D
E
H
E
L
L
1
y
b
2
Dimension in Millimeters
H
D
A
1
0.225 ––
I
2
0.9 ––
M
D
12.4 ––
M
E
12.4
10°0°0.1
1.0 0.70.50.3 14.214.013.8 14.214.013.8 0.5 12.112.011.9 12.112.011.9 0.1750.1250.105 0.280.180.13 1.4
01.7
e
A
F
e
H
D
E
H
E
D
1
20
21 40
41
60
6180
y
Lp 0.45
–
–
0.6
0.25
–
0.75
–
0.08
x
A3
M
D
l
2
b
2
M
E
e
Recommended Mount Pad
b
x
M
A
1
A
2
L
1
L
Detail F
Lp
A3
c
MMP
REVISION HISTORY 3822 GROUP (A ver.) DATA SHEET
Rev. Date Description
Page Summary
(1/X)
1.0 09/26/02 First edition
1.1 10/10/02 [FEATURES] Power source voltage: f(XIN) = → f(XIN) ≤
Table 1 P0 and P1 Function: 8-bit output port → 8-bit I/O port
Fig. 4: M 6 A → M 6 A-
Table 6: [Notes] are revised.
Fig. 27: The explanation of VREF input switch bit is revised.
Table 16: VRAM Limits (Min.) is revised.
Table 17: Test conditions of Absolute accuracy are revised.
Tables 18, 19: Some parameters are added.
1
4
6
15
30
51
52
53
1.20 12/24/03 Fig. 5: “Under development” eliminated.
Fig. 39: a resistor is added to XOUT pin and Fig. title is revised.
DATA REQUIRED FOR MASK ORDERS: URL is revised.
Table 11: Input voltage VL3 is revised
Table 17: Test conditions of Absolute accuracy is revised.
7
40
46
47
52
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Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
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