R1LV1616HBG-I Series Wide Temperature Range Version 16 M SRAM (1-Mword 16-bit) REJ03C0263-0102 Rev. 1.02 Feb.20.2020 Description The R1LV1616HBG-I Series is 16-Mbit static RAM organized 1-Mword 16-bit with embedded ECC. R1LV1616HBG-I Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is packaged in 48-ball plastic FBGA for high density surface mounting. Features Single 3.0 V supply: 2.7 V to 3.6 V Fast access time: 45/55 ns (max) Power dissipation: Active: 9 mW/MHz (typ) Standby: 1.5 W (typ) Completely static memory. No clock or timing strobe required Equal access and cycle times Common data input and output. Three state output Battery backup operation. 2 chip selection for battery backup Temperature range: 40 to +85C Embedded ECC (error checking and correction) for single-bit error correction Ordering Information Type No. Access time Package R1LV1616HBG-4SI 45 ns 48-ball plastic FBGA with 0.75 mm ball pitch R1LV1616HBG-5SI 55 ns PTBG0048HF (48FHJ) Rev.1.02, Feb.20.2020, page 1 of 13 R1LV1616HBG-I Series Pin Arrangement 48-ball FBGA 1 2 3 4 5 6 A LB# OE# A0 A1 A2 CS2 B I/O8 UB# A3 A4 CS1# I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D Vss I/O11 A17 A7 I/O3 Vcc E Vcc I/O12 Vss A16 I/O4 Vss F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 A19 A12 A13 WE# I/O7 H A18 A8 A9 A10 A11 NU (Top view) Pin Description Pin name Function A0 to A19 Address input I/O0 to I/O15 Data input/output CS1# (CS1) Chip select 1 CS2 Chip select 2 WE# (WE) Write enable OE# (OE) Output enable LB# (LB) Lower byte select UB# (UB) Upper byte select VCC Power supply VSS Ground NU*1 Not used (test mode pin) Note: 1. This pin should be connected to a ground (VSS), or not be connected (open). Rev.1.02, Feb.20.2020, page 2 of 13 R1LV1616HBG-I Series Block Diagram LSB A19 A8 A9 A10 A11 A12 A13 A14 A16 A18 A15 A3 A6 MSB VCC VSS Row decoder I/O0 Input data control Memory matrix 8,192 x 128 x 16 ECC encoder Column I/O Column decoder ECC decoder I/O15 MSB A17 A7 A5 A4 A2 A1 A0 CS2 CS1# LB# UB# WE# Control logic OE# Rev.1.02, Feb.20.2020, page 3 of 13 LSB R1LV1616HBG-I Series Operation Table CS1# CS2 WE# OE# UB# LB# I/O0 to I/O7 I/O8 to I/O15 Operation H High-Z High-Z Standby L High-Z High-Z Standby H H High-Z High-Z Standby L H H L L L Dout Dout Read L H H L H L Dout High-Z Lower byte read L H H L L H High-Z Dout Upper byte read L H L L L Din Din Write L H L H L Din High-Z Lower byte write L H L L H High-Z Din Upper byte write L H H H High-Z High-Z Output disable Note: H: VIH, L: VIL, : VIH or VIL Absolute Maximum Ratings Parameter Symbol Value VCC 0.5 to +4.6 Power supply voltage relative to VSS 0.5*1 to VCC + Unit V 0.3*2 Terminal voltage on any pin relative to VSS VT V Power dissipation PT 1.0 W Storage temperature range Tstg 55 to +125 C Storage temperature range under bias Tbias 40 to +85 C Notes: 1. VT min: 2.0 V for pulse half-width 10 ns. 2. Maximum voltage is +4.6 V. DC Operating Conditions Parameter Symbol Min Typ Max Unit VCC 2.7 3.0 3.6 V VSS 0 0 0 V Input high voltage VIH 2.2 VCC + 0.3 V Input low voltage VIL 0.3 0.6 V 1 Ambient temperature range Ta 40 +85 C Supply voltage Note: 1. VIL min: 2.0 V for pulse half-width 10 ns. Rev.1.02, Feb.20.2020, page 4 of 13 Note R1LV1616HBG-I Series DC Characteristics Parameter Symbol Min Typ Max Unit Input leakage current |ILI| 1 A Vin = VSS to VCC Output leakage current |ILO| 1 A CS1# = VIH or CS2 = VIL or OE# = VIH or WE# = VIL or LB# = UB# = VIH, VI/O = VSS to VCC Operating current ICC 20 mA CS1# = VIL, CS2 = VIH, Others = VIH/ VIL, II/O = 0 mA ICC1 (READ) 22*1 35 mA Min. cycle, duty = 100%, II/O = 0 mA, CS1# = VIL, CS2 = VIH, WE# = VIH, Others = VIH/VIL ICC1 30*1 50 mA Min. cycle, duty = 100%, II/O = 0 mA, CS1# = VIL, CS2 = VIH, Others = VIH/VIL ICC2 (READ) 3*1 8 mA Cycle time = 70 ns, duty = 100%, II/O = 0 mA, CS1# = VIL, CS2 = VIH, WE# = VIH, Others = VIH/VIL Address increment scan or decrement scan ICC2 20*1 30 mA Cycle time = 70 ns, duty = 100%, II/O = 0 mA, CS1# = VIL, CS2 = VIH, Others = VIH/VIL Address increment scan or decrement scan ICC3 3*1 8 mA Cycle time = 1 s, duty = 100%, II/O = 0 mA, CS1# 0.2 V, CS2 VCC 0.2 V VIH VCC 0.2 V, VIL 0.2 V ISB 0.1*1 0.5 mA CS2 = VIL ISB1 0.5*1 8 A 0 V Vin (1) 0 V CS2 0.2 V or (2) CS1# VCC 0.2 V, CS2 VCC 0.2 V or (3) LB# = UB# VCC 0.2 V, CS2 VCC 0.2 V, CS1# 0.2 V Average value VOH 2.4 V IOH = 1 mA VOH VCC V IOH = 100 A Average operating current Standby current Output high voltage Test conditions 0.2 Output low voltage Notes: 1. VOL 0.4 V IOL = 2 mA VOL 0.2 V IOL = 100 A Typical values are at VCC = 3.0 V, Ta = +25C and not guaranteed. Rev.1.02, Feb.20.2020, page 5 of 13 R1LV1616HBG-I Series Capacitance (Ta = +25C, f = 1.0 MHz) Parameter Symbol Min Typ Max Unit Test conditions Note Input capacitance Cin 8 pF Vin = 0 V 1 Input/output capacitance CI/O 10 pF VI/O = 0 V 1 Note: 1. This parameter is sampled and not 100% tested. AC Characteristics (Ta = 40 to +85C, VCC = 2.7 V to 3.6 V) Test Conditions Input pulse levels: VIL = 0.4 V, VIH = 2.4 V Input rise and fall time: 5 ns Input and output timing reference levels: 1.4 V Output load: See figures (Including scope and jig) 1.4V RL = 500 Dout 50 pF Rev.1.02, Feb.20.2020, page 6 of 13 R1LV1616HBG-I Series Read Cycle Parameter Read cycle time Address access time Chip select access time Output enable to output valid Output hold from address change LB#, UB# access time Chip select to output in low-Z LB#, UB# enable to low-Z Output enable to output in low-Z Chip deselect to output in high-Z LB#, UB# disable to high-Z Output disable to output in high-Z Symbol tRC tAA tACS1 tACS2 tOE tOH tBA tCLZ1 tCLZ2 tBLZ tOLZ tCHZ1 tCHZ2 tBHZ tOHZ R1LV1616HBG-I -4SI -5SI Min Max Min Max 45 55 45 55 45 55 45 55 30 35 10 10 45 55 10 10 10 10 5 5 5 5 0 0 0 0 20 20 15 15 0 0 0 0 20 20 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 2, 3 2, 3 2, 3 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Write Cycle Parameter Write cycle time Address valid to end of write Chip selection to end of write Write pulse width LB#, UB# valid to end of write Address setup time Write recovery time Data to write time overlap Data hold from write time Output active from end of write Output disable to output in high-Z Write to output in high-Z Symbol tWC tAW tCW tWP tBW tAS tWR tDW tDH tOW tOHZ tWHZ R1LV1616HBG-I -4SI -5SI Min Max Min Max 45 55 45 50 45 50 35 40 45 50 0 0 0 0 25 25 0 0 5 5 0 15 0 20 0 15 0 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns Notes 5 4 6 7 2 1, 2 1, 2 Notes: 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to device. 4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB# going low or UB# going low. A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and LB# going high or UB# going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS1# going low or CS2 going high to the end of write. 6. tAS is measured from the address valid to the beginning of write. 7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle. Rev.1.02, Feb.20.2020, page 7 of 13 R1LV1616HBG-I Series Timing Waveform Read Cycle t RC Address*2 Valid address tAA tACS1 CS1# tCLZ1 CS2 tCHZ1 tACS2 tCLZ2 tCHZ2 tBHZ tBA LB#, UB# tBLZ tOHZ tOE OE# tOLZ Dout*3 High impedance Notes: 1. BYTE# > VCC - 0.2 V or BYTE# < 0.2 V 2. Word mode: A0 to A19 Byte mode: A-1 to A19 3. Word mode: I/O0 to I/O15 Byte mode: I/O0 to I/O7 Rev.1.02, Feb.20.2020, page 8 of 13 tOH Valid data R1LV1616HBG-I Series Write Cycle (1) (WE# Clock) tWC Valid address Address*2 tWR tCW CS1# tCW CS2 tBW LB#, UB# tAW tWP WE# tAS tDW tDH Valid data Din*3 tWHZ tOW High impedance Dout*3 Notes: 1. BYTE# > VCC - 0.2 V or BYTE# < 0.2 V 2. Word mode: A0 to A19 Byte mode: A-1 to A19 3. Word mode: I/O0 to I/O15 Byte mode: I/O0 to I/O7 Rev.1.02, Feb.20.2020, page 9 of 13 R1LV1616HBG-I Series Write Cycle (2) (CS1#, CS2 Clock, OE# = VIH) tWC Valid address Address*2 tAW tAS tCW tAS tCW tWR CS1# CS2 tBW LB#, UB# tWP WE# tDW Din*3 Dout*3 Notes: 1. BYTE# > VCC - 0.2 V or BYTE# < 0.2 V 2. Word mode: A0 to A19 Byte mode: A-1 to A19 3. Word mode: I/O0 to I/O15 Byte mode: I/O0 to I/O7 Rev.1.02, Feb.20.2020, page 10 of 13 Valid data High impedance tDH R1LV1616HBG-I Series Write Cycle (3) (LB#, UB# Clock, OE# = VIH) tWC Valid address Address tAW tCW tWR CS1# tCW CS2 tAS tBW UB# (LB#) tBW LB# (UB#) tWP WE# tDW Din-UB (Din-LB) Din-LB (Din-UB) Dout Note: 1. BYTE# > VCC - 0.2 V Rev.1.02, Feb.20.2020, page 11 of 13 tDH Valid data tDW Valid data High impedance tDH R1LV1616HBG-I Series Low VCC Data Retention Characteristics (Ta = 40 to +85C) Parameter Test conditions*2 Symbol Min Typ Max Unit VCC for data retention VDR 1.5 3.6 V Vin 0 V (1) 0 V CS2 0.2 V or (2) CS2 VCC 0.2 V, CS1# VCC 0.2 V or (3) LB# = UB# VCC 0.2 V, CS2 VCC 0.2 V, CS1# 0.2 V Data retention current ICCDR 0.5*1 8 A VCC = 3.0 V, Vin 0 V (1) 0 V CS2 0.2 V or (2) CS2 VCC 0.2 V, CS1# VCC 0.2 V or (3) LB# = UB# VCC 0.2 V, CS2 VCC 0.2 V, CS1# 0.2 V Average value Chip deselect to data retention time tCDR 0 ns See retention waveforms tR 5 ms Operation recovery time Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25C and not guaranteed. 2. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer, LB#, UB# buffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE#, OE#, CS1#, LB#, UB#, I/O) can be in the high impedance state. If CS1# controls data retention mode, CS2 must be CS2 VCC 0.2 V or 0 V CS2 0.2 V. The other input levels (address, WE#, OE#, LB#, UB#, I/O) can be in the high impedance state. Rev.1.02, Feb.20.2020, page 12 of 13 R1LV1616HBG-I Series Low VCC Data Retention Timing Waveform (1) (CS1# Controlled) t CDR Data retention mode tR V CC 2.7 V 2.2 V V DR CS1# 0V CS1# VCC - 0.2 V Low VCC Data Retention Timing Waveform (2) (CS2 Controlled) t CDR Data retention mode tR V CC 2.7 V CS2 V DR 0.6 V 0 V < CS2 < 0.2 V 0V Low VCC Data Retention Timing Waveform (3) (LB#, UB# Controlled) t CDR Data retention mode V CC 2.7 V 2.2 V V DR LB#, UB# 0V Rev.1.02, Feb.20.2020, page 13 of 13 LB#, UB# V CC - 0.2 V tR Revision History Rev. R1LV1616HBG-I Series Data Sheet Date Contents of Modification Page Description 0.01 Apr.29.2005 Initial issue 1.00 Sep.21.2005 Deletion of Preliminary 1.01 Feb.23.2017 1.02 Feb.20.2020 p.1,p.3 Disclosed embedded ECC features Last page Updated the Notice to the latest version All trademarks and registered trademarks are the property of their respective owners. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES ("RENESAS") PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES "AS IS" AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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