ACPL-798J
Optically Isolated Sigma-Delta Modulator with LVDS Interface
Data Sheet
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Description
The ACPL-798J is a 1-bit, second-order sigma-delta (Σ-∆)
modulator that oversamples an analog input signal into
a highspeed data stream with galvanic isolation based
on optical coupling technology. The ACPL-798J operates
from a 5 V power supply with dynamic range of 82 dB with
an appropriate digital lter. The dierential inputs of ±200
mV (full scale ±320 mV) are ideal for direct connection to
shunt resistors or other low-level signal sources in applica-
tions such as motor phase current measurement.
The analog input is continuously sampled by means of
sigma-delta over-sampling using external clock, coupled
across the isolation barrier, which allows synchronous
operation with any digital controller. The signal infor-
mation is contained in the modulator data, as a density
of ones with data rate up to 25 MHz, and the data are
encoded and transmitted across the isolation boundary
where they are recovered and decoded into high-speed
data stream of digital ones and zeros. The original signal
information can be reconstructed with a digital lter. The
ACPL-798J comes with an LVDS interface on both clock
inputs and data outputs for better signal integrity.
Combined with superior optical coupling technology,
the modulator delivers high noise margins and excellent
immunity against isolation-mode transients. With 0.5 mm
minimum distance through insulation (DTI), the ACPL-798J
provides reliable double protection and high working in-
sulation voltage, which is suitable for fail-safe designs.
This outstanding isolation performance is superior to al-
ternatives including devices based on capacitive or mag-
netic-coupling with DTI in micro-meter range. Oered in
an SO-16 package, the isolated ADC delivers the reliability,
small size, superior isolation and over-temperature perfor-
mance motor drive designers need to accurately measure
current at much lower price compared to traditional
current transducers.
Features
• Up to 25 MHz external clock input range
• LVDS clock and data interface.
• 1-bit, second-order sigma-delta modulator
• 16 bits resolution no missing codes (12 bits ENOB)
• 75dB Typical SNDR
• 3.5mV/°C maximum oset drift
• ±1% maximum gain error
• ±200 mV linear range with single 5 V supply
• –40°C to +105°C operating temperature range
• SO-16 package
• 25 kV/ms common-mode transient immunity
• Safety and regulatory approval (pending):
IEC/EN/DIN EN 60747-5-5: 1414 Vpeak working
insulation voltage
UL 1577: 5000 Vrms/1min double protection rating
CSA: Component Acceptance Notice #5
Applications
• Motor phase and rail current sensing
• Power inverter current and voltage sensing
• Industrial process control
• Data acquisition systems
• General purpose current and voltage sensing
• Traditional current transducer replacement
Functional Block Diagram
Figure 1.
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
VIN
+
SHIELD
VIN
–
VREF
LED
DRIVER
CLOCK
DETECTOR
DECODER
LED
DRIVER
MCLKIN+
MDAT-
VDD2
GND2
GND1
VDD1
ACPL-798J
BUF
SHIELD
MCLKIN-
MDAT+
Σ−∆
MODULATOR/
ENCODER
2
Pin Conguration and Descriptions
Figure 2. Pin conguration.
Table 2. Ordering Information
Part number
Option
(RoHS Compliant) Package Tape & Reel
IEC/EN/DIN
EN 60747-5-5 Quantity
ACPL-798J -000E SO-16 X 45 per tube
-500E X X 850 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example:
ACPL-798J-500E to order product in Tape and Reel packaging.
Contact your Avago sales representative or authorized distributor for information.
Table 1. Pin descriptions.
Pin No. Symbol Description
1,7 VDD1 Supply voltage for input side relative to GND1.
2 VIN+ Positive analog input, recommended input range ±200 mV.
3 VIN– Negative analog input, recommended input range ±200 mV (normally connected to GND1).
4,8 GND1 Supply ground for signal input side.
5,6,15 NC No connection. Leave oating.
9, 16 GND2 Supply ground for data output side (digital side).
11 MDAT+ Positive LVDS modulator data output.
10 MDAT- Negative LVDS modulator data output.
13 MCLKIN+ Positive LVDS modulator clock input
12 MCLKIN- Negative LVDS modulator clock input
8 VDD2 Supply voltage for output side, referenced to GND2.
VDD1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VIN+
VIN−
GND1
NC
NC
VDD1
GND1
GND2
NC
VDD2
MCLKIN+
MCLKIN−
MDAT+
MDAT −
GND2
ACPL-798J
3
Package Outline Drawings
16-Lead Surface Mount (SO-16)
Dimensions in millimeters and (inches).
Note: Floating lead protrusion is 0.15 mm (6 mils) max.
Note: Initial and continued variation in color of the white mold compound
is normal and does not aect performance or reliability of the device.
Figure 3. 16-Lead Surface Mount.
Recommended Pb-Free IR Prole
Recommended reow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
Regulatory Information
The ACPL-798J is pending for approvals by the following organizations:
IEC/EN/DIN EN 60747-5-5 Approved with Maximum Working Insulation Voltage VIORM = 1414 Vpeak.
UL Approval under UL 1577, component recognition program up to VISO = 5000 Vrms/1min. File E55361.
CSA Approval under CSA Component Acceptance Notice #5, File CA 88324.
9
7.493 ± 0.254
(0.295 ± 0.010)
10111213141516
87654321
0.457
(0.018)
3.505 ± 0.127
(0.138 ± 0.005)
9°
10.312 ± 0.254
(0.406 ± 0.10)
10.160 ± 0.254
(0.408 ± 0.010)
0.025 MIN.
0.203 ± 0.076
(0.008 ± 0.003)
STANDOFF
8.986 ± 0.254
(0.345 ± 0.010)
0-8°
0.457
(0.018) 1.270
(0.050)
ALL LEADS
TO BE
COPLANAR
± 0.002
11.63 (0.458)
2.16 (0.085)
0.64 (0.025)
LAND PATTERN RECOMMENDATION
A 798J
YYWW
EEE
TYPE NUMBER
DATE CODE
LOT ID
AVAGO
LEAD-FREE
4
Table 3. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics[1]
Description Symbol Value Units
Installation classication per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 450 V rms
for rated mains voltage ≤ 600 Vrms
for rated mains voltage ≤ 1000 Vrms
I-IV
I-IV
I-IV
I-IV
I-III
Climatic Classication 55/105/21
Pollution Degree (DIN VDE 0110/1.89) 2
Maximum Working Insulation Voltage VIORM 1414 Vpeak
Input to Output Test Voltage, Method b
VIORM × 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial Discharge < 5 pC
VPR 2652 Vpeak
Input to Output Test Voltage, Method a
VIORM × 1.6 = VPR, Type and Sample Test, tm = 10 sec,
Partial Discharge < 5 pC
VPR 2262 Vpeak
Highest Allowable Overvoltage (Transient Overvoltage, tini = 60 sec) VIOTM 8000 Vpeak
Safety-limiting values (Maximum values allowed in the event of a failure)
Case Temperature
Input Current[2]
Output Power[2]
TS
IS,INPUT
PS,OUTPUT
175
400
600
°C
mA
mW
Insulation Resistance at TS, VIO = 500 V RS≥ 109Ω
OUTPUT POWER - PS, INPUT CURRENT - IS
0
0
T
S
- CASE TEMPERATURE - oC
20050
400
12525 75 100 150
600
800
200
100
300
500
700
175
PS (mW)
IS (mA)
Figure 4. Case Temperature chart
Notes:
1. Insulation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits within the
application.
2. Safety-limiting parameters are dependent on ambient temperature. Refer to the following gure for dependence of PS and IS on ambient
temperature.
5
Table 4. Insulation and Safety Related Specications
Parameter Symbol Value Units Conditions
Minimum External Air Gap
(External Clearance)
L(101) 8.3 mm Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking
(External Creepage)
L(102) 8.3 mm Measured from input terminals to output terminals,
shortest distance path along body
Minimum Internal Plastic Gap
(Internal Clearance)
0.5 mm Through insulation distance, conductor to conductor,
usually the direct distance between the photoemitter
and photodetector inside the optocoupler cavity
Tracking Resistance
(Comparative Tracking Index)
CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
Table 5. Absolute Maximum Ratings
Parameter Symbol Min. Max. Units
Storage Temperature TS–55 +125 °C
Ambient Operating Temperature TA–40 +105 °C
Supply voltage VDD1, VDD2 –0.5 6.0 V
Steady-State Input Voltage[1,3] VIN+, VIN– –2 VDD1 + 0.5 V
Two-Second Transient Input Voltage[2] VIN+, VIN– –6 VDD1 + 0.5 V
Digital Input/Output Voltages MCLKIN, MDAT –0.5 VDD2 + 0.5 V
Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane
Notes:
1. DC voltage of up to –2 V on the inputs does not cause latch-up or damage to the device; tested at typical operating conditions.
2. Transient voltage of 2 seconds up to –6 V on the inputs does not cause latch-up or damage to the device; tested at typical operating conditions.
3. Absolute maximum DC current on the inputs = 100 mA, no latch-up or device damage occurs.
Table 6. Recommended Operating Conditions
Parameter Symbol Min. Max. Units
Ambient Operating Temperature TA–40 +105 °C
VDD1 Supply Voltage VDD1 4.5 5.5 V
VDD2 Supply Voltage VDD2 3.3 5.5 V
Analog Input Voltage[1] VIN+, VIN– –200 +200 mV
Notes:
1. Full scale signal input range ±320 mV.
6
Table 7. Electrical Specications
Unless otherwise noted, TA = –40°C to +105°C, VDD1 = 4.5 V to 5.5 V, VDD2 = 3.3 V to 5.5 V, VIN+ = –200 mV to +200 mV, and
VIN– = 0 V (single-ended connection); tested with Sinc3 lter, 256 decimation ratio, fMCLKIN = 20 MHz.
Parameter Symbol Min. Typ.[1] Max. Units Test Conditions/Notes Fig.
STATIC CHARACTERISTICS
Resolution 16 Bits Decimation lter output set to 16bits
Integral Nonlinearity INL -15 3 15 LSB TA = –40°C to +85°C; see denitions section.
-25 3 25 LSB TA = 85°C to +105°C
Dierential Nonlinearity DNL -0.9 0.9 LSB No missing codes, guaranteed by design;
see Denitions section
Input Oset Voltage VOS -1.5 0.6 2.5 mV TA = –40°C to +105°C 9, 10
Input Oset Voltage vs.
Temperature
TCVOS 1 3.5 mV/°C TA = –40°C to +105°C
**note: Direct short across inputs.
9
Input Oset Drift vs VDD1 110 mV/V
Gain Error GE-2 2 % TA = –40°C to +105°C, VIN+ = –200 to +200 mV;
see Denitions section
11
-1 1 % TA = 25°C, VIN+ = –200 to +200mV 11
Gain Error Drift vs.
Temperature
TCGE 60 ppm/°C TA = –40°C to +105°C; 11
Gain Drift vs. VDD1 0.15% %/V TA = –40°C to +105°C; 12
ANALOG INPUTS
Full-Scale Dierential
Voltage Input Range
FSR ±320 mV Referenced to GND1
Linear Input Range VIN+,
VIN-
±200 mV Referenced to GND1
Average Input Bias Current IINA -0.5 mAVDD1 = 5V, VDD2 = 5V, VIN+ = 0 V; Note 3
Average Input Resistance RIN 12.5 kΩAcross VIN+ or VIN– to GND1; Note 3; FCLKIN=20MHz.
Input Capacitance CINA 16 pF Across VIN+ or VIN– to GND1
AC CHARACTERISTICS
Signal-to-Noise Ratio SNR 68 82 dB TA = –40°C to +105°C; see Denitions section. Note 4.
Signal-to- (Noise +
Distortion) Ratio
SNDR 65 75 dB TA = –40°C to +105°C; see Denitions section. Note 4. 13,14,15
Eective Number of Bits ENOB 12 Bits See denitions section
Isolation Transient
Immunity
CMR
(CMTI)
25 kV/msVCM = 1 kV, TA = 25°C
DIGITAL INPUTS AND OUTPUTS
Output dierential Voltage
(Mdat+, Mdat-)
Vod 350 mV Rload = 100ohm; Mdat+ - Mdat-, VDD1, VDD2 =5V.
Note 5.
Output Common Mode
Voltage
Vocm 1 1.25 1.5 V Vdd1, Vdd2 = 5V.
Output Short Circuit
Current (Mdat+, Mdat-)
IOSD 3.5 mA Output shorted to gnd.
Input Threshold high
(MCLKin+, MCLKin-)
VthH 100 mV Referenced to Vocm.
Input Threshold Low
(MCLKin+, MCLKin-)
VthL -100 mV Referenced to Vocm.
POWER SUPPLY
Input Side Supply Current IDD1 15.5 20 mA VDD1 = 5.5 V 16, 17,18
IDD2 14.5 18 mA VDD2 = 3.3 V
17 20 mA VDD2 = 5 V 19, 20, 21
Notes:
1. All Typical values are under Typical Operating Conditions at TA = 25°C, VDD1 = 5 V, VDD2 = 5 V.
2. Beyond the full-scale input range the data output is either all zeroes or all ones.
3. Because of the switched-capacitor nature of the isolated modulator, time averaged values are shown.
4. Input signal frequency = 1Khz.
5. Output dierential voltage Vod = Mdat+ - Mdat-.
7
Table 8. Timing Specications
Unless otherwise noted, TA = –40°C to +105°C, VDD1 = 4.5 V to 5.5 V, VDD2 = 3.3 V to 5.5 V.
Parameter Symbol Min. Typ. Max. Units Test Conditions/Notes Fig.
Modulator Clock Input Frequency fMCLKIN 5 20 25 MHz Clock Duty Cycle 40% to 60%.
Note 1.
Data Delay upon MCLKIN Input
Startup
TCS 150 uS VIN = 0V, VDD1 and VDD2 = 5V,
TA = 25°C.
Refer to
gure 5.
Data Propagation Delay after
MCLKIN edge [1]
TD15 nS VIN = 0V, VDD1 and VDD2 = 5V. Refer to
gure 6.
Data Delay Upon VDD1 power up TPS1 250 uS VIN = 0V, VDD1 > 3.8V VDD2
supplied, MCLKIN active,
TA = 25°C, Note 2.
Refer to
gure 7.
Data Delay Upon VDD2 power up TPS2 165 uS VIN = 0V, VDD1 supplied,
TA = 25°C , MCLKIN active
Refer to
gure 8.
Notes:
1. The ACPL-798J has an in-built clock conditioning scheme that makes it tolerant to variations on the input clock duty cycle.
2. When VDD1 is not supplied, MDAT+ is high and MDAT- is low ie modulator output level is “1”.
Table 9. Package Characteristics
Parameter Symbol Min. Typ. Max. Units Test Conditions Note
Input-Output Momentary
Withstand Voltage
VISO 5000 Vrms RH ≤ 50%, t = 1 min;
TA = 25°C
1, 2
Input-Output Resistance RI-O 1012 1013 ΩVI-O = 500 Vdc 2
1011 ΩTA = 100°C 2
Input-Output Capacitance CI-O 1.4 pF f = 1 MHz 2
Input IC Junction-to-Ambient
Thermal Resistance
θJAI 83 °C/W 1 oz. trace, 2-layer PCB,
still air, TA = 25°C
3
Output IC Junction-to- Ambient
Thermal Resistance
θJAO 85 °C/W 1 oz. trace, 2-layer PCB,
still air, TA = 25°C
3
Notes:
1. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 Vrms for 1 second. This test is performed
before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-5 Insulation Characteristic Table.
2. This is a two-terminal measurement: pins 1-8 are shorted together and pins 9-16 are shorted together.
3. Maximum power dissipation in analog side and digital side IC’s needs to be limited to ensure that their respective junction temperature is less than
125°C. The maximum permissible power dissipation is dependent on the thermal impedance and the ambient temperature.
Figure 5. Data delay upon clock input startup Figure 6. Data propagation delay
Figure 7. Data delay upon VDD1 startup Figure 8. Data delay upon VDD2 startup
TCS
MCLKIN+
MCLKIN-
MDAT+
MDAT-
TD
MDAT+
MDAT-
MCLKIN-
MCLKIN+
TPS1
MDAT+
MDAT-
VDD1
TPS2
MDAT+
MDAT-
VDD2
8
Typical Performance Plots
Unless otherwise noted, TA = 25°C, VDD1 = 5 V, VDD2 = 5 V, VIN+ = –200 mV to +200 mV, and VIN– = 0 V, fMCLKIN = 20 MHz,
with Sinc3 lter, 256 decimation ratio.
50
55
60
65
70
75
80
-40 -20 0 20 40 60 80 100 120
SNDR (dB)
Temperature (˚C)
Vdd1 = 4.5V
Vdd1 = 5.0V
Vdd1 = 5.5V
50
55
60
65
70
75
80
85
10 15 20 25
SNDR (dB)
Frequency (Mhz)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
-40 -20 0 20 40 60 80 100 120
Oset (mV)
Temperature (˚C)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
10 15 20 25
Oset (mV)
Frequency (Mhz)
- 0.20%
- 0.15%
- 0.10%
- 0.05%
0.00%
0.05%
0.10%
0.15%
0.20%
4.5 5 5.5
Gain Err (%)
Vdd1 (V)
-1.00%
-0.50%
0.00%
0.50%
1.00%
-40 -20 0 20 40 60 80 100 120
Gain Err (%)
Temperature (˚C)
Vdd1 =5.0
Vdd1 =5.5
Vdd1 =4.5
Figure 9. Oset vs. Temperature Figure 10. Oset vs. MCLKIN Clock
Figure 11. Gain vs. Temperature Figure 12. Gain vs. VDD1
Figure 13. SNDR vs. Temperature Figure 14. SNDR vs. MCLKIN Frequency
9
50
55
60
65
70
75
80
100 200 300 400 500
SNDR (dB)
Vin (Vpp)
7
8
9
10
11
12
13
14
15
16
-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4
Idd1 (mA)
Vin (V)
0
2
4
6
8
10
12
14
16
18
10.00 15.00 20.00 25.00
Idd1 (mA)
Frequency (Mhz)
Vin+ = 400mV
Vin+ = -400mV
7
9
11
13
15
17
19
10 15 20 25
Idd2 (mA)
Frequency (Mhz)
Vdd2 = 5.5V
Vdd2 = 3.3V
0
2
4
6
8
10
12
14
16
18
20
-40 -20 0 20 40 60 80 100 120
Idd2 (mA)
Temperature (˚C)
Vdd2 = 3.3V
Vdd2 = 5.5V
12
13
14
15
16
17
18
-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4
Idd2 (mA)
Vin+ (V); Vin-= GND
Vdd2 = 3.3
Vdd2 = 5.5
10
11
12
13
14
15
16
17
18
-40 -20 0 20 40 60 80 100 120
Idd1 (mA)
Temperature (˚C)
Vdd1 = 4.5V
Vdd1 = 5.0V
Vdd1 = 5.5V
Figure 15. SNDR vs. Input Voltage VIN
Figure 17. IDD1 vs. Input Voltage VIN
Figure 19. IDD2 vs. MCLKIN Frequency
Figure 21. IDD2 vs. Temperature
Figure 16. IDD1 vs. MCLKIN Frequency
Figure 18. IDD1 vs. Temperature
Figure 20. IDD2 vs Input Voltage VIN
10
Denitions
Signal-to-Noise Ratio (SNR)
The SNR is the measured ratio of AC signal power to noise
power below half of the sampling frequency. The noise
power excludes harmonic signals and DC.
Signal-to-(Noise + Distortion) Ratio (SNDR)
The SNDR is the measured ratio of AC signal power to
noise plus distortion power at the output of the ADC. The
signal power is the rms amplitude of the fundamental
input signal. Noise plus distortion power is the rms sum
of all non-fundamental signals up to half the sampling
frequency (excluding DC).
Eective Number of Bits (ENOB)
The ENOB determines the eective resolution of an ADC,
expressed in bits, dened by ENOB = (SNDR − 1.76)/6.02
Isolation Transient Immunity (CMR)
The isolation transient immunity (also known as Common-
Mode Rejection or CMR) species the minimum rate-of-
rise/fall of a common-mode signal applied across the
isolation boundary beyond which the modulator clock or
data is corrupted.
Integral Nonlinearity (INL)
INL is the maximum deviation of a transfer curve from a
straight line passing through the endpoints of the ADC
transfer function, with oset and gain errors adjusted out.
Dierential Nonlinearity (DNL)
DNL is the deviation of an actual code width from the
ideal value of 1 LSB between any two adjacent codes in
the ADC transfer curve. DNL is a critical specication in
closed-loop applications. A DNL error of less than ±1 LSB
guarantees no missing codes and a monotonic transfer
function.
Oset Error
Oset error is the deviation of the actual input voltage
corresponding to the mid-scale code (32,768 for a 16-bit
system with an unsigned decimation lter) from 0 V. Oset
error can be corrected by software or hardware.
Gain Error
Gain error is the the dierence between the ideal gain
slope and the actual gain slope, with oset error adjusted
out. Gain error includes reference error. Gain error can be
corrected by software or hardware.
11
Product Overview
Figure 22. Analog input equivalent circuit.
Figure 23. Simplied dierential input connection diagram.
200Ω (TYP)
3 pF (TYP)
3 pF (TYP)
fSWITCH
= MCLKIN
VIN+
VIN–
200
Ω
(TYP)
1.5 pF
1.5 pF
COMMON MODE
VOLTAGE
fSWITCH
= MCLKIN
ANALOG
GROUND
VIN+
VIN–
ACPL-798J
VDD1
GND1
5 V
+Analog Input
–
Ra
Rb C
–Analog Input
In the typical application circuit (Figure 25.), the ACPL-798J
is connected in a single-ended input mode. Given the
fully dierential input structure, a dierential input con-
nection method (balanced input mode as shown in Figure
23) is recommended to achieve better performance. The
input currents created by the switching actions on both of
the pins are balanced on the lter resistors and cancelled
out each other. Any noise induced on one pin will be
coupled to the other pin by the capacitor C and creates
only common mode noise which is rejected by the device.
The resistors and the capacitor also forms an anti-aliasing
lter for the sigma-delta modulator. Typical value for RA
and RB is 22 W and 10 nF for C.
Description
The ACPL-798J isolated sigma-delta (∑-∆) modulator
converts an analog input signal into a high-speed (up
to 25MHz) single-bit data stream by means of a sigma-
delta over-sampling modulator. The time average of the
modulator data is directly proportional to the input signal
voltage. The modulator uses external clock ranges from 5
MHz to 25 MHz that is coupled across the isolation barrier.
This arrangement allows synchronous operation of data
acquisition to any digital controller, and adjustable clock
for speed requirements of the application. The modulator
data are encoded and transmitted across the isolation
boundary where they are recovered and decoded into
high-speed data stream of digital ones and zeros. The
original signal information is represented by the density
of ones in the data output.
The other main function of the modulator (optocoupler)
is to provide galvanic isolation between the analog signal
input and the digital data output. It provides high noise
margins and excellent immunity against isolation-mode
transients that allows direct measurement of low-level
signals in highly noisy environments, for example mea-
surement of motor phase currents in power inverters.
With 0.5 mm minimum DTI, the ACPL-798J provides
reliable double protection and high working insulation
voltage, which is suitable for fail-safe designs. This out-
standing isolation performance is superior to alterna-
tives including devices based on capacitive- or magnet-
ic-coupling with DTI in micro-meter range. Oered in an
SO-16 package, the isolated ADC delivers the reliability,
compact size, superior isolation and over-temperature
performance motor drive designers need to accurately
measure current at much lower price compared to tradi-
tional current transducers.
Analog Input
The dierential analog inputs of the ACPL-798J are im-
plemented with a fully-dierential, switched-capacitor
circuit. The ACPL-798J accepts signal of ±200 mV (full scale
±320 mV), which is ideal for direct connection to shunt
based current sensing or other low-level signal sources
applications such as motor phase current measurement.
An internal voltage reference determines the full-scale
analog input range of the modulator (±320 mV); an input
range of ±200 mV is recommended to achieve optimal
performance. Users are able to use higher input range,
for example ±250 mV, as long as within full-scale range,
for purpose of over-current or overload detection. Figure
22 shows the simplied equivalent circuit of the analog
input.
Latch-up Consideration
Latch-up risk of CMOS devices needs careful consider-
ation, especially in applications with direct connection to
signal source that is subject to frequent transient noise.
The well designed analog input structure of the ACPL-798J
is resilient to transients, which are often encountered
in highly noisy application environments such as motor
drive and other power inverter systems. Other situations
could cause transient voltages to the inputs include short
circuit and overload conditions. The ACPL-798J is tested to
be able to reject DC voltage of –2 V and 2-second transient
voltage of –6 V presented to the analog inputs without
any latch-up or damage to the device.
12
Modulator Data Output
Input signal information is contained in the modulator
output data stream, represented by the density of ones
and zeros. The density of ones is proportional to the input
signal voltage, as shown in Figure 24. A dierential input
signal of 0 V ideally produces a data stream of ones 50%
of the time and zeros 50% of the time. A dierential input
of –200 mV corresponds to 18.75% density of ones, and
a dierential input of +200 mV is represented by 81.25%
density of ones in the data stream. A dierential input of
+320 mV or higher results in ideally all ones in the data
stream, while input of –320 mV or lower will result in all
zeros ideally. Table 10 shows this relationship.
Figure 24. Moudlator output vs. analog input.
–FS (ANALOG INPUT)
+FS (ANALOG INPUT)
0 V (ANALOG INPUT)
TIME
MODULATOR OUTPUT
ANALOG INPUT
Table 10. Input voltage with ideal corresponding density of 1s at modulator data output, and ADC code.
Analog Input Voltage Input Density of 1s ADC Code (16-bit unsigned decimation)
Full-Scale Range 640 mV
+Full-Scale +320 mV 100% 65,535
+Recommended Input Range +200 mV 81.25% 53,248
Zero 0 mV 50% 32,768
–Recommended Input Range –200 mV 18.75% 12,288
–Full-Scale –320 mV 0% 0
Notes:
1. With bipolar oset binary coding scheme, the digital code begins with digital 0 at –FS input and increases proportionally to the analog input until
the full-scale code is reached at the +FS input. The zero crossing occurs at the mid-scale input.
2. Ideal density of 1s at modulator data output can be calculated with VIN/640 mV + 50%; similarly, the ADC code can be calculated with (VIN/640 mV)
× 65,536 + 32,768, assuming a 16-bit unsigned decimation lter.
Digital Filter
The original analog signal that is converted to a digital bit
stream by the over-sampling sigma-delta modulator, can
be recovered by means of ltering in the digital domain.
A common and simple way is through implementation of
a cascaded integrated comb (CIC) lter or Sinc3 lter. The
digital lter averages or decimates the over-sampled bit
stream and eectively converts it into a multi-bit digital
equivalent code of the original analog input signal. With
a 20MHz external clock frequency, 256 decimation ratio
and 16-bit word settings, the output data rate is 58 kHz (=
20MHz/256). This lter can be implemented in an ASIC, an
FPGA or a DSP. Some of the equivalent digital codes with
corresponding input voltages are shown in Table 10.
13
Note: In applications, a 0.1 mF bypass capacitor must be connected between pins VDD1 and GND1, and between pins VDD2 and GND2 of the ACPL-798J.
Figure 25. Typical application circuit with a Sinc3 lter.
Application Information
Figure 26. Typical application circuit for motor phase current sensing.
ACPL-798J
INPUT
CURRENT
RSHUNT
VIN +
VIN –
VDD1
GND1
5 V
MCLKIN+
MCLKIN-
MDAT+
MDAT-
VDD2
GND2
Non-Isolated
5 V/3.3 V
CLOCK+
CLOCK-
DATA+
DATA-
ISOLATION
BARRIER
MCU/FPGA
CIC/SINC 3Filter
Decimation ratio = M
Fs Fs/M
100 Ω
100 Ω
Power Supplies and Bypassing
As shown in Figure 26, a oating power supply (which in
many applications could be the same supply that is used
to drive the high-side power transistor) is regulated to 5 V
using a low cost and common regulator like the LM78L05.
Digital Current Sensing Circuit
Figure 26 shows a typical application circuit for motor
control phase current sensing. By choosing the appro-
priate shunt resistance, any range of current can be
monitored, from less than 1 A to more than 100 A.
HV -
V
DD1
HV+
Gate Drive
Circuit
78L05
Cin
10nF
C1
GND1
VIN+
R2a 22Ω
IN OUT
Floating Positive
Supply
MCLKIN+
MCLKIN+
VDD2
GND2
5V/3.3V
VIN−
R2b 22Ω
RSENSE
+-
MOTOR
MDAT+
MDAT−
C5
0.1µF
VDD1
ACPL-798J
R3a 100Ω
R3b 100Ω
C2
C4
C3
10µF
FPGA
/MCU/
DSP
0.1µF
0.1µF
10µF0.1µF
10µF
14
Alternatively a simple zener diode could also be used to
in place of the regulator to provide the required power
supply. The voltage from the current sensing resistor or
shunt (RSENSE) is applied to the input of the ACPL- 798J
through an RC anti-aliasing lter (R2 and Cin). Although
the application circuit is relatively simple, a few recom-
mendations should be followed to ensure optimal per-
formance. The power supply for the isolated modulator is
most often obtained from the same supply used to power
the power transistor gate drive circuit. If a dedicated
supply is required, in many cases it is possible to add an
additional winding on an existing transformer. Otherwise,
some sort of simple isolated supply can be used, such as
a line powered transformer or a high-frequency DC-DC
converter. To help attenuate high-frequency power
supply noise or ripple, a resistor or inductor can be used
in series with the input of the regulator to form a low-pass
lter with the regulator’s input bypass capacitor. A ferrite
bead is also recommended to be placed close to Vdd1 pin
to lter out any high-frequency noise in the supply. As
shown in Figure 26, bypass capacitors (C2 to C5) should
be located as close as possible to the input and output
power-supply pins of the isolated modulator (U2). The
bypass capacitors are required because of the high-speed
digital nature of the signals inside the isolated modulator.
Tantalum capacitors are also recommended over electro-
lytic capacitors due to their lower ESR which translates to
faster response to support the switching currents required
by the isolated modulator. A 10nF bypass capacitor (Cin)
is also recommended at the input due to the switched-
capacitor nature of the input circuit. The input bypass
capacitor together with the resistors R2a and R2b also
forms part of the anti-aliasing lter, which is recommend-
ed to prevent high frequency noise from aliasing down to
lower frequencies and interfering with the input signal.
LVDS Interface
One of the features on the ACPL-798J is that it uses a Low
Voltage Dierential Signalling (LVDS) interface on both
the clock input and the modulator output. In a typical
motor drive application where the ACPL-798J is used,
the surrounding environment is usually noisy. Very often,
the current sensor or modulator can be partitioned on
another separate board and interfaced through connect-
ers or cables to the controller board. The benets of using
LVDS in this case helps to make the interface between
the modulator and the controller more robust and less
susceptible to electromagnetic interference from the sur-
roundings. LVDS also helps to reduce the EMI emissions
associated with high speed digital signaling. Being high
speed in general, LVDS signals are treated as transmis-
sion lines and must be resistively terminated properly
(as shown in gure 26) to reduce or eliminate transmis-
sion line reection. The same resistors (R3a and R3b) also
perform the function of terminating the LVDS lines which
are current mode outputs, and should be place as close
as possible to the end receiver. The value of the dieren-
tial terminating resistor is typically 100Ω which should
match the dierential impedence of the transmission line.
The LVDS interface is in accordance to the TIA/EIA-644-A
standard.
PC Board Layout
The design of the printed circuit board (PCB) should follow
good layout practices, such as keeping bypass capacitors
close to the supply pins, keeping output signals away from
input signals, the use of ground and power planes, etc.
The input anti-aliasing lter network should be placed as
close as possible to the input pin to minimize any stray in-
ductance. The termination resistor for the LVDS interfaces
should be placed as close as possible at the receiver pins,
and the dierential traces should be of the same length
and be running along side each other. In addition, the
layout of the PCB can also aect the isolation transient
immunity (CMR) of the isolated modulator, due primarily
to stray capacitive coupling between the input and the
output circuits. To obtain optimal CMR performance, the
layout of the PC board should minimize any stray coupling
by maintaining the maximum possible distance between
the input and output sides of the circuit and ensuring that
any ground or power plane on the PC board does not pass
directly below or extend much wider than the body of the
isolated modulator.
Shunt Resistors
The current-sensing shunt resistor should have low re-
sistance (to minimize power dissipation), low inductance
(to minimize di/dt induced voltage spikes which could
adversely aect operation), and reasonable tolerance (to
maintain overall circuit accuracy). Choosing a particu-
lar value for the shunt is usually a compromise between
minimizing power dissipation and maximizing accuracy.
Smaller shunt resistances decrease power dissipa-
tion, while larger shunt resistances can improve circuit
accuracy by utilizing the full input range of the isolated
modulator. The rst step in selecting a shunt is deter-
mining how much current the shunt will be sensing. The
graph in Figure 27 shows the RMS current in each phase
of a three-phase induction motor as a function of average
Figure 27. Motor Output Horsepower vs. Motor Phase Current and Supply.
15
5
40
15 20 25 30
25
MOTOR PHASE CURRENT - A (rms)
10
30
MOTOR OUTPUT POWER - HORSEPOWER
5 350
0
440
380
220
120
10
20
35
15
motor output power (in horsepower, hp) and motor drive
supply voltage. The maximum value of the shunt is deter-
mined by the current being measured and the maximum
recommended input voltage of the isolated modulator.
The maximum shunt resistance can be calculated by
taking the maximum recommended input voltage and
dividing by the peak current that the shunt should see
during normal operation. For example, if a motor will
have a maximum RMS current of 10 A and can experi-
ence up to 50% overloads during normal operation, then
the peak current is 21.1 A (=10x1.414x1.5). Assuming a
maximum input voltage of 200 mV, the maximum value
of shunt resistance in this case would be about 10 mW.
The maximum average power dissipation in the shunt
can also be easily calculated by multiplying the shunt re-
sistance times the square of the maximum RMS current,
which is about 1 W in the previous example. If the power
dissipation in the shunt is too high, the resistance of the
shunt can be decreased below the maximum value to
decrease power dissipation. The minimum value of the
shunt is limited by precision and accuracy requirements
of the design. As the shunt value is reduced, the output
voltage across the shunt is also reduced, which means
that the oset and noise, which are xed, become a larger
percentage of the signal amplitude. The selected value of
the shunt will fall somewhere between the minimum and
maximum values, depending on the particular require-
ments of a specic design. When sensing currents large
enough to cause signicant heating of the shunt, the tem-
perature coecient (tempco) of the shunt can introduce
nonlinearity due to the signal dependent temperature
rise of the shunt. The eect increases as the shunt-to-
ambient thermal resistance increases. This eect can
be minimized either by reducing the thermal resistance
of the shunt or by using a shunt with a lower tempco.
Lowering the thermal resistance can be accomplished by
repositioning the shunt on the PC board, by using larger
PC board traces to carry away more heat, or by using a
heat sink. For a two-terminal shunt, as the value of shunt
resistance decreases, the resistance of the leads becomes
a signicant percentage of the total shunt resistance.
This has two primary eects on shunt accuracy. First, the
eective resistance of the shunt can become dependent
on factors such as how long the leads are, how they are
bent, how far they are inserted into the board, and how
far solder wicks up the lead during assembly (these issues
will be discussed in more detail shortly). Second, the leads
are typically made from a material such as copper, which
has a much higher tempco than the material from which
the resistive element itself is made, resulting in a higher
tempco for the shunt overall. Both of these eects are
eliminated when a four-terminal shunt is used. A four-
terminal shunt has two additional terminals that are
Kelvin-connected directly across the resistive element
itself; these two terminals are used to monitor the voltage
across the resistive element while the other two terminals
are used to carry the load current. Because of the Kelvin
connection, any voltage drops across the leads carrying
the load current should have no impact on the measured
voltage. Several four-terminal shunts from Isotek (Isabel-
lenhütte) suitable for sensing currents in motor drives up
to 71 Arms (71 hp or 53 kW) are shown in Table 11; the
maximum current and motor power range for each of the
PBVseries shunts are indicated. For shunt resistances from
50mΩ down to 10mm, the maximum current is limited
by the input voltage range of the isolated modulator. For
the 5 mΩ and 2 mΩ shunts, a heat sink may be required
due to the increased power dissipation at higher currents.
When laying out a PC board for the shunts, a couple of
points should be kept in mind. The Kelvin connections to
the shunt should be brought together under the body
of the shunt and then run very close to each other to the
input of the isolated modulator; this minimizes the loop
area of the connection and reduces the possibility of stray
magnetic elds from interfering with the measured signal.
If the shunt is not located on the same PC board as the
isolated modulator circuit, a tightly twisted pair of wires
can accomplish the same thing. Also, multiple layers of
the PC board can be used to increase current carrying
capacity. Numerous plated-through vias should surround
each non-Kelvin terminal of the shunt to help distribute
the current between the layers of the PC board. The PC
board should use 2 or 4 oz. copper for the layers, resulting
in a current carrying capacity in excess of 20 A. Making
the current carrying traces on the PC board fairly large
can also improve the shunt’s power dissipation capabil-
ity by acting as a heat sink. Liberal use of vias where the
load current enters and exits the PC board is also recom-
mended.
Shunt Connections
The recommended method for connecting the isolated
modulator to the shunt resistor is shown in Figure 26.
VIN+ is connected to the positive terminal of the shunt
resistor, while VIN– is shorted to GND1, with the power-
supply return path functioning as the sense line to the
negative terminal of the current shunt. This allows a single
pair of wires or PC board traces to connect the isolated
modulator circuit to the shunt resistor. By referencing the
input circuit to the negative side of the sense resistor, any
load current induced noise transients on the shunt are
seen as a common-mode signal and will not interfere with
the current-sense signal. This is important because the
large load currents owing through the motor drive, along
with the parasitic inductances inherent in the wiring of
the circuit, can generate both noise spikes and osets that
are relatively large compared to the small voltages that
are being measured across the current shunt. If the same
power supply is used both for the gate drive circuit and
for the current sensing circuit, it is very important that the
connection from GND1 of the isolated modulator to the
sense resistor be the only return path for supply current
16
Figure 28. Schematic for three conductor shunt connection.
to the gate drive power supply in order to eliminate
potential ground loop problems. The only direct connec-
tion between the isolated modulator circuit and the gate
drive circuit should be the positive power supply line.
In some applications, however, supply currents owing
through the power-supply return path may cause oset
or noise problems. In this case, better performance may
be obtained by connecting VIN+ and VIN– directly across
the shunt resistor with two conductors, and connecting
GND1 to the shunt resistor with a third conductor for the
power-supply return path, as shown in Figure 27. When
connected this way, both input pins should be bypassed.
To minimize electromagnetic interference of the sense
signal, all of the conductors (whether two or three are
Table 11. Four-terminal shunts
Shunt Resistor
Part Number
Shunt
Resistance Tol.
Maximum
RMS Current
Motor Power Range
120 VAC - 440 VAC
mΩ% A hp kW
PBV-R050-0.5 50 0.5 3 0.8 - 3 0.6 - 2
PBV-R020-0.5 20 0.5 7 2 - 7 0.6 - 2
PBV-R010-0.5 10 0.5 14 4 - 14 3 - 10
PBV-R005-0.5 5 0.5 25 [28] 7 - 25 [8 - 28] 5 - 19 [6 - 21]
PBV-R002-0.5 2 0.5 39 [71] 11 - 39 [19 - 71] 8 - 29 [14 - 53]
Note: Values in brackets are with a heatsink for the shunt.
used) connecting the isolated modulator to the sense
resistor should be either twisted pair wire or closely
spaced traces on a PC board. The 22Ω resistor in series
with the input lead (R2) forms a lowpass anti-aliasing lter
with the 20nF input bypass capacitor (Cin) with a 723KHz
bandwidth. The resistor performs another important
function as well; it dampens any ringing which might
be present in the circuit formed by the shunt, the input
bypass capacitor, and the inductance of wires or traces
connecting the two. Undamped ringing of the input
circuit near the input sampling frequency can alias into
the baseband producing what might appear to be noise
at the output of the device.
HV -
V
DD1
HV+
Gate Drive
Circuit
78L05
Cin
20nF
C1
0.1µF
GND1
VIN +
R2a 22Ω
IN OUT
Floating Positive
Supply
MCLKIN+
MCLKIN−
VDD2
GND2
5V/3.3V
VIN -
R2b 22Ω
RSENSE
+-
MOTOR
MDAT+
MDAT−
C5
0.1µF
VDD1
ACPL-798J
R3a 100 Ω
R3b 100Ω
C2
10µFC4
0.1µF
C3
10µF
FPGA
/MCU/
DSP
Cin
20nF
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Data subject to change. Copyright © 2005-2014 Avago Technologies. All rights reserved.
AV02-4339EN - August 28, 2014
Voltage Sensing
The ACPL-798J can also be used to isolate signals with am-
plitudes larger than its recommended input range with
the use of a resistive voltage divider at its input. The only
restrictions are that the impedance of the divider be rela-
tively small (less than 1 kΩ) so that the input resistance
(12.8KΩ) and input bias current (0.5mA) do not aect the
accuracy of the measurement. An input bypass capacitor
is still required, although the 22Ω series damping resistor
is not (the resistance of the voltage divider provides the
same function). The low-pass lter formed by the divider
resistance and the input bypass capacitor may limit the
achievable bandwidth. To obtain higher bandwidth, the
input bypass capacitor (C2) can be reduced, but it should
not be reduced much below 1000 pF to maintain adequate
input bypassing of the isolated modulator.
Mouser Electronics
Authorized Distributor
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ACPL-798J-000E ACPL-798J-500E