NuMicroTM M058/M0516 Product Brief ARM CortexTM-M0 32-BIT MICROCONTROLLER NuMicro Family M058/M0516 Product Brief -1- Publication Release Date: May 30, 2011 Revision V2.00 NuMicroTM M058/M0516 Product Brief TABLE OF CONTENTS 1 GENERAL DESCRIPTION 5 2 FEATURES6 3 BLOCK DIAGRAM10 4 SELECTION TABLE 11 5 PIN CONFIGURATION 12 5.1 QFN 33 pin 12 5.2 LQFP 48 pin 13 5.3 Pin Description14 6 TYPICAL APPLICATION CIRCUIT17 7 ELECTRICAL CHARACTERISTICS18 7.1 Absolute Maximum Ratings 18 7.2 DC Electrical Characteristics 19 7.3 AC Electrical Characteristics 22 7.3.1 External 4~24 MHz High Speed Crystal 22 7.3.2 External 4~24 MHz High Speed Oscillator22 7.3.3 Typical Crystal Application Circuits 23 7.3.4 Internal 22.1184 MHz High Speed Oscillator24 7.3.5 Internal 10 kHz Low Speed Oscillator24 7.4 Analog Characteristics25 7.4.1 Specification of 600 kHz sps 12-bit SARADC25 7.4.2 Specification of LDO and Power management26 7.4.3 Specification of Low Voltage Reset27 7.4.4 Specification of Brownout Detector 27 7.4.5 Specification of Power-On Reset (5V) 27 7.5 SPI Dynamic characteristics 28 8 PACKAGE DIMENSIONS30 8.1 LQFP-48 (7x7x1.4mm2 Footprint 2.0mm)30 8.2 QFN-33 (5X5 mm2, Thickness 0.8mm, Pitch 0.5 mm) 31 9 REVISION HISTORY32 -2- Publication Release Date: May 30, 2011 Revision V2.00 NuMicroTM M058/M0516 Product Brief LIST OF FIGURES Figure 3-1 NuMicroTM M051 Series Block Diagram ....................................................................... 10 Figure 4-1 NuMicro M051TM Naming Rule..................................................................................... 11 Figure 5-1 NuMicroTM M051 Series QFN33 Pin Diagram............................................................... 12 Figure 5-2 NuMicroTM M051 Series LQFP-48 Pin Diagram............................................................ 13 Figure 8-1 Typical Crystal Application Circuit ................................................................................ 23 Figure 8-2 SPI Master timing ......................................................................................................... 29 Figure 8-3 SPI Slave timing ........................................................................................................... 29 -3- Publication Release Date: May 30, 2011 Revision V2.00 NuMicroTM M058/M0516 Product Brief LIST OF TABLES Table 4-1 NuMicroTM M051 Series Product Selection Guide......................................................... 11 Table 5-1 NuMicroTM M051 Series Pin Description ........................................................................ 16 -4- Publication Release Date: May 30, 2011 Revision V2.00 NuMicroTM M058/M0516 Product Brief 1 GENERAL DESCRIPTION The NuMicro M051TM series is a 32-bit microcontroller with embedded ARM(R) CortexTM-M0 core for industrial control and applications which need rich communication interfaces. The CortexTM-M0 is the newest ARM embedded processor with 32-bit performance and at a cost equivalent to traditional 8-bit microcontroller. The NuMicro M051TM series includes M052, M054, M058 and M0516 families. The M058/M0516 can run up to 50 MHz. Thus it can afford to support a variety of industrial control and applications which need high CPU performance. The M058/M0516 has 32K/64K-byte embedded flash, 4K-byte data flash, 4K-byte flash for the ISP, and 4K-byte embedded SRAM. Many system level peripheral functions, such as I/O Port, EBI (External Bus Interface), Timer, UART, SPI, I2C, PWM, ADC, Watchdog Timer and Brownout Detector, have been incorporated into the M058/M0516 in order to reduce component count, board space and system cost. These useful functions make the M058/M0516 powerful for a wide range of applications. Additionally, the M058/M0516 is equipped with ISP (In-System Programming) and ICP (In-Circuit Programming) functions, which allow the user to update the program memory without removing the chip from the actual end product. -5- Publication Release Date: May 30, 2011 Revision V2.00 NuMicroTM M058/M0516 Product Brief 2 FEATURES z Core ARM(R) CortexTM-M0 core runs up to 50 MHz. One 24-bit system timer. Supports low power sleep mode. A single-cycle 32-bit hardware multiplier. NVIC for the 32 interrupt inputs, each with 4-levels of priority. Supports Serial Wire Debug (SWD) interface and 2 watchpoints/4 breakpoints. z Built-in LDO for Wide Operating Voltage Range: 2.5V to 5.5V z Memory z z 32KB/64KB Flash memory for program memory (APROM) 4KB Flash memory for data memory (DataFlash) 4KB Flash memory for loader (LDROM) 4KB SRAM for internal scratch-pad RAM (SRAM) Clock Control Programmable system clock source External 4~24 MHz high speed crystal input Internal 22.1184 MHz high speed oscillator (trimmed to 1% accuracy) Internal 10 kHz low speed oscillator for Watchdog Timer PLL allows CPU operation up to the maximum 50MHz I/O Port Up to 40 general-purpose I/O (GPIO) pins for LQFP-48 package Four I/O modes: Quasi bi-direction -6- Publication Release Date: May 30, 2011 Revision V2.00 NuMicroTM M058/M0516 Product Brief z z z z Push-Pull output Open-Drain output Input only with high impendence TTL/Schmitt trigger input selectable I/O pin can be configured as interrupt source with edge/level setting Supports high driver and high sink IO mode Timer Provides four channel 32-bit timers, one 8-bit pre-scale counter with 24-bit up-timer for each timer. Independent clock source for each timer. 24-bit timer value is readable through TDR (Timer Data Register) Provides one-shot, periodic and toggle operation modes. Watchdog Timer Multiple clock sources Supports wake-up from power down or idle mode Interrupt or reset selectable on watchdog time-out PWM Built-in up to four 16-bit PWM generators; providing eight PWM outputs or four complementary paired PWM outputs Individual clock source, clock divider, 8-bit pre-scalar and dead-zone generator for each PWM generator PWM interrupt synchronized to PWM period 16-bit digital Capture timers (shared with PWM timers) with rising/falling capture inputs Supports capture interrupt UART Up to two sets of UART device -7- Publication Release Date: May 30, 2011 Revision V2.00 NuMicroTM M058/M0516 Product Brief z z Programmable baud-rate generator Buffered receiver and transmitter, each with 15 bytes FIFO Optional flow control function (CTS and RTS) Supports IrDA(SIR) function Supports RS485 function SPI Up to two sets of SPI device. Supports master/slave mode Master mode clock rate up to 20 MHz, and slave mode clock rate up to 10 MHz Full duplex synchronous serial data transfer Variable length of transfer data from 1 to 32 bits MSB or LSB first data transfer Rx latching data can be either at rising edge or at falling edge of serial clock Tx sending data can be either at rising edge or at falling edge of serial clock Supports Byte suspend mode in 32-bit transmission I2C Supports master/slave mode Bidirectional data transfer between masters and slaves Multi-master bus (no central master). Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. Programmable clocks allow versatile rate control. -8- Publication Release Date: May 30, 2011 Revision V2.00 NuMicroTM M058/M0516 Product Brief z z Supports multiple address recognition (four slave address with mask option) ADC 12-bit SAR ADC with 600k SPS Up to 8-ch single-ended input or 4-ch differential input Supports single mode/burst mode/single-cycle scan mode/continuous scan mode Each channel with an individual result register Supports conversion value monitoring (or comparison) for threshold voltage detection Conversion can be started either by software trigger or external pin trigger EBI (External Bus Interface) for external memory-mapped device access Accessible space: 64KB in 8-bit mode or 128KB in 16-bit mode Supports 8-bit/16-bit data width z In-System Programming (ISP) and In-Circuit Programming (ICP) z Brownout Detector z With 4 levels: 4.5V/3.8V/2.7V/2.2V Supports brownout interrupt and reset option LVR (Low Voltage Reset) Threshold voltage levels: 2.0V z Operating Temperature: -40~85 z Packages: Green package (RoHS) 48-pin LQFP, 33-pin QFN -9- Publication Release Date: May 30, 2011 Revision V2.00 NuMicroTM M058/M0516 Product Brief 3 BLOCK DIAGRAM Figure 3-1 NuMicroTM M051 Series Block Diagram - 10 - Publication Release Date: May 30, 2011 Revision V2.00 NuMicroTM M058/M0516 Product Brief 4 SELECTION TABLE NuMicro M051TM Series Selection Guide Part No. APROM RAM Data Flash Connectivity LDROM I/O ISP Timer PWM UART SPI ADC EBI Package ICP I2C M058LAN 32KB 4KB 4KB 4KB 40 4x32-bit 2 2 1 8 8x12-bit M058ZAN 32KB 4KB 4KB 4KB 24 4x32-bit 2 1 1 5 5x12-bit M0516LAN 64KB 4KB 4KB 4KB 40 4x32-bit 2 2 1 8 8x12-bit M0516ZAN 64KB 4KB 4KB 4KB 24 4x32-bit 2 1 1 5 5x12-bit v v v LQFP48 v QFN 33 v LQFP48 v QFN 33 Table 4-1 NuMicroTM M051 Series Product Selection Guide M0 5X - X X X CPU core ARM Cortex-M0 Temperature Part Number 52 : 54 : 8K Flash ROM 16K Flash ROM N : -40 ~ +85 E : -40 ~ +105 C : -40 ~ +105 Reserved Package L : LQFP 48 Z : QFN 33 Figure 4-1 NuMicro M051TM Naming Rule - 11 - Publication Release Date: May 30, 2011 Revision V2.00 NuMicroTM M058/M0516 Product Brief 5 PIN CONFIGURATION 5.1 QFN 33 pin CTS1, P0.0 RTS1, P0.1 P2.2, PWM2 P2.3, PWM3 P2.4, PWM4 LDO_CAP VDD AVDD VSS XTAL1 AIN0, T2, P1.0 RXD1, AIN2, P1.2 XTAL2 P3.6, CKO TXD1, AIN3, P1.3 AIN4, P1.4 Figure 5-1 NuMicroTM M051 Series QFN33 Pin Diagram - 12 - Publication Release Date: May 30, 2011 Revision V2.00 NuMicroTM M058/M0516 Product Brief 5.2 LQFP 48 pin Figure 5-2 NuMicroTM M051 Series LQFP-48 Pin Diagram - 13 - Publication Release Date: May 30, 2011 Revision V2.00 NuMicroTM M058/M0516 Product Brief 5.3 Pin Description Pin number Alternate Function Symbol QFN33 LQFP48 Type 1 [1] Description 2 I CRYSTAL1: This is the input pin to the internal inverting amplifier. The system clock is from external crystal or resonator when FOSC[1:0] (CONFIG3[1:0]) are both logic 1 by default. 11 16 XTAL1 10 15 XTAL2 O CRYSTAL2: This is the output pin from the internal inverting amplifier. It emits the inverted signal of XTAL1. 27 41 VDD P POWER SUPPLY: operation. 17 VSS P GROUND: Digital Ground potential. 28 42 AVDD P POWER SUPPLY: Supply voltage Analog AVDD for operation. 4 6 AVSS P GROUND: Analog Ground potential. 13 18 LDO_C AP P (ST) Supply voltage Digital VDD for 12 33 LDO: LDO output pin Note: It needs to be connected with a 10uF capacitor. I (ST) RESET: /RST pin is a Schmitt trigger input pin for hardware device reset. A "Low" on this pin for 768 clock counter of Internal 22.1184 MHz high speed oscillator while the system clock is running will reset the device. /RST pin has an internal pull-up resistor allowing power-on reset by simply connecting an external capacitor to GND. 2 4 /RST 26 40 P0.0 CTS1 AD0 D, I/O 25 39 P0.1 RTS1 AD1 D, I/O PORT0: Port 0 is an 8-bit four mode output pin and two mode input. Its multifunction pins are for CTS1, RTS1, CTS0, RTS0, SPISS1, MOSI_1, MISO_1, and SPICLK1. NC 38 P0.2 CTS0 AD2 D, I/O P0 has an alternative function as AD[7:0] while external memory interface (EBI) is enabled. NC 37 P0.3 RTS0 AD3 D, I/O These pins which are SPISS1, MOSI_1, MISO_1, and SPICLK1 for the SPI function used. 24 35 P0.4 SPISS1 AD4 D, I/O CTS0/1: Clear to Send input pin for UART0/1 - 14 - Publication Release Date: May 30, 2011 Revision V2.00 NuMicroTM M058/M0516 Product Brief Pin number Alternate Function Symbol QFN33 LQFP48 Type 1 2 [1] Description RTS0/1: Request to Send output pin for UART0/1 23 34 P0.5 MOSI_1 AD5 D, I/O 22 33 P0.6 MISO_1 AD6 D, I/O 21 32 P0.7 SPICLK1 AD7 D, I/O 29 43 P1.0 T2 AIN0 I/O NC 44 P1.1 T3 AIN1 I/O 30 45 P1.2 RXD1 AIN2 I/O 31 46 P1.3 TXD1 AIN3 I/O 32 47 P1.4 SPISS0 AIN4 I/O These pins which are SPISS0, MOSI_0, MISO_0, and SPICLK0 for the SPI function used. 1 1 P1.5 MOSI_0 AIN5 I/O These pins which are AIN0~AIN7for the 12 bits ADC function used. NC 2 P1.6 MISO_0 AIN6 I/O The RXD1/TXD1 pins are for UART1 function used. NC 3 P1.7 SPICLK0 AIN7 I/O NC 19 P2.0 PWM0 AD8 D, I/O NC 20 P2.1 PWM1 AD9 D, I/O 14 21 P2.2 PWM2 AD10 D, I/O 15 22 P2.3 PWM3 AD11 D, I/O 16 23 P2.4 PWM4 AD12 D, I/O 17 25 P2.5 PWM5 AD13 D, I/O 18 26 P2.6 PWM6 AD14 D, I/O NC 27 P2.7 PWM7 AD15 D, I/O 3 5 P3.0 RXD I/O 5 7 P3.1 TXD I/O PORT1: Port 1 is an 8-bit four mode output pin and two mode input. Its multifunction pins are for T2, T3, RXD1, TXD1, SPISS0, MOSI_0, MISO_0, and SPICLK0. T2: Timer2 external input - 15 - T3: Timer3 external input PORT2: Port 2 is an 8-bit four mode output pin and two mode input. It has an alternative function P2 has an alternative function as AD[15:8] while external memory interface (EBI) is enabled. These pins which are PWM0~PWM7 for the PWM function. PORT3: Port 3 is an 8-bit four mode output pin and two mode input. Its multifunction pins are for RXD, TXD, INT0 , Publication Release Date: May 30, 2011 Revision V2.00 NuMicroTM M058/M0516 Product Brief Pin number Alternate Function Symbol QFN33 LQFP48 Type 1 2 INT0 STADC I/O I/O 6 8 P3.2 NC 9 P3.3 INT1 MCLK 7 10 P3.4 T0 SDA I/O 8 11 P3.5 T1 SCL I/O [1] Description INT1 , T0, T1, WR , and RD . T0: Timer0 external input T1: Timer1 external input The RXD/TXD pins are for UART0 function used. 2 The SDA/SCL pins are for I C function used. MCLK: EBI clock output pin. CKO: HCLK clock output The STADC pin is for ADC external trigger input. 9 13 P3.6 WR NC 14 P3.7 RD I/O NC 24 P4.0 PWM0 I/O NC 36 P4.1 PWM1 I/O NC 48 P4.2 PWM2 I/O NC 12 P4.3 PWM3 I/O NC 28 P4.4 /CS I/O ALE (Address Latch Enable) is used to enable the address latch that separates the address from the data on Port 0 and Port 2. NC 29 P4.5 ALE I/O The ICE_CLK/ICE_DAT pins are for JTAG-ICE function used. 19 30 P4.6 ICE_CLK I/O 20 31 P4.7 ICE_DAT I/O CKO I/O PORT4: Port 4 is an 8-bit four mode output pin and two mode input. Its multifunction pins are for /CS, ALE, ICE_CLK and ICE_DAT. /CS for EBI (External Bus Interface) used. PWM0-3 can be used from P4.0-P4.3 when EBI is active. Table 5-1 NuMicroTM M051 Series Pin Description [1] I/O type description. I: input, O: output, I/O: quasi bi-direction, D: open-drain, P: power pins, ST: Schmitt trigger. - 16 - Publication Release Date: May 30, 2011 Revision V2.00 NuMicroTM M058/M0516 Product Brief TYPICAL APPLICATION CIRCUIT DVDD DVDD DVDD LE OE L2 FB AVDD R1 10K ALE 11 1 D0 D1 D2 D3 D4 D5 D6 D7 U2 74F373 2 5 6 9 12 15 16 19 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 C1 10uF/10V AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 TANT-A LE OE D VSS 3 4 7 8 13 14 17 18 AVSS 20 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 VC C AA0 AA1 AA2 AA3 AA4 AA5 AA6 AA7 FB CB3 0.1 uF Reset Circuit CB4 0.1 uF C2 20p 10 11 1 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 L1 nTICERST CB2 0.1 uF U1 74F373 20 ALE D0 D1 D2 D3 D4 D5 D6 D7 VC C 3 4 7 8 13 14 17 18 GND AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND CB1 0.1 uF DVDD 10 D12MO ADC CB6 0.1 uF A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 A12 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 AA5 AA6 AA7 nRD AD15 AD14 AD13 AD12 DVSS DVDD AD11 AD10 AD9 AD8 ADC Input 1 2 CON1 1X2 HEADER P11 RXD1 TXD1 nSS0 P42 C3 820pF 1 2 U4 M052_LQFP_48 AVD D D VD D A4 A3 A2 A1 A0 CS I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A17 A16 A15 A14 A13 CB5 0.1 uF MOSI_0 MISO_0 SCLK0 nTICERST RXD0 AVSS TXD0 P32 P33 SDA SCL P43 AA8 AA9 AA10 AA11 AA12 MOSI_0/AIN5/P1.5 MISO_0/AIN6/P1.6 SCLK0/AIN7/P1.7 RST RXD/P3.0 AVSS TXD/P3.1 INT0/P3.2 MCLK/INT1/P3.3 SDA/T0/P3.4 SCL/T1/P3.5 P4.3 EBI XTAL3-1 D12MI Crystal ICEJP1 P4.1 P0.4/AD4/SS1 P0.5/AD5/MOSI_1 P0.6/AD6/MISO_1 M052_54 LQFP 48 P0.7/AD7/SCLK1 P4.7/ICE_DAT P4.6/ICE_CLK P4.5/ALE P4.4/CS P2.7/AD15/PWM7 P2.6/AD14/PWM6 P2.5/AD13/PWM5 36 35 34 33 32 31 30 29 28 27 26 25 1 3 5 7 9 P41 AD4 AD5 AD6 AD7 TICEDAT TICECLK ALE nCS AD15 AD14 AD13 2 4 6 8 10 TICEDAT TICECLK nTICERST HEADER 5X2 HEADER5X2 ICE Interface P 3.6/W R /C K O P 3.7/R D XT AL2 XT AL1 VSS LD O _C AP P 2.0/A D 8/P W M 0 P 2.1/A D 9/P W M 1 P 2.2/A D 10/P W M 2 P 2.3/A D 11/P W M 3 P 2.4/A D 12/P W M 4 P 4.0 BS616LV4017EG70(TSOP-44) 1 2 3 4 5 6 7 8 9 10 11 12 C4 20p AD0 AD1 AD2 AD3 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 X1 12MHz P4.2 AIN 3/S S0/P 1.4 A IN 3/T X D 1/P1.3 AIN 2/R X D 1/P1.2 A IN 1/T 2/P1.1 A IN 0/T 2/P1.0 AVD D VD D P0.0/AD 0/C T S1 P0.1/AD 1/R T S1 P0.2/AD 2/C T S0 P0.3/AD 3/R T S0 AA4 AA3 AA2 AA1 AA0 nCS AD0 AD1 AD2 AD3 DVDD DVSS AD4 AD5 AD6 AD7 nWR DVSS DVSS AA15 AA14 AA13 U3 SPI 13 14 15 16 17 18 19 20 21 22 23 24 6 nWR nRD D12MO D12MI 1 2 3 4 UART_RXD UART_TXD S1 8 7 6 5 P40 AD12 AD11 AD10 AD9 AD8 RXD0 TXD0 RXD1 TXD1 DVDD DVDD CB7 0.1 uF C5 10uF TANT-B SW DIP-4 SWDIP8 RSPI1 4.7K nSS1 MISO_1 MET22 1 2 3 4 RSPI2 4.7K USPI1 W25X16VSSIG CS# DO WP# GND VCC HOLD# CLK DI 8 7 6 5 DVDD MET23 SCLK1 MOSI_1 SOIC-8P UART C6 1uF TANT-A P1 11 VSS 1 6 2 7 3 8 4 9 5 10 DB9-M () DB9L-HP VDD C8 1uF TANT-A NET10 NET11 R3 33 R5 33 C7 1uF TANT-A NET3 NET4 NET40 NET5 NET6 NET7 NET8 NET9 C9 1uF TANT-A I2C DVDD 1 2 3 4 5 6 7 8 U5 MAX232A C1+ V+ C1C2+ C2VT2OUT R2IN SOP16/150 VCC GND T1OUT R1IN R1OUT T1IN T2IN R2OUT 16 15 14 13 12 11 10 9 CB8 0.1 uF DVDD NET12 NET13 R4 33 EEPROM ADDRESS:0H UART_TXD UART_RXD R6 33 1 2 3 4 I2C-EEPROM UI2C1 A0 A1 A2 GND VCC WP SCL SDA RI2C1 4.7K 8 7 6 5 24LC64 SOIC8\1.27\5.6MM - 17 - RI2C2 4.7K CB9 0.1 uF Title SCL SDA M052_54 Application Circuit Size Document Number Date: Thursday , August 19, 2010 Rev Application.dsn 1.0 Sheet 1 of 1 Publication Release Date: May 30, 2011 Revision V2.00 NuMicroTM M058/M0516 Product Brief 7 ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings SYMBOL PARAMETER MIN MAX UNIT VDD-VSS -0.3 +7.0 V VIN VSS-0.3 VDD+0.3 V 1/tCLCL 0 40 MHz TA -40 +85 C TST -55 +150 C - 120 mA Maximum Current out of VSS 120 mA Maximum Current sunk by a I/O pin 35 mA Maximum Current sourced by a I/O pin 35 mA Maximum Current sunk by total I/O pins 100 mA Maximum Current sourced by total I/O pins 100 mA DC Power Supply Input Voltage Oscillator Frequency Operating Temperature Storage Temperature Maximum Current into VDD Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability of the device. - 18 - Publication Release Date: May 30, 2011 Revision V2.00 NuMicroTM M058/M0516 Product Brief 7.2 DC Electrical Characteristics (VDD-VSS=2.5~5.5V, TA = 25C, FOSC = 50 MHz unless otherwise specified.) SPECIFICATION PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT 5.5 V Operation voltage VDD 2.5 Power Ground VSS AVSS -0.3 LDO Output Voltage VLDO -10% 2.45 +10% V VDD > 2.7V Band Gap Analog Input VBG -5% 1.26 +5% V VDD =2.5V ~ 5.5V AVDD 0 VDD V Analog Operating Voltage Operating Current Normal Run Mode @ 50 MHz Operating Current Normal Run Mode @ 12 MHz Operating Current Normal Run Mode @ 4 MHz Operating Current VDD =2.5V ~ 5.5V up to 50 MHz V IDD1 32 mA VDD= 5.5V@50 MHz, enable all IP and PLL, XTAL=12 MHz IDD2 24 mA VDD=5.5V@50 MHz, disable all IP and enable PLL, XTAL=12 MHz IDD3 31 mA VDD = 3V@50 MHz, enable all IP and PLL, XTAL=12 MHz IDD4 23 mA VDD = 3V@50 MHz, disable all IP and enable PLL, XTAL=12 MHz IDD5 17 mA VDD = 5.5V@ 12MHz, enable all IP and disable PLL, XTAL=12 MHz IDD6 14 mA VDD = 5.5V@12 MHz, disable all IP and disable PLL, XTAL=12 MHz IDD7 16 mA VDD = 3V@12 MHz, enable all IP and disable PLL, XTAL=12 MHz IDD8 13 mA VDD = 3V@12 MHz, disable all IP and disable PLL, XTAL=12 MHz IDD9 12 mA VDD = 5.5V@4 MHz, enable all IP and disable PLL, XTAL=4MHz IDD10 10 mA VDD = 5.5V@4 MHz, disable all IP and disable PLL, XTAL=4MHz IDD11 10 mA VDD = 3V@4 MHz, enable all IP and disable PLL, XTAL=4MHz IDD12 9 mA VDD = 3V@4 MHz, disable all IP and disable PLL, XTAL=4 MHz IIDLE1 19 mA VDD= 5.5V@50 MHz, enable all IP and PLL, XTAL=12 MHz - 19 - Publication Release Date: May 30, 2011 Revision V2.00 NuMicroTM M058/M0516 Product Brief Idle Mode @ 50 MHz IIDLE2 11 mA VDD=5.5V@50 MHz, disable all IP and enable PLL, XTAL=12 MHz IIDLE3 18 mA VDD = 3V@50 MHz, enable all IP and PLL, XTAL=12 MHz IIDLE4 10 mA VDD = 3V@50 MHz, disable all IP and enable PLL, XTAL=12 MHz IIDLE5 10 mA VDD = 5.5V@12 MHz, enable all IP and disable PLL, XTAL=12 MHz IIDLE6 7 mA VDD = 5.5V@12 MHz, disable all IP and disable PLL, XTAL=12 MHz IIDLE7 9 mA VDD = 3V@12 MHz, enable all IP and disable PLL, XTAL=12 MHz IIDLE8 6 mA VDD = 3V@12 MHz, disable all IP and disable PLL, XTAL=12 MHz IIDLE9 5 mA VDD = 5.5V@4 MHz, enable all IP and disable PLL, XTAL=4 MHz IIDLE10 4 mA VDD = 5.5V@4 MHz, disable all IP and disable PLL, XTAL=4 MHz IIDLE11 4 mA VDD = 3V@4 MHz, enable all IP and disable PLL, XTAL=4 MHz IIDLE12 3 mA VDD = 3V@4 MHz, disable all IP and disable PLL, XTAL=4 MHz IPWD1 15 A VDD = 5.5V, No load @ Disable BOV function IPWD2 11 A VDD = 3.0V, No load @ Disable BOV function Input Current P0/1/2/3/4 (Quasi-bidirectional mode) IIN1 -50 -60 A VDD = 5.5V, VIN = 0.4V Input Leakage Current P0/1/2/3/4 ILK -2 - +2 A VDD = 5.5V, 0 2.7V Temperature -40 25 85 - 100 - uA - 5 - uA Iload (PD=0) - - 100 mA Iload (PD=1) - - 100 uA Cbp - 10 - uF Quiescent Current (PD=0) Quiescent Current (PD=1) Resr=1ohm Note: 1. It is recommended that a 10uF (or higher) capacitor and a 100nF bypass capacitor are connected between VDD and the closest VSS pin of the device. 2. For ensuring power stability, a 4.7uF or higher capacitor must be connected between LDO pin and the closest VSS pin of the device. - 26 - Publication Release Date: May 30, 2011 Revision V2.00 NuMicroTM M058/M0516 Product Brief 7.4.3 Specification of Low Voltage Reset PARAMETER CONDITION MIN. TYP. MAX. UNIT Operation voltage - 1.7 - 5.5 V Quiescent current VDD5V=5.5V - - 5 uA Temperature=25 1.7 2.0 2.3 V Temperature=-40 - 2.4 - V Temperature=85 - 1.6 - V - 0 0 0 V Threshold voltage Hysteresis 7.4.4 Specification of Brownout Detector PARAMETER CONDITION MIN. TYP. MAX. UNIT Operation voltage - 2.5 - 5.5 V Quiescent current AVDD=5.5V - - 125 A Temperature - -40 25 85 BOV_VL[1:0]=11 4.4 4.5 4.6 V BOV_VL [1:0]=10 3.7 3.8 3.9 V BOV_VL [1:0]=01 2.6 2.7 2.8 V BOV_VL [1:0]=00 2.1 2.2 2.3 V - 30m - 150m V Brown-out voltage Hysteresis 7.4.5 Specification of Power-On Reset (5V) PARAMETER CONDITION MIN. TYP. MAX. UNIT Reset voltage V+ - 2 - V Quiescent current Vin>reset voltage - 1 - nA - 27 - Publication Release Date: May 30, 2011 Revision V2.00 NuMicroTM M058/M0516 Product Brief 7.5 SPI Dynamic characteristics PARAMETER CONDITION MIN. TYP. MAX. UNIT SPI master mode (VDD = 4.5V ~ 5.5V, 30pF loading Capacitor) tDS Data setup time 26 - - ns tDH Data hold time 0 - - ns tV Data output valid time - - 6 ns SPI master mode (VDD = 3.0V ~ 3.6V, 30pF loading Capacitor) tDS Data setup time 39 - - ns tDH Data hold time 0 - - ns tV Data output valid time - - 10 ns SPI slave mode (VDD = 4.5V ~ 5.5V, 30pF loading Capacitor) tDS Data setup time 0 - - ns tDH Data hold time 2*PCLK+4 - - ns tV Data output valid time - - 2*PCLK+27 ns SPI slave mode (VDD = 3.0V ~ 3.6V, 30pF loading Capacitor) tDS Data setup time 0 - - ns tDH Data hold time 2*PCLK+8 - - ns tV Data output valid time - - 2*PCLK+40 ns - 28 - Publication Release Date: May 30, 2011 Revision V2.00 NuMicroTM M058/M0516 Product Brief Figure 7-2 SPI Master timing Figure 7-3 SPI Slave timing - 29 - Publication Release Date: May 30, 2011 Revision V2.00 NuMicroTM M058/M0516 Product Brief 8 PACKAGE DIMENSIONS 8.1 LQFP-48 (7x7x1.4mm2 Footprint 2.0mm) - 30 - Publication Release Date: May 30, 2011 Revision V2.00 NuMicroTM M058/M0516 Product Brief 8.2 QFN-33 (5X5 mm2, Thickness 0.8mm, Pitch 0.5 mm) - 31 - Publication Release Date: May 30, 2011 Revision V2.00 NuMicroTM M058/M0516 Product Brief 9 REVISION HISTORY VERSION DATE PAGE V1.0 Jan 31, 2011 - V1.1 Mar 08, 2011 25 - V2.0 May 30, 2011 DESCRIPTION Initial issued Removed the Note 2 of Table 7.4.2 Add "Whole Chip Clock generator block diagram" 26 Revise the spec of LDO 28 Add SPI Dynamic Characteristics - 32 - Publication Release Date: May 30, 2011 Revision V2.00 NuMicroTM M058/M0516 Product Brief Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, "Insecure Usage". Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. All Insecure Usage shall be made at customer's risk, and in the event that third parties lay claims to Nuvoton as a result of customer's Insecure Usage, customer shall indemnify the damages and liabilities thus incurred by Nuvoton. - 33 - Publication Release Date: May 30, 2011 Revision V2.00