MC100EP809 3.3V 2:1:9 Differential HSTL/PECL/LVDS to HSTL Clock Driver with LVTTL Clock Select and Enable www.onsemi.com Description The MC100EP809 is a low skew 2:1:9 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage applications which require a large number of outputs to drive precisely aligned low skew signals to their destination. The two clock inputs are one differential HSTL and one differential LVPECL. Both input pairs can accept LVDS levels. They are selected by the CLK_SEL pin which is LVTTL. To avoid generation of a runt clock pulse when the device is enabled/disabled, the Output Enable (OE), which is LVTTL, is synchronous ensuring the outputs will only be enabled/disabled when they are already in LOW state (Figure 9). The MC100EP809 guarantees low output-to-output skew. The optimal design, layout, and processing minimize skew within a device and from lot to lot. The MC100EP809 output structure uses open emitter architecture and will be terminated with 50 to ground instead of a standard HSTL configuration (Figure 7). To ensure the tight skew specification is realized, both sides of the differential output need to be terminated identically into 50 even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew. Designers can take advantage of the EP809's performance to distribute low skew clocks across the backplane of the board. Both clock inputs may be single-end driven by biasing the non-driven pin in an input pair (Figure 8). Features * 100 ps Typical Device-to-Device Skew * 15 ps Typical within Device Skew * HSTL Compatible Outputs Drive 50 to GND with no * * * * * * MARKING DIAGRAMS* MC100 EP809 32-LEAD LQFP FA SUFFIX CASE 873A AWLYYWWG 32 1 1 1 32 QFN32 MN SUFFIX CASE 488AM MC100 EP809 AWLYYWWG G A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. Offset Voltage Maximum Frequency > 750 MHz 850 ps Typical Propagation Delay Fully Compatible with Micrel SY89809L PECL and HSTL Mode Operating Range: VCCI = 3 V to 3.6 V with GND = 0 V, VCCO = 1.6 V to 2.0 V Open Input Default State These Devices are Pb-Free and are RoHS Compliant (c) Semiconductor Components Industries, LLC, 2015 April, 2015 - Rev. 10 1 Publication Order Number: MC100EP809/D MC100EP809 VCCO Q0 Q0 Q1 Q1 Q2 Q2 VCCO 32 31 30 29 28 27 26 25 8 OE Q5 17 7 GND Q5 18 6 LVPECL_CLK Q4 19 5 LVPECL_CLK Q4 20 4 MC100EP809 Q3 21 3 CLK_SEL Q3 22 HSTL_CLK VCCO 23 2 HSTL_CLK 24 1 VCCI VCCO 16 15 14 13 12 11 10 9 VCCO Q6 Q6 Q7 Q7 Q8 Q8 VCCO All VCCI, VCCO, and GND pins must be externally connected to appropriate Power Supply to guarantee proper operation (VCCI 0 VCCO). Figure 1. 32-Lead LQFP Pinout (Top View) VCCO Q0 Q0 Q1 Q1 Q2 Q2 VCCO 32 31 30 29 28 27 26 25 Exposed Pad (EP) VCCI 1 24 V CCO HSTL_CLK 2 23 Q3 HSTL_CLK 3 22 Q3 CLK_SEL 4 21 Q4 LVPECL_CLK 5 LVPECL_CLK 6 19 Q5 GND 7 18 Q5 OE 8 17 MC100EP809 13 14 15 16 Q6 Q6 VCCO Q8 12 Q7 VCCO 11 Q7 10 Q8 9 20 Q4 Figure 2. 32-Lead QFN Pinout (Top View) www.onsemi.com 2 VCCO MC100EP809 Table 1. PIN DESCRIPTION Table 2. TRUTH TABLE PIN FUNCTION HSTL_CLK*, HSTL_CLK** HSTL or LVDS Differential Inputs LVPECL_CLK*, LVPECL_CLK** LVPECL or LVDS Differential Inputs CLK_SEL** LVCMOS/LVTTL Input CLK Select OE** LVCMOS/LVTTL Output Enable Q0 - Q8, Q0 - Q8 HSTL Differential Outputs VCC1 Positive Supply_Core (3.0 V - 3.6 V) VCC0 Positive Supply_HSTL Outputs (1.6 V - 2.0 V) GND Ground EP The exposed pad (EP) on the QFN-32 package bottom is thermally connected to the die for improved heat transfer out of the package. THe exposed pad must be attached to a heat-sinking conduit. The pad is electrically connected to GND. OE* CLK_SEL Q0 - Q8 Q0 - Q8 L L L H L H L H H L HSTL_CLK HSTL_CLK H H LVPECL_CLK LVPECL_CLK *The OE (Output Enable) signal is synchronized with the rising edge of the HSTL_CLK and LVOCL_CLK signals. * Pins will default LOW when left open. ** Pins will default HIGH when left open. CLK_SEL HSTL_CLK 0 9 HSTL_CLK Q0-Q8 (HSTL) 9 Q0-Q8 (HSTL) LVPECL_CLK 1 VCCI GND LVPECL_CLK VCCO Q D OE Figure 3. Logic Diagram Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor ESD Protection 37.5 k Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) LQFP-32 QFN-32 Flammability Rating Oxygen Index: 28 to 34 Transistor Count > 2 kV > 200 V > 2 kV Pb Pkg Pb-Free Pkg Level 2 N/A Level 2 Level 1 UL 94 V-0 @ 0.125 in 478 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 3 MC100EP809 Table 4. MAXIMUM RATINGS Symbol Rating Unit VCC1 Core Power Supply Parameter GND = 0 V Condition 1 VCC0 = 1.6 to 2.0 V Condition 2 4 V VCC0 HSTL Output Power Supply GND = 0 V VCC1 = 3.0 to 3.6 V 4 V VI Input Voltage GND = 0 V VI v VCC1 4 V Iout Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range 0 to +85 C Tstg Storage Temperature Range -65 to +150 C JA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm LQFP-32 LQFP-32 80 55 C/W C/W JC Thermal Resistance (Junction-to-Case) Standard Board LQFP-32 12 to 17 C/W JA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm QFN-32 QFN-32 31 27 C/W C/W JC Thermal Resistance (Junction-to-Case) 2S2P QFN-32 12 C/W Tsol Wave Solder 265 265 C Pb Pb-Free Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Table 5. LVPECL DC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V 0C Symbol Characteristic 25C 85C Min Typ Max Min Typ Max Min Typ Max Unit 75 95 115 75 95 115 75 95 115 mA ICC Core Power Supply Current VIH Input HIGH Voltage (Single-Ended) VCCI - 1.165 VCCI - 0.88 VCCI - 1.165 VCCI - 0.88 VCCI - 1.165 VCCI - 0.88 V VIL Input LOW Voltage (Single-Ended) VCCI - 1.945 VCCI - 1.6 VCCI - 1.945 VCCI - 1.6 VCCI - 1.945 VCCI - 1.6 V VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 2) (Figure 5) LVPECL_CLK/LVPECL_CLK 1.2 VCCI 1.2 VCCI 1.2 VCCI V IIH Input HIGH Current -150 150 -150 150 -150 150 A IIL Input LOW Current -150 150 -150 150 -150 150 A NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 2. VIHCMR max varies 1:1 with VCCI. The VIHCMR range is referenced to the most positive side of the differential input signal. www.onsemi.com 4 MC100EP809 Table 6. LVTTL/LVCMOS DC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V 0C Symbol Characteristic Min Typ 25C Max 2.0 Min Typ 85C Max VIH Input HIGH Voltage 2.0 VIL Input LOW Voltage IIH Input HIGH Current -150 150 -150 150 IIL Input LOW Current -300 300 -300 300 Min Typ Max 2.0 0.8 Unit V 0.8 0.8 V -150 150 A -300 300 A NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Table 7. HSTL DC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V 0C Characteristic Min Max Min VOH Output HIGH Voltage (Note 3) 1.0 1.2 VOL VIH Output LOW Voltage (Note 3) 0.1 Input HIGH Voltage (Figure 6) VX + 0.1 VIL Input LOW Voltage (Figure 6) -0.3 VX HSTL Input Crossover Voltage 0.68 IIH Input HIGH Current IIL Input LOW Current VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) HSTL_CLK/HSTL_CLK Symbol Typ 25C Max Min 1.0 1.2 0.4 0.1 1.6 VX + 0.1 VX - 0.1 -0.3 0.9 0.68 -150 150 -300 300 0.6 VCCI - 1.2 - Typ 85C Max Unit 1.0 1.2 V 0.4 0.1 0.4 V 1.6 VX + 0.1 1.6 V VX - 0.1 -0.3 VX - 0.1 V 0.9 0.68 0.9 V -150 150 -150 150 A -300 300 -300 300 A 0.6 VCCI - 1.2 0.6 VCCI - 1.2 V V - Typ - NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 3. All outputs loaded with 50 to GND (Figure 7). 4. VIHCMR max varies 1:1 with VCCI. The VIHCMR range is referenced to the most positive side of the differential input signal. www.onsemi.com 5 MC100EP809 Table 8. AC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V (Note 5) 0C 25C Characteristic Min Typ Differential Output Voltage fout < 100 MHz (Figure 4) fout < 500 MHz fout < 750 MHz 600 600 450 850 750 575 tPLH tPHL Propagation Delay (Differential Configuration) LVPECL_CLK to Q HSTL_CLK to Q 680 690 800 830 930 990 tskew Within-Device Skew (Note 6) Device-to-Device Skew (Note 7) 15 100 tJITTER Random Clock Jitter (Figure 4) (RMS) 1.4 VPP Input Swing (Differential Configuration) (Note 8) (Figure 5) LVPECL HSTL 200 200 200 200 200 200 mV mV tS OE Set Up Time (Note 9) 0.5 0.5 0.5 ns tH OE Hold Time 0.5 tr/tf Output Rise/Fall Time (20% - 80%) 350 Symbol VOpp Max 85C Min Typ 600 600 450 850 750 575 Max Min Typ 600 600 450 850 750 575 700 700 820 850 950 1000 50 200 15 100 3.0 1.4 780 790 920 950 1070 1110 ps ps 50 200 15 100 50 200 ps ps 3.0 1.4 3.0 ps 0.5 600 350 Max mV mV 0.5 450 600 350 Unit ns 600 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 5. Measured with 750 mV (LVPECL) source or 1 V (HSTL) source, 50% duty cycle clock source. All outputs loaded with 50 to GND (Figure 7). 6. Skew is measured between outputs under identical transitions and conditions on any one device. 7. Device-to-Device skew for identical transitions and conditions. 8. VPP is the Differential Input Voltage swing required to maintain AC characteristics listed herein. 9. OE Set Up Time is defined with respect to the rising edge of the clock. OE High-to-Low transition ensures outputs remain disabled during the next clock cycle. OE Low-to-High transition enables normal operation of the next input clock (Figure 9). 900 9 800 8 VOPP 7 600 6 500 5 400 4 300 3 tJITTER ps (RMS) VOPP (mV) 700 RMS JITTER 200 2 100 1 0 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) Figure 4. Output Frequency (FOUT) versus Output Voltage (VOPP) and Random Clock Jitter (tJITTER) www.onsemi.com 6 MC100EP809 VCCI VCCO(HSTL) VCCI(LVPECL) VIH(DIFF) VX VIH(DIFF) VPP VIHCMR VIL(DIFF) VIL(DIFF) VPP GND Figure 5. LVPECL Differential Input Levels GND Figure 6. HSTL Differential Input Levels Z = 50 Q HSTL OUTPUT Q 50 50 GROUND Figure 7. HSTL Output Termination and AC Test Reference CLK/CLK D.C. Bias* *Must be CLK/CLK common mode voltage: ((VIH + VIL)/2). Figure 8. Single-Ended CLK/CLK Input Configuration CLK CLK OE Q Q Figure 9. Output Enable (OE) Timing Diagram www.onsemi.com 7 MC100EP809 ORDERING INFORMATION Package Shipping MC100EP809FAG LQFP-32 (Pb-Free) 250 Units / Tray MC100EP809FAR2G LQFP-32 (Pb-Free) 2000 / Tape & Reel MC100EP809MNG QFN32 (Pb-Free) 74 Units / Rail MC100EP809MNR4G QFN32 (Pb-Free) 1000 / Tape & Reel Device For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D - ECL Clock Distribution Techniques AN1406/D - Designing with PECL (ECL at +5.0 V) AN1503/D - ECLinPSt I/O SPiCE Modeling Kit AN1504/D - Metastability and the ECLinPS Family AN1568/D - Interfacing Between LVDS and ECL AN1672/D - The ECL Translator Guide AND8001/D - Odd Number Counters Design AND8002/D - Marking and Date Codes AND8020/D - Termination of ECL Logic Devices AND8066/D - Interfacing with ECLinPS AND8090/D - AC Characteristics of ECL Devices www.onsemi.com 8 MC100EP809 PACKAGE DIMENSIONS A 4X A1 32 -T-, -U-, -Z- 32 LEAD LQFP CASE 873A-02 ISSUE C 25 0.20 (0.008) AB T-U Z 1 -U- -T- AE V 17 V1 BASE METAL AE DETAIL Y 9 -Z- 9 S1 EE EE EE N 4X 0.20 (0.008) AC T-U Z F S 8X M_ J R D DETAIL AD G SECTION AE-AE -AB- C E -AC- H W K X DETAIL AD NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X www.onsemi.com 9 MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.450 0.750 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.018 0.030 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF Q_ 0.250 (0.010) 0.10 (0.004) AC GAUGE PLANE SEATING PLANE AC T-U Z DETAIL Y 8 M B1 P 0.20 (0.008) B MC100EP809 PACKAGE DIMENSIONS QFN32 5x5, 0.5P CASE 488AM ISSUE A A D PIN ONE LOCATION EE EE L L B L1 DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e K L L1 0.15 C 0.15 C A DETAIL B 0.10 C EE EE CC EXPOSED Cu TOP VIEW (A3) A1 MOLD CMPD DETAIL B ALTERNATE CONSTRUCTION 0.08 C SEATING PLANE C SIDE VIEW NOTE 4 RECOMMENDED SOLDERING FOOTPRINT* DETAIL A 9 K D2 32X 5.30 17 8 MILLIMETERS MIN MAX 0.80 1.00 --- 0.05 0.20 REF 0.18 0.30 5.00 BSC 2.95 3.25 5.00 BSC 2.95 3.25 0.50 BSC 0.20 --- 0.30 0.50 --- 0.15 3.35 32X 0.63 L E2 1 32 3.35 5.30 25 e e/2 32X BOTTOM VIEW b 0.10 M C A B 0.05 M C NOTE 3 0.50 PITCH 32X 0.30 DIMENSION: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). 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American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5817-1050 www.onsemi.com 10 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC100EP809/D