© Semiconductor Components Industries, LLC, 2015
April, 2015 − Rev. 10 1Publication Order Number:
MC100EP809/D
MC100EP809
3.3V 2:1:9 Differential
HSTL/PECL/LVDS to HSTL
Clock Driver with LVTTL
Clock Select and Enable
Description
The MC100EP809 is a low skew 2:1:9 differential clock driver,
designed with clock distribution in mind, accepting two clock sources
into an input multiplexer. The part is designed for use in low voltage
applications which require a large number of outputs to drive precisely
aligned low skew signals to their destination. The two clock inputs are
one differential HSTL and one differential LVPECL. Both input pairs
can accept LVDS levels. They are selected by the CLK_SEL pin
which is LVTTL. To avoid generation of a runt clock pulse when the
device is enabled/disabled, the Output Enable (OE), which is LVTTL,
is synchronous ensuring the outputs will only be enabled/disabled
when they are already in LOW state (Figure 9).
The MC100EP809 guarantees low output−to−output skew. The
optimal design, layout, and processing minimize skew within a device
and from lot to lot. The MC100EP809 output structure uses open
emitter architecture and will be terminated with 50 to ground
instead of a standard HSTL configuration (Figure 7). To ensure the
tight skew specification is realized, both sides of the dif ferential output
need to be terminated identically into 50 even if only one output is
being used. If an output pair is unused, both outputs may be left open
(unterminated) without affecting skew.
Designers can take advantage of the EP809’s performance to
distribute low skew clocks across the backplane of the board. Both
clock inputs may be single−end driven by biasing the non−driven pin
in an input pair (Figure 8).
Features
•100 ps Typical Device−to− Device Skew
•15 ps Typical within Device Skew
•HSTL Compatible Outputs Drive 50 to GND with no
Offset Voltage
•Maximum Frequency > 750 MHz
•850 ps Typical Propagation Delay
•Fully Compatible with Micrel SY89809L
•PECL and HSTL Mode Operating Range: VCCI = 3 V to 3.6 V
with GND = 0 V, VCCO = 1.6 V to 2.0 V
•Open Input Default State
•These Devices are Pb−Free and are RoHS Compliant
32
1
MC100
AWLYYWWG
EP809
32−LEAD LQFP
FA SUFFIX
CASE 873A
MARKING
DIAGRAMS*
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G or G= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
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32
1MC100
EP809
AWLYYWWG
G
1
QFN32
MN SUFFIX
CASE 488AM
MC100EP809
www.onsemi.com
2
25
26
27
28
29
30
31
32
15
14
13
12
11
10
9
12345678
24 23 22 21 20 19 18 17
16
All VCCI, VCCO, and GND pins must be externally connected to
appropriate Power Supply to guarantee proper operation (VCCI 0 VCCO).
Figure 1. 32−Lead LQFP Pinout (Top View)
VCCI
HSTL_CLK
HSTL_CLK
CLK_SEL
LVPECL_CLK
LVPECL_CLK
GND
OE
VCCO
VCCO
Q3
Q3
Q4
Q4
Q5
Q5
Q2
VCCO
Q2
Q1
Q1
Q0
Q0
VCCO
VCCO
Q6
Q6
Q7
Q7
Q8
Q8
VCCO
MC100EP809
2526272829303132
1514131211109
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
Figure 2. 32−Lead QFN Pinout (Top View)
VCCI
HSTL_CLK
HSTL_CLK
CLK_SEL
LVPECL_CLK
LVPECL_CLK
GND
OE
VCCO
VCCO
Q3
Q3
Q4
Q4
Q5
Q5
Q2
VCCO
Q2
Q1
Q1
Q0
Q0
VCCO
VCCO
Q6
Q6
Q7
Q7
Q8
Q8
VCCO
MC100EP809
Exposed Pad
(EP)
MC100EP809
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Table 1. PIN DESCRIPTION
PIN FUNCTION
HSTL_CLK*,
HSTL_CLK** HSTL or LVDS Differential Inputs
LVPECL_CLK*,
LVPECL_CLK** LVPECL or LVDS Differential Inputs
CLK_SEL** LVCMOS/LVTTL Input CLK Select
OE** LVCMOS/LVTTL Output Enable
Q0 − Q8,
Q0 − Q8 HSTL Differential Outputs
VCC1 Positive Supply_Core
(3.0 V − 3.6 V)
VCC0 Positive Supply_HSTL Outputs
(1.6 V − 2.0 V)
GND Ground
EP The exposed pad (EP) on the QFN−32
package bottom is thermally connected to
the die for improved heat transfer out of the
package. THe exposed pad must be at-
tached to a heat−sinking conduit. The pad
is electrically connected to GND.
* Pins will default LOW when left open.
** Pins will default HIGH when left open.
Table 2. TRUTH TABLE
OE* CLK_SEL Q0 − Q8 Q0 − Q8
L L L H
L H L H
H L HSTL_CLK HSTL_CLK
H H LVPECL_CLK LVPECL_CLK
*The OE (Output Enable) signal is synchronized with the rising edge
of the HSTL_CLK and LVOCL_CLK signals.
0
1
Figure 3. Logic Diagram
CLK_SEL
HSTL_CLK
HSTL_CLK
LVPECL_CLK
LVPECL_CLK
OE
Q0−Q8 (HSTL)
Q0−Q8 (HSTL)
Q
D
9
9
VCCI
GND VCCO
Table 3. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor 75 k
Internal Input Pullup Resistor 37.5 k
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg Pb−Free Pkg
LQFP−32
QFN−32 Level 2
N/A Level 2
Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 478 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MC100EP809
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Table 4. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
VCC1 Core Power Supply GND = 0 V VCC0 = 1.6 to 2.0 V 4 V
VCC0 HSTL Output Power Supply GND = 0 V VCC1 = 3.0 to 3.6 V 4 V
VIInput Voltage GND = 0 V VI v VCC1 4 V
Iout Output Current Continuous
Surge 50
100 mA
mA
TAOperating Temperature Range 0 to +85 °C
Tstg Storage Temperature Range −65 to +150 °C
JA Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm LQFP−32
LQFP−32 80
55
°C/W
°C/W
JC Thermal Resistance (Junction−to−Case) Standard Board LQFP−32 12 to 17 °C/W
JA Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm QFN−32
QFN−32 31
27
°C/W
°C/W
JC Thermal Resistance (Junction−to−Case) 2S2P QFN−32 12 °C/W
Tsol Wave Solder Pb
Pb−Free 265
265 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
Table 5. LVPECL DC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V
Symbo
l
Characteristic
0°C 25°C 85°C
Uni
t
Min Typ Max Min Typ Max Min Typ Max
ICC Core Power Supply Current 75 95 115 75 95 115 75 95 115 mA
VIH Input HIGH Voltage (Single−Ended) VCCI −
1.165 VCCI −
0.88 VCCI −
1.165 VCCI −
0.88 VCCI −
1.165 VCCI −
0.88 V
VIL Input LOW Voltage (Single−Ended) VCCI −
1.945 VCCI −
1.6 VCCI −
1.945 VCCI −
1.6 VCCI −
1.945 VCCI −
1.6 V
VIHCMR Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 2) (Figure 5)
LVPECL_CLK/LVPECL_CLK 1.2 VCCI 1.2 VCCI 1.2 VCCI V
IIH Input HIGH Current −150 150 −150 150 −150 150 A
IIL Input LOW Current −150 150 −150 150 −150 150 A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
2. VIHCMR max varies 1:1 with VCCI. The VIHCMR range is referenced to the most positive side of the differential input signal.
MC100EP809
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Table 6. LVTTL/LVCMOS DC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V
Symbo
l
Characteristic
0°C 25°C 85°C
Uni
t
Min Typ Max Min Typ Max Min Typ Max
VIH Input HIGH Voltage 2.0 2.0 2.0 V
VIL Input LOW Voltage 0.8 0.8 0.8 V
IIH Input HIGH Current −150 150 −150 150 −150 150 A
IIL Input LOW Current −300 300 −300 300 −300 300 A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
Table 7. HSTL DC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V
Symbo
l
Characteristic
0°C 25°C 85°C
Uni
t
Min Typ Max Min Typ Max Min Typ Max
VOH Output HIGH Voltage (Note 3) 1.0 1.2 1.0 1.2 1.0 1.2 V
VOL Output LOW Voltage (Note 3) 0.1 0.4 0.1 0.4 0.1 0.4 V
VIH Input HIGH Voltage (Figure 6) VX +
0.1 1.6 VX +
0.1 1.6 VX +
0.1 1.6 V
VIL Input LOW Voltage (Figure 6) −0.3 VX −
0.1 −0.3 VX −
0.1 −0.3 VX −
0.1 V
VXHSTL Input Crossover Voltage 0.68 − 0.9 0.68 − 0.9 0.68 − 0.9 V
IIH Input HIGH Current −150 150 −150 150 −150 150 A
IIL Input LOW Current −300 300 −300 300 −300 300 A
VIHCMR Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 4)
HSTL_CLK/HSTL_CLK 0.6 VCCI
− 1.2 0.6 VCCI
− 1.2 0.6 VCCI
− 1.2 V
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
3. All outputs loaded with 50 to GND (Figure 7).
4. VIHCMR max varies 1:1 with VCCI. The VIHCMR range is referenced to the most positive side of the differential input signal.
MC100EP809
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Table 8. AC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V (Note 5)
Symbo
l
Characteristic
0°C 25°C 85°C
Uni
t
Min Typ Max Min Typ Max Min Typ Max
VOpp Differential Output Voltage fout < 100 MHz
(Figure 4) fout < 500 MHz
fout < 750 MHz
600
600
450
850
750
575
600
600
450
850
750
575
600
600
450
850
750
575 mV
mV
tPLH
tPHL Propagation Delay (Differential Configura-
tion) LVPECL_CLK to Q
HSTL_CLK to Q 680
690 800
830 930
990 700
700 820
850 950
1000 780
790 920
950 1070
1110 ps
ps
tskew Within−Device Skew (Note 6)
Device−to−Device Skew (Note 7) 15
100 50
200 15
100 50
200 15
100 50
200 ps
ps
tJITTER Random Clock Jitter (Figure 4) (RMS) 1.4 3.0 1.4 3.0 1.4 3.0 ps
VPP Input Swing (Differential Configuration)
(Note 8) (Figure 5) LVPECL
HSTL 200
200 200
200 200
200 mV
mV
tSOE Set Up Time (Note 9) 0.5 0.5 0.5 ns
tHOE Hold Time 0.5 0.5 0.5 ns
tr/tfOutput Rise/Fall Time
(20% − 80%) 350 600 350 450 600 350 600 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
5. Measured with 750 mV (L VPECL) source or 1 V (HSTL) source, 50% duty cycle clock source. All outputs loaded with 50 to GND (Figure 7).
6. Skew is measured between outputs under identical transitions and conditions on any one device.
7. Device−to−Device skew for identical transitions and conditions.
8. VPP is the Differential Input Voltage swing required to maintain AC characteristics listed herein.
9. OE Set Up Time is defined with respect to the rising edge of the clock. OE High−to−Low transition ensures outputs remain disabled during
the next clock cycle. OE Low−to−High transition enables normal operation of the next input clock (Figure 9).
0
100
200
300
400
500
600
700
800
900
0 100 200 300 400 500 600 700 800 900 1000
Figure 4. Output Frequency (FOUT) versus Output Voltage (VOPP) and Random Clock Jitter (tJITTER)
2
3
4
5
6
7
8
VOPP (mV)
tJITTER ps (RMS)
9
1
FREQUENCY (MHz)
VOPP
RMS JITTER
MC100EP809
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Figure 5. LVPECL Differential Input Levels
GROUND
HSTL OUTPUT Q
Q
50 50
VIH(DIFF)
VIL(DIFF)
GND
VCCI(LVPECL)
VIH(DIFF)
VIL(DIFF)
GND
VCCO(HSTL)
Figure 6. HSTL Differential Input Levels
Figure 7. HSTL Output Termination and AC Test Reference
VIHCMR
VPP
VPP
VX
Z = 50
CLK
CLK
OE
Q
Q
CLK/CLK
D.C. Bias*
Figure 8. Single−Ended CLK/CLK Input Configuration
*Must be CLK/CLK common mode voltage: ((VIH + VIL)/2).
Figure 9. Output Enable (OE) Timing Diagram
V
CCI
MC100EP809
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ORDERING INFORMATION
Device Package Shipping†
MC100EP809FAG LQFP−32
(Pb−Free) 250 Units / Tray
MC100EP809FAR2G LQFP−32
(Pb−Free) 2000 / Tape & Reel
MC100EP809MNG QFN32
(Pb−Free) 74 Units / Rail
MC100EP809MNR4G QFN32
(Pb−Free) 1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D − ECL Clock Distribution Techniques
AN1406/D − Designing with PECL (ECL at +5.0 V)
AN1503/D −ECLinPSt I/O SPiCE Modeling Kit
AN1504/D − Metastability and the ECLinPS Family
AN1568/D − Interfacing Between LVDS and ECL
AN1672/D − The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
MC100EP809
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PACKAGE DIMENSIONS
ÉÉ
ÉÉ
ÉÉ
DETAIL Y
A
S1
VB
1
8
9
17
25
32
AE
AE
P
DETAIL Y
BASE
N
J
DF
METAL
SECTION AE−AE
G
SEATING
PLANE
R
Q_
WK
X
0.250 (0.010)
GAUGE PLANE
E
C
H
DETAIL AD
DETAIL AD
A1
B1 V1
4X
S
4X
9
−T−
−Z−
−U−
T-U0.20 (0.008) ZAC
T-U0.20 (0.008) ZAB
0.10 (0.004) AC
−AC−
−AB−
M_
8X
−T−, −U−, −Z−
T-U
M
0.20 (0.008) ZAC
32 LEAD LQFP
CASE 873A−02
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DATUM PLANE −AB− IS LOCATED AT
BOTTOM OF LEAD AND IS COINCIDENT
WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DA TUMS −T−, −U−, AND −Z− TO BE
DETERMINED AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE
MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL NOT CAUSE THE
D DIMENSION TO EXCEED 0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY
VARY FROM DEPICTION.
DIM
A
MIN MAX MIN MAX
INCHES
7.000 BSC 0.276 BSC
MILLIMETERS
B7.000 BSC 0.276 BSC
C1.400 1.600 0.055 0.063
D0.300 0.450 0.012 0.018
E1.350 1.450 0.053 0.057
F0.300 0.400 0.012 0.016
G0.800 BSC 0.031 BSC
H0.050 0.150 0.002 0.006
J0.090 0.200 0.004 0.008
K0.450 0.750 0.018 0.030
M12 REF 12 REF
N0.090 0.160 0.004 0.006
P0.400 BSC 0.016 BSC
Q1 5 1 5
R0.150 0.250 0.006 0.010
V9.000 BSC 0.354 BSC
V1 4.500 BSC 0.177 BSC
__
___ _
B1 3.500 BSC 0.138 BSC
A1 3.500 BSC 0.138 BSC
S9.000 BSC 0.354 BSC
S1 4.500 BSC 0.177 BSC
W0.200 REF 0.008 REF
X1.000 REF 0.039 REF
MC100EP809
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10
PACKAGE DIMENSIONS
QFN32 5x5, 0.5P
CASE 488AM
ISSUE A
SEATING
NOTE 4
K
0.15 C
(A3)
A
A1
D2
b
1
9
17
32
E2
32X
8
L
32X
BOTTOM VIEW
TOP VIEW
SIDE VIEW
DA
B
E
0.15 C
ÉÉ
ÉÉ
PIN ONE
LOCATION
0.10 C
0.08 C C
25
e
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PLANE
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.50
3.35
0.30
3.35
32X
0.63
32X
5.30
5.30
L1
DETAIL A
L
ALTERNATE TERMINAL
CONSTRUCTIONS
L
ÉÉ
ÉÉ
ÇÇ
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTION
DETAIL B
DET AIL A
DIM
AMIN
MILLIMETERS
0.80
A1 −−−
A3 0.20 REF
b0.18
D5.00 BSC
D2 2.95
E5.00 BSC
2.95
E2
e0.50 BSC
0.30
L
K0.20
1.00
0.05
0.30
3.25
3.25
0.50
−−−
MAX
−−−
L1 0.15
e/2 NOTE 3
PITCH DIMENSION: MILLIMETERS
RECOMMENDED
A
M
0.10 BC
M
0.05 C
P
UBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
MC100EP809/D
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
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Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your loc
al
Sales Representative
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specifically disclaims any and all l iabilit y, including without limitation special, consequential or i ncident al d amages. “Typical” parameters which may be provided in S CILLC d a ta s heet s
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC an d it s officer s, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
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