78Q8430 10/100 Ethernet
MAC and PHY
Simplifying System Integration TM DATA SHEET
March 2009
Rev. 1.2 © 2009 Teridian Semiconductor Co rpora ti on 1
DESCRIPTION
The Teridian 78Q8 430 is a 10/100 Fast E thernet
controller sup porting multi-media offload. The
device is optimi zed f or host processor offloading
and throughput enhancements for demanding
multi-media applicat i ons found in Set To p Box,
IP Video and Broadband Media Appliance
applications. The 78Q8430 seamlessly
interfaces to non-PCI processors throug h a
simplified pseudo S RA M-like Host Bus Interface
supporting 32/ 16/8 bit data bus widths.
Supported features include IEEE802.3x flow
control and full IEEE802.3 and 802.3u standards
compliance.
Supporting 10Base-T and 100Base-TX, the
transceiver prov i des A uto MDI-X cable
cross-over correcti on, AUTO Negotiat i on, Link
Configuration and full/half duplex s upport with
full duplex flow control. The line interface
requires only a dual 1:1 isolation transformer.
Numerous pack et processing and IP address
resolution cont rol functions are inco rporated,
including an extensive set of Error Moni toring,
Reporting and T roubleshooting features. The
78Q8430 provi des opt imal 10/100 Ethe r net
connectivity in demanding video stre am ing and
mixed-media application s.
BENEFITS
• Support for IEEE-802.3, IEEE-802.3u and
IEEE-802.3-2000 Annex 31.B
• Low host CPU utilization/overhead with
minimal software driver overhead and small
driver memory space requirements
• Improved packet processing, low latency and
low host CPU utilization
• Highest performance streaming Video over IP
• Optimized performance in mixed media
application such as video, data and voice
• Ease of use, faster development cycles, high
throughput
• Optimized power conservation with automatic
turn on when needed
• Reduced host CPU utilization and overhead
• Improved packet processing
• Optimized performance in mixed media
applications
FEATURES
• Single chip 10Base-T/100Base-TX
IEEE-802.3 compliant MAC and PHY
Adaptive 32 kB SRAM FIFO memory
allocation between Tx and Rx paths
Queue independent user settable water
marks
Per queue status indication
• Address Resolution Controller (ARC)
Multiple perfect address filtering: 8 default
(max 12)
Wildcard address filtering, individual,
multicast and broadcast address
recognition and filtering
Positive/negative filtering and promiscuous
mode
• 64 kB JUMBO packet support
• QoS: 4 Transmit priority levels
• Non-PCI pseudo-SRAM Host Bus Interface
8-bit, 16-bit and 32-bit bus width
Big/little endian support for 16-bit/32-bit bus
widths
Asynchronous (100 MHz) and synchronous
(50 MHz) bus clock support
• Low power and flexible power supply
management
Power down/save
Wake on LAN (Magic Packet™, OnNow
packet)
Link status change
• Traffic Offload Engine Functionality
Transfer frame: APF & ICMP Echo
IP Firewall configuration: drop frames on
source IP address
IP Checksum
• Available in an industrial temperature range
(-40 °C to +85 °C)
• RoHS compliant (6/6) lead-free package
APPLICATIONS
• Satellite, cable and IPTV Set Top B oxes
• Multi Media Resid ential Gateways
• High Definitio n 1080p/1080i DTVs
• IP-PVR and video distribut ion systems
• Digital Video Recorders/P l ayers
• Routers and IADs
• Video over IP system, IP-PBX
• IP Security Cameras / PVRs
• Low latency industrial automation
78Q8430 Data Sheet DS_8430_001
2 Teridian Propri etary and Confidenti al Rev. 1.2
Table of Contents
1 Introduction ......................................................................................................................................... 7
1.1 Systems Application s ................................................................................................................... 7
1.2 System Level Appli cat ion Information .......................................................................................... 8
1.2.1 Set Top Box Applicatio n .................................................................................................. 8
1.2.2 IP Security Application ..................................................................................................... 8
1.2.3 IP PBX Application ........................................................................................................... 9
1.3 Overview ...................................................................................................................................... 9
1.4 Application Environm ents .......................................................................................................... 10
1.5 Supply Voltages ......................................................................................................................... 10
1.6 Power Management ................................................................................................................... 10
2 Pinout ................................................................................................................................................. 11
3 Pin Description .................................................................................................................................. 12
3.1 Pin Legend ................................................................................................................................. 12
3.2 Pin Descriptions ......................................................................................................................... 12
3.2.1 Clock Pins ...................................................................................................................... 12
3.2.2 Media Dependent Int erface (MDI) Pin s ......................................................................... 13
3.2.3 LED Display (PHY) Pins ................................................................................................ 13
3.2.4 EEPROM Pins ............................................................................................................... 13
3.2.5 GBI Data Pins ................................................................................................................ 14
3.2.6 GBI Address Pins .......................................................................................................... 15
3.2.7 GBI Control Pins ............................................................................................................ 15
3.2.8 Mode Pins ...................................................................................................................... 16
3.2.9 JTAG Pins ...................................................................................................................... 16
3.2.10 Power Pins ..................................................................................................................... 17
4 Electrical Specification ..................................................................................................................... 18
4.1 Absolute Maximum Ratings ....................................................................................................... 18
4.2 Recommended Operation Con dition s ........................................................................................ 18
4.3 DC Characterist ic s ..................................................................................................................... 18
4.4 Digital I/O Characteristics .......................................................................................................... 19
4.5 Analog Electrical Characteristics ............................................................................................... 19
4.5.1 100Base-TX Transmitter ................................................................................................ 19
4.5.2 100Base-TX Transmitter (Informative) .......................................................................... 19
4.5.3 100Base-TX Receiver .................................................................................................... 20
4.5.4 10Base-T Transmitter .................................................................................................... 20
4.5.5 10Base-T Transmitter (Informative) ............................................................................... 20
4.5.6 10Base-T Receiver ........................................................................................................ 21
5 Host Interface Timing Specification ................................................................................................ 22
5.1 Host Interface ............................................................................................................................. 22
5.1.1 Synchronous Mode Timing ............................................................................................ 23
5.1.2 Bus Clock Timing ........................................................................................................... 24
5.1.3 Reset Timing .................................................................................................................. 24
6 Functional Description ..................................................................................................................... 25
6.1 Internal Block Diagrams ............................................................................................................. 25
6.1.1 Internal Digital Block ...................................................................................................... 25
6.1.2 Internal PHY ................................................................................................................... 25
6.2 Data Queuing ............................................................................................................................. 26
6.3 Host Interface ............................................................................................................................. 27
6.3.1 Reading Receive Data ................................................................................................... 27
6.3.2 Writing Transmit Data .................................................................................................... 27
6.3.3 DMA Slave Mode Access .............................................................................................. 29
6.4 Snoop Mode Access .................................................................................................................. 29
6.5 Water Marking ............................................................................................................................ 30
6.5.1 Interrupt Watermark ....................................................................................................... 30
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 3
6.5.2 PAUSE Watermark ........................................................................................................ 30
6.5.3 Headroom Watermark ................................................................................................... 30
6.6 Counters ..................................................................................................................................... 30
6.6.1 Summary of Counters .................................................................................................... 30
6.6.2 Reading and Setti ng Counter Values ............................................................................ 31
6.6.3 Precision Counting ......................................................................................................... 32
6.6.4 Rollover Interrupts ......................................................................................................... 32
6.7 Packet Classification .................................................................................................................. 32
6.7.1 Address Filtering ............................................................................................................ 34
6.7.2 Configuring the CAM ..................................................................................................... 38
6.7.3 Frame Format ................................................................................................................ 39
6.7.4 Default CAM Rule Summ ary .......................................................................................... 39
6.8 Timers ........................................................................................................................................ 44
6.8.1 PAUSE Timer ................................................................................................................. 44
6.8.2 HNR Timer ..................................................................................................................... 44
6.8.3 Interrupt Delay Timer ..................................................................................................... 44
6.9 EEPROM Controller ................................................................................................................... 44
6.10 Ethernet MAC ............................................................................................................................ 44
6.10.1 MAC Transmit Block ...................................................................................................... 44
6.10.2 MAC Receive Block ....................................................................................................... 45
6.10.3 MAC Control Regi ster .................................................................................................... 45
6.10.4 Transmitt ing a Fram e ..................................................................................................... 45
6.10.5 IEEE 802.3 Transmit Protocols ...................................................................................... 45
6.10.6 Transmit O peration ........................................................................................................ 46
6.10.7 Receiving a Frame ......................................................................................................... 46
6.10.8 Strip Padding/FCS ......................................................................................................... 47
6.11 MAC Error R eporting ................................................................................................................. 47
6.11.1 MAC Transmit Errors ..................................................................................................... 47
6.11.2 MAC Re cei ve Errors ...................................................................................................... 48
6.12 PHY Operat i ons ......................................................................................................................... 49
6.12.1 Automat ic MDI/MDIX Cable Crossover Configurat i on ................................................... 49
6.12.2 100Base-TX Transmit .................................................................................................... 49
6.12.3 100Base-TX Receive ..................................................................................................... 49
6.12.4 10Base-T Tra nsmit ........................................................................................................ 49
6.12.5 10Base-T Receive ......................................................................................................... 50
6.12.6 SQE Test ....................................................................................................................... 50
6.12.7 Polarity Correction ......................................................................................................... 50
6.12.8 Natural Loopback ........................................................................................................... 50
6.12.9 Auto-Negotiation ............................................................................................................ 51
6.12.10 LED Indicators .............................................................................................................. 51
6.12.11 PHY Interrupts .............................................................................................................. 51
6.12.12 Internal Clock PLL ........................................................................................................ 51
7 Register Descriptions ....................................................................................................................... 52
7.1 Register Overview ...................................................................................................................... 52
7.2 QUE Register Overview ............................................................................................................. 53
7.3 CTL Register Overview .............................................................................................................. 54
7.4 Snoop Address Space Overview ............................................................................................... 55
7.5 QUE Registers ........................................................................................................................... 56
7.5.1 Packet Control Word Register ....................................................................................... 56
7.5.2 Packet Size Register ..................................................................................................... 56
7.5.3 Setup Transmit Data Regi st er ....................................................................................... 57
7.5.4 Transmit Data Register .................................................................................................. 57
7.5.5 Receive Data Regist er ................................................................................................... 57
7.5.6 QUE First/Last Register ................................................................................................. 58
7.5.7 QUE Status Register ..................................................................................................... 58
7.6 CTL Registers ............................................................................................................................ 59
7.6.1 DMA Control and Stat us Register .................................................................................. 59
7.6.2 Receive Packet Status Register .................................................................................... 59
78Q8430 Data Sheet DS_8430_001
4 Rev. 1.2
7.6.3 Transmit Packet Status Register ................................................................................... 59
7.6.4 Transmit Producer Status .............................................................................................. 60
7.6.5 Receive Producer St atus ............................................................................................... 60
7.6.6 Revision ID ..................................................................................................................... 61
7.6.7 Configuration .................................................................................................................. 61
7.6.8 Receive to Transmit T ransfer Register .......................................................................... 61
7.6.9 Frame Disposition Register ........................................................................................... 61
7.6.10 Receive FIRST BLOCK Status Register ....................................................................... 61
7.6.11 Receive Data Status Regi ster ........................................................................................ 62
7.6.12 BIST Control Regi ster .................................................................................................... 62
7.6.13 BIST Bypass Mode Data Register ................................................................................. 63
7.6.14 Stati on M anagement Data Regist er .............................................................................. 63
7.6.15 Station M anagement Control and A ddress Register ..................................................... 63
7.6.16 PROM Data Register ..................................................................................................... 63
7.6.17 PROM Cont rol Register ................................................................................................. 64
7.6.18 MAC Control Regi ster .................................................................................................... 64
7.6.19 Count Data Registe r ...................................................................................................... 65
7.6.20 Counter Control Registe r ............................................................................................... 65
7.6.21 Counter Management Reg ist er ...................................................................................... 66
7.6.22 Snoop Cont rol Register ................................................................................................. 66
7.6.23 Interrupt Delay Count Register ...................................................................................... 66
7.6.24 Pause Delay Count Register ......................................................................................... 66
7.6.25 Host Not Responding Count Register ........................................................................... 67
7.6.26 Wake Up Status Register .............................................................................................. 67
7.6.27 Water Mark Values Register .......................................................................................... 67
7.6.28 Power Management Capabilit ies ................................................................................... 67
7.6.29 Power Management Control and S tat us Regist er ......................................................... 68
7.6.30 CAM Addr ess Register .................................................................................................. 68
7.6.31 Rule Mat ch Register ...................................................................................................... 69
7.6.32 Rule Control Regi ster .................................................................................................... 69
7.6.33 Que Stat us Interrupt Register ........................................................................................ 70
7.6.34 Que Stat us Mask Register ............................................................................................. 70
7.6.35 Overflow/Underrun Interrupt Register ............................................................................ 71
7.6.36 Overflow/ Und errun Ma sk Registe r ................................................................................. 71
7.6.37 Transmit RMON Interrupt Register ................................................................................ 71
7.6.38 Transmit RMON Mask Register ..................................................................................... 72
7.6.39 Receive RMON Interrupt Register ................................................................................. 72
7.6.40 Receive RMON Mask Register ...................................................................................... 72
7.6.41 Host I nterrupt Register ................................................................................................... 72
7.6.42 Host Interrupt Mas k Register ......................................................................................... 73
7.7 PHY Management Regi st ers ..................................................................................................... 74
7.7.1 PHY Register Overview ................................................................................................. 74
7.7.2 PHY Control Register – MR0 ......................................................................................... 75
7.7.3 PHY Status Register – MR1 .......................................................................................... 76
7.7.4 PHY Identifier Registers – MR2, MR3 ........................................................................... 77
7.7.5 PHY Auto-Negotiation Advertisement Registers – MR4 ............................................... 77
7.7.6 PHY Auto-Negotiation Line Part ner A bi l ity Register – MR5 .......................................... 78
7.7.7 PHY Auto-Negotiation Expansion Register – MR6 ........................................................ 78
7.7.8 PHY Vendor Specific Register – MR16 ......................................................................... 79
7.7.9 PHY Interrupt Control / Status Register – MR17 ........................................................... 80
7.7.10 PHY Tran sceiver Control Regist er – MR19 ................................................................... 80
7.7.11 PHY Diagnostic Register – MR18 .................................................................................. 81
7.7.12 PHY LED Co nfiguration Registe r – MR23 ..................................................................... 81
7.7.13 PHY MDI / MDIX Control Register – MR24 ................................................................... 82
8 Isolation Transformers ..................................................................................................................... 83
9 Reference Crystal ............................................................................................................................. 83
10 System Bus Interface Schematic .................................................................................................... 84
11 Line Interface Schematic .................................................................................................................. 85
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 5
12 Package Me chan ical Drawing (100-pin LQFP) ............................................................................... 86
13 Ordering Information ........................................................................................................................ 87
14 Related Documentation .................................................................................................................... 87
15 Contact Informatio n .......................................................................................................................... 87
Tables
Table 1: Pin Legend .................................................................................................................................... 12
Table 2: Clock Pin De sc ri ptions .................................................................................................................. 12
Table 3: MDI Pin Des criptions ..................................................................................................................... 13
Table 4: LED Pin Des criptions .................................................................................................................... 13
Table 5: EEPROM Interface Pin Descriptions ............................................................................................ 13
Table 6: GBI Data Pi n Descriptions ............................................................................................................ 14
Table 7: GBI Addre ss Pin Descriptions ....................................................................................................... 15
Table 8: GBI Contr ol P i n Descriptions ........................................................................................................ 15
Table 9: Chip Mode Pin Descriptions .......................................................................................................... 16
Table 10: JTAG Pin Descriptions ................................................................................................................ 16
Table 11: Power Pin Descriptions ............................................................................................................... 17
Table 12: Absolute Maximum Ratings ........................................................................................................ 18
Table 13: Recomm ended Operating C onditions ......................................................................................... 18
Table 14: DC Characteristics ...................................................................................................................... 18
Table 15: Digital I/O Characteristics ........................................................................................................... 19
Table 16: MII 100Base-TX Transmit Timing ............................................................................................... 19
Table 17: MII 100Base-TX Transmitter (Informative) ................................................................................. 19
Table 18: MII 100Base-TX Receiver Timing ............................................................................................... 20
Table 19: MII 10Bas e-T Transmitter Timing ............................................................................................... 20
Table 20: MII 10Bas e-T Transmitter (Informative) ...................................................................................... 20
Table 21: MII 10Bas e-T Re ceive Timing ..................................................................................................... 21
Table 22: Transmit Data Buffer Example .................................................................................................... 28
Table 23: Counter S um mary ....................................................................................................................... 30
Table 24: CAM Rules A ssociated with Unicast Filter Bytes ........................................................................ 34
Table 25: CAM Rules A ssociated with M ul ticast Filter Byt es ..................................................................... 36
Table 26: Control Logic Actions .................................................................................................................. 38
Table 27: RCR Matc h Control ..................................................................................................................... 39
Table 28: Ethernet Frame for Classification ................................................................................................ 39
Table 29: Process Destination Address Rules ............................................................................................ 40
Table 30: Process Sou rce Address Rules .................................................................................................. 42
Table 31: Process Length/Type, MAC Control Frames and St art IP Header Checksum Rules ................. 42
Table 32: Process Rules for OnNow Pa cket ............................................................................................... 43
Table 33: Process Rules for Magic Pac ket ................................................................................................. 43
Table 34: PHY Register Group ................................................................................................................... 74
Table 35: Isolation T ransformers ................................................................................................................ 83
Table 36: Reference Crystal ....................................................................................................................... 83
Table 37: 78Q8430 Order Numbers and Packaging Marks ........................................................................ 87
78Q8430 Data Sheet DS_8430_001
6 Rev. 1.2
Figures
Figure 1: 78Q8430 B lock Diagram ................................................................................................................ 7
Figure 2: Set Top Box Diagram .................................................................................................................... 8
Figure 3: Network Cameras Diagra m ........................................................................................................... 8
Figure 4: Typical FX O VoIP Application ........................................................................................................ 9
Figure 5: Device B l ock Diagram ................................................................................................................... 9
Figure 6: GBI B us B l ock Diagram ............................................................................................................... 10
Figure 7: Pinout ........................................................................................................................................... 11
Figure 8: Host Interface Timing Diagram .................................................................................................... 22
Figure 9: Host Bus Output Timing Diagram ................................................................................................ 23
Figure 10: Host B us I nput Timing Diagram ................................................................................................. 23
Figure 11: Bus Cloc k Ti m i ng ....................................................................................................................... 24
Figure 12: Internal Digital Bl ock Diagra m ................................................................................................... 25
Figure 13: Internal PHY Block Diagram ...................................................................................................... 26
Figure 14: Classification Architecture ......................................................................................................... 33
Figure 15: System Bus Interface Schematic ............................................................................................... 84
Figure 16: Line Interface Schemati c ........................................................................................................... 85
Figure 17: LQFP Drawing ........................................................................................................................... 86
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 7
1 Introduction
The Teridian 78Q8 430 is a single chip 10B ase -T/100Base-TX capable Fast Ethernet Media Acce ss
Controller (M A C) and Physical Layer (P HY ) transceiver. The device is optimized for video application s,
such as the Set Top B ox (STB), and easil y interfaces to availabl e STB core processors, such as the
STi5100, STi5516, STi5514, ARM™ and Intel® based pro cessors. The 78Q843 0 is compliant with
applicable IEE E-802.3 standards. MA C and PHY configuration and status regi sters are provided a s
specified by IEEE-802.3u.
The 78Q8430 operates over Category-5 Unshielded Twisted Pair (Cat-5 UTP) cabling in 100Base-TX
applications and over Cat-3 UTP in 10Base-T applications requiring only a dual 1:1 isolation transformer
interface to the copper media.
The Ethernet MAC section makes use of a 32 kB deep on-chip SRAM FIFO packet memory to adaptively buffer
transmit and receive data. SRAM memory can be dynamically allocated to either the transmit queues or the
receive queues as required to optimize throughput.
The host processor accesses the FIFO(s) using a simple asynchronous pseudo-SRAM like host bus interface.
A 32 bit wide bus is provided; the bus width can be pin-configured for 8-bit, 16-bit or 32-bit bus width at boot-up.
Big endian, little endian and mixed endian options are available in 32-bit operation; little endian is available for
16-bit operation. Different End-in variations are supported through internal circuitry with minimal user
intervention required.
The MAC interface logic may assert MEMWAIT during bus transactions, requesting wait states from the host
while critical internal data transfer completes. The MAC provides both half duplex and full duplex operation, as
well as support for full duplex flow control. Complete, portable device drivers for Linux®, OS20 and VxWorks®
1.1 Systems Applications
are available.
The 78Q8430 operat es from a single 3.3 V supply . Power down modes and power saving modes are
available. The 78Q8430 defaults to us e an on-chip crystal oscillator. In t hi s m ode, a 25 MHz reference
crystal is connected between the X T LP and XTLN pins. Alt ernat i vely, an externally generat ed 25 MHz
clock can be conne ct ed to the XTLP pin. The chip will automatically conf i gure itself to use t he external
clock. In this mode of operation, a cry st al is not required.
Figure 1 present s an overview of the 78 Q 8430 in a block diagram.
TERIDIAN
78Q8430
Single Chip
10/100 Ethernet
Controller
8-bit/16-bit/32-bit
System Bus
Configuration
EEPROM Interface
(Optional)
JTAG Interface
LED
Link (Programmable)
LED
Activity (Programmable)
RJ45
1:1
Transformer
CAT 5
Cable
Figure 1: 78Q8430 Block Diagram
78Q8430 Data Sheet DS_8430_001
8 Rev. 1.2
1.2 System Level Applicati on I nformation
This section provide s an overview of syst em l evel applications in some typical hi gh-volume consum er
equipment.
1.2.1 Set Top Box Application
Figure 2 shows a t ypical applicati on diagram for a set top box.
Figure 2: Set Top Box Diagram
1.2.2 IP Security Application
Figure 3 shows a t ypical applicati on diagram for an IPTV sec urity camera appli cat i on.
Figure 3: Network Cameras Diagram
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 9
1.2.3 IP PBX Application
Figure 4 shows a t ypical applicati on diagram for an IP P BX application.
Figure 4: Typical FXO VoIP Application
1.3 Overview
The 78Q8430 is divided into four sect ions, as shown in Figure 5.
• Generic Bus Interf ace (GBI) Control Layer
• Queue Memory Lay er
• Ethernet Media Acce ss Control (MAC) Layer
• Ethernet Physical (P HY) Layer
CAM
RMON
GBI Bus Layer Queue Memory Layer MAC Layer PHY Layer
GBI
Access
Logic
GBI
DMA Slave
Mode Logic
QUEUE
SRAM
Pause/
HNR
Timers
Snoop
Controller
QUE
Controller
QUE Write
Logic
QUE Write
Logic
QUE Read
Logic
Memory
Manager
CTL
Controller
Packet
Classify
MAC Write
Logic
MAC Read
Logic
Flow
Control MAC TX
Logic
TX
FIFO
RX
FIFO
MAC RX
Logic
MAC Control
& Status
Registers
TX
PCS
RX
PCS
PMD
SMI Control
& Status
Register
QUE Write
Logic
QUE Write
Logic
Figure 5: Devi ce Bl o ck Diagram
78Q8430
10/100 MAC/PHY
78Q8430
10/100 MAC/PHY
78Q8430 Data Sheet DS_8430_001
10 Rev. 1.2
1.4 Application Environments
This section provide s an overview of the application environments such as the STMicroelectronics and
Embest ARM9™Figure 6 processors, for which the 78Q8430 provides a seamless interface. shows a
simple application diagram for a design using the GBI base d 10/100-Mbps Ethe rnet Controller. By
providing a direct connection to the GBI bus, applications requiring Ethernet network access can be
realized with a high degree of integrat i on. The figure shows t he processor and the Ethernet controller
with connected address and data buse s. T his connection can be either on the motherboard, or via an
expansion module. The GBI Controller controls the address and data and the system control signals.
78Q8430
10/100 Mbps
Ethernet
Controller
and PHY
GBI
EEPROM
or ROM
8/16/32-bit Bus
1:1 Transformer
And RJ45
Connector
Figure 6: GBI Bus Blo ck Diagram
Figure 6 shows the components that are likely to be used with t he 10/100-Mbps Et hernet Controller. The
integrated PHY is designed to directly co nnect to an integrated 1:1 transformer and RJ-45 connector,
thereby providi ng a m i ni mum parts solution.
1.5 Supply Voltages
The 78Q8430 requires a single 3.3 V (+/ -5%) supply voltage. No external components are required to
generate on-chip bias voltages and currents. High accur acy is maintained thr ough a closed-loop t rim m ed
biasing network. O n-chip power converters generate 1. 8 V power for core digital logic and memory
blocks. The volt age regulator is not affected by the pow er-do wn mode.
1.6 Power Management
The 78Q8430 supp orts both normal and power-saving modes. When the GBI bus is active, it can be in
normal mode or Pow er M anagement low-power modes.
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 11
2 Pinout
The 78Q8430 is av ai l able in a 14x14 mm 100-pin LQFP package.
78Q8430
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
1
2
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
GND
TXP
RXP
GND
VCC
GND
BOOTSZ0
GND
TMS
DATA26
DATA25
DATA24
VCC
GND
GND
ADDR7
LED0
PROMDO
DATA27
DATA28
DATA20
DATA18
VCC
VCC
GND
VCC
TDI
TRST
TCLK
RESET
VCC
ADDR1
ADDR0
WR
OE
MEMWAIT
BUSCLK
CS
ADDR2
VCC
ADDR3
ADDR4
ADDR5
ADDR8
ADDR9
ADDR6
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DATA23
DATA22
DATA21
DATA16
VCC
VCC
VCC
BOOTSZ1
TXN
RXN
LED1
GND
XTLN
XTLP
VCC
CLKMODE
WAITMODE
BUSMODE
VCC
TDO
ENDIAN1
ENDIAN0
GND
PROMDI
VCC
GND
DATA31
PME
INT
PROMCS
DATA30
DATA29
PROMCLK
GND
DATA17
DATA19
GND
GND
49
Figure 7: Pinout
78Q8430 Data Sheet DS_8430_001
12 Rev. 1.2
3 Pin Descri ption
3.1 Pin Legend
Table 1 lists the di fferent pin types found on the 78Q8430 device. The Type field of the pin description
tables refers to one of these types.
Table 1: Pin Legend
Type Description
A Analog
IU TTL-level Input, with Pull-up
IS TTL-level Input, with Schmitt Trigger
O TTL-level Output
OD TTL-level Output (Open Drain)
S Supply
I TTL-level Input
ID TTL-level Input, with Pull-down
B TTL-level Bidirectional Pin
OZ TTL-level Output (Trist ate)
G Ground
3.2 Pin Descriptions
The pin descripti ons in the following t abl es are grouped by interf ace. A pin number, type specification per
Table 2 and a f unct i onal description is provided for each pin on the 78Q8430 device.
3.2.1 Clock Pins
Table 2: Clock Pin Descriptions
Signal
Pin Number
Type
Description
XTLP 87 A Crystal Positive/Negative
To use the internal o scillator, connect a 25 MHz crystal across
XTLP and XTLN. To use of an external clock, XTLN is grounded
and XTLP is driven wit h a 25 MHz clock.
Provides timing ref erence for all media dependant int erface
operations. An i nternal PLL is used to multiply this clock by four
for use as the main sy st em clock in internal clo ck mode.
XTLN 88
BUSCLK 15 I Peripheral Clock
The source for the m ain system clock in external clock mode. In
synchronous bus mode, all host bu s sig nal s are assumed to be
synchronous t o this clock.
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 13
3.2.2 Media Dependent Interface (MDI) Pins
Table 3: MDI Pin Descriptions
Signal Pin Number Type Description
TXP 97 A Transmit Output Positive/Negative
Transmitter out puts for both 10BASE-T and 100BAS E-TX.
MDI-X Mode: Receive Input Positive/ Negat i ve
Receiver inputs for both 10BASE-T and 100B ASE-TX.
TXN 98 A
RXP 94 A Receive Input Positive/Negative
Receiver inputs for both 10BASE-T and 100B ASE-TX.
MDI-X Mode: Transmit Output Positive/Negative
Transmitter out puts for both 10BASE-T and 100BASE- TX.
RXN
93
A
3.2.3 LED Display (PHY) Pins
The LED pins use standard logic driver s. They output a logic low when the LED is meant to be on and
are tri-state w hen i t is meant to be off. The LED cathode should be connected to the out put pin and a
series resistor f rom the power supply co nnected to the LED anode.
Table 4: LED Pin Descriptions
Signal
Pin Number
Type
Description
LED0 90 OZ PHY display LED0 (Link OK)
The default for LE D0 is Link OK (LED is on for link established).
LED1 92 OZ PHY display LED1 (Activity)
The default for LE D1 is Link Activity (LED blinks for Rx or Tx data
transferred).
3.2.4 EEPROM Pins
Table 5: EEPROM Interface Pin Descriptions
Signal Pin Number Type Description
PROM_CS 75 O EEPROM Chip Select
Used to frame t rans m i ssions to and fro m an external
EEPROM.
PROM_CLK 74 O EEPROM Clock
Clock for transmitting to and from an external EEPRO M /ROM.
This is compati bl e wit h the slowest comm ercial parts, whic h
specify a maximum frequency of 1 MHz.
PROM_DI 77 I EEPROM Data In
Data line for transmitting from the external EEP ROM to the
controller. Must be high with no EEPROM present.
PROM_DO 76 OZ EEPROM Data Out
Transfers data from the controller to an external
EEPROM/ROM.
78Q8430 Data Sheet DS_8430_001
14 Rev. 1.2
3.2.5 GBI Data Pins
Table 6: GBI Data Pin Descriptions
Signal Pin Number Type Description
DATA31 69 B Data Bus DATA[31:0]
Bi-directional host bus data. The BOOTSZ pins determi ne how
many of these are actually used. The OE input wil l di sable the
output drivers to prevent bus collisions.
DATA30 68
DATA29 67
DATA28 66
DATA27 65
DATA26 64
DATA25 63
DATA24 62
DATA23 59
DATA22 58
DATA21 57
DATA20 56
DATA19 55
DATA18 54
DATA17 53
DATA16 52
DATA15 49
DATA14 48
DATA13 47
DATA12 46
DATA11 45
DATA10 42
DATA9 41
DATA8 40
DATA7 39
DATA6 38
DATA5 33
DATA4 32
DATA3 31
DATA2 30
DATA1 29
DATA0 28
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 15
3.2.6 GBI Address Pins
Table 7: GBI Address Pin Descriptions
Signal Pin Number Type Description
ADDR9 25 I Address B us
The address lines are required to be stable for the entire duration
of a CS cycle. In synchronous bus mode, the address pins are
sampled on the f irst rising edge of BUSCLK that CS is asse rt ed
low. In asynchronous bus mode, the address pins are sampled as
soon as the falling edge of CS is synchronized to the int ernal
system clo ck.
In 32-bit bus mode, ADDR[1:0] are ignored. In 16-bit bus mod e,
ADDR[0] is ignored. In 8-bit bus mode, al l A DDR bits are used to
reference a register byte.
ADDR8 24 I
ADDR7 23 I
ADDR6 22 I
ADDR5 21 I
ADDR4 20 I
ADDR3 19 I
ADDR2 18 I
ADDR1 9 I
ADDR0 10 I
3.2.7 GBI Control Pins
Table 8: GBI Control Pin Descri ptions
Signal
Pin Number
Type
Description
RESET 7 I Reset (active low)
Referred to as hardware reset. Causes all 78Q8430 outputs to
enter a high-impedance state, st ops all current opera tions and
initializes registers.
CS 16 I Chip S elect (activ e low)
The Processor asserts this signal to initiate a read or write
operation.
WR 11 I Write Enable (active low)
The Processor asserts WR to indicate a write operation.
OE 12 I Output Enable (active low)
The Processor asserts OE to enable the 78Q8430 data drivers
during a read cycle.
MEMWAIT 13 OZ Memory Wait
During a bus cycle the 78Q8430 assert s M E M WA IT to indicate
that it is not ready to drive or receive val i d data on the DATA
lines. The polarity i s dependent on the WAITM ODE pin. When
WAITMODE is high t hen the pin is asser ted high; when
WAITMODE is low then the pin is asser ted low.
INT 72 OD Interrupt (active low)
The 78Q8430 asserts the INT signal low when it detects an
interrupt event.
PME 73 OD Po wer Management Event (acti ve low)
The 78Q8430 asserts the PME signal low when it detects a
wake-up event.
78Q8430 Data Sheet DS_8430_001
16 Rev. 1.2
3.2.8 Mode Pins
Table 9: Chip Mode Pin Descriptions
Signal Pin Number Type Description
BUSMODE 83 I BUSMODE, CL KM O DE, WAITM ODE Con fi gur ati on
0,0,0 = Sync bus, ext. system clock, memwait act low
0,0,1 = Sync bus, ext. system clock, memwait act high
0,1,0 = Reserv ed
0,1,1 = Reserv ed
1,0,0 = Async bus, ext. system clock, memwait act low
1,0,1 = Async bus, ext. system clock, memwait act high
1,1,0 = Async bus, int. system clock, memwait act low
1,1,1 = Async bus, int. system clock, memwait act high
CLKMODE 85 I
WAITMODE 84 I
ENDIAN0 79 I Data Bus Endian S elect
0,0 = Big endian (MSB at high bit positions)
0,1 = Bytes are little endian inside 16-bit words
1,0 = Word endian (MSW at low bit posit i ons)
1,1 = Little endian (MSB at low bit posit i ons)
ENDIAN1 80 I
BOOTSZ1 100 I GBI Bus Size
BOOTSZ[1:0]: is strapped to indic ate the GBI bus si ze:
00 = Bus is 32 bits wide
01 = Bus is 16 bits wid e. Only DATA[1 5:0] are used.
10 = Bus is 8 bits wide. Only DATA[7: 0] are used.
11 = Reserved
BOOTSZ0 1 I
Notes:
1. The internal P HY should never be powered down when the int ernal system cloc k is s el ected by
the CLKMODE pi n (CLKMODE=1)
2. There is no ext ernal visibility for the system clock when t he internal clock mode is selected. The
GBI interface m ust therefore alway s be used in asynchrono us bus mode.
3.2.9 JTAG Pins
Table 10: JTAG Pin Desc ri pti ons
Signal
Pin Number
Type Description
TRST 5 I Test Reset (active low)
System provided reset for JTAG logi c.
TCLK 6 I Test Clock
System provided clock for JTAG logi c.
TMS 3 IU Test Mode Select
Enables JTAG boun dary scan using serial in/serial out ports.
Sampled on rising edge of TCLK.
TDI 4 IU Test Data In
Serial input port for clocking in test data to be shifted to t he
output at the end of the boundary scan chain (TDO).
TDO 81 O Test Data Out
Serial output port for clocking out test data shifted from the
input at the beginni ng of the boundary scan chain (TDI).
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 17
3.2.10 Power Pins
Table 11: Power Pin Descriptions
Signal Pin Number Type Description
VCCA 86
95
96
S 3.3 V supply for the analog transmit section.
VCC 8
17
27
36-37
44
51
61
71
82
S 3.3 V supply for the digital logic section.
GND 2
14
26
34-35
43
50
60
70
78
89
91
99
G Com mon ground retu rn.
78Q8430 Data Sheet DS_8430_001
18 Rev. 1.2
4 Electrical Specification
4.1 Absolute Maximum Ratings
Operation above the maximum rating m ay permanently dam age the device.
Table 12: Absolute Maximu m Ratings
Parameter Rating
DC Supply Voltage (VCC -0.5 to 4.0 VDC )
Storage Temperat ure -65 to 150 °C
Pin Voltage (ex cept T X O P/N and RXIP/N) -0.3 to (VCC+0.6) VDC
Pin Voltage (TX OP/N and RXIP/N only) -0.3 to (VCC+1.4) VDC
Pin Current ± 120 mA
4.2 Recommended Operati on Condi tions
Unless otherwise noted all specifications are valid over these temperatu res and supply voltage ranges.
Table 13: Recommended Opera ti ng Conditions
Parameter Rating
DC Voltage Supply (VCC 3.3 ± 0.17 VDC
)
Ambient Operating T emperature (TAMB -40 to +85 °C
)
4.3 DC Characteristics
Table 14: DC Chara cteristics
Parameter Symbol Conditions Min Nom Max Unit
Supply Current I V
CC CC – = 3.3 V
Auto-Negotiation
10BT (Idle)
10BT (Normal Activity)
100BTX
–
124
110
230
165
–
150
140
250
190
–
mA
Supply Current I Power-down mode
CC – 14 45 mA
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 19
4.4 Digital I/O Cha ra c te r is tic s
Table 15: Digital I/O Characteristics
Parameter Symbol Conditions Min Nom Max Unit
Input Voltage Low V
IL – – 0.8 V
Input Voltage High V
IH 2.0 – – V
Input Current IIL, I
IH -1 – 1 µA
Input Capacitance C
IN – 8 – pF
Output Voltage Low V I
OL OL – = 8 mA – 0.4 V
Output Voltage
High** V I
OH OH 2.4 = -8 mA – – V
Output Transit i on
Time T C
T L = 20 pF
IOH
–
= -8 ma (H to Z ) – 6 ns
Tri-state Output
Leakage Current* IType tri-st ate only
Z -1 – 1 µA
**PMEB and INTB ar e act i ve low outputs requiring external pull-up resistors. VOH
4.5 Analog Electrical Charact er istics
for these outputs i s not
specified.
4.5.1 100Base-TX Transmitter
Table 16: MII 100B ase-TX Transmit Timing
Parameter
Conditions
Min
Nom
Max
Unit
Peak Output Ampli tude (|VP+|, |VPBest-fit over 14 bit times;
0.4 dB Transformer loss
-|)
(see note below) 950 – 1050 mVpk
Output Amplitude S ymmetry |VP +|
|VP
0.98
-| – 1.02
Output Overshoot Percent of VP+, VP– - – 5 %
Rise/Fall time (tR, tF10-90% of V) P+, VP3 - – 5 ns
Rise/Fall time Imbalance |tR
- tF– | – 500 ps
Duty Cycle Distortion Devi ation from best-fit
time-grid;
010101... Sequence
– – ±250 ps
Jitter Scrambled Idle, I nternal
Oscillator Mode – – 1.4 ns
Note: Measur ed at the line side of the t ransformer. Test Condition: Transfo rm er P/N: TLA-6T103. Line
Termination: 100 Ω±1%
4.5.2 100Base-TX Transmitter (Informative)
Table 17: MII 100B ase-TX Transmitter (Informativ e)
Parameter Conditions Min Max Unit
Return Loss 2 < f < 30 MHz
30 < f < 60 MHz
60 < f < 80 MHz
16
−MHz30 f
log2016
10
– dB
Open-Circuit I nduct ance -8 < IIN 350 < 8 mA – µH
Note: The specifi cations in the preceding table are included for information onl y. They are mainly a
function of the external transformer and termination resistors used f or m easurements.
78Q8430 Data Sheet DS_8430_001
20 Rev. 1.2
4.5.3 100Base-TX Receiver
Table 18: MII 100B ase-TX Receiver Timing
Parameter Conditions Min Nom Max Unit
Signal Detect Assertion Threshold 600 700 800 mVppd
Signal Detect De-assertion Threshold 300 350 400 mVppd
Differential In put Resistance – 20 – kΩ
Jitter Tolerance (p k -pk) 4 – – ns
Baseline Wander Tracking -75 – +75 %
Signal Detect Assertion Time Not tested – – 1000 µs
Signal Detect De-assertion Time Not tested – – 4 µs
4.5.4 10Base-T Transmitter
Table 19: MII 10Ba se-T Transmitter Timing
Parameter
Conditions
Min
Nom
Max
Unit
Peak Different i al Output Signal
(see note below) All data patterns 2.2 – 2.8 V
Harmonic Cont ent
(dB below fundamental) Any harmoni c
All ones data
Not tested
27 – – dB
Link Pulse Width – 100 – ns
Start-of-Idle Pulse Width Last bit 0
Last bit 1 –
– 300
350 –
– ns
ns
Note: The Manchester-encoded data pulses, the link pulse and the start-of-idl e pulse are tested against
the templates and using the procedur es found in Clause 14 of IEEE 802.3. Meas ured at the line side of
the transformer. T est Condition: Transformer P/N: TLA-6T1 03. Line Terminatio n: 100 Ω±1%
4.5.5 10Base-T Transmitter (Informative)
Table 20: MII 10Ba se-T Transmitter (Informative)
Parameter
Conditions
Min
Nom
Max
Unit
Output Return Loss 15 – – dB
Output Impedanc e B al ance 1 MHz < freq < 20 MHz
29 17 10
−
log f
– – dB
Peak Common-mo de O utput Voltage – – 50 mV
Common-mode Rejection 15 VPK –
, 10.1 MHz sine
wave applied to transmitter
common-mode. A l l data
sequences.
– 100 mV
Common-mode Rejection Jitter 15 VPK –
, 10.1 MHz sine
wave applied to transmitter
common-mode. A l l data
sequences.
– 1 ns
Note: The specifi cations in the preceding table are includ ed for information only. They are mainly a
function of the ex ternal transformer a nd termination resi st ors used for measure m ents
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 21
4.5.6 10Base-T Receiver
Table 21: MII 10Ba se-T Receive Ti mi ng
Parameter Conditions Min Nom Max Unit
DLL Phase Acquisit i on T i me – 10 – BT
Jitter Tolerance (p k -pk) 30 – – ns
Input Squelched Threshold 500 600 700 mVppd
Input Unsquel ched Threshold 275 350 425 mVppd
Differential In put Resistance – 20 – kΩ
Bit Error Ratio – 10 –
-10
Common-mode Rejection Square wav e
0 < f < 500 kHz
Not tested
25 – – V
78Q8430 Data Sheet DS_8430_001
22 Rev. 1.2
5 Host Interface Timing Specification
5.1 Host Interface
CS
DATA
WR/OE
ADDR
MEMWAIT
T
SU
T
SL
T
WT
T
HWT
T
HCS
T
HO
T
L
T
H
THOWT
Figure 8: Host Interface Tim i ng Diagram
Name
Description
Requirement
Min
Max
TCS and ADDR setup time
SU CS and ADDR must be stable on or
before the falling edge of WR/OE. 0 ns –
TOutput settlin g time
SL The maximum amount of time that it will
take the MEMWAIT, or DATA when th ere
is no MEMWAIT, outputs to become
stable after the falling edge of WR/OE.
– 13.7 ns
TMaximum wait time
WT The max i m um amount of tim e that the
MEMWAIT out put will held asserted. – 17 ck
TWait hold time
HWT The minimum amount of tim e that the
WR/OE input must be held past the
de-assertion of MEMWAIT.
10 ns –
TCS hold time
HCS The CS input m ust be stable low for the
entire duration of the WR/OE low cycle. 0 ns –
TADDR and DATA hol d time
HO The ADDR and DATA inputs must be
stable for no less t han this amount of tim e
after the falling edge of WR.
2.5 ck –
TWR/OE min low pulse
L The minimum am ount of time that the
WR/OE input s must be held low. 2 ck –
TWR/OE min high pulse
H The minimum am ount of time that the
WR/OE input s must be held high. 2 ck –
Note: On read cycles when MEM WA IT is asserted the DATA outputs will be valid before t he
de-assertion of MEMWAIT.
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 23
5.1.1 Synchronous Mode Timing
TFALL
TRISE
BUSCLK
Output
Delay
Output
Delay
Figure 9: Host Bus Output Ti ming Diagram
BUSCLK
Input
T
SU
T
H
Figure 10: Host Bus Input Ti ming Diagram
Parameter
Symbol
Min
Nom
Max
Unit
Input Setup Time T 6
SU
– – ns
Input Hold Time T 6
H
– – ns
Output Fall Delay T –
FALL
– 8 ns
Output Rise Delay T –
RISE
– 8 ns
CSB min low P 1
WL
– – clk
CSB min high P 2
WH
– – clk
78Q8430 Data Sheet DS_8430_001
24 Rev. 1.2
5.1.2 Bus Clock Timing
T
CYC
T
HIGH
T
LOW
V
IH
V
IL
80%
50%
20%
Figure 11: Bus Clock Tim i ng
Parameter Symbol Sync 50 Async 100 Units
Min Max Min Max
BUSCLK Cycle Time T 20
CYC
– 10 – ns
BUSCLK Frequen cy – – 50 – 100 MHz
BUSCLK High Time T 8
HIGH – 3 – ns
BUSCLK Low Time T 8
LOW – 3 – ns
BUSCLK Slew Rate – 1 3 1 3 V/ns
5.1.3 Reset Timing
Parameter
Symbol
Min
Nom
Max
Units
RESETB Minimum Duration T 1
RESET – – clocks
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 25
6 Functional Description
6.1 Internal Block Diagram s
6.1.1 Internal Digital Block
Figure 12 presents an overview of the functional layers of t he 78Q8430. On the left side are the signals,
which connect to the GBI bus. On the u pper and middle right, the blocks that implem ent the MAC side of
the MII are shown. These blocks are co nnected to the embedded PHY. On the lower right, connections
to the EEPROM are shown.
Bus
Control
EMI
Address
& Data
EMI
System
MAC MII
Transmit
MAC Half
Duplex
MAC
MII
Receive
MII
Register
Controller
EEPROM/
ROM
Control
Queue
Memory
Snoop
Controller
Network
Wake-up
Flow
Control
Queue
Read/Write
Logic
CAM
Packet
Classify
CTL
Controller
Memory
Manager
RMON
DMA Status
Register
TX/RX
Packet Status
Register
QUE Status
Register MAC Status
Register
PROM_CS
PROM_CLK
PROM_DO
PROM_DI
4 Queue
Write Logic
1 Queue
Read Logic
JTAG
IEEE
1149.1
Boundary
Scan
TRSTB
TDO
TDI
TMS
TCLK
MEMWAIT
WRB/OEB
CSB
ENDIAN[1:0]
BOOTSZ[1:0]
WAITMODE
CLKMODE
BUSMODE
DATA
ADDR
PMEB
INTB
RESETB
BUSCLK
Figure 12: Internal Digital Block Diagram
6.1.2 Internal PHY
Figure 13 shows t he functional block s of the internal 78Q 8430 PHY. The signals shown on the left side
are the internal M II signals to the MAC. These signals are m ultiplexed with their respective external pins
for use with an ex ternal PHY device. The 78Q8430 is not a two-port device. Only one PHY interface can
be operational .
78Q8430 Data Sheet DS_8430_001
26 Rev. 1.2
MII
Transmit
Logic
4B/5B Encoder
Scrambler,
Parallel to Serial
100M
NRZ/NRZI
MLT3 Encoder Pulse Shaper
and Filter
Parallel to Serial
Manchester
Encoder
Tx Clock
Generator
UTP
Driver
TXOP
TXON
UTP
Receiver
RXIP
RXIN
LED0
LED1
Auto
Negotiation
Clock
Recovery
Carrier Sense,
Collosion Detect
10M
Serial to Parallel
Descrambler,
5B/4B Decoder
Manchester
Decoder,
Serial to Parallel
100M
Clock
Reference
XTLP/CLKIN
XTLN VCC GND
MII
Receive
Logic
MII
Activity
MII
Registers
Interrupt
Logic
10M
Adaptive Equalizer,
Baseline Wander,
MLT3 Decoder,
NRZI/NRZ
LED
Control
Logic
LINK
TXA
RXA
COLI
100BT
10BT
FDX
TX_CLK
TXD[3:0]
TX_EN
TX_ER
INTR
CRS
COL
RX_CLK
RXD[3:0]
RX_DV
RX_ER
MDC
MDIO
Figure 13: Internal PHY Block Diagram
On the right side are the signals, which connect to the status LEDs and a 1:1 isolation transformer before
connecting to an RJ-45 connector, or e qui valent media components.
6.2 Data Queuing
Ethernet frame data in the 78Q8430 is m anaged in queuing stru ctures called QUEs. The host bus
address space al located for QUEs has enough space f or ei ght, while the 78Q8 430 circuit only
implements five. QUEs are identifi ed numerically, QUE0 through QUE7, based on the registers in the
QUE register space that are used to access them. QUE1, QUE 6 and QUE7 are unimplemented and
reserved for fut ure use.
A QUE allocates m ain buffer memory as needed and stores discrete frames as they are written into the
QUE. The QUE then reads back frame s in the same order that they were written and frees the main
buffer memory. A QUE can contain a m aximum of 125 frames at any one time. If a QUE is unable to
allocate main buf fer memory when writi ng a frame, the frame will b e part i al l y added to the QUE as a
truncated frame. If a QUE is unable to allocate main buffer memory to st art a frame, the entire f ram e i s
dropped.
The QUEs are divided into two categ ories: receive QUEs, that store received f rame data and transmit
QUEs, that store t ransmit frame d ata. Frames are written to a receiv e Q UE by the MAC and read out by
the host. Frames a re written to a transmit QUE by the host and read out by the MAC. QUE0 and QUE1
are receive QUEs (only QUE0 is implemented), and QUE2 through QUE7 are tra nsmi t QUEs (QUE2
through QUE5 are implemented). Writing to the Transmit Dat a Register (TDR) for a receive QUE or
reading from the Read Data Regist er (RDR) for a transmit QUE is not supported and the result is
undefined in this specification.
The transmit QUEs are further divided into standard QUEs, as described a bove, and static QUEs. Static
QUEs differ fr om the standard QUEs in that they can only cont ain a single fram e, and that frame must be
252 bytes or less in t otal size. Unlike st andard QUEs, stat i c QUEs do not remove a f rame when it is read
from the QUE. O nce a frame is written t o a st atic QUE, it can be read out any number of ti m es and the
static QUE will al way s read out the same one frame. If a second fram e i s w ri tten to a static QUE then it
will replace the fi rst as the one frame contained in the QUE.
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 27
The purpose of a st atic transmit QUE i s to allow the host to confi gure a frame that will need to be
transmitted multiple times or transmitted at a later time without any interaction wit h the host. Transmit
QUE2 and QUE5 ar e st atic QUEs. Tra nsmi t QUE2 is best suited for MAC control pause frames as it can
be triggered to transmit by a main buffer watermark. Transmit QUE5 is best suited to Host Not
Responding (HNR) frames as it can be triggered to t ransmit by a host interrupt timeout.
When the MAC transmi tter is idle and ready to transmit a frame, it determines which QUE to read f rom on
a priority basis. The lowest numbered QUE cont aining data that needs to be transmit ted is selected by
the MAC, which mea ns when more than one transmit QUE is ready, the one with the lowest number
always gets priority.
6.3 Host Interface
6.3.1 Reading Receive Data
The status of the frame at the top of the receive FIFO can be obtain ed by reading the Receive Packet
Status Register (RPSR). The 16 LSBs of the RPSR contain a count of the t otal number of bytes that
have entered t he receive FIFO for this f rame. A value of zero means that there are no new frames in the
receive FIFO. As frame bytes ente r the FIFO, the count value is incremented. However, the count value
does not decrease the bytes read out of the read FIFO such that the final value will al way s be the final
frame size.
The MSB of the RPSR is the DONE bit. Once the last byte in the fram e has entered the receive FIFO,
the DONE bit is set indicating t hat the count value contained in the total bytes field now contai ns t he final
size in bytes of the frame and the error st atus and classification fields now contain the final frame status.
When the DONE bi t is asserted, this also indicates tha t the status for this fram e has been remov ed from
the receive stat us FIFO and future reads of the RPSR will refer to the nex t frame in the recei ve FIFO,
even if all of the data for the current frame has not been retrieved.
The frame data is read f rom the receive FIFO 32 bits at a time by successive reads to the Receive Data
Register (RDR). If the frame lengt h i s not an even mult ipl e of 4 bytes then the final read of the RPDR
register for that frame will be padded with zeros.
6.3.2 Writing Transmit Data
A transmit QUE is initialized by writing to its Packet Control Word Register (PCWR). This will assi gn an
ID to the frame and sel ect various trans m i ssion options. The frame size must then be set by writing to the
QUE Packet Size Register (PSZR). Transmit data is then writt en to the transmit FIFO 32 bits at a time via
successive writes t o the Transmit Data Regi st er (TDR).
If more bytes are written to the TDR than indicated n the PS ZR, the excess bytes are ignored. Writes to
the TDR past the end of the frame, however, wil l trigger a transmit FIFO overrun i nterrupt condition.
Similarly, if a new frame is initialized by a write to the PCWR before the frame length counter is expired, a
transmit FIFO under -run interrupt co ndi tion will result and the previous frame will be aborted. If there is
any question, the PSZR can be queried for the remaining number of bytes expected in the previous frame
before a new frame is initialized.
In the event that t he host wishes to terminat e a frame early without triggering an under-run interrupt and
aborting the frame, or if the size of t he frame is not init i al ly known, the PSZR can be rewritten at any t im e
before the end of the frame’s transmission. As an example, no m atter what the current value of the PSZR
is, if it is writt en with a value of one then the next write to the TDR will add one byte to the completed
frame. Conversel y, if the frame byte counter is about to expire then writing a larger value to the PSZR will
extend the fram e. It is an error to write a value of zero to the PSZR and the ci rc uit behavior in this case is
undefined.
As each frame egresses the transmit F IFO, its status is placed in the transmit status FIFO. Tran smit
frame status i s recovered by reading the Transmit Packet Status Register (TPSR). The Packet ID f i el d
from the PCWR is also placed i n the TPSR such that the status can be associated with the exact frame to
which it belongs.
78Q8430 Data Sheet DS_8430_001
28 Rev. 1.2
6.3.2.1 Using the Setup Transmit Data Regist er
The Setup Transmi t Data Register (STDR) can be used to control the way in which 32-bit data words are
transferred to the transmit FIFO. The STDR can be changed on a word-by-word basis t o change the
network endianne ss or buffer-byte-alignment, or the STDR can be used to setup the transfer of an entire
buffer of transmit data. A new frame must be initialized by a write to the PCWR before the STDR is setup
for transferring frame data to t he QUE .
The Count field of the STDR contains one less than the number of write s t o the TDR that will be needed
to complete the t ransfer of the buffer. The Start Off set field contains the number of bytes in the first write
to the TDR to ignore. The End Offset fi el d cont ains the number of bytes in the last write (when the Count
field is equal to zero) to ignore.
Table 22: Transmit Data Buffer Exa mple
32-bit Write Data
Transmit Order:
Byte-1
Byte-2
Byte-3
Byte-4
Start Offset = 2 X X B1 B2
B3 B4 B5 B6
Count decrement s f or
each write … … … …
… … … …
B B
N-4 B
N-3 B
N-2 N-1
End Offset = 3 B X
N X X
Notes:
1. The End Offset will continue t o be appl ied as long as the COUNT field of the STDR contains zero. If
a non-zero End Offset is used, it must be cleared at the end of the block transfer.
2. The COUNT field m ust expire before the PSZR expires. Frames that are entirely contained within
one block should not use the End Offset. Instead, use t he PSZR to clip the last write to the TDR.
The Endian field of the STDR is used to set the transmit order of the data written on the bus, or how host
bus write data by tes are mapped to transmit buffer bytes. If the Endian bit i s s et then the most signif i cant
byte of the host bus as defined by the logical endiannes s, i s m apped to the first transmitted byte in t he
buffer, otherw i se, the least significant byte is mapped to the first transmitted by te.
6.3.2.2 Preloading Transmit Data
A transmit QUE signals the MAC tran smitter that it is ready to transmit by asserting the QUE Data Ready
bit (QDR) in its QUE Stat us Register (QSR). The default behavior of the QDR f or a transmit QUE is to
assert anytime the QUE contains a ny data. This mea ns t hat a transmit QUE c an potentially begin
transmitting a s soon as the first B LO CK is added to the QUE. Once the QUE begins tra nsmitting, data f or
the packet being transmitted must be added to the QUE f ast er than the transmitter removes it or a T X
FIFO under-run co ndi tion will eventually abort the packet (see TPSR).
In the event that interrupt latency, host bus performance, or other issues may prevent the host from
loading data into the QUE faster th an i t is removed by the MAC, the QSR can be used to modify the QDR
behavior and prevent an under-run condition on the QUE. Bits 25 and 24 of the QSR are the Mode fi eld.
The default setti ng for the Mode field is 00b. In this mode the QDR bit is set anytime the QUE contains at
least one BLOCK. In this mode, the host m ust be di ligent in keeping the QUE populated wit h data to
avoid a TX FIFO under-run conditio n in the MAC.
If the Mode set ting is 01b then the QDR bit for the QUE i s set only when the number of BLOCKs in the
QUE is above the val ue indicated by the Threshold field. This will allow the host to fill the QUE up to the
threshold level at its leisure without risk of a TX FIFO under-run. The drawback to this mode is that a
small packet that uses f ewer than the threshold number of BLOCK s will be stranded in the Q UE until
more data is adde d to the QUE to bring t he total number of BLOCKs up and over the threshold.
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 29
If small packet s are a problem, then the M ode setting of 10b can be used. In this mode, the QDR bit for
the QUE is set onl y when there is an EOF i n the QUE, or in other words, the QUE contai ns at least one
entire frame. I n this mode, TX FIFO under-runs are not possibl e since the QUE will not begin to transmit
until it contains the entire frame. The draw-back to this mode i s with very large frames. If a frame is too
large to fit into the QUE all at one t i m e then it will never begin transmitt i ng and the QUE will be stalled.
If both small and large packets are to be handl ed then a Mode setting of 11b should be used. In this
mode, the QDR bit for the QUE is set anytime there is an EOF i n the QUE or the number of B LO CKs in
the QUE is above the threshold. In thi s way , large packets can preload a fixed number of B LO CKs while
small packets are guaranteed to transmit.
To facilitate the handling of very l arge packets by a fast ho st , an interrupt that is tied to the QSR
Threshold is provided. To make use of this, the host sets t he Threshold field based on the interrupt
latency. The host then preloads the QUE with some number of BLOCKs. As soon as t he total number of
blocks left in the QUE falls below the Thr eshold, an interrupt is generated. In response to the interrupt
the host writes m ore data to the QUE to put the number back above the threshold. The host can then go
on to other tasks unt i l the next interrupt. T his cycle is repeate d until the frame is c om pl eted.
6.3.3 DMA Slave Mode Access
Reading or writi ng l arge amounts of data into and out of a single QUE involves acces sing the same RDR
or TDR register re peatedly. A DMA Slave Mode is implemente d to facilitate this act i vity and reduce
overhead on the host side. While in DMA S l ave Mode, the address bu s on the host interfa ce is ignored
and all access is ass um ed to be to the programmed address until DMA mode is term inated. In this way
the host can use a DMA engine or block t ransfer facility to write or read QUE da ta without regard to the
addresses generated.
DMA Slave Mode is cont rolled by the DMA Register (DMA) at address 0x100.
To read data from a Q UE using DMA Slave Mode, the host writes the address of the RDR for the desired
QUE into bits nine through zero and set s bit 17, the Read Mode bi t, in the DMA register at add ress
0x100. The host t hen st arts the DMA transfer and all read access to the host interface will go to the
programmed RDR addres s. When the DMA t ransfer is complete, the DMA Mode is terminat ed by writing
a zero to bit 17 of t he DMA Register (DMA).
To write data to a Q UE using DMA Slave Mode, the host writes the address of the TDR for the desired
QUE into bits nine through zero and set s bit 16, the Write Mode bi t, in the DMA Register. The host then
starts the DMA transfer and all write a cc ess to the host interf ace will go to the progra m m ed TDR address.
When the DMA t ransf er is complete, read i ng the cleared Write Mode bit from the DMA Register
terminates th e DMA Mode.
DMA Slave Mode does not have any effect on other operations of the interface such that , for example,
the ENDIAN settings, STDR settings, etc. are all in effect during a DMA Mode transfer. During a DMA
mode transfer, the actual register address of the host bus a cc ess is ignored. Th is m eans that using DMA
Slave Mode to transfer data out of order is not supported. Data words must al ways be written to a
transmit QUE i n the desired transmit order and are always read f rom a receive QUE in received order.
6.4 Snoop Mode Access
The Snoop Interface provides a means by which QUE data can be inspected and modified in situ, leaving
the state of the QUE unchanged. The Snoop Interface work s by presenting the contents of a specific
BLOCK of QUE mem ory at the SNOOP address space 0x300-0x3FF. The Snoop Cont rol Register
(SNCR) is used to set which BLOCK of Q UE m emory is mapped i nto the SNOOP address space.
For example, an application that wish es to inspect or modif y the contents of t he first frame in the re ceive
QUE, QUE0, f i rst reads the value of t he FIRST BLOCK in QUE0 from its QFLR Register (QFLR). The
pointer to the FIRST BLOCK in QUE0 is then written to the SNCR register. Now that the SNCR Register
has programmed the S NOOP interface t o poi nt to the FIRST BLOCK for QUE0, accessi ng registers in the
address space from 0x300 to 0x3FF wil l be directly accessing t he data for the firs t frame contained in
QUE0.
78Q8430 Data Sheet DS_8430_001
30 Rev. 1.2
Snooping the cont ents of a frame before it is read out of the receive QUE can be useful if additional
inspection of t he frame is needed, beyond what is provided by classificatio n, to determine the di sposition
of a received frame. It can also be used, in conjunct ion with the QUE t ransf er feature, to m i ni mize host
bus overhead in responding to simple ARP or ICMP request s. In this case, the host can use the Snoop
Interface to modi fy a received ARP or ICMP request and co nvert it into the appropriate respon se, while
the frame is st i ll resident in the receive QUE. The QUE Transfer feature is the n used to transfer the
response directly to a TX QUE and tra nsmit it back to the source without having to read the entire frame
into host memory.
6.5 Water Marking
The Timers module (see Section 6.8) monitors the number of free memory blocks in the syst em input.
There are three watermarks (Interrupt, PAUSE and Headroom), accessed via the Water Mark Values
Register (WMVR), which can be used to manage memory usage based on the size of the free memory pool.
6.5.1 Interrupt Watermark
When the number of free BLOCKs falls below the interrupt threshold, the WA TER MARK interrupt in the
HIR is triggered. An i nterrupt threshold set ting of zero disabl es this feature.
6.5.2 PAUSE Watermark
When the number of free BLOCKs falls below the pause threshold, the QDR bit for the PAUSE QUE
triggers the transmission of the pause frame. A pause threshold setting of zero disables this feature.
6.5.3 Headroom Watermark
When the number of free BLOCKs falls below the headro om threshold then the MAC receiver i s halted
causing the MAC to drop any frames receiv ed after completion of the current frame. This condit ion is
cleared once the number of free BLOCKs rises back above t he threshold. This prevents a saturated
receiver from con suming all free memory thereby locking out the local transmitter. A headroom set ting of
zero disables t his feature.
6.6 Counters
A block of hardware counters is implemented to allow monitoring transmit and receive statistic s. These
counters are acce ss ed and managed by using the Count Data Register (CDR), the Counter Control
Register (CCR) and the Counter M anagement Register (CMR).
6.6.1 Summary of Counters
Table 23 provides a summary of al l counters by address. Count ers at addresses 0x 00 through 0x0E are
transmit coun ters. Counters at add resses 0x0F through 0x27 are receive counters.
Table 23: Counter Summ ary
Counter
Address Counter Description
0x00 Transmitt ed Packets, 0 Colli sions, not deferred or excessive deferred
0x01 Transmitt ed Packets, 1 Colli sion
0x02 Transmitt ed Packet s, 2-15 Collisions
0x03 Excessive Collisions
0x04 Deferred transmissions
0x05 Late Collisions
0x06 MAC errors (TX under-run or transmit halted)
0x07 Lost carrier sense errors
0x08 Excessive deferrals
0x09 Total packets transmitted
0x0A Multicast packets
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 31
Counter
Address
Counter Description
0x0B Broadcast packets
0x0C SQE errors
0x0D Pause packets transmitted
0x0E Transmitted bytes
0x0F Received pac ket s, 63 bytes or less
0x10 Received p ackets, 64 bytes
0x11 Received p ackets, 65 to 127 byt es
0x12 Received p ackets, 128 to 255 byt es
0x13 Received p ackets, 256 to 511 byt es
0x14 Received p ackets, 512 to 1023 byt es
0x15 Received p ackets, 1024 to 1518 (1522 for VLAN tag) by tes
0x16 Received p ackets, 1519 byt es or m ore (1523 or more for VLAN tag) bytes
0x17 CRC error and no alignment error
0x18 Alignment errors
0x19 Fragment errors (less than 64 bytes with CRC or alig nment error)
0x1A Jabbers (gre ater than 1518 or 1522 and CRC or alignment error)
0x1B MAC errors
0x1C Dropped pa ckets
0x1D Classificat ion dropped packet
0x1E Total receiv ed packets with no errors
0x1F Total received multicast packets with no errors
0x20 Total receiv ed broadcast pac ket s with no errors
0x21 Range erro rs (length field <= 1500 and received data <= 1500 and not control packet and
length field does n ot match data bytes received and unpadded packet and no
CRC/alignment errors
0x22 Out of rang e count (length field > 1500 and not control packet 8808)
0x23 Total receiv ed VLAN packets with no errors
0x24 Total receiv ed Pause packets wit h no errors
0x25 Total received Control pa ckets with no errors
0x26 Total receiv ed bytes with no errors
0x27 Total receiv ed bytes with erro rs but not jabber nor fragment
6.6.2 Reading and Setting Counter Values
Before any counter s c an be accessed, the CCR value must be set appropriately. Bits 0 to 5 of the CCR
are the Address field. These bits must c ontain the address of the first counter to be accessed. B i t eight
of the CCR is the Access Mode bit. When the Access Mode bit is clear, the access mode is read. When
the Access Mode bit is set, the access mode is write. B i t nine of the CCR is the Clear on Read bit. The
Clear on Read bit is onl y relevant when t he acc ess mode is read. When the Clear on Read bit is set,
then the counter values are automaticall y reset to zero after the counter value i s read. If a countabl e
event occurs at the same time as the r eset, then the counter val ue is reset to one suc h that no countable
events are miss ed. Bit ten of the CCR must always be set .
Once the CCR has been conf i gured for the desired counter acces s, the CDR is used to gain access to
the actual counter values. When the CCR Access Mode bit is cleared f or read, only read access to the
CDR is allowed, and a read of the CDR will return the value of the counter specified by the CCR Address
field. When the CCR Access Mode bit i s set to write, only writ e access to the CDR is allowed, and the
value written t o the CDR will be written to the counter at the address specif ied by the CCR Address field.
The CCR Addre ss fi eld value is automati call y incremented after each read or w rite access to the CDR
allowing many count ers to be accessed through repeat ed reads or writes on the CDR without the need to
reconfigure th e CCR each t i m e. When writing a val ue to a counter, if a countable event oc cur s at the
78Q8430 Data Sheet DS_8430_001
32 Rev. 1.2
same time then t he act ual value placed i nto the counter is the CDR value plus o ne to prevent the loss of
any countable ev ents.
6.6.3 Precision Counting
Applications that require a high degree of temporal pr ecision across all the counters can use the CMR for
this purpose.
Bit two of the CMR is the Freeze bit. The Freeze bit can be used when the values of many or al l counters
must be known at an ex act point in time. S etting the Freeze bit in the CMR will cause all counters to stop
counting at that m om ent. Any countable events that occur after the Freeze bit is set are stored in an
event FIFO. A fter the application has set the CMR Freeze bit , it should read all the co unter values as
quickly as possi bl e. The event FIFO s are deep enough to hold off countable events f or up to 28
microseconds assuming minimum sized frames are ingressing and or egressing at full 100 Mbps data
rate, or 280 micros econds for 10 Mbps. When the application ha s finished reading t he counter values, i t
should clear the CMR Freeze bit. All of the events stored in the FIFOs will be counted at that time. If any
event FIFO fill s bef ore the application h as cleared the CMR Freez e bi t, then the hardwa re wil l auto-clear
the freeze condition and count all events in the event FIFOs. To check for this condition, the application
can query the CMR Freeze bit before clearing it. If it is already clear then the freeze condition had to be
cleared by hardwar e i n order to avoid losing any counts. In this case, not al l of the counters read are
guaranteed to be at their frozen value.
In the case that t he appl ication wants to st art all the counters count i ng at the same time, the CMR
provides a Clear Rec ei ve bit and a Clear Transmit bit. These bits are write only, t hey will always read
back zero. When one is set, it causes all the read or write counters to be reset to zero at exactly the
same time.
6.6.4 Rollover Interrupts
For applicatio ns that only need a much more coarse counter treatment, roll over interrupts are prov i ded for
each counter. T he counter rollover interrupts can be indivi dual l y enabled or disa bl ed for each counter. In
some cases it may be desirable to preloa d a counter with a nonzero value to set how many counts, it will
take to roll the cou nter and trigger an i nterrupt.
The rollover indic ation for transmit counters zero thro ugh fourteen are bits zero through fourteen of the
TRIR respectively. The rollover indication for receiv e counters fifteen through thirty-nine are bits zero
through twenty -four of the RRIR respectively.
Each transmit and receive rollover bit ca n be i ndi vidually enabled or di sabled in terms of triggering a host
interrupt. Wh en a roll over bit is set t hen the RMON bit of the HIR will be set unless the mask bit
corresponding to the rollover bit is clear. The RMON bit of t he HI R will , in turn, trigger a host i nterrupt
when its corresponding mask bit is set.
6.7 Packet Classifi cat ion
The packet clas sif i cat i on engine is comprised of a content addressable memory (CAM ) l inked to control
logic (WCS), which is responsible for acting on the C AM result and generating the next CAM reference
word. The WCS applies the first byte of packet data to the CAM using a previous hit value of zero. The
resulting CAM address is then used to i ndex a control word for the control logic to process. The control
logic then uses the c ontrol word along with the CAM address and the next packet byte to generate
another reference word to apply to the CAM. This proces s iterates until the packet i s done or the control
word calls for complet i on. The final clas sif i cat i on result is the address of the last CAM hit.
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 33
Data Byte
WCS
CAM
Reference
Word
CAM Address
Control Signals
EOF
Figure 14: Classification Architec ture
The CAM is a 128-word by 15-bit wide content addressable memory. When a reference data word is
applied to the CAM, the result is the highest numbered address that contains a data word that m atches
the reference. Each data word contained in the CAM also contains 15 mask b its that conditionally disable
individual data bits from preventi ng a match. Address 0 is reserved and can never match such that no
reference data can ever result in a CAM address of zero. A ddress 1 is also reserved and always
matches such that a reference word that does not match any entry in the CAM will gi ve a result of one.
Associated wit h each CAM entry is a con trol word. When a refe rence data word is presented to the CAM
and an address results, the control word associated with that address is pa ssed to the control logi c t hat
determines the nex t action taken by the packet classifier.
The control logic c an execute any of the following actions:
• Set the most significant byte of the pause counter.
• Set the least significant byte of the pause counter.
• Start the pause timer.
• Cause the packet to be dropped.
• Wake the host from power down mode (starts the HNR timer).
• Interrupt the host.
• Manipulate the cla ssif ication result reported in the RPSR.
• Identify mult i cast/broadcast frames for RMON statistics.
• Identify the Len/Type field for frame size checking.
• Identify the IP header for checksum checking.
To facilitate classification, the control logic contains a general purpose 8-bit register, ‘X’ and a 5-bit
counter, ‘C’. The ‘X’ register can be used to store a p acket byte or a CAM result for later u se. The
counter can be used as a loop index to it erate a set of rules a fix ed number of times. The TOC action is
used to set the count er and the DEC action i s used to decrement the counter. When a DEC action
causes the counter to expire, the loop is broken by decrementing the actual CAM address of the rule that
executed the DEC act i on for the purposes of the next CAM reference word. To prevent ambiguity, the
rule immediat el y below a rule that uses the DEC action should generally not be used.
Additionally, t he control logic is responsible for generating the next 15-bit CAM mat ch word by
concatenating the next 8-bit packet data byte or t he ‘ X ’ regist er value with the 7-bit address of the current
CAM match. At the beginning of t he packet, the previous CAM match is initi al ized to zero as is t he
control logic ‘X’ regi st er. The CAM address of zero is reserved and will never resul t from a CAM match
such that the first data byte in the frame is guaranteed to be the only byte t hat is accompanied by a zero
value for the previous hit. In other words, a CAM rule with a specified value for the previous hit of zero
will only match t he first byte of the f ram e.
78Q8430 Data Sheet DS_8430_001
34 Rev. 1.2
6.7.1 Address Filtering
The 78Q8430 CAM is loaded upon reset with a set of default rules for users who only want to use the
address filter feature (see Section 6.7. 4). The following rules are intended as a template to pr ovide
address-filtering functionali ty. They support four multicast and eight unicast address filters. The last
unicast address filter rule is configured by default as a prom iscuous mode rul e such that the address-filter
is in promiscuous mode right out of reset.
6.7.1.1 Promiscuous Mode Off
In promiscuous mode, all addresses are passed on to t he host driver. This means that, as long as
promiscuous mode i s enabled, none of the other address fi lters are effectiv e. Promiscuous mode mu st
therefore be disa bl ed before any address filtering can happe n. The following procedure should be used
to deactivate promiscuo us mode:
STEP 1. Change the Match Contro l field of rule 0x30 from MD to DROP . This will cause any frame with
an address that does not match any othe r address filter t o be dropped.
6.7.1.2 Promiscuous Mode On
The promiscuous mo de filter is a filter wi th all address bits m asked as wildcard bit s such that any address
will match. Turning promiscuous mode on and off is the sam e as changing the promiscuous mode fil ter
from a positive filter to a negative filter (s ee Section 6.7.1.5). The following procedure should be used to
activate prom isc uous mode:
STEP 1. Change the Match Contro l field of rule 0x30 from DROP to MD. T hi s will cause all frame s to
pass the address f i l ters.
6.7.1.3 Unicast Address Filters
The default CAM rule set supports eight unicast address filters. The first, unicast filter #0, i s the
promiscuous mode filter and is reserved for that purpose. The remaini ng seven are general use. Each
filter has two comp onents, the 48-bit address that it matches and a mask that defines whi ch bi ts of the
address are relevant and which bits are wildcards. Each byte of each addres s f i l ter has a rule assigned
to it. The followin g table summarizes the association of unicast filter bytes and CAM rules.
Table 24: CAM Rul es Associated with Unicast Filter Bytes
Byte [0] Byte [1] Byte [2] Byte [3] Byte [4] Byte [5]
U/C Filter # 7 0x77 0x6F 0x5F 0x57 0x47 0x37
U/C Filter # 6 0x76 0x6E 0x5E 0x56 0x46 0x36
U/C Filter # 5 0x75 0x6D 0x5D 0x55 0x45 0x35
U/C Filter # 4 0x74 0x6C 0x5C 0x54 0x44 0x34
U/C Filter # 3 0x73 0x6B 0x5B 0x53 0x43 0x33
U/C Filter # 2 0x72 0x6A 0x5A 0x52 0x42 0x32
U/C Filter # 1 0x71 0x69 0x59 0x51 0x41 0x31
Note: Bytes are in network transmit order starting with Byte [0].
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 35
For an arbitrary uni cast filter number N, the following procedure should be u sed to set the addres s and
mask values:
STEP 1. Write address and mask byte [0] to the CAM. CAM rule 0x70+N should be written as shown in
the following tabl e:
Reg.
Field
Value to write
CAR ADDR 0x70+N
RMR Data Match Value of M A C address byte [0]
Data Mask Value of m ask byte [0] from t he Wil d Card setting (0x FF i s
for a perfect match)
Previous Hit Match 0x00 to disable the filter
Previous Hit Mask 0x00
RCR Byte Offset Retain default: 0x00
Interrupt Retain d efault: 0
Control Logic Action Retain default: NOP
Match Control Retain default: MD
STEP 2. Write address and mask byte [1] through by te [4] to the CAM. For each byte the CAM rule
indicated by Table 24 based on the filt er num ber, N, and byte number s hould be written a s
follows.
Reg.
Field
Value to write
CAR ADDR byte [1]: byte [2]: byte [3]: byte [4]:
0x68+N 0x58+N 0x50+N 0x40+N
RMR Data Match Value of M A C address byte [1] … byte [4]
Data Mask Value of m ask byte [1] . . . byte [4]
Previous Hit Match Value of the CAM rule used by the previous byte
Previous Hit Mask 0x7F
RCR Byte Offset Retain default: 0x00
Interrupt Retain d efault: 0
Control Logic Action Retain default: NOP
Match Control Retain default: MD
Unlike the sett ings for byte [0], the Previous Hit Mask field is set to 0x 7F and the Previous Hit
Match field is always set to t he value of the CAM rule used by the previous byte. A s an
example, the Previous Hit Mask fields for filter #1 woul d be 0x71, 0x69, 0x59 and 0x51, for byte
[1] through byte [4] respectiv el y.
STEP 3. Write address and mask byte [5] to the CAM. CA M rule 0x30+N should be writ ten as follows.
Reg. Field Value to write
CAR ADDR 0x30+N
RMR Data Match Value of M A C address byte [5]
Data Mask Value of m ask byte [5]
Previous Hit Match Set to the CAM rule that was used for byte [4] (0x40+N).
Previous Hit Mask 0x7F
RCR Byte Offset Retain default: 0x00
Interrupt Retain d ef ault: 0
Control Logic Action Set to TAX
Match Control Retain default: MD
78Q8430 Data Sheet DS_8430_001
36 Rev. 1.2
STEP 4. Enable the filter. The unicast address filter is enabled by setting t he Previous Hit Mask field of
the CAM rule for by te [0] to 0x7F. This step must be done last to prevent an ingressing f rame
from matching a partial set of fil ter rules. All the rules f or a filter must be in place before
enabling the filt er.
An address filter can be simply activated/deactivated by toggling the value of the Previous Hit Mask field
for the byte [0] CAM rul e between 0x7F and 0x00 respectively. The promiscuous mode filter, filter #0,
should not be deactiv ated in this way.
It is important that STEP 1 deactiv ates the filter so that no frames are filtered using a partial filter
setting before all relevant rules are writ ten. Step 4 reactivat es t he filter once the new settings are in
place.
6.7.1.4 Multicast Address Filters
The defaul t CAM rule set supports four multicast address filters. The first, multicast filter #0, serves the same
purpose as the promiscuous mode filter except it applies only to multicast addresses. The last, multicast filter
#3, is the broadcast filter and is reserved for that purpose. The second, multicast filter #1, is the PAUSE filter
and is set up b y defa ult to m atch t he PAUSE address. Multicast filter #2 is unused by default and available for
general use. Each filter has two components, the 48-bit add ress t hat it matc hes a nd a ma sk that defi nes
which bit s of t he add ress a re relev ant and whi ch bit s are wildca rds. Each byte of each address filter has a
CAM rule as signed to it. Table 25 summarizes the association of multicast filter bytes and CAM rules.
Table 25: CAM Rul es Associated with Multicast Filter Bytes
Byte [0] Byte [1] Byte [2] Byte [3] Byte [4] Byte [5]
M/C Filter #3 0x7F 0x67 0x63 0x4F 0x4B 0x3F
M/C Filter #2 0x7E 0x66 0x62 0x4E 0x4A 0x3E
M/C Filter #1 0x7D 0x65 0x61 0x4D 0x49 0x3D
Note: Bytes are in network transmit order starting with Byte [0].
For an arbitrary m ulticast filter number N, the following procedure should be u sed to set the address and
mask values:
STEP 1. Write address and mask byte [0] to CAM rule 0x 7C+N as follows.
Reg.
Field
Value to write
CAR ADDR 0x7C+N
RMR Data Match Value of MAC address byte [0]
1
Data Mask Value of m ask byte [0]
1
Previous Hit Match 0x00 to disable the filter
Previous Hit Mask 0x00
RCR Byte Offset Retain default: 0x00
Interrupt Retain d efault: 0
Control Logic Action SETMC
Match Control Retain default: MD
1The LSB of both add ress byte [0] and mask byte [0] must be set for multicast address filters. If the
LSBs are not set then the address is not m ul ticast and belongs in the unicast filter set.
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 37
STEP 2. Write address and mask byte [1] through byte [4] to the CAM. For each byte the CAM rule
indicated by table 5.7.2 based on the filter number and byte number should be written as follows.
Reg.
Field
Value to write
CAR ADDR byte [1]: byte [2]: byte [3]: byte [4]:
0x64+N 0x60+N 0x4C+N 0x48+N
RMR Data Match Value of M A C address byte [1] … byte [4]
Data Mask Value of m ask byte [1] . . . byte [4]
Previous Hit Match Value of the CAM rule used by the previous byte
1
Previous Hit Mask 0x7F
RCR Byte Offset Retain default: 0x00
Interrupt Retain default: 0
Control Logic Action Retain default: NOP
2
Match Control Retain default: MD
1As an example, t he P revious Hit Match fields for filter #1 woul d be 0x7D, 0x65, 0x61 and 0x4D, for
byte [1] through by te [4] respectively .
2
Reg.
An exception is byte [4] of the broadcast filter. Multicast filter #3, byte [4] should have the Control
Logic Action field set to TAX.
STEP 3. Write address and mask byte [5] to CAM rule 0x3C+N as follows.
Field
Value to write
CAR ADDR 0x3C+N
RMR Data Match Value of M A C address byte [5]
Data Mask Value of m ask byte [5]
Previous Hit Match Set to the CAM rule that was used for byte [4] (0x48+N).
Previous Hit Mask 0x7F
RCR Byte Offset Retain default: 0x00
Interrupt Retain d efault: 0
Control Logic Action Set to TAX
1
Match Control Retain default: MD
1
It is important that STEP 1 deactivates the filter so that no frames are filtered using a partial filter setting
before all relevant r ules are writ ten. STEP 4 reactiv ates the fi lter once t he new settin gs are in pla ce.
Exception: Multicast filter #3, byt e [5] should have the Action field set to SETBC.
STEP 4. Enable the filter. The multicast address filter is enabled by setting the Previous Hit Mask field of the
CAM rule for byte [0] to 0x7F. This step must be done last to prevent an ingressing frame from
matching a partial set of filter rules. All the rules for a filter must be in place before enabling the filter.
A Multicast address filter can be simply act i vated/deactiv ated by toggling the value of the Previous Hit
Mask field for the byte [0] CAM rule between 0x7F and 0x00 respectivel y. Multicast fi l ter #0 should not be
deactivated in t hi s way.
6.7.1.5 Negative Address Filters
Any address filter, either multicast or unicast, can be set as either a positi ve or negative fil ter. A positive
filter is a filter that passes frames wit h a source MAC addr ess that matches the filter. A negative filter is a
filter that bloc ks f rames with a sourc e MAC address that matches the f i lter. By default, all filters are
positive actin g. The following proce dure is used to change a filter to negative action:
STEP 1. Change the Match Contro l field for t he CA M rule for byte [5] from MD to DROP.
To change a filt er back to a positive acting filter, change t he same M atch Control field back to MD.
78Q8430 Data Sheet DS_8430_001
38 Rev. 1.2
6.7.2 Configuring the CAM
The CAM rules are accessed indirectly one at a time via the CAM Address Register (CAR). The cont ents
of the rule whose number is indicated by the CAR are available for read and write via the Rule Match
Register (RMR) and the Rule Control Register (RCR). The RMR contains a template that the CAM
reference word m ust m atch in order to trigger the rule, and the RCR contains the control word that is
passed to the control l ogic when the rule i s t riggered.
6.7.2.1 Rule Match Register
The RMR contains f our fields that cont rol when a rule is triggered: Previous Hit Match and Previous Hit
Mask, Data Mat ch and Data Mask. The mask fields are used to determine which bits in their respective
match field are required to make a mat ch and which bits are ignored. A mask bit value of one means that
the correspondi ng m atch bit must be exactly equal to the same bit in the CAM re ference word to trigger
the rule. Inversely, a m ask bit value of zero means that the corresponding bit in t he CA M ref erence word
is ignored. A special case is that all previous hit mask bits are zero. In thi s case, the rule is deactivated
and can never be triggered.
6.7.2.2 Rule Control Register
The RCR cont ai ns f our fields that cont rol the actions take n by the control logi c when the rule is trigge red:
Byte Offset, Interrupt, Action and M atch Control fields.
RCR Byte O ffset
The Byte Offset field is generally used t o skip over bytes in t he frame that are not relevant to the current
classification. When the Byt e O ffset is non-zero then t he classification will skip the number of bytes
indicated. The except i on is when the TOC action is u sed, in which case, t he value of the By te Offset field
is used to initialize t he control logic co unter and no offset is applied.
An offset value of 0x3F will skip just the ri ght number of bytes to jump over the cur rent IPv4 header.
RCR Interrupt
When the Interrupt bit in the RCR for a given rule is set, then the triggering of the rule will cause an HIR
classification int errupt .
Control Logic Action
The value of the cont rol logic Action field in the RCR determines the action t hat will be taken by the
control logic when the rule is triggered.
Table 26: Control Logic Actions
Hex
Value Binary
Value Name Action Taken
0x0 00000b NOP No action taken.
0x2 00010b PAUSE Start the local pause timer.
0x4 00100b WAKE Send a wake-up signal to the host and start the HNR timer.
0x6 00110b IPCK Start the IP header checks um check and the IP header counter.
0x7 00111b TIPO Transfer IP header counter to offset.
0x8 01000b TDX ‘X’ is assigned the value of the frame data.
0xA 01010b TAX ‘X’ is assigned the value of the current rule number.
0xC 01100b TAXH The high-o rder nibble of ‘X’ is as signed the value of the low-order nibble
of the current rule number.
0xD 01110b TAXL The low-order ni bble of ‘X’ is assigned the value of the low-ord er nibble
of the current rule number.
0x10 10000b TXA The classification resul t is assigned the v al ue of ‘X’.
0x12 10010b TLXA The low-order nibble of the classificat i on result is assigned the value of
the low-order nibble of ‘ X ’ .
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 39
Hex
Value
Binary
Value
Name Action Taken
0x14 10100b THXA The hi gh-order nibble of the classification res ul t is assigned the value of
the high-order nibble value of ‘X’ .
0x15 10101b SETMC Mark the fram e as mul ticast for Rx statistics purposes.
0x16 10110b VLAN Mark the frame as VLAN tagged for lengt h checking and statist ics.
0x17 10111b SETBC Mar k t he frame as broadcast for Rx statistics purposes.
0x18 11000b TOC The control logic counter value is initi al ized to the value contained in the
Byte Offset field. No offset is applied.
0x1A 11010b DEC The control logic counte r value is decremented. If the counter has
reached zero then the control logic wil l decrement the previous hit value
used to generat e the next CAM reference word by one.
0x1B 11011b MCTL Cla ssif y the frame as a MAC control frame. Thi s also sets the Len/Type
LSB.
0x1C 11100b TDPH The pau se counter most si gni ficant byte is set f rom the frame data.
0x1D 11101b TDLTH The Len/Type most significant byte is set from the frame data.
0x1E 11110b TDPL The pau se counter least si gni ficant byte is set from the frame data.
0x1F 11111b TDLTL The Len/Type least significant byte is set from the frame data.
RCR Match Contr ol
The value of the Match Control field will determine how t he control logic generates the next C AM
reference word.
Table 27: RCR M atch Contro l
Value
Name
Action Taken
00b DONE No mo re CAM reference words are generated. No further classification is
done for the current frame.
10b MD The next frame data is used to generate the next CAM ref erence word.
01b MX The ‘X’ value i s us ed i n pl ace of the frame dat a to generate the next CAM
reference word.
11b DROP Drop the frame. If this is executed within the first 128 bytes of t he frame
then the entire f ram e i s dropped from the Q UE. No more CAM re ference
words are generated.
6.7.3 Frame Format
The following t abl e shows the format of an E thernet frame. The fields are in the order that the
classification engine sees them, from left to right . The byte count for each field is specified on the bottom
row of the table.
Table 28: Ethernet Fram e for Classification
Destination
Address Source
Address
Len/Typ
LLC Data
CRC (FCS)
Hi
Lo
User
Pad
MSB
LSB
6 Bytes 6 Bytes 1B 1B 0-1500B 46-0B 4 Bytes
If the Len/Type field contains a 16-bit value that is less than 0x0600, the field is i nterpreted as a lengt h
field that specif i es t he number of bytes in the User field. If the value is greater than or equal to 0x0600,
the type interpretat i on is to be used.
6.7.4 Default CAM Rule Summary
This section provide s the default rules that the 78Q8430B CAM i s loaded with on reset.
78Q8430 Data Sheet DS_8430_001
40 Rev. 1.2
6.7.4.1 Destination Address
Table 29 contains the rules proces sing destination address, which also in cludes the pause packet and
promiscuous mode.
Table 29: Process Destination Address Rules
Rule# PrevHit PH-Mask Data D-Mask Next Offset Action Interrupt Comment
0x7F 0x00 0x7F 0xFF 0xFF MD 0x00 SETMC 0
0x7E 0x00 0x00 0x00 0x00 MD 0x00 SETMC 0
0x7D 0x00 0x7F 0x01 0xFF MD 0x00 SETMC 0
0x7C 0x00 0x7F 0x01 0x01 MD 0x00 SETMC 0
0x7B 0x00 0x00 0x00 0x00 MD 0x00 NOP 0 Not used
0x7A 0x00 0x00 0x00 0x00 MD 0x00 NOP 0 Not used
0x79 0x00 0x00 0x00 0x00 MD 0x00 NOP 0 Not used
0x78 0x00 0x00 0x00 0x00 MD 0x00 NOP 0 Not used
0x77 0x00 0x00 0x00 0x00 MD 0x00 NOP 0
0x76 0x00 0x00 0x00 0x00 MD 0x00 NOP 0
0x75 0x00 0x00 0x00 0x00 MD 0x00 NOP 0
0x74 0x00 0x00 0x00 0x00 MD 0x00 NOP 0
0x73 0x00 0x00 0x00 0x00 MD 0x00 NOP 0
0x72 0x00 0x00 0x00 0x00 MD 0x00 NOP 0
0x71 0x00 0x00 0x00 0x00 MD 0x00 NOP 0
0x70 0x00 0x7F 0x00 0x00 MD 0x00 NOP 0
0x6F 0x77 0x00 0x00 0x00 MD 0x00 NOP 0
0x6E 0x76 0x00 0x00 0x00 MD 0x00 NOP 0
0x6D 0x75 0x00 0x00 0x00 MD 0x00 NOP 0
0x6C 0x74 0x00 0x00 0x00 MD 0x00 NOP 0
0x6B 0x73 0x00 0x00 0x00 MD 0x00 NOP 0
0x6A 0x72 0x00 0x00 0x00 MD 0x00 NOP 0
0x69 0x71 0x00 0x00 0x00 MD 0x00 NOP 0
0x68 0x70 0x78 0x00 0x00 MD 0x00 NOP 0
0x67 0x7F 0x7F 0xFF 0xFF MD 0x00 NOP 0
0x66 0x7E 0x00 0x00 0x00 MD 0x00 NOP 0
0x65 0x7D 0x7F 0x80 0xFF MD 0x00 NOP 0
0x64 0x7C 0x7C 0x00 0x00 MD 0x00 NOP 0
0x63 0x67 0x7F 0xFF 0xFF MD 0x00 NOP 0
0x62 0x66 0x00 0x00 0x00 MD 0x00 NOP 0
0x61 0x65 0x7F 0xC2 0xFF MD 0x00 NOP 0
0x60 0x64 0x7C 0x00 0x00 MD 0x00 NOP 0
0x5F 0x6F 0x00 0x00 0x00 MD 0x00 NOP 0
0x5E 0x6E 0x00 0x00 0x00 MD 0x00 NOP 0
0x5D 0x6D 0x00 0x00 0x00 MD 0x00 NOP 0
0x5C 0x6C 0x00 0x00 0x00 MD 0x00 NOP 0
0x5B 0x6B 0x00 0x00 0x00 MD 0x00 NOP 0
0x5A 0x6A 0x00 0x00 0x00 MD 0x00 NOP 0
0x59 0x69 0x00 0x00 0x00 MD 0x00 NOP 0
0x58 0x68 0x78 0x00 0x00 MD 0x00 NOP 0
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 41
Rule# PrevHit PH-Mask Data D-Mask Next Offset Action Interrupt Comment
0x57 0x5F 0x00 0x00 0x00 MD 0x00 NOP 0
0x56 0x5E 0x00 0x00 0x00 MD 0x00 NOP 0
0x55 0x5D 0x00 0x00 0x00 MD 0x00 NOP 0
0x54 0x5C 0x00 0x00 0x00 MD 0x00 NOP 0
0x53 0x5B 0x00 0x00 0x00 MD 0x00 NOP 0
0x52 0x5A 0x00 0x00 0x00 MD 0x00 NOP 0
0x51 0x59 0x00 0x00 0x00 MD 0x00 NOP 0
0x50 0x58 0x78 0x00 0x00 MD 0x00 NOP 0
0x4F 0x63 0x7F 0xFF 0xFF MD 0x00 NOP 0
0x4E 0x62 0x00 0x00 0x00 MD 0x00 NOP 0
0x4D 0x61 0x7F 0x00 0xFF MD 0x00 NOP 0
0x4C 0x60 0x7C 0x00 0x00 MD 0x00 NOP 0
0x4B 0x4F 0x7F 0xFF 0xFF MD 0x00 TAX 0
0x4A 0x4E 0x00 0x00 0x00 MD 0x00 NOP 0
0x49 0x4D 0x7F 0x00 0xFF MD 0x00 NOP 0
0x48 0x4C 0x7C 0x00 0x00 MD 0x00 NOP 0
0x47 0x57 0x00 0x00 0x00 MD 0x00 NOP 0
0x46 0x56 0x00 0x00 0x00 MD 0x00 NOP 0
0x45 0x55 0x00 0x00 0x00 MD 0x00 NOP 0
0x44 0x54 0x00 0x00 0x00 MD 0x00 NOP 0
0x43 0x53 0x00 0x00 0x00 MD 0x00 NOP 0
0x42 0x52 0x00 0x00 0x00 MD 0x00 NOP 0
0x41 0x51 0x00 0x00 0x00 MD 0x00 NOP 0
0x40 0x50 0x78 0x00 0x00 MD 0x00 NOP 0
0x3F 0x4B 0x7F 0xFF 0xFF MD 0x00 SETBC 0 BC
0x3E 0x4A 0x00 0x00 0x00 MD 0x00 TAX 0
0x3D 0x49 0x7F 0x01 0xFF MD 0x00 TAX 0 PAUSE
0x3C 0x48 0x7C 0x00 0x00 MD 0x00 TAX 0 MC
0x3B 0x00 0x00 0x00 0x00 MD 0x00 TAX 0 Not used
0x3A 0x00 0x00 0x00 0x00 MD 0x00 TAX 0 Not used
0x39 0x00 0x00 0x00 0x00 MD 0x00 TAX 0 Not used
0x38 0x00 0x00 0x00 0x00 MD 0x00 TAX 0 Not used
0x37 0x47 0x00 0x00 0x00 MD 0x00 TAX 0
0x36 0x46 0x00 0x00 0x00 MD 0x00 TAX 0
0x35 0x45 0x00 0x00 0x00 MD 0x00 TAX 0
0x34 0x44 0x00 0x00 0x00 MD 0x00 TAX 0
0x33 0x43 0x00 0x00 0x00 MD 0x00 TAX 0
0x32 0x42 0x00 0x00 0x00 MD 0x00 TAX 0
0x31 0x41 0x00 0x00 0x00 MD 0x00 TAX 0
0x30 0x40 0x78 0x00 0x00 MD 0x00 TAX 0 promiscuous
78Q8430 Data Sheet DS_8430_001
42 Rev. 1.2
6.7.4.2 Source Address Filtering
Source address filt ering can be used to drop frames with a specific address while passing al l others.
Table 30 contai ns t he rules on processi ng source addres s.
Table 30: Process Source Address Rules
Rule# PrevHit PH-Mask Data D-Mask
Next
Offset Action Interrupt Comment
0x2F 0x30 0x70 0x01 0x01 DROP 0x00 NOP 0 MC drop
0x2E 0x30 0x70 0x00 0x00 MD 0x05 NOP 0 pass other
6.7.4.3 Length/Type Field, MAC Control Frames and IP Head er Ch ecksum
Table 31 contai ns t he rules on processi ng length/type, M A C control frames and start IP header checksum
check.
Table 31: Process Length/Type, MAC Control Frames and Start IP Header Checksum Rules
Rule#
PrevHit
PH-Mask
Data
D-Mask
Next
Offset
Action
Interrupt
Comment
0x2D 0x2B 0x7F 0x00 0xFF MD 0x02 VLAN 0
0x2C 0x00 0x00 0x00 0x00 DONE 0x00 NOP 0
0x2B 0x2E 0x7F 0x81 0xFF MD 0x00 TDLTH 0
0x2A 0x2B 0x7F 0x00 0x00 DONE 0x00 TDLTL 0
0x29 0x2F 0x7C 0x88 0xFF MD 0x00 TDLTH 0
0x28 0x29 0x7F 0x08 0xFF MD 0x00 MCTL 0
0x27 0x29 0x7F 0x00 0x00 DONE 0x00 TDLTL 0
0x26 0x2F 0x7C 0x00 0x00 MD 0x00 TDLTH 0
0x25 0x26 0x7F 0x00 0x00 MD 0x00 TDLTL 0
0x24 0x25 0x7F 0x40 0xF0 MD 0x00 IPCK 0
0x23 0x24 0x7E 0x00 0x00 MD 0x3F TXA 0
0x22 0x28 0x7F 0x00 0xFF MD 0x00 NOP 0
0x21 0x28 0x7F 0x00 0x00 DONE 0x00 NOP 0
0x20 0x22 0x7F 0x01 0xFF MD 0x00 NOP 0 MCTL pause
0x1F 0x22 0x7F 0x00 0x00 DONE 0x00 NOP 0 MCTL oth er
0x1E 0x20 0x7F 0x00 0x00 MD 0x00 TDPH 0
0x1D 0x1E 0x7F 0x00 0x00 MX 0x00 TDPL 0
0x1C 0x1D 0x7F 0x3D 0xFF DONE 0x00 PAUSE 0
0x1B 0x1D 0x7F 0x00 0x00 DONE 0x00 NOP 0 MCTL pause
with bad SRC
6.7.4.4 Wake on LAN
The packet clas sif i cat i on engine can us e the WAKE action to signal the host to come o ut of power down
mode. This is used to i m plement the Wake-On-LAN feature.
The Power Manag ement Control and St atus Register (PMCSR) is used to control the hardware respon se
to a WAKE action. If the PS field of the PMCSR is zero then all WAKE actions are ignored. The
WAKE action is only honored if the part i s currently in a power down mode as determined by the
PS field. If the PME_ENB bit in the PMCSR is set then a valid WAKE action will trigger the assertion of
the PMEB primary output. If the P M E_ENB bit is clear then a valid WA K E action will only res ult in the
normal HIR WAKE interrupt.
When the host is notified of a valid WAKE event, either by the assertion of the PMEB primary output or
assertion of INTB via the WAKE HIR in terrupt, the rule that triggered the event can be read from the
Wake Up Status Regist er (WUSR). A valid WAKE event will also start the Host Not Responding (HNR)
timer. When the host i s notified of a WA KE event, it must clear t he event by set ting the PME bit in the
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 43
PMCSR. This action will clear the WAK E event and clear the WA KE bit in the HIR and the PMEB primary
output, if it was enabled. If the HNR timer ex pi res before the host clears the WAKE event then the QDR
bit for QUE5 is set triggering the transmission of t he HNR frame contai ned in QUE5. The leng th of the
HNR timer is determined by the val ue cont ai ned in the Host Not Responding Count Registe r (HNRCR).
When configuring f or Wake On LAN, the host should set the HN RCR with a value based on the longest
anticipated interrupt service latency.
OnNow Packets
The OnNow specification states that an OnNow compliant node m ust be able to wake up upon the
reception of a f ram e that matches a reference frame with a byte mask applie d. Table 32 contains the
rules on proces sing OnNow packet s.
Table 32: Process Rules for OnNow Packet
Rule# PrevHit PH-Mask Data D-Mask Next Offset Action Interrupt Comment
0x15 0x23 0x7F 0x54 0xFF MD 0x00 NOP 0
0x14 0x15 0x7F 0x00 0x00 MD 0x02 NOP 0
0x13 0x14 0x7F 0x04 0xFF MD 0x00 NOP 0
0x12 0x13 0x7F 0x05 0xFF MD 0x00 NOP 0
0x11 0x12 0x7F 0x06 0xFF MD 0x00 NOP 0
0x10 0x11 0x7F 0x07 0xFF DONE 0x00 WAKE 0
Magic Packets
A magic packet i s def i ned to be a frame that contains a specifi c sequence of bytes any where in its USER
field. Table 33 contains the rules on checking for the sequence in a frame an d waking the host if it finds a
magic packet.
Table 33: Process Rul es for Magic Packet
Rule# PrevHit PH-Mask Data D-Mask Next Offset
Action Interrupt Comment
0x0F 0x25 0x7F 0xFF 0xFF MD 0x05 TOC 0 Bare Ethernet
0x0E 0x23 0x7F 0xFF 0xFF MD 0x05 TOC 0 IP payload
0x0D 0x01 0x7F 0xFF 0xFF MD 0x05 TOC 0 offset payload
0x0C 0x0F 0x7C 0xFF 0xFF MD 0x00 DEC 0
0x0B 0x0B 0x7F 0xFF 0xFF MD 0x00 NOP 0
0x0A 0x00 0x00 0x00 0x00 DONE 0x00 NOP 0
0x09 0x0B 0x7F 0x10 0xFF MD 0x0F TOC 0
0x08 0x03 0x7F 0x10 0xFF MD 0x00 NOP 0
0x07 0x08 0x7E 0x20 0xFF MD 0x00 NOP 0
0x06 0x07 0x7F 0x30 0xFF MD 0x00 NOP 0
0x05 0x06 0x7F 0x40 0xFF MD 0x00 NOP 0
0x04 0x05 0x7F 0x50 0xFF MD 0x00 NOP 0
0x03 0x04 0x7F 0x60 0xFF MD 0x00 DEC 0
0x02
0x02 0x7F 0x00 0x00 DONE 0x00
WAKE 0
78Q8430 Data Sheet DS_8430_001
44 Rev. 1.2
6.8 Timers
The Timers block impl ements several timers used within the system. Watermarking for main memory is
also handled in this block as it relates to the PAUSE operation.
6.8.1 PAUSE Timer
The PAUSE timer is used to implement the MAC Control P AUSE operation described i n Annex 31B of
IEEE STD 802.3-2002. It consists of a 16-bi t counter that determines the duration of the pause state.
The host can also trigger a local pause st ate via the Start Paus e bi t of the PDCR.
6.8.2 HNR Timer
The Host Not Responding timer is used to notify remot e nodes that have reque st ed a Wake-On-LAN that
the local host is not responding to the request. The host, kno wing about how long it shoul d take to wake,
sets the value for how l ong to wait aft er a wake request for the host to clear the interrupt before a timeout
triggers the transmission of a Host Not Responding pack et. This value is set in the Host Not Responding
Count Register (HNRCR).
The host can determine the wake status by reading the Power Man agement Control and Status Register
(PMCSR). The defaul t state is clear.
The HNR counter is de cremented on every sy st em clock that it has a non-zero value.
6.8.3 Interrupt Delay Timer
The Interrupt Delay Timer is used to delay the received data i nterrupt to the host. The host determines
how long the delay should be by writing a value to the Interrupt Delay Count Register (IDCR).
As noted above, the interrupt ti m er i s using MAC receive by te times as its unit of time. The value writt en
to the IDCR c an therefore be thoug ht of as the maxim um num ber of bytes that could possibly be received
between the time the first data was added to the QUE and w hen the received dat a i nterrupt is actually
triggered.
6.9 EEPROM Contro lle r
The PROM controller provides logic for reading and w riting an optional ext ernal EEPROM or ROM device.
The external device s supported are the M i cr oChip 93LC46B and the National NM93C 46. Timing
compatible devices, smal ler devices and read-only equi valent devices are also supported.
The basic sequence s of events in accessi ng an external EEPRO M or serial ROM are:
• System software reads the busy bit t o ensure the EEPROM cont roller is not bus y.
• On a write, the data should be written into the data register before setting the control registe r.
• Software writes the address and the read/write fl ag and sets the busy bi t.
• The controller completes the operation and clears the busy bit.
• On a read, when system software detects the busy bit i s cleared, it can read the data register.
6.10 Ethernet MAC
The MAC consists of a transmit block, a receive block, a cont rol register, a flow control block and a serial
controller for stat i on m anagement communications to t he P HY and the optional ex ternal EEPROM/ROM.
The MAC also has a lo op back circuit.
6.10.1 MAC Transmit Block
The MAC transmit block moves the outgoi ng data from the MAC transmit FIFO, enc apsulates it and
passes it on to the M II interface logic in the PHY. The transmit block has circuits for generating preamble
and jam bytes, pad bytes, the CRC val ue and error extension. The transmit bl ock also has a timer for the
back-off delay after a collision and a timer for the inter-packet gap af ter transmission.
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 45
6.10.2 MAC Receive Block
The receive block receives frames from the PHY via the MII interface. It stri ps t he preamble and SOF
and passes the rem ai nder of the receiv ed frame data and error i nformation to the MAC receive FIFO.
The MAC receiver passes all frames re ceived, including er ror f rames and collisions. Dropping of error
frames is handled by the receive produ cer in the QUE logic.
6.10.3 MAC Control Register
The MAC Control Registe r (MCR) provides controls for network operation, i ncluding:
• Enable and disabl e transmit and receiv e circuit, including requests to halt at end of current packet.
• Enable and disabl e full duplex operation and loopback modes.
• Enable and disabl e various MAC features like ex cessive-deferral detection, SQE and CRC checking.
6.10.4 Transmitting a Frame
To transmit a frame, the transmit enable bit in the MCR must be se t and the transmit halt request bit must
be clear. The MA C does not signal the DMA engine to transfer bytes to the MAC tran smi t FIFO. The
QUE transmit cont rol ler controls the t ransfer of bytes to the MAC transmit FIFO.
The MAC transmit block then starts transmitting the data in the FIFO, but wil l retain the first 64 bytes until
it has acquired the net. At that t i m e, the MAC transmit bl ock will request mo re data and transmit it until
the QUE transmit controller signals the end of the frame to be transmitted. T he M AC transmit bloc k
generates pad by tes, if needed, appen ds the calculated C RC to the end of the packet if requested and
transmission stops. It sets the completion bit i n the Transmit Packet Status Register (TPSR), signaling
the end of a transmission, which may in turn cause an interrupt. If the QUE trans m i t controller indicates
an error then the MA C transmit block will transmit an MII error status and abort t he frame.
The MAC transmit block does not begin transmission until the number of bytes indic ated by the preload
field of the PCWR are in the MAC t ransmit FIFO. T his is to give the IP header checksum generator a
head start in generati ng the checksum. Thi s m ay be needed since the checksum is in the middle of the
IP header but cannot be known until the entire header is summ ed. The results are undefined if the
header checksum is inserted into t he frame after the c hecksum has already been transmitted.
6.10.5 IEEE 802.3 Transmit Protocols
6.10.5.1 Interpacke t Gap Ti m ing
In half duplex mode, the gap state machine is respons i ble for counting the 96 bit times from the de-
assertion of the carrier sense signal, which is the inter-record gap. It breaks the 96 bi t times for
inter-record gap i nto the first 64 bits and the last 32 bits, in order to precisely control the appropriate times
for beginning transmission. If there is any traffic within the first 64-bit times, it resets t he counter and
resumes counti ng from zero. If there i s any traffic within the last 32 bits, i t continues counting and signals
the end at 96 bit ti m es. In full duplex mode, the gap state machine starts counting at the end of
transmission and signals the end at 96 bit times (12 byte t i m es).
6.10.5.2 Coll ision Processing and Back-off
If the main transmit state machine det ects a collision, it starts the back-off state machine counters and
waits for the end of the back-off slot, before retransmit ting the collision causing packet again. Each
back-off slot is a multiple (including zer o) of 512 bit times. Each time there is a collision for the same
packet, the bac k-of f state machine increments an internal attempt counter. A pseudo-random number
generator out puts a random number by selecting a subset of the value of the generat or. The subset
grows by one bit for each subsequent attempt. This impl em ents the equation:
0 < r < 2 k, k = min. (n, 10)
where r is the number of slot times t hat the MAC has to wait in case of a collision, and n i s t he number of
attempts. For exam pl e, after the first collision, n is 1 and r is a random number bet ween 0 and 1. The
pseudo-random-number generat or i n this case is one-bit wide and gives a random num ber of either 0 or
78Q8430 Data Sheet DS_8430_001
46 Rev. 1.2
1. After the second attempt, r is a random number between 0 a nd 3; the state machine looks at the t wo
least significant bits of the generator (n = 2) which gives a value between 0 and 3.
In order to improve the statistical independence betw een two MACs using the same pseudo-random
number generator, the MAC uses values from the CRC of p rev i ous successfully transmitted packets to
modify the basic random number seque nce.
6.10.6 Transmit Operation
If there is data to be transferred, the inter-pack et gap is OK and the M II is ready (there are no collisions
and the device i s either in full duplex mode or there is no CRS), then the MAC tr ansmit block transmits
the preamble followed by the SFD. After t he transmission of t he preamble and the SFD, it transmits 64
bytes of data regard l ess of the packet length, unless short transmission is enabled. This means that i f the
packet is less than 64 bytes, it will pad the LLC data field with zeroes, unless NoP ad i s enabled. At the
end of the packet , it appends the CR C, unl ess NoCRC generation is enabled. If there is any collision
during the first 64 bytes (8 bytes of prea m bl e and S FD and 56 bytes of the frame), it stops t he
transmission and t ransmits a jam pattern (32 bits of all ones). It increments the collision attempt count er,
returns control to t he back-off state machine and retransmits t he packet when the ba ck-of f time has
elapsed and the gap ti m e is OK.
If there is a collision after the first 64 bytes, it is reported as a l ate collision and the packet i s terminated
with an error indication. The 78Q8430 does not retry late collisions.
If there are no collisions, the MAC transmit block transmi ts the rest of t he pack et and at this time (after the
first 64 bytes hav e been transmitted without collisions), it allows the DMA engine to overwrite this packet.
After transmit ting the first 64 by tes, it transmits th e rest of the packet and appends the CRC to the end.
FIFO under-run or more than 16 collisions will cause the st ate machine to abort the packet (no retry) and
prepare for the next packet in the queue.
In case of any transmission error s, the MAC transmit bl ock sets the appropriat e error bit in the TPSR and
sends a bad TX signal to the interrupt controller.
6.10.7 Receiving a Frame
To receive a frame, the receive enable bit in the MCR must be set and the receive halt bit must be clear.
The MAC receive bl ock, when enabled, constantly monitor s a data stream coming from the integrated
PHY. If the MAC is in loop back mode, the data stream will be going to the MAC transmi t block via
internal connection s.
The MAC receive bl ock receives zero to seven bytes of preamble, followed by the Start Frame Delimi ter
(SFD). The MAC receive block checks that the first data rec ei ved is preamble and looks for the SF D in
the first eight bytes. If the SFD is not the first non-preamble byte, it treats the packet as a fr agment and
discards it. When i t has received a full byte, the MAC receive block stores the by te and several status
bits in the MAC receiv e FIFO which then signals that data is present. It receive s subsequent bytes and
stores them and thei r st atus in the FIFO. If, during the f ram e reception, the re ceive FIFO overflows, or
the PHY asserts mii_rx_er, or the frame ends on an odd nibble, the MA C receive block sets t he
corresponding stat us bit for the byte i n the FIFO.
The QUE receiv e cont roller reads bytes from the MAC receive FIFO, combines them into four-byte words,
checks the CRC, opt i onally drops the padding and/or CRC field and m oves the data into t he receive
QUE. The QUE re ceiv e controller will nev er take bytes from the FIFO on two consecutive clocks. The
status bits from the receive FIFO are held by the QUE receiv e controller for the receive status FI FO until
the EOF status bit f rom the FIFO is true , at which time the final status is added to the status FIFO and the
held status bit s are all cleared in preparation for the next frame. The QUE receive controller will signal
the receive produ cer t o drop a frame if there i s no room in the status FIFO when the frame arrives. Thi s
makes sure that there is a one-to-one rel ation between frames in the QUE and st atus words in the stat us
FIFO.
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 47
6.10.8 Strip Padding/FCS
The strip-padding feature will remov e any padding from 64-by te frames. The strip-padding feature will
also remove excess padding from frames up to 127 bytes in t otal length. Frames that are 128 bytes or
larger will never hav e any padding strip ped. Padded frames that have their padding removed by the strip-
padding feature will also have their FCS f iel d removed, even if the strip CRC feature i s not enabled. If the
strip-padding feature is enabled but the strip CR C feature is not, then frames received that have no
padding remov ed wil l st i l l have their FCS fiel d, but frames that have padding removed will not. The CRC
is always checked even if it is remove d by the strip padding feature and not t he strip CRC feature. The
strip CRC feat ure will always remove th e FCS field from all received frames.
The packet clas sification block sn oops data bytes as they are popped from the receive FIFO by the QUE
receive control ler. If the classifi er determines that a frame is to be dropped, the frame error bit to the
receive producer is set and, assuming the first BLOCK of the frame has not been added, the frame i s
dumped before it i s appended to the QUE . If the classificati on block determines that a frame is t o be
dropped after one or m ore BLOCKs have been added t o the QUE then the fram e i s truncated at that point
and the remainder of the frame is drop ped.
6.11 MAC Error Reporting
Errors report ed by the MAC are comm unicated back to the host on a frame-by-frame basis through the
Transmit Status FIFO and Receive St atus FIFO.
6.11.1 MAC Transmi t E rrors
6.11.1.1 Transmit FIFO Underrun Error
The 80-byte MAC t ransmit FIFO is cap able of handling a worst-case QUE latency of 1.28 μs (128 bit
times, or 16 byt e times) because 64 byt es are retained for possible retransmission after a collision. T he
QUE transmit cont rol ler has higher ba ndwidth than the 100 Mb P HY such that a MAC transmit FIFO
under-run usually indi cat es a host bus latency problem. See Sect i on 6.3.2.2 for a di sc ussion on how to
mitigate this situation.
In the event that t he transmit FIFO does under-run, the MA C aborts the transmission, sets the Underrun
bit in the transmit st atus and discards the remainder of the frame when it finally does arrive.
6.11.1.2 Lost Carrier Error
In half duplex m ode, Carrier Sense (CR S ) i s moni tored from the beginning of the Start F rame Delimiter
(SFD) to the last byte transmitted. A lost carrier condition indicates that CRS was never pre sent or was
dropped during transmission (a possible network problem), but transmissi on i s not aborted. Lost carrier
error is disabled during loop back mode. During full duplex operation, CRS is not passed to the transmit
block and lost car rier will not be asserted. Lost carrier sets the Carrier bit in t he Transmit Packet Status
Register (TPSR).
6.11.1.3 Excessive Collision Error
In half duplex m ode, whenever the MAC encounters a collision during transmit, it will back off, update the
collision counter and try again later. When the counter equals 16 (16 attempts all result ed in a collision)
transmission is aborted. Excessive c ol l isions probabl y indicate a network problem. Excessive collision
sets the Excessive Collision bit i n the Transmit Packet Status Register (TPSR).
6.11.1.4 Late Colli si on E rror (Transmit Out-Of-Window Collision)
In a correctly confi gured and operati ng network, the cont roll er sees a collisi on (i f there is one) within the
first 64 bytes of data being transmitted. If a collision o cc urs after this tim e a possible network p roblem is
detected. Late collision sets the Lat e Collision bit in the Transmit Packet Status Register (TPSR) and
transmission of the packet is aborted, i.e. late collision s are not retried.
78Q8430 Data Sheet DS_8430_001
48 Rev. 1.2
6.11.1.5 Signal Quality Error
In 10 Mbps mode, the M A C checks for a “heart beat” at the end of a transmitted packet. This is a short
Collision signal within the first 40 bit times af ter end of transmission. Signal Quality Error sets the No
Heart Beat bit in the Transmit Packet Status Register (TPSR).
6.11.1.6 Deferral
In half duplex m ode, during any att em pt to send a packet, the MAC may have to def er the transmissio n
because of a pre-o cc upied network. This is not an error, but is use d as a network activity indicator, but
only when collision s do not occur. Deferral sets the Def erral bi t of the Transmit Packet Status Register
(TPSR).
6.11.1.7 Excessive Deferral
In half duplex operat ion, the MAC will defer transmission of frames when there is network activity. If the
deferral time is longer than two maximum sized frame t imes (2.4 288 ms for 10-Mbps operation or 0.24288
ms for 100-Mbps operation) then the E xcessive Deferral bit of the Transmit Packet Status Register
(TPSR) is set. If the Tx Enable bit of the MCR Register (MCR) is clear, then the transmission is aborted.
Excessive deferral indicates a possible network problem.
6.11.2 MAC Receive Errors
6.11.2.1 Alignment Error
At the end of recept i on, the MAC receiv e block checks that the incoming pa ck et has been correctly
framed on an 8-bit boundary. If it is not and the CRC is invalid, data has been di sru pted through the
network and the MA C receive block repo rt s an al i gnment error. A CR C error is also report ed. The
Dangling Byte bit and the CRC bit are set i n the Receive Packet Status Re gi st er (RPSR).
6.11.2.2 CRC Error
At the end of recept i on, the MAC receiv e block checks the CR C for validity and reports a CRC error if it is
invalid.
6.11.2.3 Overflow Error
During recept ion, incoming data is put into the MAC receive FIFO before it is t ransferred to the Q UE
receive control ler. If the MAC receive FIFO fills up because of excessive system latency or other
reasons, the MAC receive block sets t he Overflow Error of the Receive Packet Status Register (RPSR)
and the remaining frame is dropped.
6.11.2.4 Length Error
The MAC receive bl ock checks the length of the incoming packet at the end of rec eption based on the
value of the Len/Ty pe field of the frame. If the length is specifie d i n the Len/Type field and the frame is
longer than the m aximum frame size of 1518 bytes, (1522 for VLAN tagged packets), the MAC receiv e
block reports a l ength error, unles s long frame mode is ena bl ed. The MAC will also flag as an error a
MAC control f rame that is not exactly 64 bytes in length.
6.11.2.5 MII Error
The PHY informs the M AC if it detects a media error (such as codi ng violation) by asse rt i ng RX_ER.
When the PHY asserts RX_ER, the M A C sets the MII error bit in the Receive Packet Status Register
(RPSR).
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 49
6.12 PHY Operations
6.12.1 Automatic MDI/MDIX Cable Crossover Configuration
The transmitt er and receiver cont ai n l ogic and mux to det ect and correct for cross over cabling errors.
The implement ation is fully compliant with IEEE 802.3 specifications, ensuring interoperation with other
PHYs, which may or m ay not implement automatic MDI/MDI-X configuration. The automatic MDI/MDI-X
state machine f acil itates switching T X N and TXP pins with the RXN and RXP pins, prior to the auto-
negotiation mode of operation. The correct polarization of the crossover circuit is determined by an
algorithm that con t rols the swit ching function. Use of an 11-bit Linear Feedback Shif t Register (LFSR)
creates a pseudo-ra ndom sequence to det erm ine the MDI configuration. Upon making the selection to
either MDI or M DI-X , the 78Q8430 wai ts for a specified am ount of time while evaluating its receiv e
channel to determi ne whether the othe r end of the link is s ending link pulses or 10BASE-T or
100BASE-TX data. If link pulses or data are detected, the 78Q8430 rem ai ns in that configur ation. If link
pulses or data are not detected, it increments it’s LFSR and makes a decision to switch based on the
value of the next bi t. The state machine does not move from one st ate to another while lin k pulses are
being transmi tted.
6.12.2 100Base-TX Transmit
The 78Q8430 P HY cont ai ns all of the necess ary circuitry to convert the transmit M II signaling from a MA C
to an IEEE-802.3 compliant data-stream driving Cat-5 UTP cabling. The internal PCS interface ma ps
4-bit nibbles from the MII to 5-bit code groups as defined in Table 24-1 of IEEE-802.3. The 5-bit code
groups are then s cra m bl ed and converted to a serial stream bef ore being sent to the MLT-3 pulse
shaping circuit ry and line driver. The pulse-shaper uses current modulation t o produce the desired out put
waveform. Controlled rise/fall time in the MLT-3 signal is achieved using an accurately controlled volt age
ramp generator. T he l i ne driver require s an external 1:1 isolation transformer to i nterface with the l i ne
media. The center-tap of the primary side of the transformer connects to the 3.3 V supply.
6.12.3 100Base-TX Receive
The 78Q8430 P HY rec ei ves a 125 MBaud MLT-3 signal through a 1:1 transformer. The sig nal then goes
through a combination of adaptive off set adjustment (baseline wa nder co rrecti on) and adapti v e
equalization. T he effect of these cir cuits is to sense the am ount of dispersion and attenuation caused by
the cable and transformer and restore t he received pulses to logic levels. The amount of gain and
equalization applied to the pulses varie s with the detected attenuation and di spersion and, ther efore, with
the length of the ca bl e. The 78Q8430 PHY can compensate f or cable loss of up to 10dB at 16 MHz. This
loss is represented as test_chan_5 i n Annex A of the ANSI X 3.263:1995 specification and correspond s to
approximately 140 m of CAT-5 UTP cabl i ng. The equalized MLT -3 data signal is bi-directionally sliced
and the resulting bit -stream is presented to the CDR where it is re-timed and decoded to NRZ f orm at.
The retimed serial dat a is converted to parall el , then de-scrambled and aligned into 5 bit code groups.
The receive PCS i nterface maps these code groups to 4 bit data for the internal M II as outlined in Clause
24 of IEEE-802.3.
6.12.4 10Base-T Transmit
The 78Q8430 P HY takes 4-bit parallel N RZ data via the MII i nterface and passes it through a parallel t o
serial converter. T he data is then passed through a Manchest er encoder, pre-emphasis pulse-shaper,
media filter and finally to the twisted-pair line driver. The pulse sh aper and filter ensures the output
waveforms meet the output volt age template and spectral content require m ents detailed in Clause 14 of
IEEE-802.3. Interfac e to the twisted pair m edi a i s through a center-tapped 1:1 transformer. N o external
filtering is requi red. During auto-negotiation and 10BASE-T idle periods, link pulses are transmitted.
The 78Q8430 P HY em pl oys an on board tim er to prevent the MAC from capturing a network through
excessively long transmissions. When this timer is exceed ed the chip enters the j abber state and
transmission is dis abl ed. The jabber state is exited after t he M II goes idle for 500 m s ± 250 ms.
78Q8430 Data Sheet DS_8430_001
50 Rev. 1.2
6.12.5 10Base-T Receive
The 78Q8430 P HY rec ei ves Manchester encoded 10BASE-T data through the twisted pair inputs and
re-establishe s l ogic levels through a slicer with a sma rt squelch function. The slicer automatical l y adjusts
its level after val i d data with the appropriate levels are detected. Data is pas sed on to the CDR where the
clock is recovered and data is re-timed and passed through a Manchester decoder. From here, data
enter the serial t o paral lel converter for transmission to t he M AC via the media independent interface.
Interface to t he twisted pair media is through a 1:1 transform er. Polarity information is detect ed and
corrected in internal circuitry.
6.12.6 SQE Test
The 78Q8430 P HY supports the signal q ual i ty error (SQE) funct i on detailed in IEEE-802. 3. At an interval
of 1µs after each n egative transition of the TXEN pin in 10BASE-T mode, t he COL pin will go high for a
period of 1µs. S Q E i s not signaled if a collision is detected during transmission. This function can be
disabled through regi st er bit MR16.11.
6.12.7 Polarity Correction
The 78Q8430 P HY i s cap able of either aut omat i c or manual polarity reversal for 10BASE-T and
auto-negotiat ion. These features ar e controlled by the P HY m anagement register MR16, bits APOL and
RVSPOL. The default i s automatic mod e, where APOL is negated and RVSPOL indicates if the detecti on
circuitry has inverted the in put signal. To enter ma nual mode, APOL needs to be asserted and t hen
RVSPOL will control the signal polarit y.
6.12.8 Natural Loopback
The natural loop back function can be enabled by setting register bit MR16.10. With natural loop bac k
enabled, whenev er the 78Q8430 PHY is transmitting and not receiving on the twisted pair media
(10BASE-T Half Duplex mode), data on the TXD pin s is looped back onto t he RXD pins. During a
collision, data from the RXI pins is routed to the RXD pins.
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 51
6.12.9 Auto-Negotiation
The 78Q8430 P HY supports the auto-negotiation func tions of Clause 28 of I EEE-802.3. This functi on can
be controlled via regi st er settings. The auto-negotiati on function defaults to on and bit MR0[12],
ANEGEN, is high after reset. Software can disable the auto-negotiation function by writing to bit MR0[12].
The contents of regi st er MR4 are sent to the PHY’s link pa rtner during auto-negotiation, coded in fast link
pulses. Bits MR4.8:5 reflect the state of the TECH[2:0] bits after reset. If TECH[2:0] = 111b, then all 4
bits are high. If TECH[2:0] = 001b, then only bi t 5 is high. After reset, software can ch ange any of these
bits from a 1 to a 0.
With auto-negoti ation enabled, the 78Q8430 PHY will st art sending fast link pulses at power on, los s of
link or a command to restart. At the same time, it will l ook f or ei ther 10BASE-T idle, 100B ASE-TX idle or
fast link pulses from i ts link partner. I f either idle pattern i s detected, the 78Q8430 PHY configures itself
in half- duplex m ode at the appropriate s peed. If it detects fa st l i nk pulses, it decode s and analyzes the
link code transmitted by the link part ner. When three identical link code words are received (ignoring the
acknowledge bit ), the link code word is stored in register 5. Upon receiving three more i dentical link co de
words, with the acknowledge bit set, the 78Q8430 PHY conf i gures itself to the hi ghest priority technology
common to the two l ink partners. The te chnology prioriti es are, in descending order:
• 100BASE-TX, Full Duplex.
• 100BASE-TX, Half Duplex.
• 10BASE-T, Full Duplex.
• 10BASE-T, Half Duplex.
Once auto-negotiation is complete, register bits M R18[11:10] will refl ect the actual speed and duplex that
was chosen. If auto-negotiation fails t o est abl ish a link for any reason, register bit M R18[12] will reflect
this and auto negotiat i on will restart from the beginning. Writ i ng a one to bit MR0[9], RANEG, will also
cause auto nego tiation to restart.
6.12.10 LED Indicators
Two LED pins can be used to indicate v arious states of operat ion of the 78Q8430 PHY. T he default
configuration use s LE D0 to indicate the li nk i s up and LED1 to indi cate either RX or TX acti vity. LED0
and LED1 may be redef i ned via MR23. There is no direct hardware for controlling the M A C from the PHY
LED status, therefore software drivers m ust obtain the DUPLEX and S PEED parameters from the PHY
register MR18[11:10] and configure the MAC accordi ngly .
6.12.11 PHY Interrupts
The 78Q8430 P HY has an Interrupt signal that is asserted whenever any of the eight int errupt bits of
MR17[7:0] are set . The PHY bit in the Host Interrupt Register (HIR) is set to indicate and interrupt from
the PHY. Indiv i dual P HY interrupt conditi ons c an be enabled via MR17, bits 15:8, the PHY Interrupt
Enable bits. PHY int errupt bits are cleared when MR17 is read.
6.12.12 Internal Clock PLL
When the internal clock mode is selecte d by the CLKMODE pin, the 100 MHz system clock is provided by
a PLL inside the PHY. This PLL multipli es t he frequency of the 25 M Hz P LL crystal oscillat or up to the
100 MHz needed to run the system clo ck.
When the PHY is powered down, the PLL used to generate the internal system clock is also powered
down and ceases to function. For this reason, the internal PHY should never be powered down when the
internal system clock is selected by the CLK M ODE pin.
There is no external visibility for the system clock when t he i nternal clock mode is selected. The GBI
interface mus t therefore always be used in asynchron ous bus mode when the internal clock m ode i s
used.
78Q8430 Data Sheet DS_8430_001
52 Rev. 1.2
7 Register Descriptions
7.1 Register Overview
The 78Q8430 has 10 address bits for a total address space of 1024 bytes. This address space is divid ed
into four 256-locati on blocks: QUE, CTL, Reserved and S NOOP.
The QUE secti on cont ains registers used to control transmit and receive queues. Each queue is
allocated eight 32-bi t registers for a m aximum of eight queues supported.
The CTL section contains control r egisters used to control the behavior of 78Q8430.
A block of 256 addresses is reserved for future use.
The SNOOP section i s mapped to cache mem ory via the Snoop Control Register.
Address Range
Group
0x000
QUE
…
0x0FF
0x100
CTL
…
0x1FF
0x200
Reserved
…
0x2FF
0x300
SNOOP
…
0x3FF
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 53
7.2 QUE Register Overview
Address Range
QUE #
Symbol
Name
0x000-0x01C QUE 0
0x00 PCWR Packet Contr ol Word Register
0x04 PSZR Packet Size Regist er
0x08 STDR Setup Transm i t Data Register
0x0C TDR Transmit Dat a Register
0x10 RDR Receive Data Register
0x14 Reserved
0x18 QFLR QUE First/Last poi nters.
0x1C QSR QUE Status Register
0x020-0x03F QUE 1
… QUE 1 Registers
0x040-0x05F QUE 2
… QUE 2 Registers
0x060-0x07F QUE 3
… QUE 3 Registers
0x080-0x09F QUE 4
… QUE 4 Registers
0x0A0-0x0BF QUE 5
… QUE 5 Registers
0x0C0-0x0DF QUE 6
… QUE 6 Registers
0x0E0-0x0FF QUE 7
… QUE 7 Registers
78Q8430 Data Sheet DS_8430_001
54 Rev. 1.2
7.3 CTL Register Overview
Address Symbol Page Name
0x100 DMA 59 DMA Slave Mode Control a nd Status
0x104 RPSR 59 Receive Packet Status FIFO
0x108 TPSR 59 Transmit Packet Status FIFO
0x10C TPROS 60 Transmit Producer Status
0x110 RPROS 60 Receive Prod ucer Status
0x114 Reserved
0x118 GBI_ID 61 Part ID Register
0x11C GBI_CS 61 Configurat i on Register
0x120 Reserved
0x124 Reserved
0x128 RTTR 61 Receive to Transmit Transfer Register
0x12C FDR 61 Frame Disposition Register
0x130 RFBSR 61 Receive FIRST BLOCK Status Register
0x134 RDSR 62 Receive Data Status Register
0x138 BCR 62 BIST Control Regi ster
0x13C BBDR 63 BIST B ypass Mode Data Register
0x140 MDDAR 63 Station Mana gem ent Data Register
0x144 MDCAR 63 Station Management Control and Address Register
0x148 PRDR 63 PROM Data
0x14C PRCR 64 PROM Contr ol
0x150 Reserved
0x154 MCR 64 MAC Control Regi ster
0x158 Reserved
0x15C Reserved
0x160 Reserved
0x164 CDR 65 Count Data Register
0x168 CCR 65 Count Contr ol Register
0x16C CMR 66 Count M anagement Register
0x170 SNCR 66 Snoop Control Register
0x174 -
0x17C Reserved
0x180 IDCR 66 Interrupt Delay Count Register
0x184 PDCR 66 Pause Delay Count Regist er
0x188 HNRCR 67 Host Not Responding Count Register
0x18C WUSR 67 Wake Up Status Re gist er
0x190 WMVR 67 Water Mark Values Register
0x194 Reserved
0x198 PMCAP 67 Power Mana gem ent Capabilities
0x19C PMCSR 68 Power Mana gem ent Control and St atus
0x1A0 CAR 68 Address of CAM rule being access ed
0x1A4 RMR 69 Rule Mat ch Register
0x1A8 RCR 69 Rule Control Register
0x1AC Reserved
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 55
Address
Symbol
Page
Name
0x1B0 Reserved
0x1B4 Reserved
0x1B8 Reserved
0x1BC Reserved
0x1C0 QSIR 70 QUE St atus Interrupt Register
0x1C4 QSMR 70 QUE Status Mask Register
0x1C8 OUIR 71 Overf l ow/Underrun Interrupt Register
0x1CC OUMR 71 Overflow/Underr un Mask Regist er
0x1D0 TRIR 71 Transmit RMON Interrupt Register
0x1D4 TRMR 72 Transmit RMON Mask Register
0x1D8 RRIR 72 Receive RMON Interrupt Register
0x1DC RRMR 72 Receive RMON Mask Register
0x1E0 Reserved
0x1E4 Reserved
0x1E8 HIR 72 Host Interrupt Register
0x1EC HIMR 73 Host I nterrupt Mask Register
0x1F0 Reserved
0x1F4 Reserved
0x1F8 Reserved
0x1FC Reserved
7.4 Snoop Address Space Overview
0x300-0x3FF SNOOP Accessing da ta in this address space will be
mapped to the contents of the buffer memory
BLOCK indicated by the SNCR.
78Q8430 Data Sheet DS_8430_001
56 Rev. 1.2
7.5 QUE Registers
7.5.1 Packet Control Word Register
Name: PCWR
Reset Val: 0x0000_0000
Block: QUE
Address: 0x000
Bits Type Default Description
31:30 X Reserved
29:25 WO N/A Preload
The number of by tes to pre-load into the MAC TX FIFO before the
frame begins trans m i ssion to the PHY. This may need to be non-zero
for large IP heade rs t hat want to have t he checksum inserted to ensure
the checksum i s not transmitt ed before the end of the header is loaded.
24:16 WO N/A Packet I D
The 9-bit ID value used to identify this packet in the TX st atus FIFO.
15:10 WO N/A IP Header Offset
Offset in bytes t o the IP header in this frame. If this value i s non-zero
then the IP header checksum will be corrected.
9 WO N/A Append CRC
When set, the trans m itter shall append the correct CRC checksum to
the end of the f ram e.
8 WO N/A Fix CRC
When set, the trans m itter shall correct the existing CRC checksum on
the end of the pac ket .
7 X Reserved
6 WO N/A Disable Padding
For small packets (<64 Bytes).
5 WO N/A Late Notify
Interrupt on compl etion.
4 WO N/A Early Notify
Interrupt at beginning of transmission.
3 WO N/A Interrupt on excessive collisions.
2 WO N/A Disable deferral timeout.
1 WO N/A Enable fast bac k-off timer.
0 X Reserved
7.5.2 Packet Size Register
Name: PSZR
Reset Val: 0x0000_0000
Block: QUE
Address: 0x004
Bits Type Default Description
31:16 X Reserved
15:0 RW 0000 Packet Size
The size, in bytes, of the packet that will be added to the QUE.
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 57
7.5.3 Setup Transmit Data Register
Name: STDR
Reset Val: 0x0000_0000
Block: QUE
Address: 0x008
Bits Type Default Description
31:25 X Reserved
24 RW Endian
The network transmi t byte order.
Set = big endian (Mo st significant byte t ransmit first)
Clear = little endian (Least significant byte transmit fi rst)
23:20 X Reserved
19:18 RW 00 Start Offset
The number of by tes to ignore on the first data word written for this
buffer. This byte mask is a ppli ed any time the Count value is
non-zero. After each time it is appli ed, however, it i s reset to zero such
that it is really only applied on the first write.
17:16 RW 00 En d Offset
The number of by tes to ignore on the la st data word written for this
buffer. This byte mask is applied any time the Count value i s zero.
Unlike the Start Offset, the End Of fset is not self clearing. This means
that the End Offset will be applied to all writes to the QUE once the
Count value reac hes zero, unless the host clears the End O ffset. The
remainder of PS ZR wil l override the End Offset when a write occ urs
and the PSZR value i s less than four.
15:14 X Reserved
13:0 RW 0000 Count
The total number of writes needed to co m pl ete the buffer minus one.
This counter dec rements on each write operation to the QUE. T his
counter decrem ents on each write oper ation to the QUE unt il i t reaches
zero. The Count v al ue wil l remain zero unt i l the next host write. T he
value written here must be one less than the number of writes in the
buffer so that t he Count value will equal zer o on the last write and
cause the End Offset to be applied.
Note: The PCWR and PSZR must be set before writing to t he S T DR.
7.5.4 Transmit Data Register
Name: TDR
Reset Val: 0x0000_0000
Block: QUE
Address: 0x00C
Bits Type Default Description
31:0 WO N/A Packet Data to Add to the QUE
Data written to this register is added to the QUE to which the register
belongs.
7.5.5 Receive Data Register
Name: RDR Reset Val: 0x0000_0000 Block: QUE Address: 0x010
Bits Type Default Description
1:0 RO N/A Packet Data Read from the QUE
Data read from t hi s register is shifted out of the QUE to whi ch t he
register belongs. The RPSR should be consulted t o m ake sure data is
available before reading this register.
78Q8430 Data Sheet DS_8430_001
58 Rev. 1.2
7.5.6 QUE First/Last Register
Name: QFLR
Reset Val: 0x0000_0000
Block: QUE
Address: 0x018
Bits Type Default Description
31:23 X Reserved
22:16 RW 0x00 Last
The value of the La st poi nter for this QUE.
15:7 X Reserved
6:0 RW 0x00 First
The value of the First pointer for this QUE.
Note: The default values will vary for static QUEs 2 and 5.
7.5.7 QUE Status Register
Name: QSR
Reset Val: 0x0000_0000
Block: QUE
Address: 0x01C
Bits
Type
Default
Description
31 RW 0 QDR
QUE data is ready.
30 RW 0 Pause Mask
When set, pause mo de has no effect on the QDR bit for this QUE. The
default behavior wh en clear is to disallow the setting of the QDR bit in
pause mode.
29:26 X Reserved
25:24 RW 00 Mode
The current QSR v al ue for the QDR mode.
00 = QDR set when First is not 0
01 = QDR set when a bove is set.
10 = QDR set when LEOP is not zero.
11 = QDR set when a bove is set or LEO P is not 0.
23:19 X Reserved
18 RO 0 EOP
The QUE contains at l east one EOP.
17 RO 0 Above
The Count value is ab ove the threshold.
16 RO 0 Below
The Count value is bel ow the threshold.
15 X Reserved
14:8 RW 0x00 Threshold
The number to compare to Count to determine the above and below
bits.
7 X Reserved
6:0 RO 0x00 Count
The total number of B LOCKs assigned to this QUE.
Note: Only bits 31 and 30 are valid for s tatic QUEs 2 and 5.
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 59
7.6 CTL Registers
7.6.1 DMA Control and Status Register
Name: DMA
Reset Val: 0x0000_0000
Block: CTL
Address: 0x100
Bits Type Default Description
31:18 X 0 Reserved
17 RW 0 Read Mode
Once this bit is set t he host interface will be i n DMA read mode until the
bit is cleared by a write to this registe r.
16 RW 0 Write Mode
Once this bit is set t he ho st interface will be in DMA write mode unti l the
bit is cleared by a read to this register.
15:10 X 0 Reserved
9:0 RW 0 Address
The location of the register to direct DMA access to.
7.6.2 Receive Packet Status Register
Name: RPSR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x104
Bits
Type
Default
Description
31 RO 0 Done
When not set the packet is still in the proce ss of ingressing the QUE.
30 RO 0 Length Error
The packet length wa s not correct.
29 RO 0 Truncated
The packet was truncated and is incomplet e.
28 RO 0 Collision
The packet suffered a collision and is i ncomplete.
27 RO 0
MII Error
26 RO 0 Dangling Byte
The received packet l ength was not an int eger number of bytes.
25 RO 0 CRC
Ethernet CRC checksum error.
24 RO 0 Checksum
IP Header checksum error.
23:16 RO 0 Classification
The packet clas sif i cat i on results.
15:0 RO 0 Count
The total number of bytes currently i n the QUE for this packet. When
the Done bit is set, this represents the actual packet size.
7.6.3 Transmit Packet Status Register
Name: TPSR
Reset Val: 0x0E00_0000
Block: CTL
Address: 0x108
Bits
Type
Default
Description
31 RO 0 Done
When not set, the frame is still in transm ission. When set, the content
is
egressing the QUE.
30 RO 0 Halted
The packet was halted.
29 RO 0 Truncated
The packet was trun cat ed and is incomplete.
78Q8430 Data Sheet DS_8430_001
60 Rev. 1.2
Name: TPSR
Reset Val: 0x0E00_0000
Block: CTL
Address: 0x108
Bits
Type
Default
Description
28 RO 0 Carrier
Loss of carrier during transmission.
27:25 RO 7 QUE
The number of t he Q UE that was the source f or this packet.
24:16 RO 0 Packet ID
The packet ID that was assigned to this packet by the PCWR when it
was loaded int o the QUE.
15:13 X Reserved
12 RO 0 No Heart Beat
No heartbeat was detected at the end of transmission.
11 RO 0 Excessive Deferrals
10 RO 0 Deferred
9 RO 0 Late Collision
8 RO 0 Excessive Collisi on s
7:4 X Reserved
3:0 RO 0 Collision Count
The number of collisions experience d by this packet.
Note: When the Done bit is not set, the Collision Count field may not be correct . In this case, a non-zero
value does indicate that the frame c urrently being transmitted has ex perienced at least one collision, but
the actual count value may not be correct until the Done bi t is set.
7.6.4 Transmit Producer Status
Name: TPROS
Reset Val: 0x0000_0000
Block: CTL
Address: 0x10C
Bits Type Default Description
31:8 X Reserved
7 RO 0 QUE7: QUE is dropping a packet.
6 RO 0 QUE6: QUE is dropping a packet.
5 RO 0 QUE5: QUE is dropping a packet.
4 RO 0 QUE4: QUE is dropping a packet.
3 RO 0 QUE3: QUE is dropping a packet.
2 RO 0 QUE2: QUE is dropping a packet.
1 RO 0 QUE1: QUE is dropping a packet.
0 RO 0 QUE0: QUE is dropping a packet.
7.6.5 Receive Producer Status
Name: RPROS
Reset Val: 0x0000_0000
Block: CTL
Address: 0x110
Bits Type Default Description
31:8 X Reserved
7 RO 0 QUE7: QUE is dropping a packet.
6 RO 0 QUE6: QUE is dropping a packet.
5 RO 0 QUE5: QUE is dropping a packet.
4 RO 0 QUE4: QUE is dropping a packet.
3 RO 0 QUE3: QUE is dropping a packet.
2 RO 0 QUE2: QUE is dropping a packet.
1 RO 0 QUE1: QUE is dropping a packet.
0 RO 0 QUE0: QUE is dropping a packet.
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 61
7.6.6 Revision ID
Name: ID
Reset Val: 0x8430_0102
Block: CTL
Address: 0x118
Bits Type Default Description
31:16 RO 8430 P rod ID
Indicates the product number.
15:8 RO 2 Ver ID
Indicates the product version number.
7:0 RO 1 Rev ID
Indicates the sili con revision numbe r.
7.6.7 Configuration
Name: GBI_CS
Reset Val: 0x0000_0000
Block: CTL
Address: 0x11C
Bits
Type
Default
Description
31:5 X Reserved
4:0 RO 0 CONF
The current status of the configurat i on pins.
7.6.8 Receive to Transmit Transfer Register
Name: RTTR Reset Val: 0x0000_0000 Block: CTL Address: 0x128
Bits Type Default Description
31:1 X Reserved
0 RW 0 Transfer
Writing a one to this bit signals the QUE logic to transfer the QUE0
FIRST BLOCK to QUE 3. The QUE logic clears t he bit when the
operation is complete.
7.6.9 Frame Disposition Register
Name: FDR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x12C
Bits Type Default Description
31:1 Reserved
0 W Drop Rx Frame
Writing a 1 to this bit causes the Rx consum er to drop the current frame
entirely from the QUE.
7.6.10 Receive FIRST BLOCK Status Register
Name: RFBSR
Reset Val: 0x0002_0000
Block: CTL
Address: 0x130
Bits Type Default Description
31:18 Reserved
17 R 1 EOF
The FIRST BLOCK is the end of its fra m e.
16 R 0 ERR
The FIRST BLOCK is the end of a trunc ated frame.
15 Reserved
14:8 R 00 Next
The BLOCK that i s nex t in QUE0 after the cur rent FIRST BLO CK .
7:0 R 00 Used
The number of v al id bytes in the FIRST BLOCK for QUE0.
78Q8430 Data Sheet DS_8430_001
62 Rev. 1.2
7.6.11 Receive Data Status Register
Name: RDSR
Reset Val: 0x0001_0000
Block: CTL
Address: 0x134
Bits Type Default Description
31:25 Reserved
24 R 0 EOF
When set this bit i ndi cat es that the next data word read from QUE 0 will
be the end of its f ram e.
23:17 Reserved
16 R 1 QUE0 Empty
When set this bit indi cat es that QUE0 cont ai ns no data.
15:2 Reserved
1:0 R 00b QUE0 Dat a Size
The number of v al id bytes in the next data word read from QUE0.
7.6.12 BIST Control Register
Name: BCR
Reset Val: 0x2010_0000
Block: CTL
Address: 0x138
Bits Type Default Description
31 W BIST Start
Writing a 1 to this bit triggers the selected BIST test (s ee BIST Mode
below).
30 R 0 Fail
The BIST operation fai l ed.
29 R 1 Pass
The BIST operation p assed.
28:21 Reserved
20 R/W 1 Auto Increment
When set, the RAM A ddress field will auto-increment after each RAM
access.
19 R/W BIST Enable
Enable BIST mode op eration.
18:16 R/W 000 BIST Mode
Set the BIST test mode:
000b – Reserved.
001b – PATTERN.
010b – FILL 0.
011b – READ 0.
100b – FILL 1.
101b – READ 1.
110b – BYPASS.
111b – Reserved.
15:14 Reserved
13:0 R/W 0x000 RAM Addr e ss
Set the address of the RAM that is accessed via BBDR in BYPASS
mode.
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 63
7.6.13 BIST Bypass Mode Data Register
Name: BBDR
Reset Val: N/A
Block: CTL
Address: 0x13C
Bits Type Default Description
31:0 R/W RAM Data
Reads and writes to these bits go direct ly to the QMEM RAM at the
location indicated by BCR only when the BIST mode is set to BYPASS.
7.6.14 Station Management Data Register
Name:
MDDAR
Reset Val:
0x0000_0000
Block:
CTL
Address:
0x140
Bits Type Default Description
31:16 X 0000 Reserved
15:0 RW 0 SMI Data
Data read from or dat a to be written to t he PHY. See Section 7.7.
7.6.15 Station Management Control and Address Register
Name: MDCAR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x144
Bits
Type
Default
Description
31:13 X 0000 Reserved
12 RW 0 Preamble
Writing a 1 suppres ses the generation of the 32-bit PHY station
management prea m bl e before the PHY register transfer. The i nternal
PHY of the 8430 does not require the preamble.
11 RW 0 Busy
Writing a 1 initiat es t he P HY register transfer. T he hardware will c l ear
the bit when the operation completes.
10 RW 0 RegWr
Writing a 1 indicated the MDDAR data is to be written to the PHY.
Writing a 0 causes the P HY register to be read and the data placed in
the MDDAR .
9:5 RW 0 PHY Addr
Address of the PHY to access.
4:0 RW 0 PHY Reg
Address of the PHY register to acces s.
7.6.16 PROM Data Register
Name: PRDR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x148
Bits Type Default Description
31:16 X 0000 Reserved
15:0 RW 0000 PROM Data
Data to write to or read from the EE P ROM device.
78Q8430 Data Sheet DS_8430_001
64 Rev. 1.2
7.6.17 PROM Control Register
Name: PRCR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x14C
Bits Type Default Description
31:9 X 0000 Reserved
8 RW 0 Busy
Writing a 1 initiat es t he E EPROM data transfer. The hardware will clear
the bit when the operation completes.
7:6 RW 0x0 Operation
1 1 = Erase.
1 0 = Read.
0 1 = Write.
0 0 = Enable or Disable Writing, as speci fied in PROM Addr:
[5:4] = 11, Enable
[5:4] = 00, Disable
5:0 RW 0x00 PROM A ddr
Address of the EEPROM to access.
7.6.18 MAC Control Register
Name: MCR
Reset Val: 0x0080_0050
Block: CTL
Address: 0x154
Bits
Type
Default
Description
31:28 X 0000 Reserved
27 RW 0 Tx Enable
When this bit is clear transmitting stops immediately.
26 RW 0 Tx Halt
When this bit is set transmitting stops at the end of the cur rent frame.
25 RW 0 Rx Enable
When this bit is clear receiving stops immediately.
24 RW 0 Rx Halt
When this bit is set r eceiving stops at the end of the current frame.
23 RW 1 Rx Drop Error
When this bit is set then an error in the fi rst 256 bytes will ca use a
packet to be dropped. If clear, error packets are forw arded to the host.
22 RW 0 Keep Dropped Status
Normally, the st atus for a dropped fram e is not added to t he receive
status FIFO. When this bit is set then a status for all frames, including
dropped frames, i s added to the receive st atus FIFO. The stat us for a
dropped frame wil l have a size of zero in the RPSR.
21 RW 0 Jumbo OK
Normally fram es in excess of the maxi m um al l owed by 802.3 are
flagged as bad. If this bit is set then larg er frame sizes are allowed.
20:18 0000 Reserved
17 RW 0 MACRST
Software re-initialization. Setting this bit will also automat i cally set both
Rx and Tx Halt bits and clear both Rx and Tx Enable bits. This bit is
only cleared by writ i ng a zero.
16 RW 0 MACLOOP
Loopback mode for t he M AC.
15:8 X 0x000 Reserved
7 RW 0 No Rx PAD
Strip the padding by tes from the end of rec ei ved frames that are 64
bytes in length. When the padding is stripped from a frame the CRC is
stripped as well.
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 65
6 RW 1 FullDup
1 = Full Duplex
0 = Half Duplex
The default setti ng for the MAC is full duplex mode. This bit need s to
be updated each time there is a link status change in the PHY.
5 RW 0 SQE
Enable SQE checking.
4 RW 1 No Ex Diff
Disable checking f or excessive deferrals.
3 X 0 Reserved
2 X 0 Reserved
1 RW 0 No Rx CRC
When this bit is set, the MAC receiver will strip the CRC bytes f rom the
end of received f rames after the CRC check is complete.
0 RW 0 No CRC Chk
When this bit is set, CRC checking is disabled. This bit should never be
set when the No Rx CR C bit is set as there will be no way to verify the
CRC.
7.6.19 Count Data Register
Name: CDR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x164
Bits
Type
Default
Description
31:0 RW Count
Value of the counter indicated by CCR.
7.6.20 Counter Control Register
Name: CCR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x168
Bits Type Default Description
31:11 X Reserved
10 RW Auto Increment
When this bit is set, the address of the counter being acce ss ed i s
automatically i ncr em ented after each access to the CDR.
9 RW Clear on Read
When this bit is set, the counter being read is automatically cleared to
zero after each access to the CDR.
8 RW Access Mode
When this bit is clear, the CDR is in read mode. Wh en set, the CDR is
in write mode.
7:6 X Reserved
5:0 RW Address
Address of the cou nter to access. (00 to 0E, Transmit Count ers; 0F to
25, Receive Counters)
78Q8430 Data Sheet DS_8430_001
66 Rev. 1.2
7.6.21 Counter Management Register
Name: CMR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x16C
Bits Type Default Description
31:3 X Reserved
2 RW Freeze
When this bit is set, the values of the co unters are frozen until the bit is
cleared. Count able events that occu r while this bit is set are stored in a
FIFO and proce ss ed after the bit is cleared such that no counts are lost.
If the FIFO f i l ls before the Freeze bit is cleared then the bit i s
automatically cleared and the counters updated.
1 W Clear Receive
When a 1 is written to this bit then all receive counters are automatically
cleared.
0 W Clear Transmit
When a 1 is written to this bit than all transmit counters are
automatically cleared.
7.6.22 Snoop Control Register
Name: SNCR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x170
Bits
Type
Default
Description
31:7 X Reserved
6:0 RW 0x00 BLOCK
Pointer to the BLOCK that is accessed directly via the SNOOP register
space.
7.6.23 Interrupt Delay Count Register
Name: IDCR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x180
Bits
Type
Default
Description
31:24 X Reserved
23:0 RW IDC
How long to delay the data received interrupt, measured i n byte times.
7.6.24 Pause Delay Count Register
Name: PDCR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x184
Bits
Type
Default
Description
31:17 X Reserved
16 WO Start
Start local pause. W riting a one to this bi t triggers a local p ause
condition immedi ately.
15:0 RW Pause
How long to halt transmit QUEs for a lo cal pause condition, measured in
delay quanta of 512 Rx bit times.
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 67
7.6.25 Host Not Responding Count Register
Name: HNRCR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x188
Bits Type Default Description
31:0 RW Count
Number of system cycles to wait for t he host to respond t o a wake
condition before s ending an HNR response.
7.6.26 Wake Up Status Register
Name:
WUSR
Reset Val:
0x0000_0000
Block:
CTL
Address:
0x18C
Bits Type Default Description
31:8 X Reserved
7:0 RO Class
The classificat i on result that triggere d the wake up event.
7.6.27 Water Mark Values Register
Name: WMVR
Reset Val: 0x0000_0400
Block: CTL
Address: 0x190
Bits
Type
Default
Description
31 X Reserved
30:24 RO 0x7D Free
A count of the number of free memory bl ocks in the memory ma nager.
23 X
Reserved
22:16 RW 0x00 Interrupt
Minimum number of free blocks before the host is interrupted.
15 X Reserved
14:8 RW 0x04 Headroom
Minimum number of free blocks before the MAC receiv er i s halted.
7 X Reserved
6:0 RW 0x00 PAUSE
Minimum number of free blocks before the PAUSE packet is sent.
Note: For all watermarks, a value of zero will disable the related feature.
7.6.28 Power Management Capabilities
Name: PMCAP
Reset Val: 0x120A_4801
Block: CTL
Address: 0x198
Bits
Type
Default
Description
31:27 RO 0x02 Support
Power management ev ents supported. This f i el d always reads back
00010b to indicate PME from D1 is supported.
26 RO 0 D2 Support
Reads back 0 to indi cat e D2 is not supported.
25 RO 1 D1 Support
Reads back 1 to indi cat e D1 is supported.
24:20 RO 0x00 Init
Reads back 00000 b to indicate no devi ce specific initializat i on.
19 RO 1 CLK
Reads back 1 to indi cat e the clock (BUSCLK ) is needed for PME
operation.
18:16 RO 010 VER
Reads back 010b to i ndicate specification version 1.1 compl iance.
78Q8430 Data Sheet DS_8430_001
68 Rev. 1.2
Name: PMCAP
Reset Val: 0x120A_4801
Block: CTL
Address: 0x198
Bits
Type
Default
Description
15:8 RO 0x48 Next
Reads back 0x48. Points to next capability.
7:0 RO 0x01 ID
Reads back 0x01.
7.6.29 Power Management Control and Status Register
Name: PMCSR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x19C
Bits
Type
Default
Description
31:24 X Reserved
23:22 RW 00 Psmarg1
Voltage regulat or #1 m argin.
21:20 RW 00 Psmarg2
Voltage regulat or #2 m argin.
19:18 RW 00 Psmarg3
Voltage regulat or #3 m argin.
17:16 X Reserved
15 RW 0 PME
Power management ev ent status. This bit is set by a WAKE signal from
the CAM and only cleared when the host writes a 1 to thi s bit.
14:9 X Reserved
8 RW 0 PME_ENB
Enables assertion of PME when there is a power management event.
7:2 X Reserved
1:0 RW 00 PS
Present power management state, 01b = D1, 00b = D0. (Any non-zero
value here tells the part that the host is i n power down mode). In any
state other than D0, wake signals from classification are allowed to
generate PME interrupts and the m ovement of receive data into QUEs
is inhibited.
7.6.30 CAM Address Register
Name: CAR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1A0
Bits
Type
Default
Description
31:7 X Reserved
6:0 RW 0x00 ADDR
CAM address of rul e bei ng accessed by the RMR and RCR.
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 69
7.6.31 Rule Match Register
Name: RMR
Reset Val: 0xFE3E_FF00
Block: CTL
Address: 0x1A4
Bits Type Default Description
31:25 RW 0x7F Previous Hit Mask
Mask bits to mat ch for the previous hit m atch. A zero means the
corresponding bit in the previous hit match doe s not have to matc h to
be a hit.
24 X Reserved
23:17 RW 0x1F Previous Hit Match
This CAM entry m atches against the address of the previous CAM hit.
16 X Reserved
15:8 RW 0xFF Data Mask
Mask bits to mat ch for the data match. A zero means the
corresponding bit in the data match does not have to match to be a hit.
7:0 RW 0x00 Data M atch
This CAM field mat ches against either t he packet byte or the co ntrol
logic ‘X’ regist er value selected by the match control field of the control
word register.
Note:
1. If all previous hi t mask bits are zero, then the rule is disabled and will never match.
2. The RMR value i s not valid for CAR ADDR val ues of zero or one.
7.6.32 Rule Control Register
Name: RCR
Reset Val: 0x0000_0002
Block: CTL
Address: 0x1A8
Bits Type Default Description
31:22 X Reserved
21:16 RW 0x00 Byte Offset
When this rule matches, do not attempt another match f or this number of
bytes. A zero means t hat the very next byte will be execut ed. A value of
one means that the very next packet byt e i s ignored but the byt e after
that is executed, etc. When this field is used to initialize t he counter, no
offset is applied (see the TOC Control Logic A ct i on).
15:8 X Reserved
7 RW 0 Interrupt
When a match is made f or this rule then trigger an interrupt to the host.
6:2 RW 0x0 Control Logic Action
Specifies what act i on to take when a match is made.
The Control Logic Acti ons are described i n detail in Table 26.
0x0 = NOP 0x14 = THXA
0x2 = PAUSE 0x15 = SETMC
0x4 = WAKE 0x16 = VLAN
0x6 = IPCK 0x17 = SETBC
0x7 = TIPO 0x18 = TOC
0x8 = TDX 0x1A = DEC
0xA = TAX 0x1B = MCTL
0xC = TAXH 0x1C = TDPH
0xD = TAXL 0x1D = TDLTH
0x10 = TXA 0x1E = TDPL
0x12 = TLXA 0x1F = TDLTL
78Q8430 Data Sheet DS_8430_001
70 Rev. 1.2
Name: RCR
Reset Val: 0x0000_0002
Block: CTL
Address: 0x1A8
Bits
Type
Default
Description
1:0 RW 10 Match Control
How to generate a CA M reference word for the next pass. Mat ch c ontrol
is described in detai l i n Table 27.
00 = DONE
10 = MD
01 = MX
11 = DROP
7.6.33 Que Status Interrupt Register
Name: QSIR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1C0
Bits
Type
Default
Description
31 RO QDR Rise
Rising edge detect ed on QUE 7 QDR bit.
30 RO QDR Fall
Falling edge detect ed on QUE 7 QDR bi t.
29 RO A Rise
Rising edge detect ed on QUE 7 QSR A bit. (See QSR)
28 RO B Rise
Rising edge detect ed on QUE 7 QSR B bit. (See QSR)
27:24 RO QUE 6
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 6.
23:20 RO QUE 5
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 5.
19:16 RO QUE 4
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 4.
15:12 RO QUE 3
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 3.
11:8 RO QUE 2
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 2.
7:4 RO QUE 1
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 1.
3:0 RO QUE 0
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 0.
Note: All bits are cle ared on read.
7.6.34 Que Status Mask Register
Name: QSMR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1C4
Bits Type Default Description
31:0 RW QUE Status Interrupt Mask
When a bit is set it enables the QUE status interrupt for the
corresponding bit in the QSIR. When a bit is clear, t he corresponding
bit in the QSIR will still be set on i ts event and cleare d on read but will
not be passed on t o the HIR.
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 71
7.6.35 Overflow/Underrun Interrupt Register
Name: OUIR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1C8
Bits Type Default Description
31 RO 0 QUE Data Overflow
Overflow condit ion detected on QUE 7.
30 RO 0 QUE Data Underrun
Under-run condit i on detected on QUE 7.
29:28 RO 00 Reserved
27:26 RO 0x0 QUE 6
QUE Data Overfl ow and QUE Data Und errun bits for QUE 6.
25:24 RO 00 Reserved
23:22 RO 0x0 QUE 5
QUE Data Overflow and QUE Data Und errun bits for QUE 5.
21:20 RO 00 Reserved
19:18 RO 0x0 QUE 4
QUE Data Overflow and QUE Data Und errun bits for QUE 4.
17:16 RO 00 Reserved
15:14 RO 0x0 QUE 3
QUE Data Overflow and QUE Data Und errun bits for QUE 3.
13:12 RO 00 Reserved
11:10 RO 0x0 QUE 2
QUE Data Overflow and QUE Data Und errun bits for QUE 2.
9:8 RO 00 Reserved
7:6 RO 0x0 QUE 1
QUE Data Overflow and QUE Data Underrun bi ts for QUE 1.
5:4 RO 00 Reserved
3:2 RO 0x0 QUE 0
QUE Data Overflow and QUE Data Und errun bits for QUE 0.
1:0 RO 00 Reserved
Note: All bits are cle ared on read.
7.6.36 Overflow/Underrun Mask Register
Name: OUMR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1CC
Bits Type Default Description
31:0 RW 0x0000
0000 Overflow/Underrun Interrupt Mask
When a bit is set, it enabl es the overflow/underrun interrupt for the
corresponding bit in the OUIR. When a bit is clear, t he corresponding
bit in the OUIR will still be set on its event and cleare d on read but will
not be passed on t o the HIR.
7.6.37 Transmit RMON Interrupt Register
Name: TRIR Reset Val: 0x0000_0000 Block: CTL Address: 0x1D0
Bits Type Default Description
31:0 RO 0x0000
0000 RMON Tx Counter Roll over
Set when the RMO N Tx counter with the same index number as the bit
number has rolled ov er.
Note: All bits are cle ared on read.
78Q8430 Data Sheet DS_8430_001
72 Rev. 1.2
7.6.38 Transmit RMON Mask Register
Name: TRMR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1D4
Bits Type Default Description
31:0 RW 0x0000
0000 Tx RMON Interrupt Mask
When a bit is set, it enabl es the Tx RMON interrupt for the
corresponding bit in the TRIR. When a bit is clear, the corresponding
bit in the TRIR will still be set on i ts event and cleare d on read but will
not be passed on t o the HIR.
7.6.39 Receive RMON Interrupt Register
Name: RRIR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1D8
Bits Type Default Description
31:0 RO 0x0000
0000 RMON Rx Counter Rollover
Set when the RMO N Rx counter with an index equal to the bit number
plus 32 has rolled ov er.
Note: All bits are cle ared on read.
7.6.40 Receive RMON Mask Register
Name: RRMR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1DC
Bits
Type
Default
Description
31:0 RW 0x0000
0000 Rx RMON In terrupt Mask
When a bit is set, it enabl es the Rx RMON interrupt for the
corresponding bit in the RRIR. When a bit i s clear, the corresponding
bit in the RRIR will still be set on its event and cleared on read but will
not be passed on t o the HIR.
7.6.41 Host Interrupt Register
Name: HIR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1E8
Bits Type Default Description
31:21 X 0x000 Reserved
20 RO 0 WAKE
PME is asserted low (a power event has occu rred).
19 RO 0 QUE Status
QSIR interrupt.
18 RO 0 QUE Overflow/Underrun
OUIR interrupt.
17 RO 0
PHY
16 RO 0
RMON
15:13 X 0 Reserved
12 RO 0 Tx Bad
A transmitted frame had an error.
11 RO 0 Rx Bad
A frame was received with an error.
10:9 X Reserved
8 RO 0 Late Rx Notify
This interrupt is asserted each time an entire frame is added to the
receive QUE.
7 RO 0 Early Rx Notify
Data reception has started (delayed by the IDCR).
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 73
Name: HIR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1E8
Bits
Type
Default
Description
6 RO 0 Reserved.
5 RO 0 Late Tx Notify
Interrupt on compl etion. (See PCWR)
4 RO 0 Early Tx Notify
Interrupt at t he st art of transmission. (S ee PCWR)
3 RO 0 WATER MARK
Interrupt when t he free BLOCK count hits the low water mar k.
2 RO 0 QUE Overflow
Interrupt when a QUE requests memory and there is none.
1 RO 0 PAUSE
Interrupt when t he local pause changes state (on/off).
0 RO 0 Class
Packet classifi cat i on i nterrupt.
Note: Bits 15: 0 are cleared on read. Bits 31:16 are only clear ed when the source is cle ared.
7.6.42 Host Interrupt Mask Register
Name: HIMR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1EC
Bits Type Default Description
31:0 RW Host Interrupt Mask
When a bit is set here it enables the host interrupt for the corre sponding
bit in the HIR. When a bit is clear here, the correspon di ng bi t in the HIR
will still be set on i ts event and cleared on read but will not tri gger an
interrupt on INT.
78Q8430 Data Sheet DS_8430_001
74 Rev. 1.2
7.7 PHY Management Registers
7.7.1 PHY Register Overview
The 78Q8430 P HY i m plements sixteen-bit registers which ar e accessible via th e M A C S tation
Management Acce ss Registers. The supported registe rs are shown below. Unsupported registers will be
read as all zeroes. T he 78Q8430 PHY resp onds to PHYAD value 00001b.
The types of PHY Register access are sum m arized in Table 34.
Table 34: PHY Register Group
Address
Symbol
Name
Default (Hex)
0 MR0 Control 3100
1 MR1 Status (7849)
2 MR2 PHY Identifier 1 000E
3 MR3 PHY Identifier 2 7237
4 MR4 Auto-Negotiation Advertisement (01E1)
5 MR5 Auto-Negotiation Link Partner Ability 0001
6 MR6 Auto-Negotiation Expansion 0000
7-15 Reserved 0000
16 MR16 Vendor Specif i c (0140)
17 MR17 Interrupt Control/Status 0000
18 MR18 Diagnostic Regist er 0000
19 MR19 Transceiver Control 4XXX
20-22 Reserved XXXX
23 MR23 LED Configuration 0010
24 MR24 MDI/MDIX Control (00C0)
Notes:
1. These registers can only be accessed i ndirectly via t he MDDAR and MDCAR registers. They cannot
be accessed direct l y through the GBI address space.
2. The default values annotated with () are dependent on conf iguration states.
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 75
7.7.2 PHY Control Register – MR0
Bits
Symbol
Type
Default
Description
15 RESET R/WC 0 Reset
Setting this bit to 1 resets the device and sets all registers to
the default states. This bit is self-clearing.
14 LOOPBK R/W 0 Loopback
When this bit is set to 1, input data at TXD[3:0] is output at
RXD[3:0]. No transmission of dat a on the network medium
occurs and receive data on the networ k medium is ignore d.
By default, the loopback signal path encom passes most of the
digital functional bl ocks. This bit allo ws for diagnostic t est i ng.
13 SPEEDSL R/W 1 Speed Selection
This bit determi nes t he speed of operation of the 78Q8430
PHY. Setting this bit to 1 indicates 100Base-TX operation an d
a 0 indicates 10Bas e-T mode. This bit will default to 1 upon
reset. When auto-negotiation is en abl ed, this bit wil l not be
writable and will have no effect on the 78Q 8430 PHY. If
auto-negotiation is not enabled, this bit may be written to force
manual configuration.
12 ANEGEN R/W 1 Auto-negotiation Enable
The auto-negotiation process is enabled by setting this bit to 1.
This bit will default to 1. If this bit is cleared to 0, manual speed
and duplex mode selection is accomplished through bit 13
(SPEEDSL) and bit 8 (DUPLEX) of t he MR0 Control Register.
11 PWRDN R/W 0 Power-down
The device may be pl aced in a low power con sumption state
by setting this bit to 1. While in the powe r-down state, the
device will stil l respond to management transactions.
10 RSVD R 0 Reserved
9 RANEG R/WC 0 Restart Auto-negotiation
Normally, the A uto-
Negotiation process is started at power up.
The process can b e restarted by setti ng this bit to 1. This bit
is self-clearing.
8 DUPLEX R/W 1 Duplex Mode
This bit determi nes whether the device sup ports full- duplex or
half duplex. A 1 indi cat es full duplex operation and a 0
indicates half duplex . This bit will defaul t to 1 upon reset.
When auto-negoti ation is enabled, thi s bit will not be writable
and will have no eff ect on t he 78Q8430 PHY. If
auto-negotiation is not enabled, this bit may be written to force
manual configuration.
7 COLT R/W 0 Collision Test
When this bit is set to 1, the device will assert the COL signal
in response to t he assertion of the TX_E N signal. Collision
test is disabled if the PCSBP bi t, MR16[1], is high. The
Collision test can be activated regardless of the duplex m ode
of operation.
6:0 RSVD R 0 Reserved
78Q8430 Data Sheet DS_8430_001
76 Rev. 1.2
7.7.3 PHY Status Register – MR1
MR1 bits 15 through 11 reflect the ability of the 78Q8430 PHY. T hey do not reflect any abi l i ty changes
made via the MII M anagement interface t o MR0 bits 13 (SPEEDSL), 12 (ANEGEN) and 8 (DUPLEX).
Bits Symbol Type Default Description
15 100T4 R 0 100BASE-T4 Ability
Reads 0 to indicate t he 78Q8430 PHY does not support
100BASE-T4 mode.
14 100X_F R 1 100BASE-TX Full Duplex Ability
0 = Not able
1 = Able (default)
13 100X_H R 1 100BASE-TX Half Duplex Ability
0 = Not able
1 = Able (default)
12 10T_F R 1 10BASE-T Full Duplex Ability
0 = Not able
1 = Able (default)
11 10T_H R 1 10BASE-T Half Duplex Ability
0 = Not able
1 = Able (default)
10 100T2_F R 0 100BASE-T2 Full Duplex Ability
Reads 0 to indicate t he 78Q8430 PHY does not support
100BASE-T2 full duplex mode.
9 100T2_H R 0 100BASE-T2 Half Duplex Ability
Reads 0 to indicate the 78Q8430 PHY does not support
100BASE-T2 half duplex mode.
8 EXTS R 0 Extended Status Information Availability
Reads 0 to indicate t he 78Q8430 PHY does not support
Extended Status information in MR15.
7 RSVD R 0 Reserved
6 MFPS R 0 Management Frame Preambl e S uppression Support
A 0 indicates that the 78Q8430 PHY can read m anagement
frames with a preamble.
5 ANEGC R 0 Auto-negotiation Complete
Logic one indicates that the auto-negotiation process has
been completed and that the contents of regi st ers MR4, 5, 6
are valid.
4 RFAULT RC/LH 0 Remote Fault
A logic one indicates that a remote fault condition has been
detected and when so, i t remains set until it is cleared. This
bit can only be clea red by reading this regi st er (MR1) via t he
management int erface.
3 ANEGA R (1) Auto-negotiation Ability
When set, this bit i ndicates the device’s abi li ty to perform
Auto-Negotiation. The value of this bit is determined by the
ANEGEN bit (MR0.12).
2 LINK RC/LL 0 Link Status
A logic one indicates that a valid link has been establishe d. If
the link status should transition from an OK status to a NOT-
OK status, thi s bit will become cleared and remains cleared
until it is read.
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 77
Bits Symbol Type Default Description
1 JAB RC/LH 0 Jabber Detect
In 10Base-T mode, this bit is set during a jabber event. After
the event, the bit remains set until cleared by a read operati on.
0 EXTD R 1 Extended Capability
Reads 1 to indicate t he 78Q8430 PHY provi des an extended
register set (M R2 and beyond).
7.7.4 PHY Identifier Registers – MR2, MR3
MR2: PHY Identifi er Register 1
Bits
Symbol
Type
Value
Description
15:0 OUI
[23:6] R 000Eh Organizationally Unique Identifier
This value is 00-C0-
39 for Teridian Semiconductor Corporation.
This register contains 16 of the upper 18 bits of the identifier.
MR3: PHY Identifi er Register 2
Bits
Symbol
Type
Value
Description
15:10 OUI
[5:0] R 1Ch Organizationally Unique Identifier
The remaining 6 bit s of the 24-bit OUI.
9:4 MN R 23h Model Number
The 23 from the model number is encoded into the 6 bits.
3:0 RN R 03h
Revision Number
The value 0011 corresponds to the third revision of the silicon.
7.7.5 PHY Auto-Negotiation Advertisement Registers – MR4
Bits
Symbol
Type
Default
Description
15 NP R 0 Next Page
Not supported. Reads logic zero.
14 RSVD R 0 Reserved
13 RF R/W 0 Remote Fault
Setting this bit to 1 allows the device to indi cate to the link
partner a Remote Fault Condition.
12:5 TAF R/W (0Fh) Technology Ability Field
The default value of this field is dependent upon the MR1.15:
11 register bits. T his field can be overwritten by management
to auto-negotiate to an alternate common technology. Writing
to this register has no effect until auto-negotiation is re-initiated.
12 A7 R 0 Reserved
11 ASYMP R/W 0 Asymmetric PAUSE Operation for Full Duplex Links
0 = Asymmetric PA US E operation not support ed
1 = Asymmetric PA US E operation is support ed
Writing to this regist er has no effect until auto-negoti ation is
re-initiated.
10 PAUSE R/W 0 PAUSE Operation for Full Dupl ex Li nks
0 = PAUSE operation not supported
1 = PAUSE operation is supported
Writing to this regist er has no effect until auto-negoti ation is
re-initiated.
9 A4 R 0 100BASE-T4
The 78Q8430 P HY does not support 100BA S E-T4 operations.
8 A3 R/W 1 100BASE-TX Full Dupl ex
This bit will be set to 1 upon reset and is writeable. Writing to
this register has no effect until aut o-negotiation is re-initiated.
78Q8430 Data Sheet DS_8430_001
78 Rev. 1.2
Bits
Symbol
Type
Default
Description
7 A2 R/W 1 100BASE-TX Half Duplex
This bit will be set t o 1 upon reset and is writeable. Writing to
this register has no effect until auto-negotiation is re-initiated.
6 A1 R/W 1 10BASE-T Full Duplex
This bit will be set t o 1 upon reset and is writeable. Writing to
this register has no effect until aut o-negotiation is re-initiated.
5 A0 R/W 1 10BASE-T
This bit will be set t o 1 upon reset and is writeable. Writing to
this register has no effect until aut o-negotiation is re-initiated.
4:0 S4:0 R 01h Protocol Selector Fiel d
The value is 00001 f or IEEE 802.3.
7.7.6 PHY Auto-Negotiation Line Partner Ability Register – MR5
Bits
Symbol
Type
Default
Description
15 NP R 0 Next Page
When 1 is read, it i ndicat es the link partner wishes to engage in
Next Page exchange.
14 ACK R 0 Acknowledge
When 1 is read, it i ndicat es the link partner has successfully
received at least 3 consecutive and consistent FLP bursts.
13 RF R 0 Remote Fault
When 1 is read, it i ndicat es the link partner has a fault.
12:5 A7:0 R 0 Technology Ability Field
This field cont ai ns t he technology abilit y of the link partner.
The bit definition is t he same as MR4.12:5.
4:0 S4:0 R 00h Selector Field
This field contai ns the type of message sent by the link partner.
For IEEE 802. 3 compl i ant link partner, this field should be
00001.
When MR5 contains a next page message, the bit definit i on i s the same as MR7.
7.7.7 PHY Auto-Negotiation Expansion Register – MR6
Bits
Symbol
Type
Default
Description
15:5 RSVD R 0 Reserved
4 PDF RC/LH 0 Parallel Detecti o n Fau lt
When 1 is read, it i ndicat es that more than one technology has
been detected during link up. This bit is cleared when read.
3 LPNPA R 0 Link Partner Next Page Able
When 1 is read, it i ndicat es the link partner supports the Next
Page function.
2 NPA R 0 Next Page Able
Reads 0 since t he 78Q8430 PHY does not support the Next
Page function.
1 PRX RC/LH 0 Page Received
Reads 1 when a new link code word has been re ceived into the
Auto-negotiation Link Partner Ability Register. This bit i s
cleared upon read.
6.0 LPANEGA R 0 Link Partner Auto-negotiation Able
When 1 is read, it i ndicat es the link partner i s able to participate
in the Auto-Negotiation function.
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 79
7.7.8 PHY Vendor Specific Register – MR16
Bits
Symbol
Type
Default
Description
15 RSVD R 0 Reserved
14 RSVD R 0 Reserved
13 RSVD R 0 Reserved
12
TXHIM R/W 0 Transmitter High-Impedance Mode
When set, the TXOP /TXON transmit pins and the TX_CLK pin
are put into a high-impedance state. The receive circuit ry
remains fully funct i onal.
11 SQEI R/W 0 SQE Test Inhibit
Setting this bit to 1 disables 10Base-T SQE testing. By
default, this b i t is 0 and generates a COL pulse following the
completion of a packet transmission to perform the S QE test.
10 NL10 R/W 0 10Base-T Natural Loopback
Setting this bit to 1 causes transmit data received on the
TXD0-3 pins to be automati call y looped back to the RXD0-3
pins when 10Base-T mode is enabled.
9 RSVD R 0 Reserved
8 RSVD R 1 Reserved
7 RSVD R 0 Reserved
6 RSVD R 1 Reserved
5 APOL R/W 0 Auto Polarity
During auto-negot i ation and 10BASE-T mode, the 78Q843 0
PHY is able to autom atically inv ert the received signal due to a
wrong polarity connection. It does so by detecting th e pol arity
of the link pulses. Setting this bit to 1 dis abl es this feature.
4 RVSPOL R/W 0 Reverse Polari ty
The reverse polarity i s detected either throu gh 8 i nverted
10Base-T link pulses (NLP) or through one burst of inverted
clock pulses in t he auto-negotiation li nk pulses (FLP). When
the reverse polarity is detected and if the Auto Polarity f eature
is enabled, the 78Q 8430 PHY will invert the receive data input
and set this bit to 1. If Auto Polarity i s disabled, then this bit is
writeable. Writ i ng a 1 to this bit forces the polarity of the
receive signal to be reversed.
3:2 RSVD R/W 0h Reserved. M ust set to 00.
1 PCSBP R/W 0 PCS Bypass Mode
When set, the 100Base-TX PCS and scrambling/
descrambling functions are bypassed. Scrambled 5-bit code
groups for transmission are applied to the TX_ER, TXD3-0
pins and received on the RX_ER, RXD3-0 pins. The RX_DV
and TX_EN signals are not valid in thi s mode. PCSBP mode
is valid only when 100Base-TX mode is enabled and auto-
negotiation is di sabled.
0 RXCC R/W 0 Receive Clock Control
This function is valid only in 100Base-TX mode. When set to
1, the RX_CLK signal will be held low when there is no data
being received (to save power). The RX _CLK signal will
restart 1 clock cycle before the as serti on of RX_DV and will be
shut off 64 clock cy cles after RX_DV g oes low. RXCC is
disabled when loopback mode is enabl ed (MR0.14 is high).
This bit should be ke pt at logic zero when P CS Bypass mode
is used.
78Q8430 Data Sheet DS_8430_001
80 Rev. 1.2
7.7.9 PHY Interrupt Control / Status Register – MR17
The Interrupt Contr ol/ Stat us Registe r provides the means for co ntrolling and observi ng the events that
trigger an interrupt on the internal PHY interrupt signal. This register can al so be used in a poll ing m ode
via the MII Serial Interface as a means to observe key events withi n the PHY via one register address.
Bits 0 through 7 are st atus bits, which are each set to logic one based upon an event. These bits are
cleared after the register is read. Bi ts 8 through 15 of t hi s register, when set to logic one, enable their
corresponding bit in the lower byte to signal an i nterrupt on the PHY interrupt signal.
Bits Symbol Type Default Description
15 JABBER_IE R/W 0 Jabber Interrupt Enable
14 RXER_IE R/W 0 Receive Error Interrupt Enable
13 PRX_IE R/W 0 Page Received Interrupt Enable
12 PDF_IE R/W 0 Parallel Detect Fault Interrupt Enable
11 LP_ACK_IE R/W 0 Link Partner Ackno wledge Interrupt Enable
10 LS_CHANGE_IE R/W 0 Link Status Change Interrupt Enable
9 RFAULT_IE R/W 0 Remote Fault Interrupt Enable
8 ANEG-COMP_IE R/W 0 Auto-Negotiation Complete Interrupt Enable
7 JAB_INT RC 0 Jabber Interrupt
This bit is set high when a Jabber event is det ected by
the 10Base-T circuitry.
6 RXER_INT RC 0 Receive Error Interrupt
This bit is set high when the RX_ER signal transitions
high.
5 PRX_INT RC 0 Page Received Interrupt
This bit is set high when a new page has been
received from t he li nk part ner during auto-negotiation.
4 PDF_INT RC 0 Parallel Detect Fault Interrupt
This bit is set high by the auto-negotiation logic when a
parallel detect fault condition is indi cat ed.
3 LP_ACK_INT RC 0 Link Partner Acknowledge Interrupt
This bit is set high by the auto-negotiat io n logic when
FLP bursts are rec ei ved with the acknowledge bit set.
2 LS_CHANGE_INT RC 0 Link Status Change Interrupt
This bit is set when t he l ink status transiti ons from an
OK status to a FA IL status, or vice v ers a.
1 RFAULT_INT RC 0 Remote Fault Interrupt
This bit is set when a remote fault condition is
detected.
0 ANEG_COMP_INT RC 0 Auto-Negotiation Complete Int errupt
This bit is set by t he auto-negotiation lo gic upon
completion of auto-negotiation.
7.7.10 PHY Transceiver Control Register – MR19
Bit
Symbol
Type
Default
Description
15:14 TXO[1:0]
R/W 01 Transmit Amplitude Selection
Sets the transmit output am pl itude to account for transmit
transformer i nsertion loss.
00 = Gain set for 0. 0dB of insertion loss
01 = Gain set for 0. 4dB of insertion loss
10 = Gain set for 0. 8dB of insertion loss
11 = Gain set for 1. 2dB of insertion loss
13:0 RSVD R/W XXX Reserved
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 81
7.7.11 PHY Diagnostic Register – MR18
This register contains both user ac cessible and non-user a ccessible bits ( Res erved) for internal
testmodes. The user-accessible bits are l ocat ed at bit 12:8 locations.
Bit
Symbol
Type
Default
Description
15:13 RSVD R 0 Reserved
12 ANEGF RC 0 Auto-Negotiation Fail Indication
This bit is set when auto-negotiation completes and no
common technology was found. I t remains set until read.
11 DPLX R 0 Duplex Indication
This bit indicat es the result of t he auto-negotiation for
duplex arbitrat i on as follows:
0 = half duplex was the highest common denom i nator
1 = full duplex was the highest comm on denominator
10 RATE R 0 Rate Indication
This bit indicat es the result of t he auto-negotiation for data
rate arbitration as follows:
0 = 10Base-T was the highest common denom inator
1 = 100Base-TX was the highest commo n denom inator
9 RXSD R 0 Receiver Signal Detect Indication
In 10Base-T mode, this bit indicates t hat Manchester dat a
has been detected. In 100Base-TX mode, it indi cat es that
the receive signal activity has been detected (but not
necessarily locked on to).
8 RXLCK R 0 Receive PLL Lock Indication
Indicates that the Receive PLL has locked onto the receive
signal for the select ed speed of operation (10Base-T or
100Base-TX).
7:0 RSVD R 0 Reserved
7.7.12 PHY LED Configuration Register – MR23
Bit
Symbol
Type
Default
Description
15:8 RSVD R/W 0 Reserved
7:4 LED1[3:0]
R <1h> 0000 = Link OK
0001 = RX or TX Acti vity (Default LED1 )
0010 = TX Activity
0011 = RX Activity
0100 = Collision
0101 = 100 BASE -TX mode
0110 = 10 BASE-T mode
0111 = Full Duplex
1000 = Link OK/Blink=RX or TX Activity
3:0 LED0[3:0]
R <0h> 0000 = Link OK (Default LED0)
0001 = RX or TX Activity
0010 = TX Activity
0011 = RX Activity
0100 = Collision
0101 = 100 BASE -TX mode
0110 = 10 BASE-T mode
0111 = Full Duplex
1000 = Link OK/Blink=RX or TX Activity
78Q8430 Data Sheet DS_8430_001
82 Rev. 1.2
7.7.13 PHY MDI / MDIX Control Register – MR24
Bit
Symbol
Type
Default
Description
15:8 R 0 Unused
7 PD_MODE
R/W 1 Parallel Detect Mode
Write a 1 to this bit to add Parallel Detect mode. This will
allow auto-switching to work when auto-negotiation is of f
while the other device has it on.
6 AUTO_SW R/W 1 Auto Switching
Write a 1 to this bit to enable auto switc hi ng.
5 MDIX
R/W 0 MDI State
Indicates state of the MDI pair or force configuration:
1 = MDIX (cross over)
0 = MDI
When AUTO_SW is a 1, this bit will only be readable.
When AUTO_SW is a 0, this bit can be written to set the
configuration.
4 MDIX_CM R 0 Auto-Switch Completion
Indicates compl etion of auto-switch sequence.
1 = Sequence complet ed
0 = Sequence in progress or auto-switch i s disabled.
3:0 MDIX_SD R/W <0000> MDIX Seed
Write initial pat tern seed for switching algorithm. I ni tial
seed will directly affect attempts [9,8,5,4] respectively to
written bits [3:0]. Setting to [0000] wil l result in device
using its own seed of [0101].
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 83
8 Isolation Transformers
Table 35: Isolation Transform ers
Name
Value
Condition
Turns Ratio 1 CT : 1 CT ± 5%
Open-Circuit I nduct ance 350 µH (min) @ 10 mV, 10 kHz
Leakage Inductance 0.40 µH (max) @ 1 MHz (min)
Inter-Winding Capacitan ce 12 pF (max)
D.C. Resistance 0.9 Ω (max)
Insertion Loss 0.4 dB (typ) 0 - 65 MHz
HIPOT 1500 Vrms
Two simple 1:1 isolation transforme rs are all that are required at the line interface, but transformers
with integrate d common-mode choke are recommended for exceeding FCC requirements. Table 35
gives the recommended line transformer characterist i cs. T he 100Base-TX ampl itude specificati ons
assume a transformer loss of 0.4 dB. For the transmit line transform er with higher insertion losses, up to
1.2 dB of insertion loss can be compensated by selecti ng the appropriate set ting in the Transmit
Amplitude Sel ect ion bi ts in register MR19[ 11:10].
9 Reference Crystal
If the internal crystal oscillator is t o be used, a crystal with the characteristi cs given in Table 36 should be
chosen.
Table 36: Reference Crystal
Name
Value
Units
Frequency 25.00000 MHz
Load Capacitance* 4** pF
Frequency Tolerance ≤ ±50 per IEEE 802.3 requirement PPM
Oscillation Mode Parallel Resonan ce, Fundamental Mod e
Parameters at 25
o
C ± 2
o
C ; Drive Level = 0.5 mW
Shunt Capacitance (max) 10 pF
Motional Capacitance (min) 10 pF
Series Resistanc e (m ax) 60 Ω
Spurious Response (max ) > 5 dB below main within 500 k Hz
* Equivalent dif ferential capacita nce across the XTLP/XTLN pins.
** If a crystal with a larger l oad is used, external shunt capacitors to ground should be added to
make up the equivalent capacitance difference.
*** System vendors need to select the proper crystal according to their applications, such as
operating environment, product lifetime, and etc since crystal aging, operating temperature, and
other factors can affect the crystal frequency toleran ce.
78Q8430 Data Sheet DS_8430_001
84 Rev. 1.2
10 System Bus Interface Schematic
78Q8430
Single Chip
10/100 Ethernet
MAC & PHY
+3.3V
VCC
GND
DATA31
DATA30
DATA29
DATA28
DATA27
DATA26
DATA25
DATA24
DATA23
DATA22
DATA21
DATA20
DATA19
DATA18
DATA17
DATA16
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
RESET
BUSCLK
CS
WR
OE
MEMWAIT
INT
PME
ENDIAN1
ENDIAN0
BOOTSZ1
BOOTSZ0
BUSMODE
CLKMODE
WAITMODE
PROMCLK
PROMCS
PROMDO
PROMDI
Optional
JTAG
BSDL
Interface
Optional
External
EEPROM
BOOTSZ[1:0]
00 - bus is 32-bit wide
01 - bus is 16-bit wide
10 - bus is 8-bit wide
ENDIAN[1:0]
0,0 = Big Endian (MS B at high bit positions)
1,1 = Little Endian (MSB at low bit positions)
BUSMODE, CLKMODE, WAITMODE
0,0,0 = sync bus, ext. system clock, memwait act low
0,0,1 = sync bus, ext. system clock, memwait act high
1,0,0 = async bus, ext. system clock, memwait act low
1,0,1 = async bus, ext. system clock, memwait act high
1,1,0 = async bus, int. system clock, memwait act low
1,1,1 = async bus, int. system clock, memwait act high
TCLK
TRST
TMS
TDO
TDI
Figure 15: Sy stem Bus Interface Schem atic
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 85
11 Line Interface Schematic
Figure 16 shows a typical analog line interface schem atic (not all components are shown).
Activity
RJ45
LED
LED
Link
680Ω680Ω
+3.3V
A
C
A
C
1
2
3
6
1:1
Transformer
50Ω
50Ω
+3.3VA
0.1µF
50Ω
50Ω
+3.3VA
0.1µF
+3.3VA
0.1µ
F0.1µ
F
27pF
25. 000 MHz
Parallel Resonant
LED0
LED1
TXP
TXN
RXP
RXN
XTLP
XTLN
+3.3V +3.3VA
+3.3VA
VCC
VCCA
GND
0.1µF
0.1µF
0.1µF
10µF
VCCA
Ferrite
*
27pF
*
Shunt capacitor value will vary depending on crystal capacitance.
*
78Q8430
Single Chip
10/100 Ethernet
MAC and PHY
VCCA
Figure 16: Line Interface Schematic
78Q8430 Data Sheet DS_8430_001
86 Rev. 1.2
12 Package Mechanical Drawing (100-pin LQFP)
1
0.50(0.020)TYP.
0.05(0.002)
0.15(0.006)
0.18(0.007)
0.27(0.011)
0.60(0.024) TYP.
13.80 (0.543)
14.20 (0.559)
15.70 (0.618)
16.30 (0.641)
15.70 (0.618)
16.30 (0.641)
1.40(0.055)
1.60(0.063)
LQFP 10 0
Side View
Top View
Figure 17: LQFP Drawing
DS_8430_001 78Q8 430 Dat a Sheet
Rev. 1.2 87
13 Ordering Information
Table 37 lists the order numbers and packaging marks us ed to identify 78Q8430 products.
Table 37: 78Q8430 O rd er Numbers and Packaging Marks
Part Description
Order Number
Packaging Mark
78Q8430 LQFP, Lead free 78Q8430-100IGT/F 78Q8430-100IGT
78Q8430 LQFP, Lead free, Tape and Reel 78Q8430-100IGTR/F 78Q8430-100IGT
14 Related Documentation
The following 78Q8430 documents are available from Teri di an Semiconducto r Corporation:
78Q8430 Dat a Sheet (this document)
78Q8430 Layout Gui del ines
78Q8430 Soft ware Driver Development Guidelines
78Q8430 Driver Guide fo r S T 5100/OS-20 with NexGen TCP/IP Stack
78Q8430 STEM Demo Board User Manual
78Q8430 Driver Guide fo r A RM 920T Linux
78Q8430 ARM9(920T) Embest Evaluation Board User Manual
78Q8430 ARM9(920T) Linux Driver Diagnostic Guide
Check the website for the latest versions of these documents.
15 Contact Information
For more informat i on about Teridian S em i conductor product s or to check the avail abil i ty of the 78Q8430,
contact us at:
6440 Oak Canyon Ro ad
Suite 100
Irvine, CA 92618-5201
Telephone: (714) 508-8800
FAX: (714) 508-8878
Email: lan.support@teridian.com
For a complete list of worldwide sales off i ces, go to http://www.teridian.com.
78Q8430 Data Sheet DS_8430_001
88 Rev. 1.2
Revision History
Revision
Date
Description
1.0 7/21/2008 F i rst publication.
1.1 1/21/2009 Rem oved 128-pin package.
1.2 3/6/2009 Removed commercial temperature package.
© 2009 Teridian Sem i conductor Corporation. All rights reserved.
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Teridian Semiconductor Corporation makes no warrant y for the use of its products, other th an expressly
contained in the Company’s warrant y detailed in the Teridi an Semiconductor Co rporation standard Terms
and Conditions. T he company assumes no responsibil i ty for any errors which m ay appear in this
document, reserves the right t o change devices or specifications detailed herein at any ti m e without
notice and does not make any commitment to update t he i nformation contained herein. Accordingly , the
reader is cautioned t o verify that this document is current by comparing it to the latest version on
http://www.teridian.com or by checking with your sal es representative.
Teridian Semiconductor Corp., 6440 O ak Canyon, Suite 100, Irvine, CA 92618
TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com
