Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
Features
High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller
Nonvolatile program and data memories
384KBytes of in-system self-programmable flash
8KBytes boot section
4KBytes EEPROM
32KBytes internal SRAM
Peripheral features
Two -channel DMA controller
Four-channel event system
Five 16-bit timer/counters
Four timer/counters with four output compare or input capture channels
One timer/counter with two output compare or input capture channels
High resolution extension on two timer/counters
Advanced waveform extension (AWeX) on one timer/counter
One USB device interface
USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant
32 Endpoints with full configuration flexibility
Three USARTs with IrDA support for one USART
Two two-wire interfaces with dual address match (I2C and SMBus compatible)
Two serial peripheral interfaces (SPIs)
AES crypto engine
CRC-16 (CRC-CCITT) and CRC-32 (IEEE®802.3) generator
16-bit real time counter (RTC) with separate oscillator
One sixteen-channel, 12-bit, 300ksps Analog to Digital Converter
Two Analog Comparators with window compare function, and current sources
External interrupts on all general purpose I/O pins
Programmable watchdog timer with separate on-chip ultra low power oscillator
QTouch® library support
Capacitive touch buttons, sliders and wheels
Special microcontroller features
Power-on reset and programmable brown-out detection
Internal and external clock options with PLL and prescaler
Programmable multilevel interrupt controller
Five sleep modes
Programming and debug interface
PDI (program and debug interface)
I/O and packages
50 programmable I/O pins
64-lead TQFP
64-pad QFN
Operating voltage
1.6 – 3.6V
Operating frequency
0 – 12MHz from 1.6V
0 – 32MHz from 2.7V
8/16-bit Atmel XMEGA C3 Microcontroller
ATxmega384C3
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XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
1. Ordering Information
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
3. For packaging information, see “Packaging Information” on page 63.
4. Tape and Reel.
Typical Applications
Ordering code Flash
[bytes] EEPROM
[bytes] SRAM
[bytes] Speed
[MHz] Power
supply Package
(1)(2)(3) Temp.
ATxmega384C3-AU 384K + 8K 4K 32K
32 1.6 - 3.6V
64A
-40C - 85C
ATxmega384C3-AUR(4) 384K + 8K 4K 32K
ATxmega384C3-MH 384K + 8K 4K 32K
64Z3
ATxmega384C3-MHR(4) 384K + 8K 4K 32K
ATxmega384C3-AN 384K + 8K 4K 32K
64A
-40C - 105C
ATxmega384C3-ANR(4) 384K + 8K 4K 32K
ATxmega384C3-M7 384K + 8K 4K 32K
64Z3
ATxmega384C3-M7R(4) 384K + 8K 4K 32K
Package type
64A 64-lead, 14 x 14mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (TQFP)
64Z3 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, 7.65 x 7.65mm exposed pad, quad flat no-lead package (VQFN Sawn)
Industrial control Climate control Low power battery applications
Factory automation RF and ZigBee®Power tools
Building control USB connectivity HVAC
Board control Sensor control Utility metering
White goods Optical Medical applications
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Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
2. Pinout/Block Diagram
Figure 2- 1. Blo ck Diagram and Pinout
Notes: 1. For full details on pinout and alternate pin functions refer to “Pinout and Pin Functions” on page 51.
2. The large center pad underneath the QFN/MLF package should be soldered to ground on the board to ensure good mechanical stability.
1
2
3
4
64
63
62
61
60
59
58
VCC
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
57
56
55
54
53
52
51
50
49
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GND
GND
VCC
AVCC
GND
PB0
PB1
PB3
PB2
PB7
PB5
PB4
PB6
PA7
PA6
PA0
PA1
PA2
PA3
PA4
PA5
PDI
PR0
PR1
VDD
GND
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
VCC
GND
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
VDD
GND
Power
Supervision
Port A
EVENT ROUTING NETWORK
SRAMFLASH
ADC
AC0:1
OCD
Port E
Prog/Debug
Interface
EEPROM
Port C
TC0:1
Event System
Controller
Watchdog
Timer
Internal
oscillators
OSC/CLK
Control
Real Time
Counter
Interrupt
Controller
DATA BUS
DATA BUS
Port R
USART0
TWI
SPI
TC0
USART0
TWI
Port B
AREF
AREF
Sleep
Controller
Reset
Controller
Internal
references
IRCOM
Port F
TC0
USART0
CPU
XOSC
TOSC
Watchdog
oscillator
BUS
matrix
Crypto /
CRC
DMA
Controller
Port D
TC0
USART0
SPI
USB
RESET/PDI
Digital function
Analog function / Oscillators
Programming, debug, test
External clock / Crystal pins
General Purpose I /O
Ground
Power
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XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
3. Overview
The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based
on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA devices
achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system
designer to optimize power consumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly
connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction,
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times
faster than conventional single-accumulator or CISC based microcontrollers.
The XMEGA C3 devices provide the following features: in-system programmable flash with read-while-write capabilities;
internal EEPROM and SRAM; two-channel DMA controller, four-channel event system and programmable multilevel
interrupt controller, 50 general purpose I/O lines, 16-bit real-time counter (RTC); five, 16-bit timer/counters with compare
and PWM channels; three USARTs; two two-wire serial interfaces (TWIs); one full speed USB 2.0 interface; two serial
peripheral interfaces (SPIs); AES cryptographic engine; one sixteen-channel, 12-bit ADC with programmable gain; two
analog comparators (ACs) with window mode; programmable watchdog timer with separate internal oscillator; accurate
internal oscillators with PLL and prescaler; and programmable brown-out detection.
The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available.
The ATx devices have five software selectable power saving modes. The idle mode stops the CPU while allowing the
SRAM, DMA controller, event system, interrupt controller, and all peripherals to continue functioning. The power-down
mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the next TWI,
USB resume, or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to
run, allowing the application to maintain a timer base while the rest of the device is sleeping. In standby mode, the
external crystal oscillator keeps running while the rest of the device is sleeping. This allows very fast startup from the
external crystal, combined with low power consumption. In extended standby mode, both the main oscillator and the
asynchronous timer continue to run. To further reduce power consumption, the peripheral clock to each individual
peripheral can optionally be stopped in active mode and idle sleep mode.
Atmel offers a free QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR
microcontrollers.
The devices are manufactured using Atmel high-density, nonvolatile memory technology. The program flash memory can
be reprogrammed in-system through the PDI. A boot loader running in the device can use any interface to download the
application program to the flash memory. The boot loader software in the boot flash section will continue to run while the
application flash section is updated, providing true read-while-write operation. By combining an 8/16-bit RISC CPU with
in-system, self-programmable flash, the AVR XMEGA is a powerful microcontroller family that provides a highly flexible
and cost effective solution for many embedded applications.
All Atmel AVR XMEGA devices are supported with a full suite of program and system development tools, including: C
compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.
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3.1 Block Diagram
Figure 3-1. XMEGA C3 Block Diagram
Power
Supervision
POR/BOD &
RESET
PORT A (8)
PORT B (8)
SRAM
ADCA
ACA
OCD
Int. Refs.
PDI
PA[0..7]
PB[0..7]
Watchdog
Timer
Watchdog
Oscillator
Interrupt
Controller
DATA BUS
Prog/Debug
Controller
VCC
GND
Oscillator
Circuits/
Clock
Generation
Oscillator
Control
Real Time
Counter
Event System
Controller
AREFA
AREFB
PDI_DATA
RESET/
PDI_CLK
Sleep
Controller
CRC
PORT C (8)
PC[0..7]
TCC0:1
USARTC0
TWIC
SPIC
PD[0..7] PE[0..7]
PORT D (8)
TCD0
USARTD0
SPID
TCE0
USARTE0
TWIE
PORT E (8)
Tempref
VCC/10
PORT R (2)
XTAL1
XTAL2
PR[0..1]
DATA BUS
NVM Controller
MORPEE
h
sal
F
IRCOM
BUS Matrix
CPU
TOSC1
TOSC2
TCF0 PF[0..7]
PORT F (8)
EVENT ROUTING NETWORK
To Clock
Generator
DMA
Controller
AES
USB
Digital function
Analog function / Oscillators
Programming, debug,
External clock / Crystal pins
General Purpose I /O
Ground
Power
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4. Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
www.atmel.com/avr.
4.1 Recommended Reading
Atmel AVR XMEGA C manual
XMEGA application notes
This device data sheet only contains part specific information with a short description of each peripheral and module. The
XMEGA C manual describes the modules and peripherals in depth. The XMEGA application notes contain example code
and show applied use of the modules and peripherals.
All documentation are available from www.atmel.com/avr.
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5. Capacitive Touch Sensing
The Atmel QTouch library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR
microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced
reporting of touch keys and includes Adjacent Key Suppression® (AKS®) technology for unambiguous detection of key
events. The QTouch library includes support for the QTouch and QMatrix acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch library for the AVR
microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the
touch sensing API’s to retrieve the channel information and determine the touch sensor states.
The QTouch library is FREE and downloadable from the Atmel website at the following location:
www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the QTouch library user guide -
also available for download from the Atmel website.
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6. AVR CPU
6.1 Features
•8/16-bit, high-performance Atmel AVR RISC CPU
– 142 instructions
– Hardware multiplier
•32x8-bit registers directly conne cted to the ALU
•Stack in RAM
•Stack pointer accessible in I/O memory space
•Direct addressing of up to 16MB of program memory and 16MB of data memory
•True 16/24-bit access to 16/24-bit I/O registers
•Efficient support for 8-, 16-, and 32 -bit arithmet ic
•Configuration change protection of system-critic al feature s
6.2 Overview
All Atmel AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and
perform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the
program in the flash memory. Interrupt handling is described in a separate section, refer to “Interrupts and Programmable
Multilevel Interrupt Controller” on page 26.
6.3 Architectural Overview
In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories
and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to
be executed on every clock cycle. For details of all AVR instructions, refer to http://www.atmel.com/avr.
Figure 6-1. Block Diagram of the AVR CPU Architecture
The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a
register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is
updated to reflect information about the result of the operation.
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The ALU is directly connected to the fast-access register file. The 32 x 8-bit general purpose working registers all have
single clock cycle access time allowing single-cycle arithmetic logic unit (ALU) operation between registers or between a
register and an immediate. Six of the 32 registers can be used as three 16-bit address pointers for program and data
space addressing, enabling efficient address calculations.
The memory spaces are linear. The data memory space and the program memory space are two different memory
spaces.
The data memory space is divided into I/O registers, SRAM, and external RAM. In addition, the EEPROM can be
memory mapped in the data memory.
All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as the I/O
memory space. The lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3F.
The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be accessed as
data space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions.
The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five different
addressing modes supported in the AVR architecture. The first SRAM address is 0x2000.
Data addresses 0x1000 to 0x1FFF are reserved for memory mapping of EEPROM.
The program memory is divided in two sections, the application program section and the boot program section. Both
sections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for self-
programming of the application flash memory must reside in the boot program section. The application section contains
an application table section with separate lock bits for write and read/write protection. The application table section can
be used for safe storing of nonvolatile data in the program memory.
6.4 ALU - Arithmetic Logic Unit
The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a
register. Single-register operations can also be executed. The ALU operates in direct connection with all 32 general
purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register
and an immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the
status register is updated to reflect information about the result of the operation.
ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit
arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit aritmetic. The hardware
multiplier supports signed and unsigned multiplication and fractional format.
6.4.1 Hardware Multiplier
The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports different
variations of signed and unsigned integer and fractional numbers:
Multiplication of unsigned integers
Multiplication of signed integers
Multiplication of a signed integer with an unsigned integer
Multiplication of unsigned fractional numbers
Multiplication of signed fractional numbers
Multiplication of a signed fractional number with an unsigned one
A multiplication takes two CPU clock cycles.
6.5 Program Flow
After reset, the CPU starts to execute instructions from the lowest address in the flash programmemory ‘0.’ The program
counter (PC) addresses the next instruction to be fetched.
Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole
address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.
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During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general
data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After
reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the
I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be
accessed through the five different addressing modes supported in the AVR CPU.
6.6 Status Register
The status register (SREG) contains information about the result of the most recently executed arithmetic or logic
instruction. This information can be used for altering program flow in order to perform conditional operations. Note that
the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many
cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
The status register is not automatically stored when entering an interrupt routine nor restored when returning from an
interrupt. This must be handled by software.
The status register is accessible in the I/O memory space.
6.7 Stack and Stack Pointer
The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing
temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit
registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and
POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing
data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded
after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point
above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled.
During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be
two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program
memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices
with more than 128KB of program memory, the return address is three bytes, and hence the SP is
decremented/incremented by three. The return address is popped off the stack when returning from interrupts using the
RETI instruction, and from subroutine calls using the RET instruction.
The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one
when data is popped off the stack using the POP instruction.
To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts
for up to four instructions or until the next I/O memory write.
After reset the stack pointer is initialized to the highest address of the SRAM. See Figure 7-2 on page 13.
6.8 Register File
The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The register
file supports the following input/output schemes:
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient
address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash
program memory.
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7. Memories
7.1 Features
•Flash program memory
– One linear address space
– In-system programmable
– Self-programming and boot loader support
– Application section for application code
– Application table section for application code or data storage
– Boot section for application code or boot loader code
– Separate read/write protection lock bits for all sections
– Built in fast CRC check of a selectable flash program memory section
•Data memory
– One linear address space
– Single-cycle access from CPU
– SRAM
– EEPROM
Byte and page accessible
Optional memory mapping for direct load and store
– I/O memory
Configuration and status registers for all peripherals and modules
Four bit-accessible general purpose registers for global variables or flags
– Bus arbitration
Deterministic priority ha ndling between CPU, DMA controlle r, and other bus maste rs
– Separate buses for SRAM, EEPROM and I/O memory
Simultaneous bus access for CPU and DMA controller
•Production signature row memory for factory programmed data
– ID for each microcontroller device type
– Serial number for each device
– Calibration bytes for factory calibrated peripherals
•User signature row
– One flash page in size
– Can be read and written from software
– Content is kept after chip erase
7.2 Overview
The Atmel AVR architecture has two main memory spaces, the program memory and the data memory. Executable code
can reside only in the program memory, while data can be stored in the program memory and the data memory. The data
memory includes the internal SRAM, and EEPROM for nonvolatile data storage. All memory spaces are linear and
require no memory bank switching. Nonvolatile memory (NVM) spaces can be locked for further write and read/write
operations. This prevents unrestricted access to the application software.
A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can
only be written by an external programmer.
The available memory size configurations are shown in “Ordering Information” on page 2. In addition, each device has a
Flash memory signature row for calibration data, device identification, serial number, etc.
7.3 Flash Program Memory
The Atmel AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The
flash memory can be accessed for read and write from an external programmer through the PDI or from application
software running in the device.
All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized
in two main sections, the application section and the boot loader section. The sizes of the different sections are fixed, but
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device-dependent. These two sections have separate lock bits, and can have different levels of protection. The store
program memory (SPM) instruction, which is used to write to the flash from the application software, will only operate
when executed from the boot loader section.
The application section contains an application table section with separate lock settings. This enables safe storage of
nonvolatile data in the program memory.
Figure 7-1. Flash Program Memory (hexadecimal address)
7.3.1 Application Section
The Application section is the section of the flash that is used for storing the executable application code. The protection
level for the application section can be selected by the boot lock bits for this section. The application section can not store
any boot loader code since the SPM instruction cannot be executed from the application section.
7.3.2 Application Table Section
The application table section is a part of the application section of the flash memory that can be used for storing data.
The size is identical to the boot loader section. The protection level for the application table section can be selected by
the boot lock bits for this section. The possibilities for different protection levels on the application section and the
application table section enable safe parameter storage in the program memory. If this section is not used for data,
application code can reside here.
7.3.3 Boot Loader Section
While the application section is used for storing the application code, the boot loader software must be located in the boot
loader section because the SPM instruction can only initiate programming when executing from this section. The SPM
instruction can access the entire flash, including the boot loader section itself. The protection level for the boot loader
section can be selected by the boot loader lock bits. If this section is not used for boot loader software, application code
can be stored here.
7.3.4 Production Signature Row
The production signature row is a separate memory section for factory programmed data. It contains calibration data for
functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the
corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to
the corresponding peripheral registers from software. For details on calibration conditions, refer to “Electrical
Characteristics” on page 65.
Word address
ATxmega384C3
0
Application section (384K)
...
2EFFF
2F000
Application table section (8K)
2FFFF
30000
Boot section (8K)
30FFF
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The production signature row also contains an ID that identifies each microcontroller device type and a serial number for
each manufactured device. The serial number consists of the production lot number, wafer number, and wafer
coordinates for the device. The device ID for the available devices is shown in Table 7-1.
The production signature row cannot be written or erased, but it can be read from application software and external
programmers.
Table 7-1. Device ID Bytes
7.3.5 User Signature Row
The user signature row is a separate memory section that is fully accessible (read and write) from application software
and external programmers. It is one flash page in size, and is meant for static user parameter storage, such as calibration
data, custom serial number, identification numbers, random number seeds, etc. This section is not erased by chip erase
commands that erase the flash, and requires a dedicated erase command. This ensures parameter storage during
multiple program/erase operations and on-chip debug sessions.
7.4 Fuses and Lock Bit s
The fuses are used to configure important system functions, and can only be written from an external programmer. The
application software can read the fuses. The fuses are used to configure reset sources such as brownout detector and
watchdog, and startup configuration.
The lock bits are used to set protection levels for the different flash sections (that is, if read and/or write access should be
blocked). Lock bits can be written by external programmers and application software, but only to stricter protection levels.
Chip erase is the only way to erase the lock bits. To ensure that flash contents are protected even during chip erase, the
lock bits are erased after the rest of the flash memory has been erased.
An unprogrammed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value zero.
Both fuses and lock bits are reprogrammable like the flash program memory.
7.5 Data Memory
The data memory contains the I/O memory, internal SRAM, optionally memory mapped EEPROM, and external memory
if available. The data memory is organized as one continuous memory section, see Figure 7-2 on page 13. To simplify
development, I/O Memory, EEPROM and SRAM will always have the same start addresses for all Atmel AVR XMEGA
devices.
Figure 7-2. Data Memory Map (hexadecimal address)
Device Device ID bytes
Byte 2 Byte 1 Byte 0
ATxmega384C3 45 98 1E
Byte address ATxmega384C3
0
I/O registers (4K)
FFF
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7.6 EEPROM
All devices have EEPROM for nonvolatile data storage. It is either addressable in a separate data space (default) or
memory mapped and accessed in normal data space. The EEPROM supports both byte and page access. Memory
mapped EEPROM allows highly efficient EEPROM reading and EEPROM buffer loading. When doing this, EEPROM is
accessible using load and store instructions. Memory mapped EEPROM will always start at hexadecimal address
0x1000.
7.7 I/O Memory
The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O
memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions,
which are used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT
instructions can address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00 - 0x1F,
single-cycle instructions for manipulation and checking of individual bits are available.
The I/O memory address for all peripherals and modules is shown in the “Peripheral Module Address Map” on page 56.
7.7.1 General Purpose I/O Registers
The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for
storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
7.8 Data Memory and Bus Arbitration
Since the data memory is organized as four separate sets of memories, the different bus masters (CPU, DMA controller
read and DMA controller write, etc.) can access different memory sections at the same time.
7.9 Memory Timing
Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from
SRAM takes two cycles. For burst read (DMA), new data are available every cycle. EEPROM page load (write) takes one
cycle, and three cycles are required for read. For burst read, new data are available every second cycle. Refer to the
instruction summary for more details on instructions and instruction timing.
7.10 Device ID and Revision
Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A
separate register contains the revision number of the device.
7.11 I/O Memory Protection
Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the
I/O register related to the clock system, the event system, and the advanced waveform extensions. As long as the lock is
enabled, all related I/O registers are locked and they can not be written from the application software. The lock registers
themselves are protected by the configuration change protection mechanism.
1000
EEPROM (4K)
1FFF
2000
Internal SRAM (32K)
9FFF
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7.12 Flash and EEPROM Page Size
The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for the
flash and byte accessible for the EEPROM.
Table 7-2 on page 15 shows the Flash Program Memory organization and Program Counter (PC) size. Flash write and
erase operations are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash
access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) give the page
number and the least significant address bits (FWORD) give the word in the page.
Table 7-2. Number of Words and Pages in the Flash
Table 7-3 shows EEPROM memory organization. EEEPROM write and erase operations can be performed one page or
one byte at a time, while reading the EEPROM is done one byte at a time. For EEPROM access the NVM address
register (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) give the page number
and the least significant address bits (E2BYTE) give the byte in the page.
Table 7-3. Number of Bytes and Pages in the EEPROM
Devices PC size Flash size Page size FWORD FPAGE Application Boot
bits bytes words Size No. of
pages Size No. of
pages
ATxmega384C3 18 384K + 8K 256 Z[8:1] Z[19:9] 384K 768 8K 16
Devices EEPROM Page size E2BYTE E2PAGE No. of pages
Size bytes
ATxmega384C3 4K 32 ADDR[4:0] ADDR[11:5] 128
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8. DMAC – Direct Memory Access Controller
8.1 Features
•Allows high speed data transfers with minimal CPU intervention
– from data memory to data memory
– from data memory to peripheral
– from peripheral to data memory
– from peripheral to pe riph e ral
•Two DMA channels with separate
– transfer triggers
– interrupt vectors
– addressing modes
•Programmable channel priority
•From one byte to 16MB of data in a single transaction
– Up to 64KB block transfers with repeat
– 1, 2, 4, or 8 byte burst transfers
•Multiple addressing modes
–Static
–Incremental
– Decremental
•Optional reload of source and destination addresses at the end of each
–Burst
–Block
– Transaction
•Optional interrupt on end of transaction
•Optional connection to CRC generator for CRC on DMA data
8.2 Overview
The two-channel direct memory access (DMA) controller can transfer data between memories and peripherals, and thus
off-load these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU
time. The four DMA channels enable up to four independent and parallel transfers.
The DMA controller can move data between SRAM and peripherals, between SRAM locations and directly between
peripheral registers. With access to all peripherals, the DMA controller can handle automatic transfer of data to/from
communication modules. The DMA controller can also read from memory mapped EEPROM.
Data transfers are done in continuous bursts of 1, 2, 4, or 8 bytes. They build block transfers of configurable size from 1
byte to 64KB. A repeat counter can be used to repeat each block transfer for single transactions up to 16MB. Source and
destination addressing can be static, incremental or decremental. Automatic reload of source and/or destination
addresses can be done after each burst or block transfer, or when a transaction is complete. Application software,
peripherals, and events can trigger DMA transfers.
The two DMA channels have individual configuration and control settings. This include source, destination, transfer
triggers, and transaction sizes. They have individual interrupt settings. Interrupt requests can be generated when a
transaction is complete or when the DMA controller detects an error on a DMA channel.
To allow for continuous transfers, two channels can be interlinked so that the second takes over the transfer when the
first is finished, and vice versa.
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9. Event System
9.1 Features
•System for direct peripheral-to-peripheral commu ni ca tio n and signaling
•Peripherals can directly send, receive, and react to peripheral events
– CPU and DMA controller independen t ope ration
– 100% predictable signal timing
– Short and guarantee d response time
•Four event chann els for up to fou r diffe re nt and parallel signal routing co nfigurations
•Events can be sent and/or used by most peripherals, clock system, an d software
•Additional functions include
– Quadrature decoders
– Digital filtering of I/O pin state
•Works in active mode and idle sleep mode
9.2 Overview
The event system enables direct peripheral-to-peripheral communication and signaling. It allows a change in one
peripheral’s state to automatically trigger actions in other peripherals. It is designed to provide a predictable system for
short and predictable response times between peripherals. It allows for autonomous peripheral control and interaction
without the use of interrupts, CPU, or DMA controller resources, and is thus a powerful tool for reducing the complexity,
size and execution time of application code. It also allows for synchronized timing of actions in several peripheral
modules.
A change in a peripheral’s state is referred to as an event, and usually corresponds to the peripheral’s interrupt
conditions. Events can be directly passed to other peripherals using a dedicated routing network called the event routing
network. How events are routed and used by the peripherals is configured in software.
Figure on page 17 shows a basic diagram of all connected peripherals. The event system can directly connect together
analog to digital converter, analog comparators, I/O port pins, the real-time counter, timer/counters, IR communication
module (IRCOM), and USB interface. It can also be used to trigger DMA transactions (DMA controller). Events can also
be generated from software and the peripheral clock.
Figure 9-1. Event System Overview and Connected Peripherals
The event routing network consists of four software-configurable multiplexers that control how events are routed and
used. These are called event channels, and allow for up to four parallel event routing configurations. The maximum
routing latency is two peripheral clock cycles. The event system works in both active mode and idle sleep mode.
Timer /
Counters
USB
ADC Real Time
Counter
Port pins
CPU /
Software
DMA
Controller
IRCOM
Event Routing Network
Event
System
Controller
clkPER
Prescaler
AC
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10. System Clock and Clock Options
10.1 Features
•Fast start-up time
•Safe run-time clock switching
•Internal oscillators:
– 32MHz run-time calibrated and tuneable oscillator
– 2MHz run-time calibrated oscillator
– 32.768kHz calibrated oscilla tor
– 32kHz ultra low power (ULP) oscillator with 1kHz output
•External clock options
– 0.4MHz - 16MHz crystal oscillator
– 32.768kHz crystal oscillator
– External clock
•PLL with 20MHz - 128MHz output frequency
– Internal and external clock options and 1x to 31x multiplication
– Lock detector
•Clock prescalers with 1x to 2048x div is io n
•Fast peripheral clocks running at two and fou r times the CPU clock
•Automatic run-time calibration of internal oscillators
•External oscillator and PLL lock failure detection with optional non-maskable interrupt
10.2 Overview
Atmel AVR XMEGA C3 devices have a flexible clock system supporting a large number of clock sources. It incorporates
both accurate internal oscillators and external crystal oscillator and resonator support. A high-frequency phase locked
loop (PLL) and clock prescalers can be used to generate a wide range of clock frequencies. A calibration feature (DFLL)
is available, and can be used for automatic run-time calibration of the internal oscillators to remove frequency drift over
voltage and temperature. An oscillator failure monitor can be enabled to issue a non-maskable interrupt and switch to the
internal oscillator if the external oscillator or PLL fails.
When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device
will always start up running from the 2MHz internal oscillator. During normal operation, the system clock source and
prescalers can be changed from software at any time.
Figure 10-1 on page 19 presents the principal clock system. Not all of the clocks need to be active at a given time. The
clocks for the CPU and peripherals can be stopped using sleep modes and power reduction registers, as described in
“Power Management and Sleep Modes” on page 21.
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Figure 10-1. The Clock System, Clock Sources, and Clock Distribution
10.3 Clock Sources
The clock sources are divided in two main groups: internal oscillators and external clock sources. Most of the clock
sources can be directly enabled and disabled from software, while others are automatically enabled or disabled,
depending on peripheral settings. After reset, the device starts up running from the 2MHz internal oscillator. The other
clock sources, DFLLs and PLL, are turned off by default.
The internal oscillators do not require any external components to run. For details on characteristics and accuracy of the
internal oscillators, refer to the device datasheet.
10.3.1 32kHz Ultra Low Power Internal Oscillator
This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low
power clock source, and it is not designed for high accuracy. The oscillator employs a built-in prescaler that provides a
1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device.
This oscillator can be selected as the clock source for the RTC.
Real Time
Counter Peripherals RAM AVR CPU Non-Volatile
Memory
Watchdog
Timer
Brown-out
Detector
System Clock Prescalers
USB
Prescaler
System Clock Multiplexer
(SCLKSEL)
PLLSRC
RTCSRC
DIV32
32kHz
Int. ULP
32.768kHz
Int. OSC
32.768kHz
TOSC
2MHz
Int. Osc
32MHz
Int. Osc
0.4 – 16MHz
XTAL
DIV32
DIV32
DIV4
XOSCSEL
PLL
USBSRC
TOSC1
TOSC2
XTAL1
XTAL2
clk
SYS
clk
RTC
clk
PER2
clk
PER
clk
CPU
clk
PER4
clk
USB
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10.3.2 32.768kHz Calibrated Internal Oscillator
This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency
close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the
oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz
output.
10.3.3 32.768kHz Crystal Oscillator
A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low
frequency oscillator input circuit. A low power mode with reduced voltage swing on TOSC2 is available. This oscillator
can be used as a clock source for the system clock and RTC, and as the DFLL reference clock.
10.3.4 0.4 - 16MHz Crystal Oscillator
This oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4 - 16MHz.
10.3.5 2MHz Run-time Calibrated Internal Os cillator
The 2MHz run-time calibrated internal oscillator is the default system clock source after reset. It is calibrated during
production to provide a default frequency close to its nominal frequency. A DFLL can be enabled for automatic run-time
calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy.
10.3.6 32MHz Run-time Calibrated Internal Oscillator
The 32MHz run-time calibrated internal oscillator is a high-frequency oscillator. It is calibrated during production to
provide a default frequency close to its nominal frequency. A digital frequency looked loop (DFLL) can be enabled for
automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator
accuracy. This oscillator can also be adjusted and calibrated to any frequency between 30MHz and 55MHz. The
production signature row contains 48MHz calibration values intended used when the oscillator is used a full-speed USB
clock source.
10.3.7 External Clock Sources
The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator.
XTAL1 can be used as input for an external clock signal. The TOSC1 and TOSC2 pins is dedicated to driving a
32.768kHz crystal oscillator.
10.3.8 PLL with 1x - 31x Multiplication Factor
The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a user-
selectable multiplication factor of from 1 to 31. In combination with the prescalers, this gives a wide range of output
frequencies from all clock sources.
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11. Power Management and Sleep Modes
11.1 Features
•Power management for ad justing power consumption and func tions
•Five sleep modes
–Idle
– Power down
– Power save
– Standby
– Extended standby
•Power reduction register to disable clock and turn off unus ed peripherals in active and idle modes
11.2 Overview
Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements.
This enables the Atmel AVR XMEGA microcontroller to stop unused modules to save power.
All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing application
code. When the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the
device again. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals
and all enabled reset sources can restore the microcontroller from sleep to active mode.
In addition, power reduction registers provide a method to stop the clock to individual peripherals from software. When
this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. This
reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power
management than sleep modes alone.
11.3 Sleep Modes
Sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. XMEGA
microcontrollers have five different sleep modes tuned to match the typical functional stages during application
execution. A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are used to wake the
device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep mode. When an
enabled interrupt occurs, the device will wake up and execute the interrupt service routine before continuing normal
program execution from the first instruction after the SLEEP instruction. If other, higher priority interrupts are pending
when the wake-up occurs, their interrupt service routines will be executed according to their priority before the interrupt
service routine for the wake-up interrupt is executed. After wake-up, the CPU is halted for four cycles before execution
starts.
The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the device will
reset, start up, and execute from the reset vector.
11.3.1 Idle Mode
In idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be completed), but
all peripherals, including the interrupt controller, event system and DMA controller are kept running. Any enabled
interrupt will wake the device.
11.3.2 Power-down Mode
In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only of
asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the two-
wire interface address match interrupt, asynchronous port interrupts, and the USB resume interrupt.
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11.3.3 Power-save Mode
Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keep
running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt.
11.3.4 Standby Mode
Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running
while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time.
11.3.5 Extended Standby Mode
Extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are
kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time.
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12. System Control and Reset
12.1 Features
•Reset the microcontroller an d set it to initial state when a reset source goes active
•Multiple reset sources that cover different situations
– Power-on reset
– External reset
– Watchdog reset
– Brownout reset
– PDI reset
– Software reset
•Asynchronous operation
– No running system clock in the device is required for re set
•Reset status register for reading the reset source from the application code
12.2 Overview
The reset system issues a microcontroller reset and sets the device to its initial state. This is for situations where
operation should not start or continue, such as when the microcontroller operates below its power supply rating. If a reset
source goes active, the device enters and is kept in reset until all reset sources have released their reset. The I/O pins
are immediately tri-stated. The program counter is set to the reset vector location, and all I/O registers are set to their
initial values. The SRAM content is kept. However, if the device accesses the SRAM when a reset occurs, the content of
the accessed location can not be guaranteed.
After reset is released from all reset sources, the default oscillator is started and calibrated before the device starts
running from the reset vector address. By default, this is the lowest program memory address, 0, but it is possible to
move the reset vector to the lowest address in the boot section.
The reset functionality is asynchronous, and so no running system clock is required to reset the device. The software
reset feature makes it possible to issue a controlled system reset from the user software.
The reset status register has individual status flags for each reset source. It is cleared at power-on reset, and shows
which sources have issued a reset since the last power-on.
12.3 Reset Sequence
A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is
active. When all reset requests are released, the device will go through three stages before the device starts running
again:
Reset counter delay
Oscillator startup
Oscillator calibration
If another reset requests occurs during this process, the reset sequence will start over again.
12.4 Reset Sources
12.4.1 Power-on Reset
A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the VCC rises and
reaches the POR threshold voltage (VPOT), and this will start the reset sequence.
The POR is also activated to power down the device properly when the VCC falls and drops below the VPOT level.
The VPOT level is higher for falling VCC than for rising VCC. Consult the datasheet for POR characteristics data.
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12.4.2 Brownout Detection
The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed,
programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip
erase and when the PDI is enabled.
12.4.3 External Reset
The external reset circuit is connected to the external RESET pin. The external reset will trigger when the RESET pin is
driven below the RESET pin threshold voltage, VRST, for longer than the minimum pulse period, tEXT. The reset will be
held as long as the pin is kept low. The RESET pin includes an internal pull-up resistor.
12.4.4 Watchdog Reset
The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from
the software within a programmable timeout period, a watchdog reset will be given. The watchdog reset is active for one
to two clock cycles of the 2MHz internal oscillator. For more details see “WDT – Watchdog Timer” on page 25.
12.4.5 Software Reset
The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset
control register. The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to execute any
instruction from when a software reset is requested until it is issued.
12.4.6 Program and Debug Interface Reset
The program and debug interface reset contains a separate reset source that is used to reset the device during external
programming and debugging. This reset source is accessible only from external debuggers and programmers.
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13. WDT – Watchdog Timer
13.1 Features
•Issues a device reset if the timer is not reset before its timeout period
•Asynchronous operation from dedicated oscillator
•1kHz output of the 32kHz ultra low power oscillator
•11 selectable timeout periods, from 8ms to 8s
•Two operation modes:
– Normal mode
– Windo w mode
•Configuration lock to prevent unwanted changes
13.2 Overview
The watchdog timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover
from error situations such as runaway or deadlocked code. The WDT is a timer, configured to a predefined timeout
period, and is constantly running when enabled. If the WDT is not reset within the timeout period, it will issue a
microcontroller reset. The WDT is reset by executing the WDR (watchdog timer reset) instruction from the application
code.
The window mode makes it possible to define a time slot or window inside the total timeout period during which WDT
must be reset. If the WDT is reset outside this window, either too early or too late, a system reset will be issued.
Compared to the normal mode, this can also catch situations where a code error causes constant WDR execution.
The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a CPU-independent clock
source, and will continue to operate to issue a system reset even if the main clocks fail.
The configuration change protection mechanism ensures that the WDT settings cannot be changed by accident. For
increased safety, a fuse for locking the WDT settings is also available.
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14. Interrupts and Programmable Multilevel Interrupt Controller
14.1 Features
•Short and predictable interrupt response time
•Separate interrupt configuration and vector address for each interrupt
•Programmable multilevel interrupt con t roller
– Interrupt prioritizing ac cording to level and vector address
– Three selectable interrupt levels for all interrupts: low, medium and high
– Selectable, round-robin priority scheme within low-level interrupts
– Non-maskable interrupts for critical functions
•Interrupt vectors optionally plac ed in the application section or the boot loader section
14.2 Overview
Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have
one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it
will generate an interrupt request when the interrupt condition is present. The programmable multilevel interrupt
controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged
by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed.
All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts are
prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level
interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level, the
interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest
interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are
serviced within a certain amount of time.
Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions.
14.3 Interrupt Vectors
The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts in
each peripheral. The base addresses for the Atmel AVR XMEGA C3 devices are shown in Table 14-1 on page 27. Offset
addresses for each interrupt available in the peripheral are described for each peripheral in the XMEGA C manual. For
peripherals or modules that have only one interrupt, the interrupt vector is shown in Table 14-1 on page 27. The program
address is the word address.
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Table 14-1. Reset and Interrupt Vectors
Program address
(base address) Source Interrupt description
0x000 RESET
0x002 OSCF_INT_vect Crystal oscillator failure interrupt vector (NMI)
0x004 PORTC_INT_base Port C interrupt base
0x008 PORTR_INT_base Port R interrupt base
0x00C DMA_INT_base DMA controller interrupt base
0x014 RTC_INT_base Real Time Counter Interrupt base
0x018 TWIC_INT_base Two-Wire Interface on Port C Interrupt base
0x01C TCC0_INT_base Timer/Counter 0 on port C Interrupt base
0x028 TCC1_INT_base Timer/Counter 1 on port C Interrupt base
0x030 SPIC_INT_vect SPI on port C Interrupt vector
0x032 USARTC0_INT_base USART 0 on port C Interrupt base
0x03E AES_INT_vect AES Interrupt vector
0x040 NVM_INT_base Non-Volatile Memory Interrupt base
0x044 PORTB_INT_base Port B Interrupt base
0x056 PORTE_INT_base Port E INT base
0x05A TWIE_INT_base Two-Wire Interface on Port E Interrupt base
0x05E TCE0_INT_base Timer/Counter 0 on port E Interrupt base
0x074 USARTE0_INT_base USART 0 on port E Interrupt base
0x080 PORTD_INT_base Port D Interrupt base
0x084 PORTA_INT_base Port A Interrupt base
0x088 ACA_INT_base Analog Comparator on Port A Interrupt base
0x08E ADCA_INT_base Analog to Digital Converter on Port A Interrupt base
0x09A TCD0_INT_base Timer/Counter 0 on port D Interrupt base
0x0AE SPID_INT_vector SPI D Interrupt vector
0x0B0 USARTD0_INT_base USART 0 on port D Interrupt base
0x0B6 USARTD1_INT_base USART 1 on port D Interrupt base
0x0D0 PORTF_INT_base Port F Interrupt base
0x0D8 TCF0_INT_base Timer/Counter 0 on port F Interrupt base
0x0FA USB_INT_base USB on port D Interrupt base
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15. I/O Ports
15.1 Features
•50 general purpose in pu t and output pins with individual c onfiguration
•Output driver with configurable driver and pull settings:
–Totem-pole
– Wired-AND
–Wired-OR
– Bus-keeper
– Inverted I/O
•Input with synchronous and/o r asynchronous sensing with interrupts and events
– Sense both edges
– Sense rising edges
– Sense falling edges
– Sense low level
•Optional pull-up and pull-down resistor on input and Wired-OR/AND configurations
•Optional slew rate control
•Asynchronous pi n change sensing that can wake the device from all sleep modes
•Two port interrupts with pin masking per I/O port
•Efficient and safe access to port pins
– Hardware read-modify-write through dedicated toggle/clear/set register s
– Configuration of multiple pins in a single operation
– Mapping of port registers into bit-accessible I/O memory space
•Peripheral cloc k s ou tpu t on po rt pin
•Real-time counter clock output to port pin
•Event channels ca n be output on port pin
•Remapping of dig ital peripheral pin function s
– Selectable USART, SPI, and timer/counter inpu t/output pin locations
15.2 Overview
One port consists of up to eight port pins: pin 0 to 7. Each port pin can be configured as input or output with configurable
driver and pull settings. They also implement synchronous and asynchronous input sensing with interrupts and events for
selectable pin change conditions. Asynchronous pin-change sensing means that a pin change can wake the device from
all sleep modes, included the modes where no clocks are running.
All functions are individual and configurable per pin, but several pins can be configured in a single operation. The pins
have hardware read-modify-write (RMW) functionality for safe and correct change of drive value and/or pull resistor
configuration. The direction of one port pin can be changed without unintentionally changing the direction of any other
pin.
The port pin configuration also controls input and output selection of other device functions. It is possible to have both the
peripheral clock and the real-time clock output to a port pin, and available for external use. The same applies to events
from the event system that can be used to synchronize and control external functions. Other digital peripherals, such as
USART, SPI, and timer/counters, can be remapped to selectable pin locations in order to optimize pin-out versus
application needs.
The notation of the ports are PORTA, PORTB, PORTC, PORTD, PORTE, PORTF, and PORTR.
15.3 Output Driver
All port pins (Pn) have programmable output configuration. The port pins also have configurable slew rate limitation to
reduce electromagnetic emission.
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15.3.1 Push-pull
Figure 15-1. I/O Configuration - Totem-pole
15.3.2 Pull-down
Figure 15-2. I/O Configuration - Totem-pole with Pull-down (on input)
15.3.3 Pull-up
Figure 15-3. I/O Conf iguration - Totem-pole with Pull-up (on input)
15.3.4 Bus-keeper
The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level
was ‘1’, and pull-down if the last level was ‘0’.
INxn
OUTxn
DIRxn
Pxn
INxn
OUTxn
DIRxn
Pxn
INxn
OUTxn
DIRxn
Pxn
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Figure 15-4. I/O Configuration - Totem-pole with Bus-keeper
15.3.5 Others
Figure 15-5. Output Configuration - Wired-OR with Optional Pull-down
Figure 15-6. I/O Configuration - Wired-AND with Optional Pull-up
INxn
OUTxn
DIRxn
Pxn
INxn
OUTxn
Pxn
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15.4 Input Sensing
Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is
shown in Figure 15-7.
Figure 15-7. Input Sensing System Overview
When a pin is configured with inverted I/O, the pin value is inverted before the input sensing.
15.5 Alternate Port Functions
Most port pins have alternate pin functions in addition to being a general purpose I/O pin. When an alternate function is
enabled, it might override the normal port pin function or pin value. This happens when other peripherals that require pins
are enabled or configured to use pins. If and how a peripheral will override and use pins is described in the section for
that peripheral. “Pinout and Pin Functions” on page 51 shows which modules on peripherals that enable alternate
functions on a pin, and which alternate functions that are available on a pin.
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16. TC0/1 – 16-bit Timer/Counter Type 0 and 1
16.1 Features
•Five 16-bit timer/counters
– Four timer/coun te rs of type 0
– One timer/counter of type 1
– Split-mode enabling two 8-bit timer/counter from each timer/counter type 0
•32-bit timer/counter support by cascading two timer/counters
•Up to four compare or capture (CC) channels
– Four CC channels for timer/counters of type 0
– Two CC channels for timer/counters of type 1
•Double buffered timer period setting
•Double buffered capture or compare channels
•Waveform generation:
– Frequency generation
– Single-slope pulse wi dth modul a t io n
– Dual-sl ope pulse width modulation
•Input capture:
– Input capture with noise cancelling
– Frequency capture
– Pulse width capture
– 32-bit input capture
•Timer overflow and error interrupts/events
•One compare match or input capture interrupt/event per CC cha nn el
•Can be used with event system for:
– Quadrature decoding
– Count and dire c t io n co ntrol
–Capture
•Can be used with DMA and to trigger DMA transactions
•High-resolution extension
– Increases frequency and waveform resolution by 4x (2-bit) or 8x (3-bit)
•Advanced waveform extension:
– Low- and high-side output with programmable dead-time insertion (DTI)
•Event controlled fault protection for safe disabling of drivers
16.2 Overview
Atmel AVR XMEGA C3 devices have a set of five flexible 16-bit timer/counters (TC). Their capabilities include accurate
program execution timing, frequency and waveform generation, and input capture with time and frequency measurement
of digital signals. Two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit capture.
A timer/counter consists of a base counter and a set of compare or capture (CC) channels. The base counter can be
used to count clock cycles or events. It has direction control and period setting that can be used for timing. The CC
channels can be used together with the base counter to do compare match control, frequency generation, and pulse
width waveform modulation, as well as various input capture operations. A timer/counter can be configured for either
capture or compare functions, but cannot perform both at the same time.
A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system.
The event system can also be used for direction control and capture trigger or to synchronize operations.
There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and
timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 0.
Only Timer/Counter 0 has the split mode feature that split it into two 8-bit Timer/Counters with four compare channels
each.
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Some timer/counters have extensions to enable more specialized waveform and frequency generation. The advanced
waveform extension (AWeX) is intended for motor control and other power control applications. It enables low- and high-
side output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers. It can
also generate a synchronized bit pattern across the port pins.
The advanced waveform extension can be enabled to provide extra and more advanced features for the Timer/Counter.
This are only available for Timer/Counter 0. See “AWeX – Advanced Waveform Extension” on page 35 for more details.
The high-resolution (hi-res) extension can be used to increase the waveform output resolution by four or eight times by
using an internal clock source running up to four times faster than the peripheral clock. See “Hi-Res – High Resolution
Extension” on page 36 for more details.
Figure 16-1. Overview of a Timer/Counter and Closely Related Peripherals
PORTC has one Timer/Counter 0 and one Timer/Counter1. PORTD, PORTE, and PORTF each has one Timer/Counter
0. Notation of these are TCC0 (Time/Counter C0), TCC1, TCD0, TCE0, and TCF0, respectively.
AWeX
Compare/Capture Channel D
Compare/Capture Channel C
Compare/Capture Channel B
Compare/Capture Channel A
Waveform
Generation
Buffer
Comparator
Hi-Res
Fault
Protection
Capture
Control
Base Counter
Counter
Control Logic
Timer Period
Prescaler
Dead-Time
Insertion
Pattern
Generation
clkPER4
PORTS
Event
System
clkPER
Timer/Counter
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17. TC2 – Timer/Counter Type 2
17.1 Features
•Eight eight-bit timer/counters
– Four Low-byte timer/co un te r
– Four High-byte timer/counter
•Up to eight compare channels in each Timer/Counter 2
– Four com pa r e channels for the low-byte timer/counter
– Four compare channels for the high-byte timer/counter
•Waveform generation
– Single slope pulse width modulation
•Timer underflow interrupts/events
•One compare match interrupt/event per compare channel for the low-byte timer/counter
•Can be used with the event system for count control
17.2 Overview
There are four Timer/Counter 2. These are realized when a Timer/Counter 0 is set in split mode. It is then a system of
two eight-bit timer/counters, each with four compare channels. This results in eight configurable pulse width modulation
(PWM) channels with individually controlled duty cycles, and is intended for applications that require a high number of
PWM channels.
The two eight-bit timer/counters in this system are referred to as the low-byte timer/counter and high-byte timer/counter,
respectively. The difference between them is that only the low-byte timer/counter can be used to generate compare
match interrupts and events. The two eight-bit timer/counters have a shared clock source and separate period and
compare settings. They can be clocked and timed from the peripheral clock, with optional prescaling, or from the event
system. The counters are always counting down.
PORTC, PORTD, PORTE, and PORTF each has one Timer/Counter 2. Notation of these are TCC2 (Time/Counter C2),
TCD2, TCE2, and TCF2, respectively.
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18. AWeX – Advanced Waveform Extension
18.1 Features
•Waveform output with complementary output from each compare channel
•Four dead-time insertion (DTI) units
– 8-bit resolution
– Separate high and low side dead-time setting
– Double buffe re d dead time
– Optionally halts timer during dead-time insertion
•Pattern generation unit creating synchronised bit pattern across the port pins
– Double buffe re d patt ern ge ne ra tio n
– Optional distribution of one compare channel output across the port pins
•Event controlled fault protection for instant and predictable fault triggering
18.2 Overview
The advanced waveform extension (AWeX) provides extra functions to the timer/counter in waveform generation (WG)
modes. It is primarily intended for use with different types of motor control and other power control applications. It
enables low- and high side output with dead-time insertion and fault protection for disabling and shutting down external
drivers. It can also generate a synchronized bit pattern across the port pins.
Each of the waveform generator outputs from the timer/counter 0 are split into a complimentary pair of outputs when any
AWeX features are enabled. These output pairs go through a dead-time insertion (DTI) unit that generates the non-
inverted low side (LS) and inverted high side (HS) of the WG output with dead-time insertion between LS and HS
switching. The DTI output will override the normal port value according to the port override setting.
The pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In addition,
the WG output from compare channel A can be distributed to and override all the port pins. When the pattern generator
unit is enabled, the DTI unit is bypassed.
The fault protection unit is connected to the event system, enabling any event to trigger a fault condition that will disable
the AWeX output. The event system ensures predictable and instant fault reaction, and gives flexibility in the selection of
fault triggers.
The AWeX is available for TCC0. The notation of this is AWEXC.
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19. Hi-Res – High Resolution Extension
19.1 Features
•Increases waveform gen erator resolution up to 8x (three bits)
•Supports frequency, single-slope PWM, and dual-slope PWM generation
•Supports the AWeX when this is used for the same tim e r/counter
19.2 Overview
The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a
timer/counter by four or eight. It can be used for a timer/counter doing frequency, single-slope PWM, or dual-slope PWM
generation. It can also be used with the AWeX if this is used for the same timer/counter.
The hi-res extension uses the peripheral 4x clock (ClkPER4). The system clock prescalers must be configured so the
peripheral 4x clock frequency is four times higher than the peripheral and CPU clock frequency when the hi-res extension
is enabled.
There is one hi-res extensions that can be enabled for timer/counters pair on PORTC. The notation of this is HIRESC.
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20. RTC – 16-bit Real-Time Counter
20.1 Features
•16-bit resolution
•Selectable clock source
– 32.768kHz external crystal
– External clock
– 32.768kHz internal oscillator
– 32kHz inter na l U LP os ci llator
•Programmable 10-bit clock prescaling
•One compare register
•One period register
•Clear counter on perio d ove rfl ow
•Optional interrupt/event on overflow and compare match
20.2 Overview
The 16-bit real-time counter (RTC) is a counter that typically runs continuously, including in low-power sleep modes, to
keep track of time. It can wake up the device from sleep modes and/or interrupt the device at regular intervals.
The reference clock is typically the 1.024kHz output from a high-accuracy crystal of 32.768kHz, and this is the
configuration most optimized for low power consumption. The faster 32.768kHz output can be selected if the RTC needs
a resolution higher than 1ms. The RTC can also be clocked from an external clock signal, the 32.768kHz internal
oscillator or the 32kHz internal ULP oscillator.
The RTC includes a 10-bit programmable prescaler that can scale down the reference clock before it reaches the
counter. A wide range of resolutions and time-out periods can be configured. With a 32.768kHz clock source, the
maximum resolution is 30.5µs, and time-out periods can range up to 2000 seconds. With a resolution of 1s, the
maximum timeout period is more than18 hours (65536 seconds). The RTC can give a compare interrupt and/or event
when the counter equals the compare register value, and an overflow interrupt and/or event when it equals the period
register value.
Figure 20-1. Real-time Counter Overview
32.768kHz Crystal Osc
32.768kHz Int. Osc
TOSC1
TOSC2
External Clock
DIV32
DIV32
32kHz int ULP (DIV32)
RTCSRC
10-bit
prescaler
clkRTC
CNT
PER
COMP
=
=
”match”/
Compare
TOP/
Overflow
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21. USB – Universal Serial Bus Interface
21.1 Features
•One USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface
•Integrated on-chip USB transceiver, no external components needed
•16 endpoint addresses with full endpoint flexibility for up to 31 endpoint s
– One input endpoint per endpoint address
– One output endpoint per endpoint address
•Endpoint address transfer type selectable to
– Control transfers
– Interrupt transfers
– Bulk tran s f er s
– Isochronou s transfers
•Configurable data payload size per endpoint, up to 1023 bytes
•Endpoint configuration and data buffers located in internal SRAM
– Configurabl e loc a tio n for en dpoin t configuration data
– Configurable locati on for each endpoint's data buffer
•Built-in direct memory access (DMA) to internal SRAM for:
– Endpoint configurations
– Reading and writing endpoint data
•Ping-pong opera t io n for hig he r thro ug hput and double buffe red ope r ati on
– Input and outpu t endpoint data buffers used in a single directi on
– CPU/DMA controller can update data buffer during transfer
•Multipacket transfer for reduced interrupt load and software intervention
– Data payload exceeding maximum packet size is transferred in one continuous transfer
– No interrupts or software interaction on packet transaction level
•Tra nsaction complete FIFO for workflow management when usin g multiple endpoints
– Tracks all completed transactions in a first-come, first-served work queue
•Clock selection independent of system clock source and selection
•Minimum 1.5MHz CPU clock required for low speed USB operation
•Minimum 12MHz CPU clock required for full speed operation
•Connection to event system
•On chip debug possibilities during USB transactio ns
21.2 Overview
The USB module is a USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface.
The USB supports 16 endpoint addresses. All endpoint addresses have one input and one output endpoint, for a total of
31 configurable endpoints and one control endpoint. Each endpoint address is fully configurable and can be configured
for any of the four transfer types; control, interrupt, bulk, or isochronous. The data payload size is also selectable, and it
supports data payloads up to 1023 bytes.
No dedicated memory is allocated for or included in the USB module. Internal SRAM is used to keep the configuration for
each endpoint address and the data buffer for each endpoint. The memory locations used for endpoint configurations
and data buffers are fully configurable. The amount of memory allocated is fully dynamic, according to the number of
endpoints in use and the configuration of these. The USB module has built-in direct memory access (DMA), and will
read/write data from/to the SRAM when a USB transaction takes place.
To maximize throughput, an endpoint address can be configured for ping-pong operation. When done, the input and
output endpoints are both used in the same direction. The CPU or DMA controller can then read/write one data buffer
while the USB module writes/reads the others, and vice versa. This gives double buffered communication.
Multipacket transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as
multiple packets without software intervention. This reduces the CPU intervention and the interrupts needed for USB
transfers.
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For low-power operation, the USB module can put the microcontroller into any sleep mode when the USB bus is idle and
a suspend condition is given. Upon bus resumes, the USB module can wake up the microcontroller from any sleep
mode.
PORTD has one USB. Notation of this is USB.
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22. TWI – Two-Wire Interface
22.1 Features
•Two identical two-wire interface peripherals
•Bidirectional, two-wire communication inte rface
– Phillips I2C compatible
– System Management Bus (SMBus) compatible
•Bus master and slave operation supported
– Slave operation
– Single bus master operatio n
– Bus master in multi-master bus envir on ment
– Multi-master arbitration
•Flexible slave address match functions
– 7-bit and general call address recognition in hardware
– 10-bit ad dressing supported
– Address mask register for dual address match or address range masking
– Optional software address recognition for unlimited number of addresses
•Slave can operate in all sleep modes, including power-down
•Slave address match can wake device from all sleep modes
•100kHz and 400kHz bus frequency support
•Slew-rate limited output drivers
•Input filter for bus noise and spike suppres sio n
•Support arbitration betwe en start/repeated start and data bit (SMBus)
•Slave arbitration allows support for address resolve protocol (ARP) (SMBus)
22.2 Overview
The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I2C and System Management Bus
(SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each bus line.
A device connected to the bus must act as a master or a slave. The master initiates a data transaction by addressing a
slave on the bus and telling whether it wants to transmit or receive data. One bus can have many slaves and one or
several masters that can take control of the bus. An arbitration process handles priority if more than one master tries to
transmit data at the same time. Mechanisms for resolving bus contention are inherent in the protocol.
The TWI module supports master and slave functionality. The master and slave functionality are separated from each
other, and can be enabled and configured separately. The master module supports multi-master bus operation and
arbitration. It contains the baud rate generator. Both 100kHz and 400kHz bus frequency is supported. Quick command
and smart mode can be enabled to auto-trigger operations and reduce software complexity.
The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is
also supported. A dedicated address mask register can act as a second address match register or as a register for
address range masking. The slave continues to operate in all sleep modes, including power-down mode. This enables
the slave to wake up the device from all sleep modes on TWI address match. It is possible to disable the address
matching to let this be handled in software instead.
The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors, collision,
and clock hold on the bus are also detected and indicated in separate status flags available in both master and slave
modes.
It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external
TWI bus driver. This can be used for applications where the device operates from a different VCC voltage than used by
the TWI bus.
PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE.
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23. SPI – Serial Peripheral Interface
23.1 Features
•Two Identical SPI peripherals
•Full-duplex, three-wire synchronous data transfer
•Master or slave operation
•Lsb first or msb first data transfer
•Eight programmable bit rates
•Interrupt flag at the end of transmission
•Write collision flag to indicate data collision
•Wake up from idle sleep mode
•Double speed master mode
23.2 Overview
The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. It
allows fast communication between an Atmel AVR XMEGA device and peripheral devices or between several
microcontrollers. The SPI supports full-duplex communication.
A device connected to the bus must act as a master or slave. The master initiates and controls all data transactions.
PORTC and PORTD each has one SPI. Notation of these peripherals are SPIC and SPID, respectively.
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24. USART
24.1 Features
•Three identical USART peripherals
•Full-duplex operation
•Asynchronous or synchronous operation
– Synchronous clock rates up to 1/2 of the device clock frequency
– Asynchronous cloc k rat es up to 1/8 of the devi ce clo ck frequency
•Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits
•Fractional ba ud rate generator
– Can generate desired b aud rate from any system clock frequency
– No need for external oscillator with certain frequencies
•Built-in error detection and co rrection schemes
– Odd or even parity generation and parity check
– Data overrun and framing error detection
– Noise filtering includes false start bit detection and digital low-pass filter
•Separate interrupts for
– Transmit complete
– Transmit data register empty
– Receive complete
•Multiprocessor co mmunication mode
– Addressing scheme to address a specific devices on a multidevice bus
– Enable unaddressed devices to automatically ignore all frames
•Master SPI mode
– Double bu ffe re d operation
– Operation up to 1/2 of the peripheral clock frequency
•IRCOM module for IrDA compliant puls e mo du la tio n/ dem od ula t i on
24.2 Overview
The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast and flexible serial
communication module. The USART supports full-duplex communication and asynchronous and synchronous operation.
The USART can be configured to operate in SPI master mode and used for SPI communication.
Communication is frame based, and the frame format can be customized to support a wide range of standards. The
USART is buffered in both directions, enabling continued data transmission without any delay between frames. Separate
interrupts for receive and transmit complete enable fully interrupt driven communication. Frame error and buffer overflow
are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can
also be enabled.
The clock generator includes a fractional baud rate generator that is able to generate a wide range of USART baud rates
from any system clock frequencies. This removes the need to use an external crystal oscillator with a specific frequency
to achieve a required baud rate. It also supports external clock input in synchronous slave operation.
When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit and receive
buffers, shift registers, and baud rate generator enabled. Pin control and interrupt generation are identical in both modes.
The registers are used in both modes, but their functionality differs for some control settings.
An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation and
demodulation for baud rates up to 115.2kbps.
PORTC, PORTD, and PORTE each has one USART. Notation of these peripherals are USARTC0, USARTD0, and
USARTE0, respectively.
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25. IRCOM – IR Communication Module
25.1 Features
•Pulse modulation/demodul ati on for infrared commu ni cation
•IrDA compatible for baud rates up to 115.2Kbps
•Selectable pulse modulation scheme
– 3/16 of the baud rate pe riod
– Fixed pulse pe riod, 8-bit programmable
– Pulse modulation disabled
•Built-in filtering
•Can be connected to and us ed by any USART
25.2 Overview
Atmel AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates
up to 115.2Kbps. It can be connected to any USART to enable infrared pulse encoding/decoding for that USART.
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26. AES Crypto Engine
26.1 Features
•Advanced Encryption Standard (AES) crypto module
•DES Instruction
– Encryption and decryption
– DES supported
– Encryption/decryption in 16 CPU clock cycles per 8-byte block
•AES crypto module
– Encryption and decryption
– Supports 128-bit keys
– Supports XOR data load mode to the state memory
– Encryption/decryption in 375 clock cycles per 16-byte block
26.2 Overview
The Advanced Encryption Standard (AES) is a commonly used standards for cryptography. It is supported through an
AES peripheral module, and the communication interfaces and the CPU can use these for fast, encrypted
communication and secure data storage.
The AES crypto module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key. The key and data must
be loaded into the key and state memory in the module before encryption/decryption is started. It takes 375 peripheral
clock cycles before the encryption/decryption is done. The encrypted/encrypted data can then be read out, and an
optional interrupt can be generated. The AES crypto module also has DMA support with transfer triggers when
encryption/decryption is done and optional auto-start of encryption/decryption when the state memory is fully loaded.
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27. CRC – Cyclic Redundancy Check Generator
27.1 Features
•Cyclic redundancy check (CRC) generation and checking for
– Communication da ta
– Program or data in flash memory
– Data in SRAM and I/O memory space
•Integrated with flash memory, DMA controller and CPU
– Continuous CRC on data going through a DMA channel
– Automatic CRC of the complete or a selectable range of the flash memory
– CPU can load data to the CRC generator through the I/O interface
•CRC polynomial software selectable to
– CRC-16 (CRC-CCITT)
– CRC-32 (IEEE 802.3)
•Zero remainder detection
27.2 Overview
A cyclic redundancy check (CRC) is an error detection technique test algorithm used to find accidental errors in data, and
it is commonly used to determine the correctness of a data transmission, and data present in the data and program
memories. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be
appended to the data and used as a checksum. When the same data are later received or read, the device or application
repeats the calculation. If the new CRC result does not match the one calculated earlier, the block contains a data error.
The application will then detect this and may take a corrective action, such as requesting the data to be sent again or
simply not using the incorrect data.
Typically, an n-bit CRC applied to a data block of arbitrary length will detect any single error burst not longer than n bits
(any single alteration that spans no more than n bits of the data), and will detect the fraction 1-2-n of all longer error
bursts. The CRC module in Atmel AVR XMEGA devices supports two commonly used CRC polynomials; CRC-16 (CRC-
CCITT) and CRC-32 (IEEE 802.3).
CRC-16:
CRC-32:
Polynomial: x16+x12+x5+1
Hex value: 0x1021
Polynomial: x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
Hex value: 0x04C11DB7
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28. ADC – 12-bit Analog to Digital Converter
28.1 Features
•One Analog to Digital Converter (ADC)
•12-bit resolution
•Up to 300 thousand samples per second
– Down to 2.3µs conversion time with 8-bit resolution
– Down to 3.35µs conversion time with 12-bit resolution
•Differential and single-en ded input
– 16 single-ended inputs
– 16x4 differential inputs without gain
– 8x4 differ e nti al input with gain
•Built-in differential gain stage
–1/2x, 1x, 2x, 4x, 8x, 16x, 32x, and 64x gain options
•Single, continuous and scan conversion options
•Three internal inputs
– Internal temperature senso r
–AV
CC voltage divided by 10
– 1.1V bandgap voltage
•Internal and external reference options
•Compare function for accurate monitoring of user defined thresholds
•Optional event triggered co nversion for accurate timing
•Optional DMA transfer of conversion results
•Optional interrupt/event on compare result
28.2 Overview
The ADC converts analog signals to digital values. The ADC has 12-bit resolution and is capable of converting up to 300
thousand samples per second (ksps). The input selection is flexible, and both single-ended and differential
measurements can be done. For differential measurements, an optional gain stage is available to increase the dynamic
range. In addition, several internal signal inputs are available. The ADC can provide both signed and unsigned results.
The ADC measurements can either be started by application software or an incoming event from another peripheral in
the device. The ADC measurements can be started with predictable timing, and without software intervention. It is
possible to use DMA to move ADC results directly to memory or peripherals when conversions are done.
Both internal and external reference voltages can be used. An integrated temperature sensor is available for use with the
ADC. The AVCC/10 and the bandgap voltage can also be measured by the ADC.
The ADC has a compare function for accurate monitoring of user defined thresholds with minimum software intervention
required.
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Figure 28-1. ADC Overview
The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from
3.35µs for 12-bit to 2.3µs for 8-bit result.
ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This eases calculation when
the result is represented as a signed integer (signed 16-bit number).
PORTA has one ADC. Notation of this peripheral is ADCA.
CH0 Result
Compare
Register
<
>
Threshold
(Int Req)
Internal 1.00V
Internal AVCC/1.6V
AREFA
AREFB
VINP
VINN
Internal
signals
Internal AVCC/2
ADC0
A
DC15
•
•
•
ADC0
ADC7
•
•
•
Reference
Voltage
ADC
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29. AC – Analog Comparator
29.1 Features
•Two Analog Comparators (AC)
•Selectable hysteresis
–No
–Small
–Large
•Analog comparator output available on pin
•Flexible input selection
– All pins on the port
– Bandgap reference voltage
– A 64-level programmable voltage scaler of the internal AVCC voltage
•Interrupt and event generation on:
– Rising edge
– Falling edge
– Toggle
•Window function interrupt and event gene ra tion on:
– Signal above window
– Signal inside window
– Signal below window
•Constant current source with conf igurable output pin selection
29.2 Overview
The analog comparator (AC) compares the voltage levels on two inputs and gives a digital output based on this
comparison. The analog comparator may be configured to generate interrupt requests and/or events upon several
different combinations of input change.
The analog comparator hysteresis can be adjusted in order to achieve the optimal operation for each application.
The input selection includes analog port pins, several internal signals, and a 64-level programmable voltage scaler. The
analog comparator output state can also be output on a pin for use by external devices.
A constant current source can be enabled and output on a selectable pin. This can be used to replace, for example,
external resistors used to charge capacitors in capacitive touch sensing applications.
The analog comparators are always grouped in pairs on each port. These are called analog comparator 0 (AC0) and
analog comparator 1 (AC1). They have identical behavior, but separate control registers. Used as pair, they can be set in
window mode to compare a signal to a voltage range instead of a voltage level.
PORTA has one AC pair. Notation is ACA.
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Figure 29-1. Analog Comparator Overview
The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in
Figure 29-2.
Figure 29-2. Analog Comparator Window Function
ACnMUXCTRL ACnCTRL
Interrupt
Mode
Enable
Enable
Hysteresis
Hysteresis
AC1OUT
WINCTRL
Interrupt
Sensititivity
Control
&
Window
Function
Events
Interrupts
AC0OUT
Pin Input
Pin Input
Pin Input
Pin Input
Voltage
Scaler
Bandgap
+
AC0
-
+
AC1
-
AC0
+
-
AC1
+
-
Input signal
Upper limit of window
Lower limit of window
Interrupt
sensitivity
control
Interrupts
Events
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30. Programming and Debugging
30.1 Features
•Programming
– External programming through PDI interface
Minimal protocol overhead for fast operation
Built-in error detection and handling for reliable operation
– Boot loader support for programming through any communic ation interface
•Debugging
– Nonintrusive, real-time, on-chip debug system
– No software or hardware resources required from device except pin connection
– Program flo w control
Go, Stop, Reset, Step Into, Step Over, Step Out, Run-to-Cursor
– Unlimited number of user program breakpoints
– Unlimited number of user data breakpoints, break on:
Data location read, write, or both read and write
Data locati on content equal or not equal to a valu e
Data location content is greater or smaller than a value
Data location content is within or outside a range
– No limitation on device clock frequency
•Program and Debug Interface (PDI)
– Two-pin interface for external programming and debugging
– Uses the Reset pin and a dedicated pin
– No I/O pins required during programming or debugging
30.2 Overview
The Program and Debug Interface (PDI) is an Atmel proprietary interface for external programming and on-chip
debugging of a device.
The PDI supports fast programming of nonvolatile memory (NVM) spaces; flash, EEPOM, fuses, lock bits, and the user
signature row.
Debug is supported through an on-chip debug system that offers nonintrusive, real-time debug. It does not require any
software or hardware resources except for the device pin connection. Using the Atmel tool chain, it offers complete
program flow control and support for an unlimited number of program and complex data breakpoints. Application debug
can be done from a C or other high-level language source code level, as well as from an assembler and disassembler
level.
Programming and debugging can be done through the PDI physical layer. This is a two-pin interface that uses the Reset
pin for the clock input (PDI_CLK) and one other dedicated pin for data input and output (PDI_DATA). Any external
programmer or on-chip debugger/emulator can be directly connected to this interface.
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31. Pinout and Pin Functions
The device pinout is shown in “Pinout/Block Diagram” on page 3. In addition to general purpose I/O functionality, each
pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin.
Only one of the pin functions can be used at time.
31.1 Alternate Pin Function Description
The tables below show the notation for all pin functions available and describe its function.
31.1.1 Operation/Power Supply
31.1.2 Port Interrupt Functions
31.1.3 Analog Functions
31.1.4 Timer/Counter and AWEX Functions
VCC Digital supply voltage
AVCC Analog supply voltage
GND Ground
SYNC Port pin with full synchronous and limited asynchronous interrupt function
ASYNC Port pin with full synchronous and full asynchronous interrupt function
ACn Analog Comparator input pin n
ACnOUT Analog Comparator n Output
ADCn Analog to Digital Converter input pin n
AREF Analog Reference input pin
OCnxLS Output Compare Channel x Low Side for Timer/Counter n
OCnxHS Output Compare Channel x High Side for Timer/Counter n
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31.1.5 Communication Functions
31.1.6 Oscillators, Clock, and Event
31.1.7 Debug/System Functions
SCL Serial Clock for TWI
SDA Serial Data for TWI
SCLIN Serial Clock In for TWI when external driver interface is enabled
SCLOUT Serial Clock Out for TWI when external driver interface is enabled
SDAIN Serial Data In for TWI when external driver interface is enabled
SDAOUT Serial Data Out for TWI when external driver interface is enabled
XCKn Transfer Clock for USART n
RXDn Receiver Data for USART n
TXDn Transmitter Data for USART n
SS Slave Select for SPI
MOSI Master Out Slave In for SPI
MISO Master In Slave Out for SPI
SCK Serial Clock for SPI
D- Data- for USB
D+ Data+ for USB
TOSCn Timer Oscillator pin n
XTALn Input/Output for Oscillator pin n
CLKOUT Peripheral Clock Output
EVOUT Event Channel Output
RTCOUT RTC Clock Source Output
RESET Reset pin
PDI_CLK Program and Debug Interface Clock pin
PDI_DATA Program and Debug Interface Data pin
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31.2 Alternate Pin Functions
The tables below show the primary/default function for each pin on a port in the first column, the pin number in the
second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that
enable and use the alternate pin functions.
For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under the
first table where this apply.
Table 31-1. Port A - Alternate Functions
PORT A PIN # INTERRUPT ADCA POS/
GAIN POS ADCA NEG ADCA
GAINNEG ACA POS ACA NEG ACA OUT REFA
GND 60
AVCC 61
PA0 62 SYNC ADC0 ADC0 AC0 AC0 AREFA
PA1 63 SYNC ADC1 ADC1 AC1 AC1
PA2 64 SYNC/ASYN
CADC2 ADC2 AC2
PA3 1SYNC ADC3 ADC3 AC3 AC3
PA4 2SYNC ADC4 ADC4 AC4
PA5 3SYNC ADC5 ADC5 AC5 AC5
PA6 4SYNC ADC6 ADC6 AC6 AC1OUT
PA7 5SYNC ADC7 ADC7 AC7 AC0OUT
Table 31-2. Port B - Alternate Functions
PORT B PIN # INTERRUPT ADCA POS REFB
PB0 6SYNC ADC8 AREFB
PB1 6SYNC ADC9
PB2 8SYNC/
ASYNC ADC10
PB3 9SYNC ADC11
PB4 10 SYNC ADC12
PB5 11 SYNC ADC13
PB6 12 SYNC ADC14
PB7 13 SYNC ADC15
GND 14
VCC 15
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Table 31-3. Port C - Alternate Functions
Notes: 1. Pin mapping of all TC0 can optionally be moved to high nibble of port.
2. If TC0 is configured as TC2 all eight pins can be used for PWM output.
3. Pin mapping of all USART0 can optionally be moved to high nibble of port.
4. Pins MOSI and SCK for all SPI can optionally be swapped.
5. CLKOUT can optionally be moved between port C, D and E and between pin 4 and 7.
6. EVOUT can optionally be moved between port C, D and E and between pin 4 and 7.
PORT C PIN # INTERRUPT TCC0(1)(2) AWEXC TCC1 USARTC0(3) SPIC(4) TWIC CLOCKOUT (5) EVENTOUT(6)
PC0 16 SYNC OC0A OC0ALS SDA
PC1 17 SYNC OC0B OC0AHS XCK0 SCL
PC2 18 SYNC/
ASYNC OC0C OC0BLS RXD0
PC3 19 SYNC OC0D OC0BHS TXD0
PC4 20 SYNC OC0CLS OC1A SS
PC5 21 SYNC OC0CHS OC1B MOSI
PC6 22 SYNC OC0DLS MISO RTCOUT
PC7 23 SYNC OC0DHS SCK clkPER EVOUT
GND 24
VCC 25
Table 31-4. Port D - Alternate Functions
PORT D PIN # INTERRUPT TCD0 USARTD0 SPID USB CLOCKOUT EVENTOUT
PD0 26 SYNC OC0A
PD1 27 SYNC OC0B XCK0
PD2 28 SYNC/
ASYNC OC0C RXD0
PD3 29 SYNC OC0D TXD0
PD4 30 SYNC SS
PD5 31 SYNC MOSI
PD6 32 SYNC MISO D-
PD7 33 SYNC SCK D+ ClkPER EVOUT
GND 34
VCC 35
Table 31-5. Port E - Alternate Functions
PORT E PIN # INTERRUPT TCE0 USARTE0 TOSC TWIE CLOCKOUT EVENTOUT
PE0 36 SYNC OC0A SDA
PE1 37 SYNC OC0B XCK0 SCL
PE2 38 SYNC/
ASYNC OC0C RXD0
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PE3 39 SYNC OC0D TXD0
PE4 40 SYNC
PE5 41 SYNC
PE6 42 SYNC TOSC2
PE7 43 SYNC TOSC1 ClkPER EVOUT
GND 44
VCC 45
Table 31-5. Port E - Alternate Functions
PORT E PIN # INTERRUPT TCE0 USARTE0 TOSC TWIE CLOCKOUT EVENTOUT
Table 31-6. Port F - Alternate Functions
PORT F PIN # INTERRUPT TCF0
PF0 46 SYNC OC0A
PF1 47 SYNC OC0B
PF2 48 SYNC/
ASYNC OC0C
PF3 49 SYNC OC0D
PF4 50 SYNC
PF5 51 SYNC
PF6 54 SYNC
PF7 55 SYNC
GND 52
VCC 53
Table 31-7. Port R - Alternate functions
PORT R PIN # INTERRUPT PDI XTAL
PDI 56 PDI_DATA
RESET 57 PDI_CLOCK
PRO 58 SYNC XTAL2
PR1 59 SYNC XTAL1
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32. Peripheral Module Address Map
The address maps show the base address for each peripheral and module in Atmel AVR XMEGA C3. For complete
register description and summary for each peripheral module, refer to the XMEGA C manual.
Table 32-1. Peripheral Module Address Map
Base address Name Description
0x0000 GPIO General Purpose IO Registers
0x0010 VPORT0 Virtual Port 0
0x0014 VPORT1 Virtual Port 1
0x0018 VPORT2 Virtual Port 2
0x001C VPORT3 Virtual Port 2
0x0030 CPU CPU
0x0040 CLK Clock Control
0x0048 SLEEP Sleep Controller
0x0050 OSC Oscillator Control
0x0060 DFLLRC32M DFLL for the 32 MHz Internal RC Oscillator
0x0068 DFLLRC2M DFLL for the 2 MHz RC Oscillator
0x0070 PR Power Reduction
0x0078 RST Reset Controller
0x0080 WDT Watch-Dog Timer
0x0090 MCU MCU Control
0x00A0 PMIC Programmable MUltilevel Interrupt Controller
0x00B0 PORTCFG Port Configuration
0x0180 EVSYS Event System
0x00C0 AES AES Module
0x00D0 CRC CRC Module
0x0100 DMA DMA Controller
0x01C0 NVM Non Volatile Memory (NVM) Controller
0x0200 ADCA Analog to Digital Converter on port A
0x0380 ACA Analog Comparator pair on port A
0x0400 RTC Real Time Counter
0x0480 TWIC Two-Wire Interface on port C
0x04C0 USB Universal Serial Bus Interface
0x04A0 TWIE Two Wire Interface on port E
0x0600 PORTA Port A
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0x0620 PORTB Port B
0x0640 PORTC Port C
0x0660 PORTD Port D
0x0680 PORTE Port E
0x06A0 PORTF Port F
0x07E0 PORTR Port R
0x0800 TCC0 Timer/Counter 0 on port C
0x0840 TCC1 Timer/Counter 1 on port C
0x0880 AWEXC Advanced Waveform Extension on port C
0x0890 HIRESC High Resolution Extension on port C
0x08A0 USARTC0 USART 0 on port C
0x08C0 SPIC Serial Peripheral Interface on port C
0x08F8 IRCOM Infrared Communication Module
0x0900 TCD0 Timer/Counter 0 on port D
0x09A0 USARTD0 USART 0 on port D
0x09C0 SPID Serial Peripheral Interface on port D
0x0A00 TCE0 Timer/Counter 0 on port E
0x0A80 AWEXE Advanced Waveform Extensionon port E
0x0AA0 USARTE0 USART 0 on port E
0x0AC0 SPIE Serial Peripheral Interface on port E
0x0B00 TCF0 Timer/Counter 0 on port F
Base address Name Description
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33. Instruction Set Summary
Mnemonics Operands Description Operation Flags #Clocks
Arithmetic and Logic Instructions
ADD Rd, Rr Add without Carry Rd Rd + Rr Z,C,N,V,S,H 1
ADC Rd, Rr Add with Carry Rd Rd + Rr + C Z,C,N,V,S,H 1
ADIW Rd, K Add Immediate to Word Rd Rd + 1:Rd + K Z,C,N,V,S 2
SUB Rd, Rr Subtract without Carry Rd Rd - Rr Z,C,N,V,S,H 1
SUBI Rd, K Subtract Immediate Rd Rd - K Z,C,N,V,S,H 1
SBC Rd, Rr Subtract with Carry Rd Rd - Rr - C Z,C,N,V,S,H 1
SBCI Rd, K Subtract Immediate with Carry Rd Rd - K - C Z,C,N,V,S,H 1
SBIW Rd, K Subtract Immediate from Word Rd + 1:Rd Rd + 1:Rd - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Rd Rd Rr Z,N,V,S 1
ANDI Rd, K Logical AND with Immediate Rd Rd K Z,N,V,S 1
OR Rd, Rr Logical OR Rd Rd v Rr Z,N,V,S 1
ORI Rd, K Logical OR with Immediate Rd Rd v K Z,N,V,S 1
EOR Rd, Rr Exclusive OR Rd Rd Rr Z,N,V,S 1
COM Rd One’s Complement Rd $FF - Rd Z,C,N,V,S 1
NEG Rd Two’s Complement Rd $00 - Rd Z,C,N,V,S,H 1
SBR Rd,K Set Bit(s) in Register Rd Rd v K Z,N,V,S 1
CBR Rd,K Clear Bit(s) in Register Rd Rd ($FFh - K) Z,N,V,S 1
INC Rd Increment Rd Rd + 1 Z,N,V,S 1
DEC Rd Decrement Rd Rd - 1 Z,N,V,S 1
TST Rd Test for Zero or Minus Rd Rd Rd Z,N,V,S 1
CLR Rd Clear Register Rd Rd Rd Z,N,V,S 1
SER Rd Set Register Rd $FF None 1
MUL Rd,Rr Multiply Unsigned R1:R0 Rd x Rr (UU) Z,C 2
MULS Rd,Rr Multiply Signed R1:R0 Rd x Rr (SS) Z,C 2
MULSU Rd,Rr Multiply Signed with Unsigned R1:R0 Rd x Rr (SU) Z,C 2
FMUL Rd,Rr Fractional Multiply Unsigned R1:R0 Rd x Rr<<1 (UU) Z,C 2
FMULS Rd,Rr Fractional Multiply Signed R1:R0 Rd x Rr<<1 (SS) Z,C 2
FMULSU Rd,Rr Fractional Multiply Signed with Unsigned R1:R0 Rd x Rr<<1 (SU) Z,C 2
DES KData Encryption if (H = 0) then R15:R0
else if (H = 1) then R15:R0
Encrypt(R15:R0, K)
Decrypt(R15:R0, K) 1/2
Branch instructions
RJMP kRelative Jump PC PC + k + 1 None 2
IJMP Indirect Jump to (Z) PC(15:0)
PC(21:16)
Z,
0None 2
EIJMP Extended Indirect Jump to (Z) PC(15:0)
PC(21:16)
Z,
EIND None 2
JMP kJump PC kNone 3
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RCALL kRelative Call Subroutine PC PC + k + 1 None 2 / 3(1)
ICALL Indirect Call to (Z) PC(15:0)
PC(21:16)
Z,
0None 2 / 3(1)
EICALL Extended Indirect Call to (Z) PC(15:0)
PC(21:16)
Z,
EIND None 3(1)
CALL kcall Subroutine PC kNone 3 / 4(1)
RET Subroutine Return PC STACK None 4 / 5(1)
RETI Interrupt Return PC STACK I4 / 5(1)
CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC PC + 2 or 3 None 1 / 2 / 3
CP Rd,Rr Compare Rd - Rr Z,C,N,V,S,H 1
CPC Rd,Rr Compare with Carry Rd - Rr - C Z,C,N,V,S,H 1
CPI Rd,K Compare with Immediate Rd - K Z,C,N,V,S,H 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC PC + 2 or 3 None 1 / 2 / 3
SBRS Rr, b Skip if Bit in Register Set if (Rr(b) = 1) PC PC + 2 or 3 None 1 / 2 / 3
SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b) = 0) PC PC + 2 or 3 None 2 / 3 / 4
SBIS A, b Skip if Bit in I/O Register Set If (I/O(A,b) =1) PC PC + 2 or 3 None 2 / 3 / 4
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC PC + k + 1 None 1 / 2
BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC PC + k + 1 None 1 / 2
BREQ k Branch if Equal if (Z = 1) then PC PC + k + 1 None 1 / 2
BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1 None 1 / 2
BRCS k Branch if Carry Set if (C = 1) then PC PC + k + 1 None 1 / 2
BRCC k Branch if Carry Cleared if (C = 0) then PC PC + k + 1 None 1 / 2
BRSH k Branch if Same or Higher if (C = 0) then PC PC + k + 1 None 1 / 2
BRLO k Branch if Lower if (C = 1) then PC PC + k + 1 None 1 / 2
BRMI k Branch if Minus if (N = 1) then PC PC + k + 1 None 1 / 2
BRPL k Branch if Plus if (N = 0) then PC PC + k + 1 None 1 / 2
BRGE k Branch if Greater or Equal, Signed if (N V= 0) then PC PC + k + 1 None 1 / 2
BRLT k Branch if Less Than, Signed if (N V= 1) then PC PC + k + 1 None 1 / 2
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC PC + k + 1 None 1 / 2
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC PC + k + 1 None 1 / 2
BRTS k Branch if T Flag Set if (T = 1) then PC PC + k + 1 None 1 / 2
BRTC k Branch if T Flag Cleared if (T = 0) then PC PC + k + 1 None 1 / 2
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC PC + k + 1 None 1 / 2
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None 1 / 2
BRIE k Branch if Interrupt Enabled if (I = 1) then PC PC + k + 1 None 1 / 2
BRID k Branch if Interrupt Disabled if (I = 0) then PC PC + k + 1 None 1 / 2
Data transfer instructions
MOV Rd, Rr Copy Register Rd Rr None 1
MOVW Rd, Rr Copy Register Pair Rd+1:Rd Rr+1:Rr None 1
Mnemonics Operands Description Operation Flags #Clocks
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LDI Rd, K Load Immediate Rd KNone 1
LDS Rd, k Load Direct from data space Rd (k) None 2(1)(2)
LD Rd, X Load Indirect Rd (X) None 1(1)(2)
LD Rd, X+ Load Indirect and Post-Increment Rd
X
(X)
X + 1 None 1(1)(2)
LD Rd, -X Load Indirect and Pre-Decrement X X - 1,
Rd (X)
X - 1
(X) None 2(1)(2)
LD Rd, Y Load Indirect Rd (Y) (Y) None 1(1)(2)
LD Rd, Y+ Load Indirect and Post-Increment Rd
Y
(Y)
Y + 1 None 1(1)(2)
LD Rd, -Y Load Indirect and Pre-Decrement Y
Rd
Y - 1
(Y) None 2(1)(2)
LDD Rd, Y+q Load Indirect with Displacement Rd (Y + q) None 2(1)(2)
LD Rd, Z Load Indirect Rd (Z) None 1(1)(2)
LD Rd, Z+ Load Indirect and Post-Increment Rd
Z
(Z),
Z+1 None 1(1)(2)
LD Rd, -Z Load Indirect and Pre-Decrement Z
Rd
Z - 1,
(Z) None 2(1)(2)
LDD Rd, Z+q Load Indirect with Displacement Rd (Z + q) None 2(1)(2)
STS k, Rr Store Direct to Data Space (k) Rd None 2(1)
ST X, Rr Store Indirect (X) Rr None 1(1)
ST X+, Rr Store Indirect and Post-Increment (X)
X
Rr,
X + 1 None 1(1)
ST -X, Rr Store Indirect and Pre-Decrement X
(X)
X - 1,
Rr None 2(1)
ST Y, R r Store Indirect (Y) Rr None 1(1)
ST Y+, Rr Store Indirect and Post-Increment (Y)
Y
Rr,
Y + 1 None 1(1)
ST -Y, Rr Store Indirect and Pre-Decrement Y
(Y)
Y - 1,
Rr None 2(1)
STD Y+q, Rr Store Indirect with Displacement (Y + q) Rr None 2(1)
ST Z, Rr Store Indirect (Z) Rr None 1(1)
ST Z+, Rr Store Indirect and Post-Increment (Z)
Z
Rr
Z + 1 None 1(1)
ST -Z, Rr Store Indirect and Pre-Decrement ZZ - 1 None 2(1)
STD Z+q,Rr Store Indirect with Displacement (Z + q) Rr None 2(1)
LPM Load Program Memory R0 (Z) None 3
LPM Rd, Z Load Program Memory Rd (Z) None 3
LPM Rd, Z+ Load Program Memory and Post-Increment Rd
Z
(Z),
Z + 1 None 3
ELPM Extended Load Program Memory R0 (RAMPZ:Z) None 3
ELPM Rd, Z Extended Load Program Memory Rd (RAMPZ:Z) None 3
ELPM Rd, Z+ Extended Load Program Memory and Post-
Increment
Rd
Z
(RAMPZ:Z),
Z + 1 None 3
SPM Store Program Memory (RAMPZ:Z) R1:R0 None -
Mnemonics Operands Description Operation Flags #Clocks
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SPM Z+ Store Program Memory and Post-Increment by 2 (RAMPZ:Z)
Z
R1:R0,
Z + 2 None -
IN Rd, A In From I/O Location Rd I/O(A) None 1
OUT A, Rr Out To I/O Location I/O(A) Rr None 1
PUSH Rr Push Register on Stack STACK Rr None 1(1)
POP Rd Pop Register from Stack Rd STACK None 2(1)
XCH Z, Rd Exchange RAM location
Tem p
Rd
(Z)
Rd,
(Z),
Tem p
None 2
LAS Z, Rd Load and Set RAM location
Tem p
Rd
(Z)
Rd,
(Z),
Temp v (Z)
None 2
LAC Z, Rd Load and Clear RAM location
Tem p
Rd
(Z)
Rd,
(Z),
($FFh – Rd) (Z)
None 2
LAT Z, Rd Load and Toggle RAM location
Tem p
Rd
(Z)
Rd,
(Z),
Tem p (Z)
None 2
Bit and bit-test instructions
LSL Rd Logical Shift Left
Rd(n+1)
Rd(0)
C
Rd(n),
0,
Rd(7)
Z,C,N,V,H 1
LSR Rd Logical Shift Right
Rd(n)
Rd(7)
C
Rd(n+1),
0,
Rd(0)
Z,C,N,V 1
ROL Rd Rotate Left Through Carry
Rd(0)
Rd(n+1)
C
C,
Rd(n),
Rd(7)
Z,C,N,V,H 1
ROR Rd Rotate Right Through Carry
Rd(7)
Rd(n)
C
C,
Rd(n+1),
Rd(0)
Z,C,N,V 1
ASR Rd Arithmetic Shift Right Rd(n) Rd(n+1), n=0..6 Z,C,N,V 1
SWAP Rd Swap Nibbles Rd(3..0) Rd(7..4) None 1
BSET sFlag Set SREG(s) 1SREG(s) 1
BCLR sFlag Clear SREG(s) 0SREG(s) 1
SBI A, b Set Bit in I/O Register I/O(A, b) 1None 1
CBI A, b Clear Bit in I/O Register I/O(A, b) 0None 1
BST Rr, b Bit Store from Register to T TRr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b) TNone 1
SEC Set Carry C1 C 1
CLC Clear Carry C0 C 1
SEN Set Negative Flag N1 N 1
CLN Clear Negative Flag N0 N 1
SEZ Set Zero Flag Z1 Z 1
CLZ Clear Zero Flag Z0 Z 1
SEI Global Interrupt Enable I1 I 1
Mnemonics Operands Description Operation Flags #Clocks
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Notes: 1. Cycle times for data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface.
2. One extra cycle must be added when accessing internal SRAM.
CLI Global Interrupt Disable I0 I 1
SES Set Signed Test Flag S1 S 1
CLS Clear Signed Test Flag S0 S 1
SEV Set Two’s Complement Overflow V1 V 1
CLV Clear Two’s Complement Overflow V0 V 1
SET Set T in SREG T1 T 1
CLT Clear T in SREG T0 T 1
SEH Set Half Carry Flag in SREG H1 H 1
CLH Clear Half Carry Flag in SREG H0 H 1
MCU control instructions
BREAK Break (See specific descr. for BREAK) None 1
NOP No Operation None 1
SLEEP Sleep (see specific descr. for Sleep) None 1
WDR Watchdog Reset (see specific descr. for WDR) None 1
Mnemonics Operands Description Operation Flags #Clocks
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34. Packaging Information
34.1 64A
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO. REV.
64A, 64-lead, 14 x 14mm Body Size, 1.0mm Body Thickness,
0.8mm Lead Pitch, Thin Prole Plastic Quad Flat Package (TQFP) C
64A
2010-10-20
PIN 1 IDENTIFIER
0°~7°
PIN 1
L
C
A1 A2 A
D1
D
e
E1 E
B
COMMON DIMENSIONS
(Unit of measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes:
1.This package conforms to JEDEC reference MS-026, Variation AEB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 15.75 16.00 16.25
D1 13.90 14.00 14.10 Note 2
E 15.75 16.00 16.25
E1 13.90 14.00 14.10 Note 2
B 0.30 – 0.45
C 0.09 – 0.20
L 0.45 – 0.75
e 0.80 TYP
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34.2 64Z3
65
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35. Electrical Characteristics
All typical values are measured at T = 25C unless other temperature condition is given. All minimum and maximum
values are valid across operating temperature and voltage unless other conditions are given.
35.1 Absolute Maximum Ratings
Stresses beyond those listed in Table 35-1 under may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or other conditions beyond those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 35-1. Absolute Maximum Ratings
35.2 General Operating Ratings
The device must operate within the ratings listed in Table 35-2 in order for all other electrical characteristics and typical
characteristics of the device to be valid.
Table 35-2. General Operating Conditions
Table 35-3. Operating Voltage and Frequency
Symbol Parameter Condition Min. Typ. Max. Units
VCC Power supply voltage -0.3 4 V
IVCC Current into a VCC pin 200
mA
IGND Current out of a Gnd pin 200
VPIN
Pin voltage with respect to Gnd
and VCC
-0.5 VCC+0.5 V
IPIN I/O pin sink/source current -25 25 mA
TAStorage temperature -65 150
°C
TjJunction temperature 150
Symbol Parameter Condition Min. Typ. Max. Units
VCC Power supply voltage 1.60 3.6
V
AVCC Analog supply voltage 1.60 3.6
TATemperature range -40 85
°C
TjJunction temperature -40 105
Symbol Parameter Condition Min. Typ. Max. Units
ClkCPU CPU clock frequency
VCC = 1.6V 012
MHz
VCC = 1.8V 012
VCC = 2.7V 032
VCC = 3.6V 032
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The maximum CPU clock frequency depends on VCC. As shown in Figure 35-1 the Frequency vs. VCC curve is linear
between 1.8V < VCC <2.7V.
Figure 35-1. Maximum Frequency vs. VCC
1.8
12
32
MHz
V
2.7 3.6
1.6
Safe Operating Area
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35.3 Current Consumption
Table 35-4. Current Consumption for Active Mode and Sleep Modes
Notes: 1. All Power Reduction Registers set.
2. Maximum limits are based on characterization, and not tested in production.
Symbol Parameter Condition Min. Typ. Max. Units
ICC
Active power
consumption(1)
32kHz, Ext. Clk
VCC = 1.8V 150
µA
VCC = 3.0V 320
1MHz, Ext. Clk
VCC = 1.8V 410
VCC = 3.0V 830
2MHz, Ext. Clk
VCC = 1.8V 660 800
VCC = 3.0V
1.3 1.8
mA
32MHz, Ext. Clk 10 15
Idle power
consumption(1)
32kHz, Ext. Clk
VCC = 1.8V 4
µA
VCC = 3.0V 5
1MHz, Ext. Clk
VCC = 1.8V 50
VCC = 3.0V 100
2MHz, Ext. Clk
VCC = 1.8V 100 350
VCC = 3.0V
200 600
32MHz, Ext. Clk 3.3 7mA
Power-down power
consumption
T=25°C
VCC = 3.0V
0.2 1.0
µA
T=85°C 3.5 6.0
T = 105°C 16 27
WDT and sampled BOD enabled,
T=25°C
VCC = 3.0V
1.5 2.0
WDT and sampled BOD enabled,
T = 85°C 610
WDT and sampled BOD enabled,
T = 105°C 15 27
Power-save power
consumption(2)
RTC from ULP clock, WDT and
sampled BOD enabled, T = 25°C
VCC = 1.8V 1.4
VCC = 3.0V 1.5
RTC from 1.024kHz low power
32.768kHz TOSC, T = 25°C
VCC = 1.8V 0.7 2
VCC = 3.0V 0.8 2
RTC from low power 32.768kHz
TOSC, T = 25°C
VCC = 1.8V 0.9 3
VCC = 3.0V 1.1 3
Reset power consumption Current through RESET pin
substracted VCC = 3.0V 300
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Table 35-5. Current Consumption for Modules and Peripherals
Note: 1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz external clock
without prescaling, T = 25°C unless other conditions are given.
Symbol Parameter Condition(1) Min. Typ. Max. Units
ICC
ULP oscillator 0.93
µA
32.768kHz int. oscillator 27
2MHz int. oscillator
85
DFLL enabled with 32.768kHz int. osc. as reference 115
32MHz int. oscillator
240
DFLL enabled with 32.768kHz int. osc. as reference 430
PLL 20x multiplication factor,
32MHz int. osc. DIV4 as reference 300
Watchdog timer 1
BOD
Continuous mode 140
Sampled mode, includes ULP oscillator 1.3
Internal 1.0V reference 220
Temperature sensor 215
ADC
16ksps
VREF = Ext ref
1.12
mA
CURRLIMIT = LOW 1.01
CURRLIMIT = MEDIUM 0.9
CURRLIMIT = HIGH 0.8
75ksps
VREF = Ext ref CURRLIMIT = LOW 1.7
300ksps
VREF = Ext ref 3.1
DMA 615KBps between I/O registers and SRAM 115
µA
USART Rx and Tx enabled, 9600 BAUD 9.5
Flash memory and EEPROM programming 4mA
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35.4 Wake-up Time from Sleep Modes
Note: 1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 35-2. All peripherals and modules start
execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.
Figure 35-2. Wake-up Time Definition
Table 35-6. Device Wake-up Time from Sleep Modes with Various System Clock Sources
Symbol Parameter Condition Min. Typ. (1) Max. Units
twakeup
Wake-up time from idle,
standby, and extended standby
mode
External 2MHz clock 2.0
µs
32.768kHz internal oscillator 130
2MHz internal oscillator 2.0
32MHz internal oscillator 0.2
Wake-up time from power-save
and power-down mode
External 2MHz clock 4.5
32.768kHz internal oscillator 320
2MHz internal oscillator 9.0
32MHz internal oscillator 5.0
Wakeup request
Clock output
Wakeup time
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35.5 I/O Pin Characteristics
The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output
voltage limits reflect or exceed this specification.
Notes: 1. The sum of all IOH for PORTA and PORTB must not exceed 100mA.
The sum of all IOH for PORTC, PORTD, PORTE must for each port not exceed 200mA.
The sum of all IOH for pins PF[0-5] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR and PDI must not exceed 100mA.
2. The sum of all IOL for PORTA and PORTB must not exceed 100mA.
The sum of all IOL for PORTC, PORTD, PORTE must for each port not exceed 200mA.
The sum of all IOL for pins PF[0-5] on PORTF must not exceed 200mA.
The sum of all IOL for pins PF[6-7] on PORTF, PORTR and PDI must not exceed 100mA.
Table 35-7. I/O Pin Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
IOH (1)/
IOL (2) I/O pin source/sink current -15 15 mA
VIH High level input voltage
VCC = 2.4 - 3.6V 0.7*Vcc VCC+0.5
V
VCC = 1.6 - 2.4V 0.8*VCC VCC+0.5
VIL Low level input voltage
VCC = 2.4- 3.6V -0.5 0.3*VCC
VCC = 1.6 - 2.4V -0.5 0.2*VCC
VOH High level output voltage
VCC = 3.3V IOH = -4mA 2.6 2.9
VCC = 3.0V IOH = -3mA 2.1 2.6
VCC = 1.8V IOH = -1mA 1.4 1.6
VOL Low level output voltage
VCC = 3.3V IOL = 8mA 0.4 0.76
VCC = 3.0V IOL = 5mA 0.3 0.64
VCC = 1.8V IOL = 3mA 0.2 0.46
IIN Input leakage current I/O pin T = 25°C <0.01 1µA
RPPull/buss keeper resistor 25 k
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35.6 ADC Characteristics
Table 35-8. Power Supply, Reference, and Inpu t Range
Symbol Parameter Condition Min. Typ. Max. Units
AVCC Analog supply voltage VCC-0.3 VCC+0.3
V
VREF Reference voltage 1AVCC-0.6
Rin Input resistance Switched 4.5 k
Cin Input capacitance Switched 5pF
RAREF Reference input resistance (leakage only) >10 M
CAREF Reference input capacitance Static load 7pF
Vin Input range 0 VREF
VConversion range Differential mode, Vinp - Vinn -VREF VREF
Conversion range Single ended unsigned mode, Vinp -V VREF-V
VFixed offset voltage 200 lsb
Table 35-9. Clock and Timing
Symbol Parameter Condition Min. Typ. Max. Units
ClkADC ADC clock frequency
Maximum is 1/4 of peripheral clock
frequency 100 1800
kHz
Measuring internal signals 100 125
fClkADC Sample rate 16 300
ksps
fADC Sample rate
Current limitation (CURRLIMIT) off 16 300
CURRLIMIT = LOW 16 250
CURRLIMIT = MEDIUM 16 150
CURRLIMIT = HIGH 16 50
Sampling time Configurable in steps of 1/2 ClkADC cycles
up to 32 ClkADC cycles 0.28 320 µs
Conversion time (latency) (RES+1)/2 + GAIN
RES (Resolution) = 8 or 12, GAIN=0 to 3 5.5 10
ClkADC
cyclesStart-up time ADC clock cycles 12 24
ADC settling time After changing reference or input mode 7 7
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Notes: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used.
Table 35-10. Accuracy Characteristics
Symbol Parameter Condition(2) Min. Typ. Max. Units
RES Resolution 12-bit resolution
Differential 812 12
BitsSingle ended signed 711 11
Single ended unsigned 812 12
INL(1) Integral non-linearity
Differential mode
16ksps, VREF = 3V 0.5 1
lsb
16ksps, all VREF 0.8 2
300ksps, VREF = 3V 0.6 1
300ksps, all VREF 1 2
Single ended
unsigned mode
16ksps, VREF = 3.0V 0.5 1
16ksps, all VREF 1.3 2
DNL(1) Differential non-linearity
Differential mode
16ksps, VREF = 3V 0.3 1
16ksps, all VREF 0.5 1
300ksps, VREF = 3V 0.35 1
300ksps, all VREF 0.5 1
Single ended
unsigned mode
16ksps, VREF = 3.0V 0.6 1
16ksps, all VREF 0.6 1
Offset error Differential mode
300ksps, VREF=3V -7 mV
Temperature drift, VREF=3V 0.01 mV/K
Operating voltage drift 0.16 mV/V
Gain error Differential mode
External reference -5
mV
AVCC/1.6 -5
AVCC/2.0 -6
Bandgap ±10
Temperature drift 0.02 mV/K
Operating voltage drift 2mV/V
Gain error Single ended
unsigned mode
External reference -8
mV
AVCC/1.6 -8
AVCC/2.0 -8
Bandgap ±10
Temperature drift 0.03 mV/K
Operating voltage drift 2mV/V
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35.7 Analog Comparator Characteristics
Table 35-11. Gain Stage Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
Rin Input resistance Switched in normal mode 4.0 k
Csample Input capacitance Switched in normal mode 4.4 pF
Signal range Gain stage output 0AVCC- 0.6 V
Propagation delay ADC conversion rate 1/2 1 3 ClkADC
cycles
Clock rate Same as ADC 100 1800 kHz
Gain error
0.5x gain, normal mode -1
%
1x gain, normal mode -1
8x gain, normal mode -1
64x gain, normal mode 5
Offset error,
input referred
0.5x gain, normal mode 10
mV
1x gain, normal mode 5
8x gain, normal mode -20
64x gain, normal mode -126
Table 35-12. Analog Comparator Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
Voff Input offset voltage 10 mV
Ilk Input leakage current <10 50 nA
Input voltage range -0.1 AVCC V
AC startup time 50 µs
Vhys1 Hysteresis, none Vcc=1.6V - 3.6V 0
mVVhys2 Hysteresis, small Vcc=1.6V - 3.6V 15
Vhys3 Hysteresis, large Vcc=1.6V - 3.6V 30
tdelay Propagation delay
VCC = 3.0V, T= 85°C 20 90
ns
VCC = 3.0V, T= 85°C 17
64-level voltage scaler Integral non-linearity (INL) 0.3 0.5 lsb
Current source accuracy after
calibration 5 %
current source calibration
range 4 6 µA
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35.8 Bandgap and Internal 1.0V Reference Characteristics
35.9 Brownout Detection Characteristics
.
Note: 1. BOD is calibrated at 85°C within BOD level 0 values, and BOD level 0 is the default level.
35.10 External Reset Characteristics
Table 35-13. Bandgap an d Internal 1.0V Reference Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
Startup time
As reference for ADC 1 ClkPER + 2.5µs
µs
As input voltage to ADC and AC 1.5
Bandgap voltage 1.1
V
INT1V Internal 1.00V reference T= 85°C, after calibration 0.99 11.01
Variation over voltage and temperature Calibrated at T= 85°C 2 %
Table 35-14. Brownout Detection Characteristics(1)
Symbol Parameter Condition Min. Typ. Max. Units
VBOT
BOD level 0 falling VCC 1.60 1.62 1.72
V
BOD level 1 falling VCC 1.8
BOD level 2 falling VCC 2.0
BOD level 3 falling VCC 2.2
BOD level 4 falling VCC 2.4
BOD level 5 falling VCC 2.6
BOD level 6 falling VCC 2.8
BOD level 7 falling VCC 3.0
tBOD Detection time
Continuous mode 0.4
µs
Sampled mode 1000
VHYST Hysteresis 1.0 %
Table 35-15. External Reset Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
tEXT Minimum reset pulse width 1000 90 ns
VRST Reset threshold voltage
VCC = 2.7 - 3.6V 0.45*VCC V
VCC = 1.6 - 2.7V 0.45*VCC
RRST Reset pin pull-up resistor 25 k
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35.11 Power-on Reset Characteristics
Note: 1. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+.
35.12 Flash and EEPROM Memory Characteristics
Notes: 1. Programming is timed from the 2MHz internal oscillator.
2. EEPROM is not erased if the EESAVE fuse is programmed.
Table 35-16. Power-on Reset Characteris tics
Symbol Parameter Condition Min. Typ. Max. Units
VPOT- (1) POR threshold voltage falling VCC
VCC falls faster than 1V/ms 0.4 1.0
VVCC falls at 1V/ms or slower 0.8 1.3
VPOT+ POR threshold voltage rising VCC 1.3 1.59
Table 35-17. Endurance and Data Rete ntion
Symbol Parameter Condition Min. Typ. Max. Units
Flash
Write/Erase cycles
25°C 10K
Cycle85°C 10K
105°C 2K
Data retention
25°C 100
Year85°C 25
105°C 10
EEPROM
Write/Erase cycles
25°C 100K
Cycle85°C 100K
105°C 30K
Data retention
25°C 100
Year85°C 25
105°C 10
Table 35-18. Programming Time
Symbol Parameter Condition Min. Typ.(1) Max. Units
Chip erase(2) 384KB Flash, EEPROM 130
ms
Flash
Page erase 4
Page write 4
Atomic page erase and write 8
EEPROM
Page erase 4
Page write 4
Atomic page erase and write 8
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35.13 Clock and Oscillator Characteristics
35.13.1 Calibrated 32.768kHz Internal Oscillator Characteristics
35.13.2 Calibrated 2MHz RC Internal Oscillator Characteristics
35.13.3 Calibrated and Tunable 32MHz Internal Oscillator Characteristics
35.13.4 32kHz Internal ULP Oscillator Characteris tics
Table 35-19. 32.768kHz Internal Oscillator Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
Frequency 32.768 kHz
Factory calibration accuracy T = 85C, VCC = 3.0V -0.5 0.5
%
User calibration accuracy -0.5 0.5
Table 35-20. 2MHz In ternal Oscillator Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
Frequency range DFLL can tune to this frequency over
voltage and temperature 1.8 2.2
MHz
Factory calibrated frequency 2.0
Factory calibration accuracy T = 85C, VCC= 3.0V -1.5 1.5
%User calibration accuracy -0.2 0.2
DFLL calibration stepsize 0.23
Table 35-21. 32MHz Internal Oscillator Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
Frequency range DFLL can tune to this frequency over
voltage and temperature 30 32 35
MHz
Factory calibrated frequency 32
Factory calibration accuracy T = 85C, VCC= 3.0V -1.5 1.5
%User calibration accuracy -0.2 0.2
DFLL calibration step size 0.24
Table 35-22. 32kHz Internal ULP Oscillator Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
Factory calibrated frequency 32 kHz
Factory calibration accuracy T = 85C, VCC= 3.0V -12 12
%
Accuracy -30 30
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35.13.5 Internal Phase Loc ked Loop (PLL) Characteristics
Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
35.13.6 External Clock Characteristics
Figure 35-3. External Clock Drive Waveform
Notes: 1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
2. The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
Table 35-23. Internal PLL Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
fIN Input frequency Output frequency must be within fOUT 0.4 64
MHz
fOUT Output frequency (1) VCC= 1.6 - 1.8V 20 48
VCC= 2.7 - 3.6V 20 128
Start-up time 25
µs
Re-lock time 25
tCH
tCL
tCK
tCH
VIL1
VIH1
tCR tCF
Table 35-24. E xternal Clock(1)
Symbol Parameter Condition Min. Typ. Max. Units
1/tCK Clock frequency(2) VCC = 1.6 - 1.8V 090
MHz
VCC = 2.7 - 3.6V 0142
tCK Clock period
VCC = 1.6 - 1.8V 11
ns
VCC = 2.7 - 3.6V 7.0
tCH/CL Clock high/low time
VCC = 1.6 - 1.8V 4.5
VCC = 2.7 - 3.6V 2.4
VIL/IH Low/high level input voltage See Table on page 70 V
tCK
Reduction in period time from one
clock cycle to the next 10 %
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35.13.7 External 16MHz Crystal Oscillator and XOSC Characteristics
Table 35-25. External 16MHz Crystal Oscillator and XOSC Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
Cycle to cycle jitter
XOSCPWR=0
FRQRANGE=0 0
ns
FRQRANGE=1, 2, or 3 0
XOSCPWR=1 0
Long term jitter
XOSCPWR=0
FRQRANGE=0 0
FRQRANGE=1, 2, or 3 0
XOSCPWR=1 0
Frequency error
XOSCPWR=0
FRQRANGE=0 0.03
%
FRQRANGE=1 0.03
FRQRANGE=2 or 3 0.03
XOSCPWR=1 0.003
Duty cycle
XOSCPWR=0
FRQRANGE=0 50
FRQRANGE=1 50
FRQRANGE=2 or 3 50
XOSCPWR=1 50
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RQNegative impedance
XOSCPWR=0,
FRQRANGE=0
0.4MHz resonator,
CL=100pF 44k
1MHz crystal, CL=20pF 67k
2MHz crystal, CL=20pF 67k
XOSCPWR=0,
FRQRANGE=1,
CL=20pF
2MHz crystal 82k
8MHz crystal 1500
9MHz crystal 1500
XOSCPWR=0,
FRQRANGE=2,
CL=20pF
8MHz crystal 2700
9MHz crystal 2700
12MHz crystal 1000
XOSCPWR=0,
FRQRANGE=3,
CL=20pF
9MHz crystal 3600
12MHz crystal 1300
16MHz crystal 590
XOSCPWR=1,
FRQRANGE=0,
CL=20pF
9MHz crystal 390
12MHz crystal 50
16MHz crystal 10
XOSCPWR=1,
FRQRANGE=1,
CL=20pF
9MHz crystal 1500
12MHz crystal 650
16MHz crystal 270
XOSCPWR=1,
FRQRANGE=2,
CL=20pF
12MHz crystal 1000
16MHz crystal 440
XOSCPWR=1,
FRQRANGE=3,
CL=20pF
12MHz crystal 1300
16MHz crystal 590
ESR SF=Safety factor min(RQ)/SF
Start-up time
XOSCPWR=0,
FRQRANGE=0
0.4MHz resonator,
CL=100pF 1.0
ms
XOSCPWR=0,
FRQRANGE=1 2MHz crystal, CL=20pF 2.6
XOSCPWR=0,
FRQRANGE=2 8MHz crystal, CL=20pF 0.8
XOSCPWR=0,
FRQRANGE=3
12MHz crystal,
CL=20pF 1.0
XOSCPWR=1,
FRQRANGE=3
16MHz crystal,
CL=20pF 1.4
Table 35-25. External 16MHz Crystal Oscillator and XOSC Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
80
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
35.13.8 External 32.768kHz Crystal Oscillator and TOSC Characterist ics
Note: 1. See Figure 35-4 for definition.
Figure 35-4. TOSC Input Capacitance
The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating without
external capacitors.
CXTAL1
Parasitic capacitance
XTAL1 pin 5.9
pFCXTAL2
Parasitic capacitance
XTAL2 pin 8.3
CLOAD
Parasitic capacitance
load 3.5
Table 35-25. External 16MHz Crystal Oscillator and XOSC Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
Table 35-26. External 32.768kHz Crystal Oscillator and TOSC Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
ESR/R1 Recommended crystal equivalent
series resistance (ESR)
Crystal load capacitance 6.5pF 60
k
Crystal load capacitance 9.0pF 35
Crystal load capacitance 12pF 28
CTOSC1 Parasitic capacitance TOSC1 pin 3.5
pF
CTOSC2 Parasitic capacitance TOSC2 pin 3.5
Recommended safety factor capacitance load matched to
crystal specification 3
C
L1
C
L2
2CS
O
T
1
CS
O
TDevice internal
External
32.768 kHz crystal
81
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
35.14 SPI Characteristics
Figure 35-5. SPI Timing Requirements in Master Mode
Figure 35-6. SPI Timin g Requirem ents in Slave Mode
MSB LSB
BSLBSM
t
MOS
t
MIS
t
MIH
t
SCKW
t
SCK
t
MOH
t
MOH
t
SCKF
t
SCKR
t
SCKW
MOSI
(Data Output)
MISO
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
MSB LSB
BSLBSM
t
SIS
t
SIH
t
SSCKW
t
SSCKW
t
SSCK
t
SSH
t
SOSSH
t
SCKR
t
SCKF
t
SOS
t
SSS
t
SOSSS
MISO
(Data Output)
MOSI
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
82
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
Table 35-27. SPI Timing Characteristics and Requirements
Symbol Parameter Condition Min. Typ. Max. Units
tSCK SCK period Master (See Table 20-3 in
XMEGA C Manual)
ns
tSCKW SCK high/low width Master 0.5*SCK
tSCKR SCK rise time Master 2.7
tSCKF SCK fall time Master 2.7
tMIS MISO setup to SCK Master 10
tMIH MISO hold after SCK Master 10
tMOS MOSI setup SCK Master 0.5*SCK
tMOH MOSI hold after SCK Master 1
tSSCK Slave SCK Period Slave 4*t ClkPER
tSSCKW SCK high/low width Slave 2*t ClkPER
tSSCKR SCK rise time Slave 1600
tSSCKF SCK fall time Slave 1600
tSIS MOSI setup to SCK Slave 3
tSIH MOSI hold after SCK Slave tClk
PER
tSSS SS setup to SCK Slave 21
tSSH SS hold after SCK Slave 20
tSOS MISO setup SCK Slave 8
tSOH MISO hold after SCK Slave 13
tSOSS MISO setup after SS low Slave 11
tSOSH MISO hold after SS high Slave 8
83
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
35.15 Two-Wire Interface Characteristics
Table 35-28 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR XMEGA
Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 35-
7.
Figure 35-7. Two -wire Interface Bus Timing
t
HD;STA
t
of
SDA
SCL
t
LOW
t
HIGH
t
SU;STA
t
BUF
t
r
t
HD;DAT
t
SU;DAT
t
SU;STO
Table 35-28. Two -wire Interface Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
VIH Input high voltage 0.7VCC VCC+0.5
V
VIL Input low voltage 0.5 0.3VCC
Vhys Hysteresis of Schmitt trigger inputs 0.05VCC (1)
VOL Output low voltage 3mA, sink current 00.4
trRise time for both SDA and SCL 20+0.1Cb (1)(2) 300
nstof Output fall time from VIHmin to VILmax 10pF < Cb < 400pF (2) 20+0.1Cb (1)(2) 250
tSP Spikes suppressed by input filter 050
IIInput current for each I/O Pin 0.1VCC < VI < 0.9VCC -10 10 µA
CICapacitance for each I/O Pin 10 pF
fSCL SCL clock frequency fPER (3)>max(10fSCL, 250kHz) 0400 kHz
RPValue of pull-up resistor
fSCL 100kHz
fSCL > 100kHz
tHD;STA Hold time (repeated) START condition
fSCL 100kHz 4.0
µs
fSCL > 100kHz 0.6
tLOW Low period of SCL clock
fSCL 100kHz 4.7
fSCL > 100kHz 1.3
tHIGH High period of SCL clock
fSCL 100kHz 4.0
fSCL > 100kHz 0.6
tSU;STA
Set-up time for a repeated START
condition
fSCL 100kHz 4.7
fSCL > 100kHz 0.6
VCC 0.4V–
3mA
----------------------------
100ns
Cb
---------------
300ns
Cb
---------------
84
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
Notes: 1. Required only for fSCL > 100kHz.
2. Cb = Capacitance of one bus line in pF.
3. fPER = Peripheral clock frequency.
tHD;DAT Data hold time
fSCL 100kHz 03.45
µs
fSCL > 100kHz 00.9
tSU;DAT Data setup time
fSCL 100kHz 250
ns
fSCL > 100kHz 100
tSU;STO Setup time for STOP condition
fSCL 100kHz 4.0
µs
fSCL > 100kHz 0.6
tBUF
Bus free time between a STOP and
START condition
fSCL 100kHz 4.7
fSCL > 100kHz 1.3
Table 35-28. Two -wire Interface Characteristics (Continued)
Symbol Parameter Condition Min. Typ. Max. Units
85
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
36. Typical Characteristics
36.1 Current Consumption
36.1.1 Active Mode Supply Current
Figure 36-1. Active Supply Current vs. Frequency
fSYS = 0 - 1MHz external clock, T = 25°C
Figure 36-2. Active Supply Current vs. Frequency
fSYS = 1 - 32MHz external clock, T = 25°C
3.6V
3.3V
3.0V
2.7V
2.2V
1.8V
200
300
400
500
600
700
800
900
1000
1100
1200
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency [MHz]
I
CC
[µA]
3.6V
3.3V
3.0V
2.7V
0
2
4
6
8
10
12
14
0 2 4 6 8 101214161820222426283032
Frequency[MHz]
I
CC
[mA]
2.2V
1.8V
86
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
Figure 36-3. Active Mode Supply Current vs. VCC
fSYS = 32.768kHz internal oscillator
Figure 36-4. Active Mode Supply Current vs. VCC
fSYS = 1MHz external clock
105 °C
85 °C
25 °C
-40°C
0
50
100
150
200
250
300
350
400
450
500
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
I
CC
[µA]
VCC [V]
105 °C
85 °C
25 °C
-40 °C
200
320
440
560
680
800
920
1040
1160
1280
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
87
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
Figure 36-5. Active Mode Supply Current vs. VCC
fSYS = 2MHz internal oscillator
Figure 36-6. Active Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator prescaled to 8MHz
105 °C
85 °C
25 °C
-40 °C
380
580
780
980
1180
1380
1580
1780
1980
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
-40 °C
1.0
2.0
3.0
4.0
5.0
6.0
7.0
1.61.82.02.22.42.62.83.03.23.43.6
Icc [mA]
VCC [V]
88
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
Figure 36-7. Active Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator
36.1.2 Idle Mode Supply Current
Figure 36-8. Idle Mode Supply Curr ent vs. Frequency
fSYS = 0 - 1MHz external clock, T = 25°C
105 °C
85 °C
25 °C
-40 °C
8.0
9.0
10.0
11.0
12.0
13.0
14.0
15.0
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
Icc [mA]
VCC [V]
3.6V
3.3V
3.0V
2.7V
2.2V
1.8V
0
20
40
60
80
100
120
140
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency [MHz]
I
CC
[µA]
89
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
Figure 36-9. Idle Mode Supply Curr ent vs. Frequency
fSYS = 1 - 32MHz external clock, T = 25°C
Figure 36-10.Idle Mode Supply Current vs. VCC
fSYS = 32.768kHz internal oscillator
3.6V
3.3V
3.0V
2.7V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0 2 4 6 8 101214161820222426283032
Frequency [MHz]
I
CC
[mA]
2.2V
1.8V
105 °C
85 °
C
25 °
C
-40
°
C
28
30
32
34
36
38
40
42
44
46
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
90
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
Figure 36-1 1.Idle Mode Supply Current vs. VCC
fSYS = 1MHz external clock
Figure 36-12.Idle Mode Supply Current vs. VCC
fSYS = 2MHz internal oscillator
105 °C
85 °C
25 °C
-40 °C
90
120
150
180
210
240
270
300
330
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
-40 °C
190
240
290
340
390
440
490
540
590
640
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
91
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
Figure 36-13.Idle Mode Supply Current vs. VCC
fSYS = 32MHz internal oscillator prescaled to 8MHz
Figure 36-14.Idle Mode Current vs. VCC
fSYS = 32MHz internal oscillator
105 °C
85 °C
25 °C
-40 °C
500
700
900
1100
1300
1500
1700
1900
1.61.82.02.22.42.62.83.03.23.43.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
-
40
°C
3000
3300
3600
3900
4200
4500
4800
5100
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
Icc [µA]
VCC [V]
92
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
36.1.3 Power-down Mode Supply Current
Figure 36-15.Power-down Mode Supply Current vs. VCC
All functions disabled
Figure 36-16.Power-down Mode Supply Current vs. VCC
Watchdog and sampled BOD enabled
105 °C
85 °C
25 °C
-40 °C
0
2
4
6
8
10
12
14
16
18
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
105 °C
85 °C
25 °C
-40 °C
0
2
4
6
8
10
12
14
16
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Icc [µA]
VCC [V]
93
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
Figure 36-17.Power-down Mode Supply Current vs. Temperature
Watchdog and sampled BOD enabled and running from internal ULP oscillator
36.2 I/O Pin Characteristics
36.2.1 Pull-up
Figure 36-18.I/ O Pin Pul l-up Resistor Current vs. Input Voltage
VCC = 1.8V
3.0 V
2.7 V
2.2 V
1.8 V
0
2
4
6
8
10
12
14
-45-35-25-15-5 5 152535455565758595105
Icc [µA]
Temperature [°C]
105 °C
85 °C
25 °C
-40 °C
0
10
20
30
40
50
60
70
80
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
I
PIN
[µA]
VPIN [V]
94
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
Figure 36-19.I/ O Pin Pul l-up Resistor Current vs. Input Voltage
VCC = 3.0V
Figure 36-20.I/ O Pin Pul l-up Resistor Current vs. Input Voltage
VCC = 3.3V
105 °C
85 °C
25 °C
-40 °C
0
20
40
60
80
100
120
140
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
I
PIN
[µA]
VPIN [V]
105
°
°C
85 °C
25 °°C
-40 °C
0
20
40
60
80
100
120
140
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
I
PIN
[µA]
VPIN [V]
95
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
36.2.2 Output Voltage vs. Sink/Source Current
Figure 36-21.I/O Pin Output Voltage vs. Source Current
VCC = 1.8V
Figure 36-22.I/O Pin Output Voltage vs. Source Current
VCC = 3.0V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
VPIN [V]
IPIN [mA]
-40 °C
25 °C
85 °C
105 °C
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
-16 -14 -12 -10 -8 -6 -4 -2 0
VPIN [V]
IPIN [mA]
85 °C
105 °C25 °C
-40 °C
96
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
Figure 36-23.I/O Pin Output Voltage vs. Source Current
VCC = 3.3V
Figure 36-24.I/O Pin Output Voltage vs. Sink Curren t
VCC = 1.8V
85 °C
105 °C
25 °C
-40 °C
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
-16 -14 -12 -10 -8 -6 -4 -2 0
VPIN [V]
IPIN [mA]
85 °C
25 °C
-40 °C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0123456789
VPIN [V]
IPIN [mA]
105 °C
97
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
Figure 36-25.I/O Pin Output Voltage vs. Sink Current
VCC = 3.0V
Figure 36-26.I/O Pin Output Voltage vs. Sink Current
VCC = 3.3V
105 °C
85 °C
25 °C
-40 °C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 2 4 6 8 10121416
VPIN [V]
IPIN [mA]
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0 2 4 6 8 101214161820
VPIN [V]
IPIN [mA]
105 °C
85 °C
-40 °C
25 °C
98
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
36.2.3 Thresholds and Hysteresis
Figure 36-27.I/O Pin Input Threshold Voltage vs. VCC
VIH I/O pin read as “1”
Figure 36-28.I/O Pin Input Threshold Voltage vs. VCC
VIL I/O pin read as “0”
105 °C
85 °C
25 °C
-40 °C
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Vthreshold [V]
VCC [V]
105 °C
85 °C
25 °C
-40 °C
0.50
0.65
0.80
0.95
1.10
1.25
1.40
1.55
1.70
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Vthreshold [V]
VCC [V]
99
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
Figure 36-29.I/O Pin Input Hysteresis vs. V CC
36.3 ADC Characteristics
Figure 36-30.INL Error vs. External VREF
T = 25
C, VCC = 3.6V, external reference
105 °C
85 °C
25 °C
-40 °C
0.16
0.19
0.22
0.25
0.28
0.31
0.34
0.37
0.40
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Vthreshold [V]
VCC [V]
Differential mode
Single-ended signed mode
Single-ended unsigned mode
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
VREF [V]
INL[LSB]
100
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
Figure 36-31.INL Error vs. Sample Rate
T = 25
C, VCC = 3.6V, VREF = 3.0V external
Figure 36-32.INL Error vs. Input Code
Differential mode
Single-ended signed mode
Single-ended unsigned mode
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
ADC sample rate [ksps]
INL[LSB]
50 100 150 200 250 300
-1.25
-1.00
-0.75
-0.50
-0.25
0.00
0.25
0.50
0.75
1.00
1.25
0 512 1024 1536 2048 2560 3072 3584 4096
ADC input code
INL[LSB]
101
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
Figure 36-33.DNL Error vs. External VREF
T = 25
C, VCC = 3.6V, external reference
Figure 36-34.DNL Error vs. Sample Rate
T = 25
C, VCC = 3.6V, VREF = 3.0V external
Differential mode
Single-ended signed mode
Single-ended unsigned mode
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
V
REF
[V]
DNL [LSB]
Differential mode
Single-ended signed mode
Single-ended unsigned mode
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
50 100 150 200 250 300
ADC sample rate [ksps]
DNL [LSB]
102
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
Figure 36-35.DNL Error vs. Input Code
Figure 36-36.Gain Error vs. VREF
T = 25
C, VCC = 3.6V, ADC sample rate = 300ksps
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0 512 1024 1536 2048 2560 3072 3584 4096
ADC input code
DNL [LSB]
Differential mode
Single-ended signed mode
Single-ended unsigned mode
-15
-14
-13
-12
-11
-10
-9
-8
-7
-6
-5
1.01.21.41.61.82.02.22.42.62.83.0
V
REF
[V]
Gain error [mV]
103
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
Figure 36-37.Gain Error vs. VCC
T = 25
C, VREF = external 1.0V, ADC sample rate = 300ksps
Figure 36-38.Offset Error vs. VREF
T = 25
C, VCC = 3.6V, ADC sample rate = 300ksps
Differential mode
Single-ended signed
mode
Single-ended unsigned mode
-9
-8
-7
-6
-5
-4
-3
-2
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VCC [V]
Gain error [mV]
Differential mode
7.0
7.2
7.4
7.6
7.8
8.0
8.2
8.4
8.6
8.8
9.0
9.2
9.4
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
V
REF
[V]
Offset error [mV]
104
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
Figure 36-39.Gain Error vs. Temperature
VCC = 3.0V, VREF = external 2.0V
Figure 36-40.Offset Error vs. VCC
T = 25
C, VREF = external 1.0V, ADC sample rate = 300ksps
Differential mode
Single-ended signed mode
Single-ended unsigned
mode
-14
-12
-10
-8
-6
-4
-2
0
-45-35-25-15-5 5 152535455565758595105
Gain error [mV]
Temperature [°C]
Differential mode
0.00
1.00
2.00
3.00
4.00
5.00
6.00
7.00
8.00
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
CC
[V]
Offset error [mV]
105
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
36.4 Analog Comparator Characteristics
Figure 36-41.Analog Comparator Hysteresis vs. VCC
Small hysteresis
Figure 36-42.Analog Comparator Hysteresis vs. VCC
Large hysteresis
-40°C
25°C
85°C
105°C
10
11
12
13
14
15
16
17
18
19
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
HYST
[mV]
V
CC
[V]
-40°C
25°C
85°C
105
°
C
18
20
22
24
26
28
30
32
34
36
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
V
HYST
[mV]
V
CC
[V]
106
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
Figure 36-43.Analog Comparator Current Source vs. Calibration Value
VCC = 3.0V
Figure 36-44.Voltage Scaler INL vs. SCALEFAC
T = 25
C, VCC = 3.0V
2
3
4
5
6
7
8
0123456789101112131415
CALIBA[3..0]
I [µA]
3.6V
3.0V
2.4V
2.0V
1.6V
25°C
0.2
0.23
0.26
0.29
0.32
0.35
0.38
0.41
0.44
0 5 10 15 20 25 30 35 40 45 50 55 60 65
SCALEFAC
INL [LSB]
107
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
36.5 Internal 1.0V Reference Characteristics
Figure 36-45.ADC Internal 1.0V Reference vs. Temperature
36.6 BOD Characteristics
Figure 36-46.BOD Thresholds vs. Temperature
BOD level = 1.6V
3.6 V
2.7 V
1.6 V
0.997
0.998
0.999
1.000
1.001
1.002
1.003
1.004
1.005
1.006
1.007
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Bandgap Voltage [V]
T [°C]
1.59
1.60
1.61
1.62
1.63
1.64
1.65
1.66
1.67
1.68
-45-35-25-15-5 5 152535455565758595105
VBOT [V]
Temperature [°C]
108
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
Figure 36-47.BOD Thresholds vs. Temperature
BOD level = 3.0V
36.7 External Reset Characteristics
Figure 36-48.Minimum Reset Pin Pulse Width vs. VCC
3.00
3.02
3.04
3.06
3.08
3.10
3.12
3.14
3.16
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
VBOT [V]
Temperature [°C]
105 °C
85 °C
25 °C
-40 °C
80
88
96
104
112
120
128
136
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
tRST [ns]
VCC [V]
109
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
Figure 36-49.Rese t Pin Pul l-u p Res istor Current vs. Reset Pin Voltage
VCC = 1.8V
Figure 36-50.Rese t Pin Pul l-u p Res istor Current vs. Reset Pin Voltage
VCC = 3.0V
-40 °C
25 °C
85 °C
105°C
0
10
20
30
40
50
60
70
80
0.00.20.40.60.81.01.21.41.61.8
IRESET [µA]
VRESET [V]
-40 °C
25 °C
85 °C
105°C
0
20
40
60
80
100
120
140
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
IRESET [µA]
VRESET [V]
110
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
Figure 36-51.Rese t Pin Pul l-u p Res istor Current vs. Reset Pin Voltage
VCC = 3.3V
Figure 36-52.Re se t Pin In put Threshold Voltage vs. VCC
VIH - Reset pin read as “1”
0
18
36
54
72
90
108
126
144
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
IRESET [µA]
VRESET [V]
-40 °C
25 °C
85 °C
105°C
105 °C
85 °C
25 °C
-40 °C
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VTHRESHOLD [V]
VCC [V]
111
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
36.8 Oscillator Characteristics
36.8.1 Ultra Low-Pow er Internal Oscillator
Figure 36-53. Ultra Low-Power Internal Oscillator Frequency vs. Temperatur e
36.8.2 32.768kHz Internal Oscillator
Figure 36-54. 32.768kHz Internal Oscillator Frequency vs. Temperature
3.6 V
3.3 V
3.0 V
2.7 V
2.0 V
1.8 V
1.6 V
30.5
31.0
31.5
32.0
32.5
33.0
33.5
34.0
34.5
35.0
35.5
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Frequency [kHz]
Temperature [°C]
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
32.50
32.55
32.60
32.65
32.70
32.75
32.80
32.85
32.90
-45-35-25-15-5 5 152535455565758595105
Frequency [kHz]
Temperature [°C]
112
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
Figure 36-55. 32.768kHz Internal Oscillator Frequency vs. Calibration Value
VCC = 3.0V, T = 25°C
36.8.3 2MHz Internal Oscillator
Figure 36-56. 2MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
3.0 V
23
26
29
32
35
38
41
44
47
50
53
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
RC32KCAL[7..0]
Frequency [kHz]
3.3V
3.0V
2.7V
2.2V
1.8V
1.96
1.98
2.00
2.02
2.04
2.06
2.08
2.10
2.12
2.14
2.16
2.18
2.20
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Frequency [MHz]
Temperature [°C]
113
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
Figure 36-57. 2MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
Figure 36-58. 2MHz Internal Oscillator Frequency vs. CALA Calibration Value
VCC = 3V
1.8V
2.2V
1.986
1.988
1.990
1.992
1.994
1.996
1.998
2.000
2.002
2.004
2.006
2.008
2.010
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Frequency [MHz]
Temp erature [°C]
2.7V
3.3V
3.0V
105 °C
85 °C
25
°
C
-40
°
C
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128
Frequency [MHz]
CALA
114
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
36.8.4 32MHz Internal Oscillator
Figure 36-59. 32MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
Figure 36-60. 32MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
1.8V
2.7V
3.3V
3.0V
31.0
31.5
32.0
32.5
33.0
33.5
34.0
34.5
35.0
35.5
36.0
36.5
-45-35-25-15-5 5 152535455565758595105
Freq uency [MHz]
Temp erature [°C]
2.2V
1.8V
2.7V
3.3V
3.0V
2.2V
31.75
31.80
31.85
31.90
31.95
32.00
32.05
32.10
32.15
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Frequency [MHz]
Temp erature [°C]
115
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
Figure 36-61. 32MHz Internal Oscillator CALA Calibration Step Size
VCC = 3.0V
Figure 36-62. 32MHz Internal Oscillator Frequency vs. CALB Calibration Value
VCC = 3.0V
25°C
105°C
85°C
-40°C
0.15
0.17
0.19
0.21
0.23
0.25
0.27
0.29
0.31
0.33
0.35
0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128
Step size [%]
CALA
105 °C
85 °C
25 °C
-40 °C
20
26
32
38
44
50
56
62
68
74
80
0 7 14 21 28 35 42 49 56 63
Frequency [MHz]
DFLLRC2MCALB
116
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
36.8.5 32MHz Internal Oscillator Calibrated to 48 MHz
Figure 36-63. 48MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
Figure 36-64. 48MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from the 32.768kHz internal oscillator
1.8V
2.7V
3.3V
3.0V
2.2V
46
47
48
49
50
51
52
53
54
55
-45-35-25-15-5 5 152535455565758595105
Frequench [MHz]
Temperature [°C]
1.8V 2.7V
3.3V
3.0V
2.2V
47.6
47.7
47.8
47.9
48.0
48.1
48.2
48.3
-45-35-25-15-5 5 152535455565758595105
Frequency [MHz]
Temperature [°C]
117
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
36.9 Two-Wire Interface Characteristics
Figure 36-65. SDA Hold Time vs. Temperature
Figure 36-66. SDA Hold Time vs. Supply Voltage
3
2
1
0
50
100
150
200
250
300
350
400
450
500
-45-35-25-15-5 5 1525354555657585
Temperature [°C]
Hold time [ns]
3
2
1
0
50
100
150
200
250
300
350
400
450
500
V
CC
[V]
Hold time [ns]
2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
118
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
36.10 PDI Characteristics
Figure 36-67. Maximum PDI Frequency vs. V CC
85°C
25°C
-40°C
11
16
21
26
31
36
V
CC
[V]
f
MAX
[MHz]
2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
119
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
37. Errata
37.1 ATxmega384C3
37.1.1 Rev. B
Temperature sensor not calibrated
1. Temperature sensor not calibrated
Temperature sensor factory calibration not implemented.
Problem fix/Workaround
None.
120
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
38. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The referring revision in this
section are referring to the document revision.
38.1 8361G – 06/2015
38.2 8361F – 11/2014
38.3 8361E – 07/2014
38.4 8361D – 07/2013
38.5 8361C – 04/2012
38.6 8361B – 03/2012
1. Updated “Packaging Information” on page 63. Replaced the “64Z3” on page 64 drawing by a correct drawing.
1. Updated according to the template
1. Updated “Ordering Information” on page 2. Ordering codes added for ATxmega384C3 @ 105C
2. Updated Table 35-4 on page 67. Added Icc Power-down power consumption for T=105C for all functions disabled
and for WDT and sampled BOD enabled.
3. Updated Table on page 75. Updated the table to include values for T=85C and T=105C. Removed T=55C.
4. TWI electrical characteristics: Units of Data setup time (tSU;DAT) changed from μs to ns in Table 35-28 on page 83.
5. “Typical Characteristics” on page 85: Added 105°C characteristics.
6. Added info on ESR parameter for 16 MHz crystal oscillator and XOSC characteristics in Table on page 78.
7. Changed Vcc to AVCC in Section 28. “ADC – 12-bit Analog to Digital Converter” on page 46 and Section 29. “AC –
Analog Comparator” on page 48.
1. Errata Temperature sensor not calibrated added to “Rev. B” on page 119
1. Updated four plots in typical characteristics: Figures 36-1 and Figure 36-2 on page 85; Figures 36-8 and Figure 36-3
on page 86.
1. Editing update.
2. Atmel new datasheet template used.
121
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
38.7 8361A – 02/2012
1. Initial revision.
122
XMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet–06/2015
iXMEGA C3 [DATASHEET]
Atmel-8361G-AVR-ATxmega384C3-Datasheet_06/2015
Table of Contents
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Pinout/Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4. Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1 Recommended Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5. Capacitive Touch Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6. AVR CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.3 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.4 ALU - Arithmetic Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.5 Program Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.6 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.7 Stack and Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.8 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7. Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.3 Flash Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.4 Fuses and Lock Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.5 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.6 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.7 I/O Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.8 Data Memory and Bus Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.9 Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.10 Device ID and Revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.11 I/O Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.12 Flash and EEPROM Page Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8. DMAC – Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9. Event System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10. System Clock and Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10.3 Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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11. Power Management and Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11.3 Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12. System Control and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
12.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
12.3 Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
12.4 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
13. WDT – Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
13.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
14. Interrupts and Programmable Multilevel Interrupt Controller . . . . . . . . . . . . . . . . 26
14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
14.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
14.3 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
15. I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
15.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
15.3 Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
15.4 Input Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
15.5 Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
16. TC0/1 – 16-bit Timer/Counter Type 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
16.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
17. TC2 – Timer/Counter Type 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
17.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
18. AWeX – Advanced Waveform Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
18.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
19. Hi-Res – High Resolution Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
19.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
20. RTC – 16-bit Real-Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
20.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
21. USB – Universal Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
21.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
21.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
22. TWI – Two-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
22.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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22.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
23. SPI – Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
23.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
23.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
24. USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
24.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
24.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
25. IRCOM – IR Communication Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
25.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
25.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
26. AES Crypto Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
26.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
26.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
27. CRC – Cyclic Redundancy Check Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
27.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
27.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
28. ADC – 12-bit Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
28.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
28.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
29. AC – Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
29.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
29.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
30. Programming and Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
30.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
30.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
31. Pinout and Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
31.1 Alternate Pin Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
31.2 Alternate Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
32. Peripheral Module Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
33. Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
34. Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
34.1 64A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
34.2 64Z3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
35. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
35.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
35.2 General Operating Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
35.3 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
35.4 Wake-up Time from Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
35.5 I/O Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
35.6 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
35.7 Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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35.8 Bandgap and Internal 1.0V Reference Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
35.9 Brownout Detection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
35.10 External Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
35.11 Power-on Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
35.12 Flash and EEPROM Memory Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
35.13 Clock and Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
35.14 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
35.15 Two-Wire Interface Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
36. Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
36.1 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
36.2 I/O Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
36.3 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
36.4 Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
36.5 Internal 1.0V Reference Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
36.6 BOD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
36.7 External Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
36.8 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
36.9 Two-Wire Interface Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
36.10 PDI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
37. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
37.1 ATxmega384C3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
38. Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
38.1 8361G – 06/2015 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
38.2 8361F – 11/2014. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
38.3 8361E – 07/2014. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
38.4 8361D – 07/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
38.5 8361C – 04/2012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
38.6 8361B – 03/2012. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
38.7 8361A – 02/2012. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
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