Serializer
Deserializer
DS15BA101 DS15EA101
CML
LVPECL
LVDS
150 Mbps
to
1.5 Gbps
100-ohm Differential Cable
(i.e. CAT5e/6/7, Twinax)
50-ohm Coaxial Cable
(i.e. Belden 9914)
Max Cable Loss ~ 35 dB @ 750 MHz
DS15EA101
www.ti.com
SNLS235H –SEPTEMBER 2006–REVISED APRIL 2013
DS15EA101 0.15 to 1.5 Gbps Adaptive Cable Equalizer with LOS Detection
Check for Samples: DS15EA101
1FEATURES DESCRIPTION
The DS15EA101 is an adaptive equalizer optimized
2• Automatic Equalization of Coaxial, Twin-Ax for equalizing data transmitted over copper cables.
and Twisted Pair Cables The DS15EA101 operates over a wide range of data
• High Data Rates: 150 Mbps to 1.5+ Gbps rates from 150 Mbps to 1.5+ Gbps and automatically
• Up to 35 dB of Boost at 750 MHz adapts to equalize any cable length from zero meters
to lengths that attenuate the signal by 35 dB at 750
• LOS Detection and Output Enable MHz.
• Single-Ended or Differential Input The DS15EA101 allows either single-ended or
• 50ΩDifferential Outputs differential input drive. This enables equalization of
• Low Power Operation, 210 mW (typ) at 1.5 coaxial cables as well as differential twin-ax and
Gbps twisted pair cables.
• Industrial -40°C to +85°C Temperature Additional features include an LOS output and an
• Space-Saving 4 x 4 mm WQFN-16 Package output enable which, when tied together, disable the
output when no signal is present.
APPLICATIONS The DS15EA101 is powered from a single 3.3V
• Cable Extention Applications supply and consumes 210 mW at 1.5 Gbps. It
operates over the full −40°C to +85°C industrial
• Security Cameras temperature range and is available in a space saving
• Remote LCDs and LED Panels 4 x 4 mm WQFN-16 package which allows for high
• Data Recovery Equalization density placement of components in multi-channel
applications.
Typical Application
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2006–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DS15EA101
SNLS235H –SEPTEMBER 2006–REVISED APRIL 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)
Supply Voltage −0.5V to 3.6V
Input Voltage (all inputs) −0.3V to VCC+0.3V
Storage Temperature Range −65°C to +150°C
Junction Temperature +150°C
Lead Temperature
(Soldering 4 Sec) +260°C
Package Thermal Resistance
θJA RGH0016A +42.1°C/W
θJC RGH0016A +8.2°C/W
ESD Rating (HBM) 8 kV
ESD Rating (MM) 250V
(1) "Absolute Maximum Ratings" are those parameter values beyond which the life and operation of the device cannot be ensured. The
stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values.
The table of Electrical Characteristics specifies acceptable device operating conditions.
Recommended Operating Conditions
Supply Voltage (VCC ) 3.3V ±5%
Input Coupling Capacitance 1.0 µF
Loop Capacitor (Connected between
CAP+ and CAP-) 1.0 µF
Operating Free Air Temperature (TA) -40°C to +85°C
DC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (1) (2).
Symbol Parameter Conditions Reference Min Typ Max Units
VCM Input Common Mode Voltage IN+, IN- 1.9 V
VIN Input Voltage (3)(4)950 mVP-P
VCC –
VOS Output Common Mode Voltage V
VOUT/2
OUT+, OUT-
VOUT Output Voltage Swing 50Ωload, differential 750 mVP-P
VLOS LOS Output Voltage Valid signal not present LOS 2.6 V
Valid signal present 0.4 V
VIN(EN) EN Input Voltage Min to disable outputs EN 3.0 V
Max to enable outputs 0.8 V
ICC Supply Current (5) 63 77 mA
(1) Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated
referenced to 0 volts.
(2) Typical values are stated for VCC = +3.3V and TA= +25°C.
(3) Specification is ensured by characterization.
(4) The maximum input voltage amplitude assumes a DC-balanced signal.
(5) Supply current depends on the amount of cable being equalized. The current is highest for short cable and decreases as the cable
length is increased.
2Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS15EA101
GND
IN+
IN-
GND
GND
OUT+
OUT-
GND
1
2
3
4
12
10
9
11
(GND)
DAP
CAP+
CAP-
GND
GND
5
6
7
8
VCC
LOS
EN
VCC
16
14
13
15
DS15EA101
www.ti.com
SNLS235H –SEPTEMBER 2006–REVISED APRIL 2013
AC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (1).
Symbol Parameter Conditions Reference Min Typ Max Units
BRIN Input Data Rate IN+, IN- 150 1500 Mbps
tTRJ Total Residual Jitter @ BER-12 1.5 Gbps
(2) 25m CAT5e (Belden 1700A), 0.25 UI
(1)
1.0 Gbps
50m CAT5e (Belden 1700A), 0.25 UI
(1)
0.5 Gbps
100m CAT5e (Belden 1700A), 0.25 UI
(1)
1.5 Gbps
50m CAT7 (Siemon Tera), 0.25 UI
(1)
1.5 Gbps
75m CAT7 (Siemon Tera), 0.30 UI
(1)
1.0 Gbps
100m CAT7 (Siemon Tera), 0.40 UI
(1)
1.5 Gbps
200m Belden 9914, 0.25 UI
(1)
tTLH Transition Time from Low to 20% – 80%, (3) OUT+, OUT- 100 220 ps
High
tTHL Transition Time from High to 20% – 80%, (3) 100 220 ps
Low
ROUT Output Resistance single-ended, (4) 50 Ω
(1) Typical values are stated for VCC = +3.3V and TA= +25°C.
(2) The total residual jitter at BER-12 was calculated as DJ+14.1xRJ, where DJ is deterministic jitter and RJ is random jitter. The jitter is
expressed as a portion of a unit interval (UI). One UI is a reciprocal of a bit rate (or data rate). For example, a 1.5 Gbps (gigabit per
second) signal has 1 / (1.5 Gb/s) = 666.67 ps (picosecond) unit interval. A 0.25 UI jitter is equivalent to 0.25 x 666.67 ps = 166.67 ps.
(3) Specification is ensured by characterization.
(4) Specification is ensured by design.
CONNECTION DIAGRAM
16-Pad WQFN
Package Number RGH0016A
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Product Folder Links: DS15EA101
DS15EA101
SNLS235H –SEPTEMBER 2006–REVISED APRIL 2013
www.ti.com
PIN DESCRIPTIONS
Pin # Name Description
1 GND Ground pin.
2 IN+ Non-inverting input pin.
3 IN- Inverting input pin.
4 GND Ground pin.
5 CAP+ Loop filter positive pin.
6 CAP- Loop filter negative pin.
7 GND Ground pin.
8 GND Ground pin.
9 GND Ground pin.
10 OUT- Inverting output pin.
11 OUT+ Non-inverting output pin.
12 GND Ground pin.
13 VCC Power supply pin.
14 EN Output enable pin.
15 LOS Los of signal circuitry output pin.
16 VCC Power supply pin.
4Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS15EA101
OUT+
OUT-
CML3.3V
IN+
IN-
50:
50:
VCC
DS15EA101 Output
100:
100: Differential T-Line
OUT+
OUT-
LVDS
IN+
IN-
100:
50:50:
VCC
DS15EA101 Output
100: Differential T-Line
DS15EA101
www.ti.com
SNLS235H –SEPTEMBER 2006–REVISED APRIL 2013
DEVICE OPERATION
Input Interfacing
The DS15EA101 accepts either differential or single-ended input. The input must be AC coupled. Transformer
coupling is not supported. If the signal is differential, its amplitude must be 800 mVp-p ±10% (400 mV single-
ended). If the signal is single-ended, its amplitude must be 800 mV ±10%.
Output Interfacing
The DS15EA101 uses current mode outputs. They are internally terminated with 50Ω. The following two figures
illustrate typical DC-coupled interface to common differential receivers and assume that the receivers have high
impedance inputs. While most receivers have an input common mode voltage range that can accomodate CML
signals, it is recommended to check respective receiver's datasheet prior to implementing the suggested
interface implementations.
Figure 1. Typical DS15EA101 Output DC-Coupled Interface to an LVDS Receiver
Figure 2. Typical DS15EA101 Output DC-Coupled Interface to a CML Receiver
Cable Extender Application
The DS15EA101 together with the DS15BA101 form a cable extender chipset optimized for extending serial data
streams from serializer/deserializer (SerDes) pairs and field programmable gate arrays (FPGAs) over 100Ω
differential (i.e. CAT5e/6/7 and twinax) and 50Ωcoaxial cables. Setting correct DS15BA101 output amplitude and
proper cable termination are keys for optimal operation. The following two figures show recommended chipset
configuration for 100Ωdifferential and 50Ωcoaxial cables.
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: DS15EA101
DS15BA101
OUT-
IN+
IN-
OUT+
0.1 PF
50:
50:
487:
100:
1 PF1 PF
1 PFDS15EA101
IN+
IN-
50:
1 PF
OUT+
OUT-
CAP+ CAP-
0.1 PF
VCC
VCC
25:
50: Coaxial Cable
RVO
DS15BA101
OUT-
IN+
IN-
OUT+
0.1 PF
50:
50:
953:
100:
1 PF
1 PF
1 PF
1 PFDS15EA101
IN+
IN-
100:
1 PF
OUT+
OUT-
CAP+ CAP-
0.1 PF
VCC
VCC
100: Differential TP Cable
RVO
DS15EA101
SNLS235H –SEPTEMBER 2006–REVISED APRIL 2013
www.ti.com
Figure 3. Cable Extender Chipset Connection Diagram for 100ΩDifferential Cables
Figure 4. Cable Extender Chipset Connection Diagram for 50ΩCoaxial Cables
Reference Design
There is a complete reference design (P/N: DriveCable02EVK) available for evaluation of the cable extender
chipset (DS15BA101 and DS15EA101).
For more information visit http://www.ti.com/tool/drivecable02evk
6Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS15EA101
600
500
400
300
200
100
00 0.4 0.8 1.2 1.6 2.0
VCC = 3.3V
100m CAT5e
NRZ PRBS-7
RESIDUAL JITTER @ BERT-12 (ps)
DATA RATE (Gbps)
25 °C
-40 °C
85 °C
0.25 UI
0.5 UI
600
500
400
300
200
100
00 0.4 0.8 1.2 1.6 2.0
VCC = 3.3V
75m CAT5e
NRZ PRBS-7
RESIDUAL JITTER @ BERT-12 (ps)
DATA RATE (Gbps)
25 °C
-40 °C
85 °C
0.25 UI
0.5 UI
3.0
2.5
2.0
1.5
1.0
0.5
00 60 120 180 240 300
VCC= 3.3V
TA=25 °C
MAXIMUM DATA RATE (Gbps)
BELDEN 9914 LENGTH (M)
0.5 UI TJ@BERT-12
0.25 UI TJ@BERT-12
NRZ PRBS-7
600
500
400
300
200
100
00 0.4 0.8 1.2 1.6 2.0
VCC = 3.3V
50m CAT5e
NRZ PRBS-7
RESIDUAL JITTER @ BERT-12 (ps)
DATA RATE (Gbps)
25 °C
-40 °C
85 °C
0.25 UI
0.5 UI
3.0
2.5
2.0
1.5
1.0
0.5
00 20 40 60 80 100
VCC= 3.3V
TA=25°C
NRZ PRBS-7
MAXIMUM DATA RATE (Gbps)
CAT7 LENGTH (m)
0.5 UI TJ@BERT-12
0.25 UI TJ@BERT-12
3.0
2.5
2.0
1.5
1.0
0.5
00 25 50 75 100 125
VCC = 3.3V
TA = 25 °C
NRZ PRBS-7
MAXIMUM DATA RATE (Gbps)
CAT5E LENGTH (m)
0.5 UI TJ@BERT-12
0.25 UI TJ@BERT-12
DS15EA101
www.ti.com
SNLS235H –SEPTEMBER 2006–REVISED APRIL 2013
Typical Performance
Maximum Data Rate as a Function of CAT7 (Siemon CAT7 Maximum Data Rate as a Function of CAT5e (Belden 1700A)
Tera) Length Length
Figure 5. Figure 6.
Maximum Data Rate as a Function of 50ΩCoaxial (Belden Residual Jitter as a Function of Data Rate and Temperature
9914) Length for the Chipset with 50m CAT5e
Figure 7. Figure 8.
Residual Jitter as a Function of Data Rate and Temperature Residual Jitter as a Function of Data Rate and Temperature
for the Chipset with 75m CAT5e for the Chipset with 100m CAT5e
Figure 9. Figure 10.
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: DS15EA101
DS15EA101
SNLS235H –SEPTEMBER 2006–REVISED APRIL 2013
www.ti.com
Typical Performance (continued)
A 1.5 Gbps NRZ PRBS-7 After 25m CAT5e An Equalized 1.5 Gbps NRZ PRBS-7 After 25m CAT5e
V:100 mV / DIV, H:100 ps / DIV V:100 mV / DIV, H:100 ps / DIV
Figure 11. Figure 12.
A 1.0 Gbps NRZ PRBS-7 After 50m CAT5e An Equalized 1.0 Gbps NRZ PRBS-7 After 50m CAT5e
V:100 mV / DIV, H:150 ps / DIV V:100 mV / DIV, H:150 ps / DIV
Figure 13. Figure 14.
A 0.5 Gbps NRZ PRBS-7 After 100m CAT5e An Equalized 0.5 Gbps NRZ PRBS-7 After 100m CAT5e
V:100 mV / DIV, H:400 ps / DIV V:100 mV / DIV, H:400 ps / DIV
Figure 15. Figure 16.
8Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS15EA101
DS15EA101
www.ti.com
SNLS235H –SEPTEMBER 2006–REVISED APRIL 2013
Typical Performance (continued)
A 1.5 Gbps NRZ PRBS-7 After 50m CAT7 An Equalized 1.5 Gbps NRZ PRBS-7 After 50m CAT7
V:100 mV / DIV, H:100 ps / DIV V:100 mV / DIV, H:100 ps / DIV
Figure 17. Figure 18.
An Equalized 1.5 Gbps NRZ PRBS-7 After 75m CAT7 A 1.5 Gbps NRZ PRBS-7 After 75m CAT7
V:100 mV / DIV, H:100 ps / DIV V:100 mV / DIV, H:100 ps / DIV
Figure 19. Figure 20.
A 1.0 Gbps NRZ PRBS-7 After 100m CAT7 An Equalized 1.0 Gbps NRZ PRBS-7 After 100m CAT7
V:100 mV / DIV, H:150 ps / DIV V:100 mV / DIV, H:150 ps / DIV
Figure 21. Figure 22.
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: DS15EA101
DS15EA101
SNLS235H –SEPTEMBER 2006–REVISED APRIL 2013
www.ti.com
Typical Performance (continued)
A 1.5 Gbps NRZ PRBS-7 After 200m Belden 9914 An Equalized 1.5 Gbps NRZ PRBS-7 After 200m Belden
V:100 mV / DIV, H:100 ps / DIV 9914, V:100 mV / DIV, H:100 ps / DIV
Figure 23. Figure 24.
10 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS15EA101
DS15EA101
www.ti.com
SNLS235H –SEPTEMBER 2006–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision G (April 2013) to Revision H Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 10
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: DS15EA101
PACKAGE OPTION ADDENDUM
www.ti.com 23-Aug-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DS15EA101SQ/NOPB ACTIVE WQFN RGH 16 1000 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 15EA101
DS15EA101SQE/NOPB ACTIVE WQFN RGH 16 250 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 15EA101
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 23-Aug-2017
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DS15EA101SQ/NOPB WQFN RGH 16 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
DS15EA101SQE/NOPB WQFN RGH 16 250 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Aug-2017
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS15EA101SQ/NOPB WQFN RGH 16 1000 210.0 185.0 35.0
DS15EA101SQE/NOPB WQFN RGH 16 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Aug-2017
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
SEE TERMINAL
DETAIL
16X 0.3
0.2
2.6 0.1
16X 0.5
0.3
0.8 MAX
(A) TYP
0.05
0.00
12X 0.5
4X
1.5
B4.1
3.9 A
4.1
3.9 0.3
0.2
0.5
0.3
WQFN - 0.8 mm max heightRGH0016A
PLASTIC QUAD FLATPACK - NO LEAD
4214978/B 01/2017
DIM A
OPT 1 OPT 1
(0.1) (0.2)
PIN 1 INDEX AREA
0.08
SEATING PLANE
1
49
12
58
16 13
(OPTIONAL)
PIN 1 ID
0.1 C A B
0.05
EXPOSED
THERMAL PAD
17 SYMM
SYMM
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
SCALE 3.000
DETAIL
OPTIONAL TERMINAL
TYPICAL
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
16X (0.25)
16X (0.6)
( 0.2) TYP
VIA
12X (0.5)
(3.8)
(3.8)
(1)
( 2.6)
(R0.05)
TYP
(1)
WQFN - 0.8 mm max heightRGH0016A
PLASTIC QUAD FLATPACK - NO LEAD
4214978/B 01/2017
SYMM
1
4
58
9
12
13
16
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
17
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
16X (0.6)
16X (0.25)
12X (0.5)
(3.8)
(3.8)
4X ( 1.15)
(0.675)
TYP
(0.675) TYP
(R0.05)
TYP
WQFN - 0.8 mm max heightRGH0016A
PLASTIC QUAD FLATPACK - NO LEAD
4214978/B 01/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SYMM
TYP
EXPOSED METAL
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
SYMM
1
4
58
9
12
13
16
17
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