April 1999
FDC6321C
Dual N & P Channel , Digital FET
General Description Features
Absolute Maximum Ratings TA = 25oC unless other wise noted
Symbol Parameter N-Channel P-Channel Units
VDSS, VCC Drain-Source Voltage, Power Supply Voltage 25 -25 V
VGSS, VIN Gate-Source Voltage, 8-8 V
ID, IODrain/Output Current - Continuous 0.68 -0.46 A
- Pulsed 2-1.5
PDMaximum Power Dissipation (Note 1a)
(Note 1b)0.9 W
0.7
TJ,TSTG Operating and Storage Tempature Ranger-55 to 150 °C
ESD Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm) 6kV
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a)140 °C/W
RθJC Thermal Resistance, Junction-to-Case (Note 1) 60 °C/W
FDC6321C.RevB
N-Ch 25 V, 0.68 A, RDS(ON) = 0.45 @ VGS= 4.5 V
P-Ch -25 V, -0.46 A, RDS(ON) = 1.1 @ VGS= -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3 V circuits. VGS(th) < 1.0V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Replace multiple dual NPN & PNP digital transistors.
These dual N & P Channel logic level enhancement mode
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. This device has been designed
especially for low voltage applications as a replacement for
digital transistors in load switching applications. Since bias
resistors are not required this dual digital FET can replace
several digital transistors with different bias resistors.
SOT-23 SuperSOTTM-8 SOIC-16
SO-8 SOT-223
SuperSOTTM-6
Mark:.321
1
5
3
2
6
4
D1
S2
G1
D2
S1
G2
SuperSOT -6
TM
© 1999 Fairchild Semiconductor Corporation
Electrical Characteristics (TA = 25 OC unless otherwise noted )
Symbol Parameter Conditions Type Min Typ Max Units
OFF CHARACTERISTICS
BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA N-Ch 25 V
VGS = 0 V, ID = -250 µA P-Ch -25
BVDSS/TJBreakdown Voltage Temp. Coefficient ID= 250 µA, Referenced to 25 oCN-Ch 26 mV /oC
ID = -250 µA, Referenced to 25 oCP-Ch -22
IDSS Zero Gate Voltage Drain Current VDS= 20 V, VGS= 0 V, N-Ch 1µA
TJ = 55°C 10
IDSS Zero Gate Voltage Drain Current VDS =-20 V, VGS = 0 V,P-Ch -1 µA
TJ = 55°C -10
IGSS Gate - Body Leakage Current VGS = 8 V, VDS= 0 V N-Ch 100 nA
VGS = -8 V, VDS= 0 V P-Ch -100 nA
ON CHARACTERISTICS (Note 2)
VGS(th)/TJGate Threshold Voltage Temp. Coefficient ID = 250 µA, Referenced to 25 o CN-Ch -2.6 mV / oC
ID= -250 µA, Referenced to 25 o CP-Ch 2.1
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µAN-Ch 0.65 0.8 1.5 V
VDS = VGS, ID= -250 µAP-Ch -0.65 -0.86 -1.5
RDS(ON) Static Drain-Source On-Resistance VGS = 4.5 V, ID = 0.5 AN-Ch 0.33 0.45
TJ =125°C 0.51 0.72
VGS = 2.7 V, ID = 0.25A 0.44 0.6
VGS = -4.5 V, ID = -0.5 A P-Ch 0.87 1.1
TJ =125°C 1.21 1.8
VGS = -2.7 V, ID = -0.25 A1.22 1.5
ID(ON) On-State Drain Current VGS = 4.5 V, VDS = 5 V N-Ch 1A
VGS = -4.5 V, VDS = -5 V P-Ch -1
gFS Forward Transconductance VDS = 5 V, ID= 0.5 AN-Ch 1.45 S
VDS = -5 V, ID= -0.5 A P-Ch 0.8
DYNAMIC CHARACTERISTICS
Ciss Input Capacitance N-Channel N-Ch 50 pF
VDS= 10 V, VGS= 0 V, P-Ch 63
Coss Output Capacitance f = 1.0 MHz N-Ch 28 pF
P-Channel P-Ch 34
Crss Reverse Transfer Capacitance VDS= -10 V, VGS = 0V, N-Ch 9pF
f = 1.0 MHz P-Ch 10
FDC6321C.RevB
Electrical Characteristics (TA = 25 OC unless otherwise noted )
SWITCHING CHARACTERISTICS (Note 2)
Symbol Parameter Conditions Type Min Typ Max Units
tD(on)Turn - On Delay Time N-Channel N-Ch 3 6 nS
VDD = 6 V, ID = 0.5 A, P-Ch 7 20
trTurn - On Rise Time VGs = 4.5 V, RGEN = 50 N-Ch 8 16 nS
P-Ch 9 18
tD(off) Turn - Off Delay Time P-Channel N-Ch 17 30 nS
VDD = -6 V, ID = -0.5 A, P-Ch 55 110
tfTurn - Off Fall Time VGen = -4.5 V, RGEN = 50 N-Ch 13 25 nS
P-Ch 35 70
QgTotal Gate Charge N-Channel N-Ch 1.64 2.3 nC
VDS= 5 V, ID = 0.5 A, P-Ch 1.1 1.5
Qgs Gate-Source Charge VGS = 4.5 V N-Ch 0.38 nC
P- Channel P-Ch 0.32
Qgd Gate-Drain Charge VDS = -5 V, N-Ch 0.45 nC
ID = -0.25 A, VGS = -4.5 V P-Ch 0.25
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
ISMaximum Continuous Drain-Source Diode Forward Current N-Ch 0.3 A
P-Ch -0.5
VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 0.5 A (Note)N-Ch 0.83 1.2 V
TJ =125°C 0.69 0.85
VGS = 0 V, IS = -0.5 A (Note)P-Ch -0.89 -1.2
TJ =125°C -0.75 -0.85
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where thecase thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed
by design while RθCA is determined by the user's board design.
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
FDC6321C.RevB
b. 180OC/W on a 0.005 in2 of pad
of 2oz copper.
a. 140OC/W on a 0.125 in2 pad of
2oz copper.
FDC6321C.RevB
Typical Electrical Characteristics: N-Channel
00.5 11.5 2
0
0.3
0.6
0.9
1.2
1.5
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN-SOURCE CURRENT (A)
3.5
2.7
2.5
2.0
1.5
DS
D
V = 4.5V
GS
3.0
R DS(on), NORMALIZED
00.2 0.4 0.6 0.8 11.2
0.5
1
1.5
2
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
V = 2.0V
GS
2.7 3.0
4.5
D
3.5
2.5
Figure 1. On-Region Characteristics.Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
-50 -25 0 25 50 75 100 125 150
0.6
0.8
1
1.2
1.4
1.6
T , JUNCTION TEMPERATURE (°C)
DRAIN-SOURCE ON-RESISTANCE
J
V = 4.5 V
GS
I =0.5 A
D
R , NORMALIZED
DS(ON)
Figure 3. On-Resistance Variation
with Temperature.
00.5 11.5 22.5
0
0.2
0.4
0.6
0.8
1
V , GATE TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
25°C
125°C
V = 5.0V
DS
GS
D
T = -55°C
J
Figure 5. Transfer Characteristics.
00.2 0.4 0.6 0.8 11.2
0.0001
0.001
0.01
0.1
1
V , BODY DIODE FORWARD VOLTAGE (V)
I , REVERSE DRAIN CURRENT (A)
T = 125°C
J
25°C
-55°C
V = 0V
GS
SD
S
Figure 6. Body Diode Forward Voltage
Variation with Source Current and
Temperature.
Figure 4. On Resistance Variation with
Gate-To-Source Voltage.
11.5 22.5 33.5 44.5 5
0
0.4
0.8
1.2
1.6
2
V , GATE TO SOURCE VOLTAGE (V)
ID= 0.5A
GS
R , ON-RESISTANCE (OHM)
DS(on)
125°C
25°C
FDC6321C.RevB
Typical Electrical Characteristics: N-Channel (continued)
00.4 0.8 1.2 1.6 2
0
1
2
3
4
5
Q , GATE CHARGE (nC)
V , GATE-SOURCE VOLTAGE (V)
g
GS
I = 0.5A
D10V
15V
V = 5V
DS
Figure 10. Single Pulse Maximum Power
Dissipation.
0.1 0.5 1 2 5 10 25
5
10
20
50
100
150
V , DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
DS
C
iss
f = 1 MHz
V = 0V
GS
C
oss
C
rss
Figure 8. Capacitance Characteristics.Figure 7. Gate Charge Characteristics.
Figure 9. Maximum Safe Operating Area.
0.01 0.1 110 100 300
0
1
2
3
4
5
SINGLE PULSE TIME (SEC)
POWER (W)
SINGLE PULSE
R =See note 1b
T = 25°C
θJA A
0.1 0.2 0.5 1 2 5 10 20 40
0.01
0.03
0.1
0.3
1
5
V , DRAI N-SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
V = 4.5V
SINGLE PULSE
R = See note 1b
T = 25°C
GS
θJA
DS
D
DC
1s
10ms
100ms
RDS(ON) LIMIT
A
1ms
100µs
FDC6321C.RevB
Typical Electrical Characteristics: P-Channel
012345
0
0.25
0.5
0.75
1
1.25
1.5
-V , DRAIN-SOURCE VOLTAGE (V)
-I , DRAIN-SOURCE CURRENT (A)
V = -4.5V
GS
DS
D
-2.7
-2.5
-2.0
-3.0
-1.5
-3.5
00.2 0.4 0.6 0.8 1
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
-I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
V = -2.0 V
GS
D
R , NORMALIZED
DS(ON)
-3.5
-4.5
-2.7
-2.5
-3.0
-4.0
Figure 11. On-Region Characteristics.Figure 12. On-Resistance Variation with
Drain Current and Gate Voltage.
-50 -25 0 25 50 75 100 125 150
0.6
0.8
1
1.2
1.4
1.6
T , JUNCTION TEMPERATURE (°C)
DRAIN-SOURCE ON-RESISTANCE (OHMS)
J
R , NORMALIZED
DS(ON)
V = -4.5V
GS
I = -0.5A
D
Figure 13. On-Resistance Variation
with Temperature.
-3-2.5-2-1.5-1-0.5
-1
-0.75
-0.5
-0.25
0
V , GATE TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
V = -5 V
DS
GS
D
T = -55°C
J
125°C
25°C
Figure 15. Transfer Characteristics.
00.2 0.4 0.6 0.8 11.2
0.0001
0.001
0.01
0.1
0.5
-V , BODY DIODE FORWARD VOLTAGE (V)
-I , REVERSE DRAIN CURRENT (A)
T = 125°C
J
25°C
-55°C
V = 0V
GS
SD
S
Figure 16. Body Diode Forward Voltage
Variation with Source Current and
Temperature.
Figure 14. On Resistance Variation with
Gate-To- Source Voltage.
-5-4.5-4-3.5-3-2.5-2-1.5-1
0
1
2
3
4
5
V , GATE TO SOURCE VOLTAGE (V)
ID=-0.5A
GS
R , ON-RESISTANCE (OHM)
DS(on)
125°C
25°C
FDC6321C.RevB
Typical Electrical Characteristics: P-Channel (continued)
Figure 19. Maximum Safe Operating Area.
00.3 0.6 0.9 1.2 1.5 1.8
0
1
2
3
4
5
Q , GATE CHARGE (nC)
-V , GATE-SOURCE VOLTAGE (V)
g
GS
I = -0.5A
D
-15V
V = -5V
DS -10V
Figure 17. Gate Charge Characteristics.
Figure 20. Single Pulse Maximum Power
Dissipation.
0.1 0.3 0.5 1 5 10 15 25
5
10
20
50
100
150
-V , DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
DS
C
iss
f = 1 MHz
V = 0 V
GS
C
oss
C
rss
Figure 18. Capacitance Characteristics.
Figure 21. Transient Thermal Response Curve.
Note: Thermal characterization performed using the conditions described in note 1b.Transient thermal
response will change depending on the circuit board design.
0.0001 0.001 0.01 0.1 1 10 100 300
0.01
0.02
0.05
0.1
0.2
0.5
1
t , TIME (sec)
TRANSIENT THERMAL RESISTANCE
1
Single Pulse
D = 0.5
0.1
0.05
0.02
0.01
0.2
r(t), NORMALIZED EFFECTIVE
Duty Cycle, D = t / t
12
R (t) = r(t) * R
R = See Note 1b
θJA
θJA
θJA
T - T = P * R (t)
θJA
A
J
P(pk)
t
1 t
2
0.01 0.1 110 100 300
0
1
2
3
4
5
SINGLE PULSE TIME (SEC)
POWER (W)
SINGLE PULSE
R =See note 1b
T = 25°C
θJA A
0.1 0.2 0.5 1 2 5 10 20 40
0.01
0.03
0.1
0.3
1
2
- V , DRAIN-SOURCE VOLTAGE (V)
-I , DRAIN CURRENT (A)
RDS(ON) LIMIT
D
A
DC
DS
1s
100ms
10ms
1ms
V = -4.5V
SINGLE PULSE
R = See Note 1b
T = 25°C
θJA
GS
A
1998 Fairchild Semiconductor Corporation
Embossed
Carrier Tape
SSOT-6 Packaging
Configuration: Fi
g
ure 1.0
Component s Leader Tape
500mm minimum or
125 empt
y
pock ets
Trailer Tape
300mm minimum or
75 empt
y
pock ets
SSOT-6 Tape Leader and Trailer
Configuration: Fi
g
ure 2.0
Cover Tape
Carrier Tape
Note/Comments
Packaging Option
SSOT-6 Packaging Information
Standard
(no flow c ode) D87Z
Packaging type
Reel Size
TNR
7" Dia
TNR
13"
Qty per Reel/Tube/Bag 3,000 10,000
Box Dimension (mm) 184x187x47 343x343x64
Max qty per Box 9,000 30,000
Weight per unit (gm) 0.0158 0.0158
Weight per Reel (kg) 0.1440 0.4700
F63TNR
Label
Customize Label
Antistatic Cover Tape
184mm x 187mm x 47mm
Pizza Box for Standard Option
F63TNR
Label
F63TNR Label
F63TNR Label sample
343mm x 342mm x 64mm
Int erm ed ia te box for D87Z Op t i on
F63TNR
Label
SSOT-6 Unit Orienta tion
631
631631
631 631
Pi n 1
LOT: CBVK7 41B019
FSID: FDC633N
D/C1: D9842 QTY1: SPEC REV:
SPEC:
QTY: 3000
D/C2: QTY2: CPN: N/F: F (F63TNR)3
Packaging Description:
SSOT-6 parts are shipped in tape. The carrier tape is
made from a dissipative (carbon filled) polycarbonate
resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film,
adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped with
3,0 00 uni ts p er 7" or 17 7cm di amet er re el. The re els are
dark blue in color and is made of polystyrene plastic (anti-
static coated). Other option comes in 10,000 units per 13"
or 330 cm diam eter re el. Thi s and s ome ot her o ption s are
described in the Packaging Information table.
These full reels are individually barcode labeled and
placed inside a pizz a box (il lustrated in figure 1.0) made of
recyclable corrugated brown paper with a Fairchild logo
printing. One pizza box contains three reels maximum.
And these pizza boxes are placed inside a barcode
labeled shipping box which comes in different sizes
depending o n the n um ber of parts shipped.
SuperSOTTM-6 Tape and Reel Data and Package Dimensions
August 1999, Rev. C
P1
A0 D1
P0
F
W
E1
D0
E2
B0
Tc
Wc
K0
T
Dimensions are in inches and millimeters
Tape Size Reel
Option Dim A Dim B Dim C Dim D Dim N Dim W1 Dim W2 Dim W3 (LSL-USL)
8mm 7" Dia 7.00
177.8 0.059
1.5 512 +0.020/-0. 008
13 +0.5/-0.2 0.795
20.2 2.165
55 0.331 +0.059/-0.000
8.4 +1.5/0 0.567
14.4 0.311 – 0.429
7.9 – 10.9
8m m 13" Dia 13.00
330 0.059
1.5 512 +0.020/-0. 008
13 +0.5/-0.2 0.795
20.2 4.00
100 0.331 +0.059/-0.000
8.4 +1.5/0 0.567
14.4 0.311 – 0.429
7.9 – 10.9
See detail AA
Dim A
max
13" Diameter Option
7" Diameter Option
Dim A
Max
See detail AA
W3
W2 max Measured at Hub
W1 Measured at Hub
Dim N
Dim D
min
Dim C
B Min
DETAIL AA
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C).
20 deg maximum component rotation
0.5mm
maximum
0.5mm
maximum
Sketch C (Top View)
Component lateral movement
Typical
component
cavity
center line
20 deg maximum
Typical
component
center line
B0
A0
Sketch B (Top View)
Component Rotation
Sketch A (Side or Front Sectional View)
Component Rotation
User Direction of Feed
SSOT-6 Embossed Carrier Tape
Configuration: Fi
g
ure 3.0
SSOT-6 Reel Configuration: Fi
g
ure 4.0
Dimensions are in millimeter
Pkg type
A0 B0 W D0 D1 E1 E2 F P1 P0 K0 T Wc Tc
SSOT-6
(8mm)
3.23
+/-0.10 3.18
+/-0.10 8.0
+/-0.3 1.55
+/-0.05 1.125
+/-0.125 1.75
+/-0.10 6.25
min 3.50
+/-0.05 4.0
+/-0.1 4.0
+/-0.1 1.37
+/-0.10 0.255
+/-0.150 5.2
+/-0.3 0.06
+/-0.02
SuperSOTTM-6 Tape and Reel Data and Package Dimensions, continued
July 1999, Rev. C
1998 Fairchild Semiconductor Corporation
SuperSOT -6 (FS PKG Code 31, 33)
SuperSOTTM-6 Tape and Reel Data and Package Dimensions, continued
September 1998, Rev. A
1:1
Scale 1:1 on letter size paper
Dimensions shown below are in:
inches [millimeters]
Part Weight per unit (gram): 0.0158
TRADEMARKS
ACEx™
CoolFET™
CROSSVOLT™
E2CMOSTM
FACT™
FACT Quiet Series™
FAST®
FASTr™
GTO™
HiSeC™
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF FAIRCHILD SEMICONDUCTOR CORPORA TION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT ST A TUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
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OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS P ATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
TinyLogic™
UHC™
VCX™
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MICROWIRE™
POP™
PowerTrench™
QFET™
QS™
Quiet Series™
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