PIC18F1330-I/SO - Microchip Technology

PIC18F1230/1330

1.0 DEVICE OVERVIEW

This docume nt includes the program ming sp ecifications

for the following devices :

2.0 PROGRAMMING OVERVIEW

PIC18F1230/1330 devices can be programmed using

the high-voltage In-Circuit Serial Programming™

(ICSP™) method. This method can be done with the

device in the user’s system. This programming

specification applies to PIC18F1230/1330 devices in

all package types.

2.1 Hardware Requirements

In High-Voltage ICSP mode, PIC18F1230/1330

devices require two programmable power supplies:

one for VDD and one for MCLR/VPP/RA5/FLTA. Both

supplies should have a minimum resolution of 0.25V.

Refer to Section 6.0 “AC/DC Characteristic s T imi ng

Requirements for Program/Verify Test Mode” for

additional hardware parameters.

2.2 Pin Diagrams

The pi n di agra ms fo r th e PIC1 8F1 230 /133 0 fa mily are

shown in Figure 2-1, Figure 2-2 and Figure 2-3.

TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18F1230/1330

• PIC18F1230 • PIC18F1330

• PIC18F1330-ICD

Pin Name During Programming

Pin Name Pin Type Pin Description

MCLR/VPP/RA5/FLTA VPP P Programming Enable

VDD(1) VDD P Power Supply

VSS(1) VSS P Ground

RB6 PGC I Serial Clock

RB7 PGD I/O Serial Data

Legend: I = Input, O = Output, P = Power

Note 1: All power supp ly (VDD) and ground (VSS) pins must be connected.

Flash Microcontroller Pr ogramming Specification

PIC18F1230/1330

FIGURE 2-1: PIC18F1230/1330 FAMILY PIN DIAGRAMS

18-Pin PDIP, SOIC

RA0/AN0/INT0/KBI0/CMP0

RA1/AN1/INT1/KBI1

RA4/T0CKI/AN2/VREF+

VSS/AVSS

RA2/TX/CK

RA3/RX/DT

RB0/PWM0

RB1/PWM1

PIC18F1X30

RB3/INT3/KBI3/CMP1/T1OSI(1)

RB2/INT2/KBI2/CMP2/T1OSO(1)

RA7/OSC1/CLKI/T1OSI(1)/FLTA(2)

RA6/OSC2/CLKO/T1OSO(1)/AN3

VDD/AVDD

RB7/PWM5/PGD

RB6/PWM4/PGC

RB5/PWM3

RB4/PWM2

20-Pin SSOP

RA0/AN0/INT0/KBI0/CMP0

RA1/AN1/INT1/KBI1

RA4/T0CKI/AN2/VREF+

MCLR/VPP/RA5/FLTA(2)

VSS

RA2/TX/CK

RA3/RX/DT

RB0/PWM0

RB1/PWM1

PIC18F1X30

RB3/INT3/KBI3/CMP1/T1OSI(1)

RB2/INT2/KBI2/CMP2/T1OSO(1)

RA7/OSC1/CLKI/T1OSI(1)/FLTA(2)

RA6/OSC2/CLKO/T1OSO(1)/AN3

RB7/PWM5/PGD

RB5/PWM3

RB4/PWM2

AVSS

RB6/PWM4/PGC

Note 1: Placement of T1OSI and T1OSO depends on the value of the Configuration bit, T1OSCMX of CONFIG3H.

2: Placement of FLTA depends on the value of the Configuration bit, FLT AMX of CONFIG3H.

VDD

AVDD

MCLR/VPP/RA5/FLTA(2)

PIC18F1230/1330

FIGURE 2-2: PIC18F1230/1330 FAMILY PIN DIAGRAMS

28-Pin QFN

PIC18F1X30

RA3/RX/DT

VSS

AVSS

RA2/TX/CK 7

RB0/PWM0

RB1/PWM1

NC(2)

RB4/PWM2

RB5/PWM3

NC(2)

RA0/AN0/INT0/KBI0/CMP0

RB3/INT3/KBI3/CMP1/T1OSI(1)

RB2/INT2/KBI2/CMP2/T1OSO(1)

RA1/AN1/INT1/KBI1

RA7/OSC1/CLKI/T1OSI(1)/FLTA(3)

RA6/OSC2/CLKO/T1OSO(1)/AN3

VDD

AVDD

RB7/PWM5/PGD

RB6/PWM4/PGC

Note 1: Placement of T1OSI and T1OSO depends on the value of the Configuration bit, T1OSCMX of CONFIG3H.

2: Pin feature is dependent on device configuration.

3: Placement of FLT A depends on t he value of the Configuration bit, FLTAMX of CONFIG3H.

RA4/T0CKI/AN2/VREF+

MCLR/VPP/RA5/FLTA(3)

PIC18F1230/1330

FIGURE 2-3: PI C18F13 30- ICD DEVICE PIN DIAGRAM

28-Pin QFN

PIC18F1330-ICD

RA3/RX/DT

ICRST(2)/ICVPP(2)

VSS

AVSS

RA2/TX/CK 7

RB0/PWM0

RB1/PWM1

ICCK(2)/ICPGC(2)

RB4/PWM2

RB5/PWM3

ICDT(2)/ICPGD(2)

RA0/AN0/INT0/KBI0/CMP0

RB3/INT3/KBI3/CMP1/T1OSI(1)

RB2/INT2/KBI2/CMP2/T1OSO(1)

RA1/AN1/INT1/KBI1

RA7/OSC1/CLKI/T1OSI(1)/FLTA(3)

RA6/OSC2/CLKO/T1OSO(1)/AN3

VDD

AVDD

RB7/PWM5/PGD

RB6/PWM4/PGC

Note 1: Placement of T1OSI and T1OSO depends on the value of the Configuration bit, T1OSCMX of CONFIG3H.

2: Pin feature is dependent on device configuration.

3: Placement of FLTA depends on the value of the Configuration bit, FLT AMX of CONFIG3H.

RA4/T0CKI/AN2/VREF+

MCLR/VPP/RA5/FLTA(3)

PIC18F1230/1330

2.3 Memory Map s

For the PIC18F1330 device, the code memory

spa c e e xt en ds fro m 00 00 0h to 01 FFF h (8 Kbytes) i n

two 4-Kbyte blocks. For the PIC18F1230 device, the

code memory space extends from 00000h to 00FFFh

(4 Kbytes) in two 2-Kbyte blocks. Addresses 00000h

through 07FFh, however, define a “Boot Block” region

that is treated separately from Block 0. All of these

blocks define code protection boundaries within the

code memory space.

The size of the Boot Block in PIC18F1230/1330

devices can be configured as 256, 512 or 1K words.

This is done through the BBSIZ<1:0> bits in the

Config urat ion reg is ter, C ONF IG 4L (see Table 5-1). It i s

important to note that increasing the size of the Boot

Block decreases the size of Block 0.

TABLE 2-2: IMPLEMENTATION OF CODE

MEMORY

FIGURE 2-4: MEMORY MAP AND CODE MEMORY SPACE FOR THE PIC18F1230 DEVICE

Device Code Memory Size (Bytes)

PIC18F1230 00000h-00FFFh (4K)

PIC18F1330 00000h-01FFFh (8K)

000000h

01FFFFh

3FFFFFh

Note: Sizes of memory areas are not to scale.

* Boot Block size is determined by the BBSIZ<1:0> bits in CONFIG4L.

Code Memory

Unimplemented

Read as ‘0’

Configuration

and ID

Space

MEMORY SIZE/DEVICE

4Kbytes

(PIC18F1230) Address

Range

Boot Block 000000h

0001FFh* or 0003FFh*

Block 0 000200h* or 000400h

0007FFh

Block 1 000800h

000FFFh

Unimplemented

Read ‘0’s

001000h

01FFFFh

200000h

PIC18F1230/1330

FIGURE 2-5: MEMORY MAP AND CODE MEMORY SPACE FOR THE PIC18F1330 DEVICE

000000h

01FFFFh

3FFFFFh

Note: Sizes of memory areas are not to scale.

* Boot Block size is determined by the BBSIZ<1:0> bits in CONFIG4 L.

Code Memory

Unimplemented

Read as ‘0’

Configuration

and ID

Space

MEMORY SIZE/DE VI CE

8Kbytes

(PIC18F1330) Address

Range

Boot Block 000000h

0001FFh* or 0003FFh* or 0007FFh*

Block 0 000200h* or 000400h or 000800h

000FFFh

Block 1 001000h

001FFFh

Unimplemented

Read ‘0’s

01FFFFh

200000h

PIC18F1230/1330

In addition to the code memory space, there are three

blocks in the Configuration and ID space that are

accessible to the user through table reads and table

writes . Their locations in the memory ma p are shown in

Figure 2-6.

Users may store identification information (ID) in eight ID

registers. These ID registers are mapped in addresses,

200000h through 200007h. The ID locations read out

normally, even after code protection is applied.

Locations 300000h through 30000Dh are reserved for

the Configuration bits. These bits select various device

options and are described in Section 5.0 “Configura-

tion Word”. Thes e Configu ration bits read out normally,

even after code protec tion.

Locatio ns 3FFFF Eh and 3FFF FFh ar e reserved for the

Device ID bits. These bits may be used by the program-

mer to identify what device type is being programmed

and are described in Section 5.0 “Configuration

Word”. These Device ID bits read out normally, even

after code protection.

2.3.1 MEMOR Y ADDRESS POINTER

Memory in the address space, 0000000h to 3FFFFFh,

is addressed via the Table Pointer register, which is

comprised of three pointer registers:

• TBLPTRU at RAM address 0FF8h

• TBLPTRH at RAM address 0FF7h

• TBLPTRL at RAM address 0FF6h

The 4-bit command, ‘0000’ (core instruction), is used to

load the Table Pointer prior to u sing many r ead or wr ite

operations.

FIGURE 2-6: CONFIGURATION AND ID LOCATIONS FOR THE PIC 18F12 30/1 330 DEVICE S

TBLPTRU TBLPTRH TBLPTRL

Addr[21:16] Addr[15:8] Addr[7:0]

ID Location 1 200000h

ID Location 2 200001h

ID Location 3 200002h

ID Location 4 200003h

ID Location 5 200004h

ID Location 6 200005h

ID Location 7 200006h

ID Location 8 200007h

CONFIG1L 300000h

CONFIG1H 300001h

CONFIG2L 300002h

CONFIG2H 300003h

CONFIG3L 300004h

CONFIG3H 300005h

CONFIG4L 300006h

CONFIG4H 300007h

CONFIG5L 300008h

CONFIG5H 300009h

CONFIG6L 30000Ah

CONFIG6H 30000Bh

CONFIG7L 30000Ch

CONFIG7H 30000Dh

Device ID 1 3FF FFEh

Device ID 2 3FFFFFh

Note: Sizes of memory areas are not to sca le.

000000h

1FFFFFh

3FFFFFh

01FFFFh Code Memory

Unimplemented

Read as ‘0’

Configuration

and ID

Space

2FFFFFh

PIC18F1230/1330

2.4 High-Level Overview of the

Programming Process

Figure 2-7 shows the high-level overview of the

programming process. First, a Bulk Erase is performed.

Next, the code memory, ID locations and data

EEPROM are programmed (see Section 3.3 “Data

EEPROM Programming”). Thes e mem ori es a re th en

verified to ensure that programming was successful. If

no errors are detected, the Configuration bits are then

programmed and verified.

FIGURE 2-7: HIGH-LEVEL

PROGRAMMING FLOW

2.5 Entering and Exiting High-Voltage

ICSP Program/Verify Mode

As shown in Figure 2-8, the High-Voltage ICSP

Program/Verify mode is entered by holding PGC and

PGD low, and then raising MCLR/VPP/RA5/FLTA to

VIHH (high volt age). Once in thi s mode, the code mem-

ory, data EEPROM (see Section 3.3 “Data EEPROM

Programming”), ID locations and Configuration bits

can be accessed and programmed in serial fashion.

Figure 2-9 shows the exit sequence.

The sequence that enters the device into the Program/

V erify mode places all unused I/Os in the high-impedance

state.

FIGURE 2-8: ENTERING HIGH-VOLTAGE

PROGRAM/VERIFY MODE

FIGURE 2-9: EXITING HIGH-VOLTAGE

PROGRAM/VERIFY MODE

Start

Program Memory

Program IDs

Program Data EE

Verify Program

Verify IDs

Verify Data

Program

Configuration Bits

Verify

Configuration Bits

Done

Perform Bulk

Erase

P12

PGD

PGD = Input

VDD

D110

P13

PGC

MCLR/VPP/

RA5/FLTA

MCLR/VPP/

P16

PGD

PGD = Input

PGC

VDD

D110

P17

RA5/FLTA

PIC18F1230/1330

2.6 Serial Program/Verify Operation

The PGC pin is used as a clock input pin and the PGD

pin is used for entering command bits and data input/

output during serial operatio n. Commands and data are

transmitted on the rising edge of PGC, latched on the

falling edge of PGC and are Least Significant bit (LSb)

first.

2.6.1 4-BIT COMMANDS

All instructions are 20 bits, consisting of a leading 4-bit

comma nd, followed by a 16 -bit operand which dep ends

on the type of command being executed. To input a

command, PGC is cycled four times. The commands

needed for programming and verification are shown in

Table 2-3.

Depending on the 4-bit command, the 16-bit operand

represents 16 bits of input data, or 8 bits of input data

and 8 bits of output data.

Throughout this specification, commands and data are

presented as illustrated in Table 2-4. The 4-bit command

is shown Most Significant bit (MSb) first. The command

operand, or “Data Payload”, is shown <MSB><LSB>.

Figure 2-10 demonstrates how to serially present a

20-bit command/op erand to t he device.

2.6.2 CORE INST RU CTIO N

The core instruction passes a 16-bit instruction to the

CPU core for execution. This is needed to set up

TABLE 2-3: COMMANDS FOR

PROGRAMMING

TABLE 2-4: SAMPLE COMMAND

SEQUENCE

FIGURE 2-10: TABLE WRITE, POST-INCREMENT TIMING (1101)

Description 4-Bit

Command

Core In st ruction

(shift in16-b it inst ru ct i on) 0000

Shi ft o ut TA BL AT R egi s ter 0010

Table Read 1000

Table Read, Post-Increment 1001

Table R ead , Po st -Decrement 1010

Table R ead , Pre- I ncr em ent 1011

Table Write 1100

Table Write, Pos t -Increment by 2 1101

Table Write, Start Progr am m ing,

Post -In crement by 2 1110

Table Write, Start Progr am m ing 1111

4-Bit

Command Data

Payload Core Instruction

1101 3C 40 Table Write,

post-increment by 2

1234

PGD = Input

5678 1234

P5A

910 11 13 15 161412

Fetch Next 4-Bit Command

1011

1234

nnnn

P2 P2A

000000 010001111 0

04C3

4-Bit Command 16-Bit Data Payload

P2B

PGC

PGD

PIC18F1230/1330

2.7 28-Pin PIC18F1330-ICD Device

(Dedicated ICD Port)

The PIC18F1330-ICD 28-pin QFN device has a

dedicated ICSP/ICD port. The primary purpose of this

port is to provide an alternate In-Circuit Debugging

(ICD) option and free the pins (RB6, RB7 and MCLR)

that wou ld normally be used for debu gging the appl ica-

tion. In conjunction with ICD capability, however, the

dedicated ICSP/ICD port also provides an alternate

port for ICSP.

The dedicated ICSP/ICD port functions the same as

the default ICSP/ICD port; however, alternate pins are

used ins tead of the default pi ns. Table 2-5 identifies the

functionally equivalent pins for ICSP purposes.

The dedicated ICSP/ICD port is an a lternate po rt. Thus,

ICSP is still available through the default port. When

the V IH is seen on the MCLR/VPP/RA5/FLTA pin prior to

applying VIH to the ICRST/ICVPP pin, then the state of

the ICRST/ICVPP pin is ignored. Likewise, when the

VIH is seen on ICRST/ICVPP prior to applying VIH to

MCLR/VPP/RA5/FLTA, then the state of the MCLR/VPP/

RA5/FLTA pin is ignored.

TA BL E 2-5: ICSP™ EQ UIVA LEN T PINS

Pin Name During Programming

Pin Name Pin Type Dedicated Pin Pin Description

MCLR/VPP/RA5/FLTA VPP P ICRST/ICVPP Programming Enable

RB6 PGC I ICCK/ICPGC Serial Clock

RB7 PGD I/O ICDT/ICPGD Serial Data

Legend: I = Input, O = Output, P = Power

PIC18F1230/1330

3.0 DEVICE PROGRAMMING

Programming includes the ability to erase or write the

various memory regions within the device.

In all cases, except high-voltage ICSP Bulk Erase, the

EECON1 register must be configured in order to

operate on a part icular me mory regi on.

When using the EECON1 register to act on code

memory , the EEPGD bit must be set (EECON1<7> = 1)

and the CFGS bit must be cleared (EECON1<6> = 0).

The WREN bit must be set (EECON1<2> = 1) to

enable writes of any sort (e.g., erases) and this must be

done prior to initiating a write sequence. The FREE bit

must be set (EECON1<4> = 1) in order to erase the

program space being pointed to by the Table Pointer.

The erase or write sequence is initiated by setting the

WR bit (EECON1<1> = 1). It is strongl y recom me nde d

that the WREN bit only be set immediately prior to a

program eras e.

3.1 ICSP Erase

3.1.1 HIGH-VOLTAGE ICSP BULK ERASE

Erasing code or data EEPROM is accomplished by

configuring two Bulk Erase Control registers located at

3C000 4h an d 3C 000 5h. Code memo ry may be erase d

portions at a time, or the user may erase the entire

device in one action. Bulk Erase operations will also

clear any code-protect settings associated with the

memory block erased. Erase options are detailed in

Table 3-1. If data EEPROM is code-protected

(CPD = 0), the user must request an erase of data

EEPROM (e.g., 0084h as shown in Table 3-1).

TABLE 3-1: BULK ERASE OPTIONS

The actual Bulk Erase function is a self-timed

operation. Once the erase has started (falling edge of

the 4th PGC after the NOP command), serial execution

will cease until the erase completes (parameter P11).

During this time, PGC may continue to toggle but PGD

must be held low.

The code s equence to eras e the entire devic e is shown

in Table 3-2 and the flowchart is shown in Figure 3-1.

TABLE 3-2: BULK ERASE COMMAND

SEQUENCE

FIGURE 3-1: BULK ERASE FLOW

Description Data

(3C0005h:3C0004h)

Chip Erase 0F87h

Erase Data EEPROM(1) 0084h

Erase Bo ot Block 0081h

Erase Configuration Bits 0082h

Erase Code EEPROM Block 0 0180h

Erase Code EEPROM Block 1 0280h

Erase Code EEPROM Block 2 0480h

Erase Code EEPROM Block 3 0880h

Note 1: Selected devices only, see Section 3.3

“Data EEPROM Programming”.

Note: A Bulk Erase is the only way to reprogram

code-protect bits from an ON state to an

OFF sta t e.

4-Bit

Command Data

Payload Core Instruction

0000

1100

0000

1100

0000

0E 3C

6E F8

0E 00

6E F7

0E 05

6E F6

0F 0F

0E 3C

6E F8

0E 00

6E F7

0E 04

6E F6

87 87

00 00

MOVLW 3Ch

MOVWF TBLPTRU

MOVLW 00h

MOVWF TBLPTRH

MOVLW 05h

MOVWF TBLPTRL

Write 0Fh to 3C0005h

MOVLW 3Ch

MOVWF TBLPTRU

MOVLW 00h

MOVWF TBLPTRH

MOVLW 04h

MOVWF TBLPTRL

Write 8787h to 3C0004h

to eras e ent ire

device.

NOP

Hold PGD low until

erase completes.

Start

Done

Write 8787h to

3C0004h to Erase

Entire Device

Write 0F0Fh

Delay P11 + P10

Time

to 3C0005h

PIC18F1230/1330

FIGURE 3-2: BULK ERASE TIMING

3.1.2 ICSP ROW ERASE

For a PIC18F1230/1330 device, it is possible to erase

one row (64 bytes of data), provided the block is not

code or write-protected. Rows are located at static

boundaries, beginning at program memory address

000000h, extending to the internal program memory

limit (see Section 2.3 “Memo r y Maps”).

The Row Erase duration is externally timed and is

controlled by PGC. After the WR bit in EECON1 is set,

a NOP is issue d, where th e 4th PGC is he ld high for th e

duration of the program mi ng tim e, P9.

After PGC is brought low, the programming sequence

is terminated. PGC must be held low for the time

specified by parameter P10 to allow high-voltage

discharge of the memory array.

The code sequence to Row Erase a PIC18F1230/1330

device is shown in Table 3-3. The flowchart shown in

Figure 3-3 depicts the logic necessary to completely

erase a PIC18F1230/1330 device. The timing diagram

that details the Start Programming command and

parameters P9 and P10 is s hown in Figure 3-5.

1234 121516 123

PGC

P5 P5A

PGD

PGD = Input

00011

P11

P10

Erase Time

000000

12 1516

123

P5A

0000

4-Bit Command 4-Bit Command 4-Bit Command16-Bit

Data Payload

16-Bit

Data Payload 16-Bit

Data Payload

Note: The TBLPTR register can point to any byte

within the row intended for erase.

PIC18F1230/1330

TABLE 3-3: ERASE CODE MEMORY CODE SEQUENCE

FIGURE 3-3: SINGLE ROW ERASE CODE MEMORY FLOW

4-Bit

Command Data Payload Core Instruction

St ep 1: Direct access to code memory and enable writes.

0000

8E A6

9C A6

84 A6

BSF EECON1, EEPGD

BCF EECON1, CFGS

BSF EECON1, WREN

St ep 2: Point to first row in code memory.

0000

6A F8

6A F7

6A F6

CLRF TBLPTRU

CLRF TBLPTRH

CLRF TBLPTRL

Step 3: Enable erase and erase single row.

0000

88 A6

82 A6

00 00

BSF EECON1, FREE

BSF EECON1, WR

NOP – hold PGC high for time P9 and low for time P10.

Step 4: Repeat step 3, with Address Pointer incremented by 64 until all rows are erased.

Done

Start

Hold PGC Low

for Tim e P1 0

All

rows

done?

Yes

Addr = 0

Configure

Device for

Row Erases

Addr = Addr + 64

Start Erase Sequence

and Hold PGC High

for Time P9

PIC18F1230/1330

3.2 Code Memory Programming

Programming code memory is accomplished by first

loading data into the write buffer and then initiating a

programming sequence. The write and erase buffer

sizes, shown in Table 3-4, can be mapped to any

location of the same size, beginning at 000000h. The

actual memory write sequence takes the contents of

this buffer and programs the proper amount of code

memory that contains the Table Pointer.

The programming duration is externally timed and is

controlled by PGC. After a Start Programming

command is issued (4-bit command, ‘1111’), a NOP is

issued , where th e 4t h PGC is he ld hig h for the dur ation

of the programming time, P9.

After PGC is brought low, the programming sequence

is terminated. PGC must be held low for the time

specified by parameter P10 to allow high-voltage

discharge of the memory array.

The code sequence to program a PIC18F1230/1330

device is shown in Table 3-5. The flowchart, shown in

Figure 3-4, depicts the logic necessary to completely

write a PIC18F1230/1330 device. The timing diagram

that details the Start Programming command and

parameters P9 and P10 is shown in Figure 3-5.

TABLE 3-4: WRITE AND ERASE BUFFER

SIZES

TABLE 3-5: WRITE CODE MEMORY CODE SEQUENCE

Note: The TBLPTR register must point to the

same region when initiating the program-

ming sequence as it did when the write

buffers were loaded.

Device Write Buffer

Size (bytes) Erase Buffer

Size (bytes)

PIC18F1230 864

PIC18F1330

4-Bit

Command Data Payload Core Instruction

St ep 1: Direct access to code memory and enable writes.

0000

0000 8E A6

9C A6 BSF EECON1, EEPGD

BCF EECON1, CFGS

Step 2: Load write buffer.

0000

0E <Addr[21:16]>

6E F8

0E <Addr[15:8]>

6E F7

0E <Addr[7:0]>

6E F6

MOVLW <Addr[21:16]>

MOVWF TBLPTRU

MOVLW <Addr[15:8]>

MOVWF TBLPTRH

MOVLW <Addr[7:0]>

MOVWF TBLPTRL

Step 3: Repeat for all but the last two bytes.

1101 <MSB><LSB> Write 2 bytes and post-increment address by 2.

Step 4: Load write buffer for the last two bytes.

1111

0000 <MSB><LSB>

00 00 Write 2 bytes and start programming.

NOP - hold PGC high for time P9 and low for time P10.

To continue writing data, repeat steps 2 through 4, where the Address Pointer is incremented by 2 at each iteration of the loop.

PIC18F1230/1330

FIGURE 3-4: PROGRAM CODE MEMORY FLOW

FIGURE 3-5: TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111)

Start Write Sequence

All

locations

done?

Done

Start

Yes

Hold PGC Low

for Time P10

Load 2 Bytes

to Wri te

Buffer at <Addr>

All

bytes

written?

Yes

and Hold PGC

High until Done

N = 1

LoopCount = 0

Configure

Device for

Writes

N = 1

LoopCount =

LoopCount + 1

N = N + 1

and Wait P9

1234 12 1516 123 4

PGC

P5A

PGD

PGD = Input

1111

34 65

P10

Programming Time

nnn nn n n

16-Bit

Data Payload

4-Bit Command 16-Bit Data Payload 4-Bit Command

PIC18F1230/1330

3.2.1 MODIFYING CODE MEMORY

The previous programming example assumed that the

device had been Bulk Erased prior to programming

(see Section 3.1.1 “High-V oltage ICSP Bulk Erase”).

It may be the case, however, that the user wishes to

modify only a section of an already programmed

device.

The appropriate number of bytes required for the erase

buffer must be read out of code memory (as described

in Section 4.2 “Verify Code Memory and ID Loca-

tions”) and buffered. Modifications can be made on this

buffer. Then, the block of code memory that was read

out must be erased and rewritten with the modified data.

The WREN bit must be set if the WR bit in EECON1 is

used to initiate a write sequence.

TABLE 3-6: MODIFYING CODE MEMORY

4-Bit

Command Data Payload Core Instruction

St ep 1: Direct access to code memory.

Step 2: Read and modify code memory (see Sec t i on 4.1 “Rea d C o de Me mor y, ID Lo c a t i ons and Co nfigura tion Bi ts”).

0000

0000 8E A6

9C A6 BSF EECON1, EEPGD

BCF EECON1, CFGS

St ep 3: Set the Table Pointer for the block to be erased.

0000

0E <Addr[21:16]>

6E F8

0E <Addr[8:15]>

6E F7

0E <Addr[7:0]>

6E F6

MOVLW <Addr[21:16]>

MOVWF TBLPTRU

MOVLW <Addr[8:15]>

MOVWF TBLPTRH

MOVLW <Addr[7:0]>

MOVWF TBLPTRL

Step 4: Enable memory writes and set up an erase.

0000

0000 84 A6

88 A6 BSF EECON1, WREN

BSF EECON1, FREE

Step 5: Initiate erase.

0000

0000 82 A6

00 00 BSF EECON1, WR

NOP - hold PGC high for time P9 and low for time P10.

Step 6: Load write buffer. The correct bytes will be selected based on the Table Pointer.

0000

1101

1111

0000

0E <Addr[21:16]>

6E F8

0E <Addr[8:15]>

6E F7

0E <Addr[7:0]>

6E F6

00 00

MOVLW <Addr[21:16]>

MOVWF TBLPTRU

MOVLW <Addr[8:15]>

MOVWF TBLPTRH

MOVLW <Addr[7:0]>

MOVWF TBLPTRL

Write 2 bytes and post-increment address by 2.

Repeat as many times as necessary to fill the write buffer

Write 2 bytes and start programming.

NOP - hold PGC high for time P9 and low for time P10.

To continue modifying data, repeat S teps 2 through 6, where the Address Pointer is incremented by the appropriate number of bytes

(see Table 3-4) at each iteration of the loop. The write cycle must be repeated enough times to completely rewrite the contents of

the erase buffer.

Step 7: Disable writes.

0000 94 A6 BCF EECON1, WREN

PIC18F1230/1330

3.3 Data EEPROM Programming

Data EEPROM is accessed one byte at a time via an

Address Pointer (register pair, EEADRH:EEADR) and

a Data Latch (EEDATA). Data EEPROM is written by

loading EEADRH:EEADR with the desired memory

locatio n, EEDATA with the dat a to be written and initi at-

ing a memory write by appropriately configuring the

EECON1 register . A byte write automatically erases the

location and writes the new data (erase-before-write).

When using the EECON1 register to perform a data

EEPROM write, both the EEPGD and CFGS bits must

be cleared (EECON1<7:6> = 00). The WREN bit must

be set (EECON1< 2> = 1) to enable writes of any sort

and this must be done prior to initiating a write

sequen ce. The write sequence is initiated by setting the

WR bit (EECON1<1> = 1).

The write begins on the falling edge of the 4th PGC

after the WR bit is set. It ends when the WR bit is

cleared by hardware.

After the programming sequence terminates, PGC m ust

still be held low for the time specified by parameter P10

to allow high-volt age dis charge of the memory array.

FIGURE 3-6: PROGRAM DATA FLOW

FIGURE 3-7: DATA EEPROM WRITE TIMING

Start

Start W rite

Set Data

Done

Yes

Done?

Enable Write

Sequence

Set Address

WR bit

clear? No

Yes

PGC

PGD

PGD = Input

0000

BSF EECON1, WR

4-Bit Command

1234 121516

P5 P5A

P10 12

Poll WR bit, Repeat until Clear 16-Bit Data

Payload

1234 121516 123

P5 P5A

412 1516

P5 P5A

0000

MOVF EECON1, W, 04-Bi t Command

0000

4-Bit Command Shift Out Data

MOVWF TABLAT

PGC

PGD

(see below)

(see Fig ure 4-4)

PGD = Input PGD = Output

Poll WR bit

P11A

PIC18F1230/1330

TABLE 3-7: PROGRAMMING DATA MEMORY

4-Bit

Command Data Payload Core Instruction

St ep 1: Direct access to data EEPROM.

0000

0000 9E A6

9C A6 BCF EECON1, EEPGD

BCF EECON1, CFGS

Step 2: Set the data EEPROM Address Pointer .

0000

0E <Addr>

6E A9

OE <AddrH>

6E AA

MOVLW <Addr>

MOVWF EEADR

MOVLW <AddrH>

MOVWF EEADRH

Step 3: Load the data to be written.

0000

0000 0E <Data>

6E A8 MOVLW <Data>

MOVWF EEDATA

Step 4: Enable memory writes.

0000 84 A6 BSF EECON1, WREN

Step 5: Initiate write.

0000 82 A6 BSF EECON1, WR

Step 6: Poll WR bit, repeat until the bit is clear.

0000

0010

50 A6

6E F5

00 00

MOVF EECON1, W, 0

MOVWF TABLAT

NOP

Shift out data(1)

Step 7: Hold PGC low for time P10.

Step 8: Disable writes.

0000 94 A6 BCF EECON1, WREN

Repeat steps 2 through 8 to write more data.

Note 1: See F igure 4-4 for details on shift out data timing.

PIC18F1230/1330

3.4 ID Location Programming

The ID locations are programmed much like the code

memory. The ID registers are mapped in addresses

200000h through 200007h. These locations read out

normally ev en after code protection.

Table 3-8 demonst rates the cod e sequenc e required to

write the ID locations.

In order to modify the ID locations, refer to the

methodology described in Section 3.2.1 “Modifying

Code Memory”. As with code memory, the ID

locations must be erased before bei ng modified.

TABLE 3-8: WRITE ID SEQUENCE

Note: The user only needs to fill the first 8 bytes

of the write buffer in order to write the ID

locations.

4-Bit

Command Data Payload Core Instruction

St ep 1: Direct access to code memory and enable writes.

0000

0000 8E A6

9C A6 BSF EECON1, EEPGD

BCF EECON1, CFGS

Step 2: Load write buffer with 8 bytes and write.

0000

1101

1111

0000

0E 20

6E F8

0E 00

6E F7

0E 00

6E F6

00 00

MOVLW 20h

MOVWF TBLPTRU

MOVLW 00h

MOVWF TBLPTRH

MOVLW 00h

MOVWF TBLPTRL

Write 2 bytes and post-increment address by 2.

Write 2 bytes and start programming.

NOP - hold PGC high for time P9 and low for time P10.

PIC18F1230/1330

3.5 Boot Block Programming

The code sequence detailed in Table 3-5 should be

used, except t hat the a ddress u sed in “Step 2” will b e in

the range of 00000h to 007FFh.

3.6 Configuration Bits Programming

Unlike code memory, the Configuration bits are

programmed a byte at a time. The Table Write, Begin

Programming 4-bit command (‘1111’) i s us ed, but only

8 bits of the following 16-bit payload will be written. The

LSB of the payload will be written to even addresses and

the MSB will be written to odd addresses. The code

sequence to program two consecutive Configuration

locations is shown in Table 3-9.

TABLE 3-9: SET ADDRESS POINTER TO CONFIGURATION LOCATION

FIGURE 3-8: CONFIGURATION PROGRAMMING FLOW

Note: The address must be explicitly written for

each byte programmed. The addresses

can not be increm en ted in this mode .

4-Bit

Command Data Payload Core Instruction

St ep 1: Enable writes and direct access to configuration memory.

0000

0000 8E A6

8C A6 BSF EECON1, EEPGD

BSF EECON1, CFGS

Step 2: Set Table Pointer for configuration byte to be written. Write even/odd addresses.(1)

0000

1111

0000

1111

0000

0E 30

6E F8

0E 00

6E F7

0E 00

6E F6

00 00

0E 01

6E F6

00 00

MOVLW 30h

MOVWF TBLPTRU

MOVLW 00h

MOVWF TBLPRTH

MOVLW 00h

MOVWF TBLPTRL

Load 2 bytes and start programming.

NOP - hold PGC high for time P9 and low for time P10.

MOVLW 01h

MOVWF TBLPTRL

Load 2 bytes and start programming.

NOP - hold PGC high for time P9 and low for time P10.

Note 1: Enabling the write protection of Configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of Configuration

bits. Always write all the Configuration bits before enabling the write protection for Configuration bits.

Load Even

Configuration

Start

Program Program

MSB

Delay P9 and P10

Time for Write

LSB

Load Odd

Configuration

Address Address

Done

Start

Delay P9 and P10

Time for Write

Done

PIC18F1230/1330

4.0 READING THE DEVICE

4.1 Read Code Memory, ID Locations

and Configurati on Bits

Code memory is accessed one byte at a time via the

4-bit command, ‘1001’ (table read, post-increment).

The co ntents of memory p ointed to by the Table Po inter

(TBLPTRU:TB LPTRH:TBLPTRL) are serially output on

PGD.

The 4-bit command is shifted in, LSb first. The read is

executed during the next 8 clocks, then shifted out on

PGD during the last 8 clocks, LSb to MSb. A delay of

P6 must be introduced after the falling edge of the 8th

PGC of the ope ran d to a llow PGD to trans iti on fr om an

input to an output. During this time, PGC must be held

low (see Figure 4-1). This operation also increments

the Table Pointer by one, pointing to the next byte in

code memory for the next read.

This technique will work to read any memory in the

000000h to 3FFFFFh address s p a ce, s o i t a ls o a ppl ie s

to the reading of the ID and Configuration registers.

TABLE 4-1: READ CODE MEMORY SEQUENCE

FIGURE 4-1: TABLE R EAD POST-INCREMENT INSTRUCTION TIMING (1001)

4-Bit

Command Data Payload Core Instruction

Step 1: Set Table Pointer.

0000

0E <Addr[21:16]>

6E F8

0E <Addr[15:8]>

6E F7

0E <Addr[7:0]>

6E F6

MOVLW Addr[21:16]

MOVWF TBLPTRU

MOVLW <Addr[15:8]>

MOVWF TBLPTRH

MOVLW <Addr[7:0]>

MOVWF TBLPTRL

Step 2: Read memory and then shift out on PGD, LSb to MSb.

1001 00 00 TBLRD *+

1234

PGC

PGD

PGD = Input

Shift Data Out

PGD = Output

5678 1234

P5A

910 11 13 15 161412

Fetch Next 4-Bit Command

1001

PGD = Input

LSb MSb123456

1234

nnnn

P14

PIC18F1230/1330

4.2 Verify Code Memory and ID

Locations

The veri fy step invo lves read ing back the code memo ry

space and comparing it against the copy held in the

programmer’s buffer. Memory reads occur a single byte

at a time, so two bytes must be read to compare

against the word in the programmer’s buffer. Refer to

Section 4.1 “Read Code Memory, ID Locations and

Configuration Bits” for implementation details of

reading co de mem ory.

The Table Pointer must be manually set to 200000h

(base address of the ID locations) once the code

memory has been verified. The post-increment feature

of the table read 4-bit command may not be used to

increment the Table Pointer beyond the code memory

space. In an 8-Kbyte device, for example, a post-

inc remen t re ad of ad dr ess 0 1FFFh will wrap the Ta ble

Pointer back to 00000h, rather than point to

unimplemented address, 02000h.

FIGURE 4-2: VERIFY CODE MEMORY FLOW

Read Low Byte

Read High Byte

Does

Word = Expect

Data? Failure,

Report

Error

All

code memory

verified?

Yes

Set TBLPTR = 0

Start

Set TBLPTR = 200000h

Yes

Read Low Byte

Read High Byte

Does

Word = Expect

Data? Failure,

Report

Error

All

ID locations

verified?

Yes

Done

Yes

with Post-Increment

with Post-Increment Increment

Pointer

with Post-Increment

PIC18F1230/1330

4.3 Verify Configuration Bits

A Configuration address may be read and output on

PGD via th e 4-bit co mmand, ‘1001’. Config uration dat a

is read and written in a byte-wise fashion, so it is not

necessary to merge two bytes into a word prior to a

compare. The result may then be immediately

compared to the appropriate configuration data in the

programmer’s memory for verification. Refer to

Section 4.1 “Read Code Memory, ID Locations and

Configuration Bits” for implementation details of

reading C onfi gu ratio n data.

4.4 Read Data EEPROM Memory

Data EEPROM is accessed one byte at a time via an

Address Pointer (register pair, EEADRH:EEADR) and a

Data Latch (EEDA T A). Data EEPROM is read by loading

EEADRH:EEADR with the desired memory location and

initiating a memory read by appropriately configuring the

EECON1 register . The d ata will be loaded into EED A TA,

where it may be serially output on PGD via the 4-bit com-

mand, ‘0010’ (Shift Out Data Holding register). A delay

of P6 must be introduced af ter the falling edge of the 8th

PGC of the operand to allow PGD to transition from an

input to an output. During this time, PGC must be held

low (see Figure 4-4).

The command sequence to read a single byte of data

is shown in Table 4-2.

FIGURE 4-3: READ DATA E EPROM

FLOW

TABLE 4-2: READ DATA EEPROM MEMORY

Start

Set

Address

Read

Byte

Done

Yes

Done?

Move to TABLAT

Shift Out Data

4-Bit

Command Data Payload Core Instruction

St ep 1: Direct access to data EEPROM.

0000

0000 9E A6

9C A6 BCF EECON1, EEPGD

BCF EECON1, CFGS

St ep 2: Set the Data EEPROM Address Pointer.

0000

0E <Addr>

6E A9

OE <AddrH>

6E AA

MOVLW <Addr>

MOVWF EEADR

MOVLW <AddrH>

MOVWF EEADRH

Step 3: Initiate a memory read.

0000 80 A6 BSF EECON1, RD

Step 4: Load data into the Serial Data Holding register.

0000

0010

50 A8

6E F5

00 00

MOVF EEDATA, W, 0

MOVWF TABLAT

NOP

Shift Out Data(1)

Note 1: The <LSB> is undefined. The <MSB> is the data.

PIC18F1230/1330

FIGURE 4-4: SHIFT OUT DATA HOLDING REGISTER TIMING (0010)

4.5 Verify Data EEPROM

A data EEPROM add res s may b e re ad via a se qu enc e

of core instructions (4-bit command, ‘0000’) and then

output on PGD via the 4-bit command, ‘0010’ (TABLAT

compared to the appropriate data in the programmer’s

memory for verification. Refer to Section 4.4 “Read

Dat a EEPROM Memory ” for i mp lem en t ati on de tails of

reading data EEPROM.

4.6 Blank Check

The term “Blank Chec k” me ans to verify that the device

has no p ro gr amm ed m em ory ce l ls. A ll m e mo rie s mu st

be verified: code memory, data EEPROM, ID locations

and Configuration bits. The Device ID registers

(3FFFFEh:3FFFFFh) should be ignored.

A “blank” or “erased” memory cell will read as a ‘1’.

Therefore, Blank Checking a device merely means to

verify that all bytes read as FFh except the

Configuration bits. Unused (reserved) Configuration

bits will read ‘0’ (programmed). Refer to Table 5-1 for

blank configuration expect data for the various

PIC18F1 230 /13 30 dev ic es .

Given that Blank Checking is merely code and data

EEPROM verification with FFh expect data, refer to

Section 4.4 “Read Data EEPROM Memory” and

Section 4.2 “V erify Code Memory and ID Locations”

for implement atio n det ails.

FIGURE 4-5: BLANK CHECK FLOW

1234

PGC

PGD

PGD = Input

Shift Data Out

PGD = Output

5678 1234

P5A

91011 13 15161412

Fetch Next 4-Bit Command

0100

PGD = Input

LSb MSb123456

1234

nnnn

P14

Yes

Start

Blank Check Device

device

blank? Continue

Abort

PIC18F1230/1330

5.0 CONFIGURATION WORD

The PIC18F1230/1330 devic es have several Configura-

tion Words. These bits can be set or cleared to select

various device configurations. All other memory areas

should be programmed and verified prior to setting

Configuration Words. These bits may be read out nor-

mally, even after read or code protection. See Table 5-1

for a list of Configuration bits and Device IDs and

Table 5-3 for the Configuration bit descriptions.

5.1 ID Locations

A user may sto re ide ntif ic atio n inf orm atio n (ID) in eight

ID locations, mapped in 200000h:200007h. It is

recommended that the most significant nibble of each

ID be Fh. In doing so, if the user code inadvertently tries

to exe cute f rom th e ID space , the I D data wi ll exec ute

as a NOP.

5.2 Device ID Word

The Devi ce ID W ord for the PIC18F1230 /1330 de vice s

is located at 3FFFFEh:3FFFFFh. These bits may be

used by t he programmer to i den tify what devic e t ype i s

being programmed and read out normally, even after

code or read protection. See Table 5-2 for a complete

list of Device ID values.

FIGURE 5-1: READ DEVICE ID WORD

FLOW

TABLE 5-1: CONFIGURATION BITS AND DEVICE IDs

TABLE 5-2: DEVICE ID VALUE

Start

Set TBLPTR = 3FFFFE

Done

Read Low Byte

Read High Byte

with Post-Increment

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/

Unprogrammed

Value

300001h CONFIG1H IESO FCMEN —— FOSC3 FOSC2 FOSC1 FOSC0 00-- 0111

300002h CONFIG2L — — — BORV1 BORV0 BOREN1 BOREN0 PWRTEN ---1 1111

300003h CONFIG2H — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111

300004h CONFIG3L — — — — HPOL LPOL PWMPIN —---- 111-

300005h CONFIG3H MCLRE — — —T1OSCMX——FLTAMX1--- 0--1

300006h CONFIG4L BKBUG XINST BBSIZ1 BBSIZ0 — — —STVREN1000 ---1

300008h CONFIG5L — — — — — —CP1CP0---- --11

300009h CONFIG5H CPD CPB — — — — — — 11-- ----

30000Ah CONFIG6L — — — — — — WRT1 WRT0 ---- --11

30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 111- ----

30000Ch CONFIG7L — — — — — — EBTR1 EBTR0 ---- --11

30000Dh CONFIG7H —EBTRB— — — — — — -1-- ----

3FFFFEh DEVID1(1) DEV2 DEV1 DEV0 REV4 REV3 REV2 REV 1 REV0 See Table 5-2

3FFFFFh DEVID2(1) DEV10 DEV9 DEV8 D EV 7 DEEV 6 DEV 5 D EV 4 DE V3 See Table 5-2

Legend: x = unknown, u = unchanged, - = unimplemented.Shaded cells are unimplement ed, read as ‘0’.

Note 1: D EVI D regist ers are read-only and cannot be programmed by the user.

Device Dev ice ID Value

DEVID2 DEVID1

PIC18F1230 1Eh 000x xxxx

PIC18F1330 1Eh 001x xxxx

PIC18F1330-ICD 1Fh 111x xxxx

Note: The ‘x’s in DEVID1 contain the device revision code.

PIC18F1230/1330

TABLE 5-3: PIC18F1230/1330 BIT DESCRIPTIONS

Bit Name Configuration

Words Description

IESO CONFIG1H Internal External Switchover bit

1 = Internal External Switchover mode enabled

0 = Internal External Switchover mode disabled

FCMEN CONFIG1H Fail- Safe Cloc k Mo nito r Enabl e bit

1 = Fail-Safe Cloc k Mo nito r enabl ed

0 = Fail-Safe Cloc k Mo nitor disabled

FOSC<3:0> CONFIG1H Oscillator Selection bits

11xx = External RC oscillator, CLKO function on RA6

101x = External RC oscillator, CLKO function on RA6

1001 = Internal RC oscillator, CLKO function on RA6, port function on RA7

1000 = Internal RC oscillator, port function on RA6, port function on RA7

0111 = External RC os cillator, port function on RA6

0110 = HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)

0101 = EC oscillator, port function on RA6

0100 = EC oscillator, CLKO function on RA6

0011 = External RC oscillator, CLKO function on RA6

0010 = HS oscillator

0001 = XT oscillator

0000 = LP oscillat or

BORV<1:0> CONFIG2L Brown-out Reset Voltage bits

11 =V

BOR set to 2.0V

10 =V

BOR set to 2.7V

01 =V

BOR set to 4.2V

00 =V

BOR set to 4.5V

BOREN<1 :0> CONFIG2L Brow n-ou t Reset Enab le bits

11 = Brown-out Reset enabled in hardware only (SBOREN is disabled)

10 = Brown-out Reset enabled in hardware only and disabled in Sleep mode

(SB O REN is disa bled)

01 = Brown-out Reset enabled and controlled by software (SBOREN is enabled)

00 = Brown-out Reset disabled in hardware and software

PWRTEN CONFIG2L Power-up Timer Enable bit

1 = PWRT disabled

0 = PWRT enabled

WDTPS<3:0> CONFIG2H Watchdog Timer Postscaler Select bits

1111 = 1:32,768

1110 = 1:16,384

1101 = 1:8,192

1100 = 1:4,096

1011 = 1:2,048

1010 = 1:1,024

1001 = 1:512

1000 = 1:256

0111 = 1:128

0110 = 1:64

0101 = 1:32

0100 = 1:16

0011 = 1:8

0010 = 1:4

0001 = 1:2

0000 = 1:1

Note 1: The BB SIZ<1 :0> bits can not be c han ge d once any of the following code-p rote ct bits a r e e nab le d: CPB or

CP0, WRTB or WRT0, EBTRB or EBTR0.

PIC18F1230/1330

WDTEN CONFIG2H Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled (control is placed on SWDTEN bit)

HPOL CONFIG3L High Side Transistors Polarity bit (Odd PWM Output Polarity Control bit)

1 = PWM 1, 3 and 5 are acti ve-high (defau lt)

0 = PWM 1, 3 and 5 are acti ve-low

LPOL CONFIG3L Low Side Transistors Polarity bit (Even PWM Output Polarity Control bit)

1 = PWM 0, 2 and 4 are acti ve-high (defau lt)

0 = PWM 0, 2 and 4 are active-low

PWMPIN CONFIG3L PWM Output Pins Reset State Control bit

1 = PWM outputs d isa bled upon Res et

0 = PWM outputs drive active states upon Reset

MCLRE CONFIG3H MCLR Pin Enable bit

1 =MCLR pin enabled, RA5 input pin disabled

0 = RA5 input pin enabled, MCLR pin disabled

T1OSCMX CONFIG3H T1OSC MUX bit

1 = T1OSC pins reside on RA6 and RA7

0 = T1OSC pins reside on RB2 and RB3

FLTAMX CONFIG3H FLTA MUX bit

1 = FLTA is multiplexed with RA5

0 = FLTA is multiplexed with RA7

BKBUG CONFIG4L Background Debugger Enable bit

1 = Background debugger disabled, RB6 and RB7 configured as general

purpose I/O pins

0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit

Debug

XINST CONFIG4L Extended Instruction Set Enable bit

1 = Instruction set extension and Indexed Addressing mode enabled

0 = Instruction set extension and Indexed Addressing mode disabled

(Legacy mode)

BBSIZ<1:0>(1) CONFIG4L Boot Block Size Select bits

For PIC18F1330 device:

11 = 1 kW Boot Block size

10 = 1 kW Boot Block size

01 = 512W Boot Block size

00 = 256W Boot Block size

For PIC18F1230 device:

11 = 512W Boot Block size

10 = 512W Boot Block size

01 = 512W Boot Block size

00 = 256W Boot Block size

STVREN CONFIG4L Stack Overflow/Underflow Reset Enable bit

1 = Reset on stack overflow/underflow enabled

0 = Reset on stack overflow/underflow disabled

CP1 CONFIG5L Code Protection bits (Block 1 code memory area)

1 = Block 1 is not code-protected

0 = Block 1 is code-protected

TABLE 5-3: PIC18F1230/1330 BIT DESCRIPTIONS (CONTINUED)

Bit Name Configuration

Words Description

Note 1: The BB SIZ<1 :0> bits can not be c han ge d once any of the following code-p rote ct bits a r e e nab le d: CPB or

CP0, WRTB or WRT0, EBTRB or EBTR0.

PIC18F1230/1330

CP0 CONFIG5L Code Protection bits (Block 0 code memory area)

1 = Block 0 is not code-protected

0 = Block 0 is code-protected

CPD CONFIG5H Code Protection bits (Data EEPROM)

1 = Data EEPROM is not code-protected

0 = Data EEPROM is code-protected

CPB CONFIG5H Code Protection bits (Boot Block memory area)

1 = Boot Block is not code-protected

0 = Boot Block is code-protected

WRT1 CONFIG6L Write Protection bits (Block 1 code memory area)

1 = Block 1 is not write-protected

0 = Block 1 is write-prote c ted

WRT0 CONFIG6L Write Protection bits (Block 0 code memory area)

1 = Block 0 is not write-protected

0 = Bl ock 0 is writ e-pr otected

WRTD CONFIG6H Write Protection bit (Data EEPROM)

1 = Data EEPROM is not write-protected

0 = Data EEPROM is write-protected

WRTB CONFIG6H Write Protection bit (Boot Block memory area)

1 = Boot Block is not write -protec ted

0 = Boot Block is write-protected

WRTC CONFIG6H Write Protection bit (Configuration registers)

1 = Configuration registers are not write-protected

0 = Configuration registers are write-protected

EBTR1 CONFIG7L Table Read Protection bit (Block 1 code memory area)

1 = Block 1 is not protected from table reads executed in other blocks

0 = Block 1 is protected from table reads executed in other blocks

EBTR0 CONFIG7L Table Read Protection bit (Block 0 code memory area)

1 = Block 0 is not protected from table reads executed in other blocks

0 = Block 0 is protected from table reads executed in other blocks

EBTRB CONFIG7H Table Read Protection bit (Boot Block memory area)

1 = Boot Block is not protected from table reads executed in other blocks

0 = Boot Block is protected from table reads executed in other blocks

DEV<10:3> DEVID2 Device ID bits

These bits are used with the DEV<2:0> bits in the DEVID1 register to

identify the part number.

DEV<2:0> DEVID1 Device ID bits

These bits are used with the DEV<10:3> bits in the DEVID2 register to

identify the part number.

TABLE 5-3: PIC18F1230/1330 BIT DESCRIPTIONS (CONTINUED)

Bit Name Configuration

Words Description

Note 1: The BB SIZ<1 :0> bits can not be c han ge d once any of the following code-p rote ct bits a r e e nab le d: CPB or

CP0, WRTB or WRT0, EBTRB or EBTR0.

PIC18F1230/1330

5.3 Embedding Configuration Word

Info rmatio n in th e H E X File

To allow portability of code, a PIC18F1230/1330

programmer is required to read the Configuration Word

locations from the hex file. If Configuration Word

information is not present in the hex file, then a simple

warning message should be issued. Similarly, while

saving a hex file, all Configuration Word information

must be included. An option to not include the

Configuration Word information may be provided.

When embedding Configuration Word information in

the hex file, it should start at address 300000h.

Microchip Technology Inc. feels strongly that this

featur e is imp orta nt for th e bene fit of t he end cu stome r.

5.4 Embedding Data EEPROM

Info rmatio n in th e H E X File

To allow portability of code, a PIC18F1230/1330

programmer is required to read the data EEPROM

informa tion from the hex fil e. If dat a EEPROM in forma-

tion is not present, a simple warning message should

be issued. Similarly, when saving a hex file, all data

EEPROM information must be included. An option to

not include the data EEPROM information may be

provide d. When embeddi ng data EEPROM information

in the hex file, it should start at address F00000h.

Microchip Technology Inc. believes that this feature is

important for the benefit of the end customer.

5.5 Checksum Comput ation

The check s um is cal cu lat ed by sum mi ng the foll owing:

• The contents of all code me mory locations

• The Configuration Word, appropriately masked

• ID locations

The Least Significant 16 bits of this sum are the

checksum.

Table 5-4 (pages 30 through 31) describes how to

calculate the checksum for each device.

Note: The checksum calculation differs depend-

ing on the co de-prot ect setti ng. Sin ce the

code memory locations read o ut differently

dependi ng on the code-pro tect setting, th e

table describes how to manipulate the

actual code memory values to simulate

the values that would be read from a

protected device. When calculating a

checksum by reading a device, the entire

code memory can simply be read and

summed. The Configuration Word and ID

locations can always be read.

PIC18F1230/1330

TABLE 5-4: CHECKSUM COMPUTATION

Device Code-Protect Checksum Blank

Value

0xAA at 0

and Max

Address

PIC18F1230

None SUM(0000:01FF)+SUM(0200:FFF)+SUM(1000:1FFF)+(CONFIG0 & 0000)+

(CONFIG1 & 00CF)+(CONFIG2 & 001F)+(CONFIG3 & 001F)+

(CONFIG4 & 000E)+(CONFIG5 & 0089)+(CONFIG6 & 00F1)+

(CONFIG7 & 0000)+(CONFIG8 & 0003)+(CONFIG9 & 00C0)+

(CONFIG10 & 0003)+(CONFIG11 & 00E0)+(CONFIG12 & 0003)+

(CONFIG13 & 0040)

F33E F294

Boot 256W SUM(0200:FFF)+SUM(1000:1FFF)+( CONF IG0 & 0000)+(CONFIG1 & 0 0CF)+

(CONFIG2 & 001F)+(CONFIG3 & 001F)+(CONFIG4 & 000E)+

(CONFIG5 & 0089)+(CONFIG6 & 00F1)+(CONFIG7 & 0000)+

(CONFIG8 & 0003)+(CONFIG9 & 00C0)+(CONFIG10 & 0003)+

(CONFIG11 & 00E0)+(CONFIG12 & 0003)+(CONFIG13 & 0040)+SUM(IDs)

F521 F4C7

Boot 512W SUM(0400:FFF)+SUM(1000:1FFF)+( CONF IG0 & 0000)+(CONFIG1 & 0 0CF)+

(CONFIG2 & 001F)+(CONFIG3 & 001F)+(CONFIG4 & 000E)+

(CONFIG5 & 0089)+(CONFIG6 & 00F1)+(CONFIG7 & 0000)+

(CONFIG8 & 0003)+(CONFIG9 & 00C0)+(CONFIG10 & 0003)+

(CONFIG11 & 00E0)+(CONFIG12 & 0003)+(CONFIG13 & 0040)+SUM(IDs)

F732 F6D8

Boot/

Block 0 S UM (1000:1FFF)+(CONFIG0 & 0000)+(CONFIG1 & 00CF)+

(CONFIG2 & 001F)+(CONFIG3 & 001F)+(CONFIG4 & 000E)+

(CONFIG5 & 0089)+(CONFIG6 & 00F1)+(CONFIG7 & 0000)+

(CONFIG8 & 0003)+(CONFIG9 & 00C0)+(CONFIG10 & 0003)+

(CONFIG11 & 00E0)+(CONFIG12 & 0003)+(CONFIG13 & 0040)+SUM(IDs)

FB53 FAF9

All (CONFIG0 & 0000)+(CONFIG1 & 00CF)+(CONFIG2 & 001F)+

(CONFIG3 & 001F)+(CONFIG4 & 000E)+(CONFIG5 & 0089)+

(CONFIG6 & 00F1)+(CONFIG7 & 0000)+(CONFIG8 & 0003)+

(CONFIG9 & 00C0)+(CONF IG10 & 0003)+(CO NFIG11 & 00E0)+

(CONFIG12 & 0003)+(CONFIG13 & 0040)+SUM(IDs)

F351 F34C

Legend: Item Description

CFGW = Configuration Word

SUM[a:b] = Sum of locations, a to b inclusive

SUM_ID = Byte-wise sum of lower four bits of all customer ID locations

+ = Addition

& = Bit-wise AND

PIC18F1230/1330

PIC18F1330

None SUM(0000:01FF)+SUM(0200:FFF)+SUM(1000:1FFF)+(CONFIG0 & 0000)+

(CONFIG1 & 00CF)+(CONFIG2 & 001F)+(CONFIG3 & 001F)+

(CONFIG4 & 000E)+(CONFIG5 & 0089)+(CONFIG6 & 00F1)+

(CONFIG7 & 0000)+(CO NFIG8 & 0003)+(CO NF IG9 & 00C0)+

(CONFIG10 & 0003)+(CONFIG11 & 00E0)+(CONFIG12 & 0003)+

(CONFIG13 & 0040)

E33E E294

Boot 256W SUM(0200:FFF)+SUM(1000:1FFF)+( CONF IG0 & 0000)+(CONFIG1 & 0 0CF)+

(CONFIG2 & 001F)+(CONFIG3 & 001F)+(CONFIG4 & 000E)+

(CONFIG5 & 0089)+(CONFIG6 & 00F1)+(CONFIG7 & 0000)+

(CONFIG8 & 0003)+(CON FIG9 & 00C0)+(CO NF IG10 & 0003)+

(CONFIG11 & 00E0)+(CONFIG12 & 0003)+(CONFIG13 & 0040)+SUM(IDs)

E520 E4C6

Boot 512W SUM(0400:FFF)+SUM(1000:1FFF)+( CONF IG0 & 0000)+(CONFIG1 & 0 0CF)+

(CONFIG2 & 001F)+(CONFIG3 & 001F)+(CONFIG4 & 000E)+

(CONFIG5 & 0089)+(CONFIG6 & 00F1)+(CONFIG7 & 0000)+

(CONFIG8 & 0003)+(CON FIG9 & 00C0)+(CO NF IG10 & 0003)+

(CONFIG11 & 00E0)+(CONFIG12 & 0003)+(CONFIG13 & 0040)+SUM(IDs)

E731 E6D7

Boot 1 kW SUM(0800:FFF)+SUM(1000:1FFF)+(CONFIG0 & 0000)+(CONFIG1 & 00CF)+

(CONFIG2 & 001F)+(CONFIG3 & 001F)+(CONFIG4 & 000E)+

(CONFIG5 & 0089)+(CONFIG6 & 00F1)+(CONFIG7 & 0000)+

(CONFIG8 & 0003)+(CON FIG9 & 00C0)+(CO NF IG10 & 0003)+

(CONFIG11 & 00E0)+(CONFIG12 & 0003)+(CONFIG13 & 0040)+SUM(IDs)

E731 E6D7

Boot/

Block 0 S UM (1000:1FFF)+(CONFIG0 & 0000)+(CONFIG1 & 00CF)+

(CONFIG2 & 001F)+(CONFIG3 & 001F)+(CONFIG4 & 000E)+

(CONFIG5 & 0089)+(CONFIG6 & 00F1)+(CONFIG7 & 0000)+

(CONFIG8 & 0003)+(CON FIG9 & 00C0)+(CO NF IG10 & 0003)+

(CONFIG11 & 00E0)+(CONFIG12 & 0003)+(CONFIG13 & 0040)+SUM(IDs)

F352 F2F8

All (CONFIG0 & 0000)+(CONFIG1 & 00CF)+(CONFIG2 & 001F)+

(CONFIG3 & 001F)+(CONFIG4 & 000E)+(CONFIG5 & 0089)+

(CONFIG6 & 00F1)+(CONFIG7 & 0000)+(CONFIG8 & 0003)+

(CONFIG9 & 00C0)+(CO NFIG10 & 0003)+(CO NF IG11 & 00E0) +

(CONFIG12 & 0003)+(CONFIG13 & 0040)+SUM(IDs)

E34B E34B

TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED)

Device Code-Protect Checksum Blank

Value

0xAA at 0

and Max

Address

Legend: Item Description

CFGW = Configuration Word

SUM[a:b] = Sum of locations, a to b inclusive

SUM_ID = Byte-wise sum of lower four bits of all customer ID locations

+ = Addition

& = Bit-wise AND

PIC18F1230/1330

6.0 AC/DC CHAR ACTERISTICS TIMING REQUIREMENTS

FOR PROGRAM/VERIFY TEST MODE

Standard Ope ra ting Condition s

Oper ati ng Tempera tu re : 25°C i s re commended

Param

No. Sym Characteristic Min Max Units Conditions

D110 VIHH High-Voltage Programming Voltage on

MCLR/VPP/RA5/FLTA VDD + 4.0 12.5 V (No te 2)

D110A VIHL Low-Voltage Progra m m i ng Volt age on

MCLR/VPP/RA5/FLTA 2.00 5.50 V (N o te 2)

D111 VDD Suppl y Vol tage During Programmi ng 2.00 5.50 V Ext ernally ti m ed,

row erases and all wri tes

3.00 5.50 V Self-timed,

bulk erases only (Note 3)

D112 IPP Program m in g Cur r ent on M CLR/VPP/RA5/FLTA —300μA(No te 2)

D113 IDDP Supply Current During Programming — 10 mA

D031 VIL Input Low Voltage VSS 0.2 VDD V

D041 VIH Input High Voltage 0.8 VDD VDD V

D080 VOL Output Low Volt age — 0.6 V IOL = 8.5 mA @ 4. 5V

D090 VOH Output High Voltage VDD – 0.7 — V IOH = -3.0 mA @ 4.5V

D012 CIO Capacitive Loading on I/O pin (PGD) — 50 pF To meet AC specifications

P1 TRMCLR/VPP/RA5/FLTA Rise Time to Enter

Program/ Veri fy mode —1.0μs(Notes 1, 2)

P2 TPGC Serial Cl ock (P GC ) P eriod 100 — ns V DD = 5. 0V

1—μsV

DD = 2.0V

P2A TPGCL Serial Clock (PGC ) L ow Time 40 — ns VDD = 5. 0V

400 — ns VDD = 2.0V

P2B TPGCH Serial Clock (PGC ) H igh Time 40 — ns VDD = 5. 0V

400 — ns VDD = 2.0V

P3 TSET1 Input Data Setup Time to Serial Clock ↓15 — ns

P4 THLD1 Input Data Hold Time from PGC ↓ 15 — ns

P5 TDLY1 Delay between 4-bit Command and Command

Operand 40 — ns

P5A TDLY1ADelay between 4-bit Command Operand and Next

4-bit Com m and 40 — ns

P6 TDLY2 Delay between Last PGC ↓ of Command Byte to

First PGC ↑ of Read of Data Word 20 — ns

P9 TDLY5 PGC High Time ( m in imum programmi ng tim e) 1 — ms Exte rn al ly Timed

P10 TDLY6 PGC Low Time after Programming

(high-vo l tage discharge time) 100 — μs

P11 TDLY7 Delay t o al low Sel f -Timed Data Write or

Bulk Erase to Occur 5—ms

Note 1: Do not all ow excess t ime when tr ans i tioning MCLR between VIL and VIHH; this can cause spurious program

executions to occur. The maximum transition time is:

1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/ P LL and XT mode s onl y ) +

2 ms (for HS/PLL mode only) + 1.5 μs (for EC mode only)

where TCY is t he inst ruc tion cycl e time, T PWRT is the Power-up Timer period and TOSC is the oscillator period. For

speci fic val ues, refer to th e Elect r ic al C har acteris tics section of the device data she et for th e parti cular device.

2: This specification also applies to ICVPP for the PIC18F1330- I CD dev ic e.

3: At 0°C-50°C.

PIC18F1230/1330

P11A TDRWT Data W rite Polling Time 4 — ms

P12 THLD2 Input Data Hold Time from MCLR/VPP/RA5/FLTA ↑2—μs

P13 TSET2VDD ↑ Setup Time to MCLR/VPP/RA5/FLTA ↑100 — ns (No te 2)

P14 TVALID Data Out Valid from PGC ↑10 — ns

P15 TSET3PGM ↑ Setup Time to MCLR/VPP/RA5/FLTA ↑2—μs(Note 2 )

P16 TDLY8 Delay between Last PGC ↓ and

MCLR/VPP/RA5/FLTA ↓0—s

P17 THLD3MCLR/VPP/RA5/FLTA ↓ to VDD ↓—100ns

P18 THLD4MCLR/VPP/RA5/FLTA ↓ to PGM ↓0—s

6.0 AC/DC CHA RACTERISTICS TIMING REQUIREMENTS

FOR PROGRAM/VERIFY TEST MODE (CONTINUED)

Standard Ope ra ting Condition s

Oper ati ng Tempera tu re : 25°C i s re commended

Param

No. Sym Characteristic Min Max Units Conditions

Note 1: Do not all ow excess t ime when tr ans i tioning MCLR between VIL and VIHH; this can cause spurious program

executions to occur. The maximum transition time is:

1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/ P LL and XT mode s onl y ) +

2 ms (for HS/PLL mode only) + 1.5 μs (for EC mode only)

where TCY is t he inst ruc tion cycl e time, T PWRT is the Power-up Timer period and TOSC is the oscillator period. For

speci fic val ues, refer to the El ect r ic al C har acteris tics sec tion of the device data she et for th e parti cular device.

2: This specification also applies to ICVPP for the PIC18F1330- I CD dev ic e.

3: At 0°C-50°C.

PIC18F1230/1330

NOTES:

Information contained in this publication regarding device

applications and t he lik e is provid ed only f or your c on ve nience

and may be supersed ed by u pdates. I t is you r r es ponsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, rfPI C, SmartS hunt and UNI/O are registered

trademarks of Microchip Te chnology Incorporat ed in the

U.S.A. and other countries.

FilterLab, Linear Active Thermistor, MXDEV, MXLAB ,

SEEV AL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, In-Circuit Serial

Prog ra m ming , IC SP, IC E P I C , M in d i , MiWi , MPASM, MP L AB

Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,

PICkit, PICDEM, P ICDEM.net, PICtail , PIC32 logo, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select

Mode, Total Endurance, TSHARC, WiperLock and ZENA are

trademarks of Microchip Te chnology Incorporat ed in the

U.S.A. and other countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that i ts family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsP IC® DSCs, KEELOQ® code hoppi ng

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

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