SI5325C-B-GM - Silicon Laboratories, Inc.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Si5325

µP-PROGRAMMABLE PRECISION CLOCK MULTIPLIER

Description

The Si5325 is a low jitter, precision clock multiplier for

applications requiring clock multiplication without jitter

attenuation. The Si5325 accepts dual clock inputs ranging

from 10 to 710 MHz and generates two clock outputs ranging

from 10 to 945 MHz and select frequencies to 1.4 GHz. The

two outputs are divided down separately from a common

source. The device provides virtually any frequency

translation combination across this operating range. The

Si5325 input clock frequency and clock multiplication ratio

are programmable through an I2C or SPI interface. The

Si5325 is based on Silicon Laboratories' 3rd-generation

DSPLL® technology, which provides any-rate frequency

synthesis in a highly integrated PLL solution that eliminates

the need for external VCXO and loop filter components. The

DSPLL loop bandwidth is digitally programmable, providing

jitter performance optimization at the application level.

Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5325

is ideal for providing clock multiplication in high performance

timing applications.

Applications

SONET/SDH OC-48/OC-192 line cards

GbE/10GbE, 1/2/4/8/10GFC line cards

ITU G.709 and custom FEC line cards

Optical modules

Wireless basestations

Data converter clocking

xDSL

SONET/SDH + PDH clock synthesis

Test and measurement

Features

Generates any frequency from 10 to 945 MHz and

select frequencies to 1.4 GHz from an input

frequency of 10 to 710 MHz

Low jitter clock outputs w/jitter generation as low as

0.6 ps rms (30 kHz–1.3 MHz)

Integrated loop filter with selectable loop bandwidth

(150 kHz to 2 MHz)

Dual clock inputs w/manual or automatically

controlled hitless switching

Dual clock outputs with selectable signal format

(LVPECL, LVDS, CML, CMOS)

Support for ITU G.709 and custom FEC ratios

(255/238, 255/237, 255/236)

LOS, FOS alarm outputs

Digitally-controlled output phase adjust

I2C or SPI programmable

On-chip voltage regulator for 1.8, 2.5, or 3.3 V

±10% operation

Small size: 6 x 6 mm 36-lead QFN

Pb-free, ROHS compliant

PRELIMINARY DATA SHEET

DSPLL

CKOUT2

CKIN1

CKOUT1

CKIN2

÷ N31

÷ N2

÷ NC1

÷ NC2

Signal Detect

Device Interrupt

VDD (1.8, 2.5, or 3.3 V)

GND

÷ N32

Clock Select

I2C/SPI Port

Control

Alarms

Si5325

2 Preliminary Rev. 0.26

Table 1. Performance Specifications

(VDD = 1.8, 2.5, or 3.3 V ±10%, TA= –40 to 85 ºC)

Parameter Symbol Test Condition Min Typ Max Unit

Temperature Range TA–40 25 85 ºC

Supply Voltage VDD 2.97 3.3 3.63 V

2.25 2.5 2.75 V

1.62 1.8 1.98 V

Supply Current IDD fOUT = 622.08 MHz

Both CKOUTs enabled

LVPECL format output

— 251 279 mA

CKOUT2 disabled — 217 243 mA

fOUT = 19.44 MHz

Both CKOUTs enabled

CMOS format output

— 204 234 mA

CKOUT2 disabled — 194 220 mA

Tristate/Sleep Mode — TBD TBD mA

Input Clock Frequency

(CKIN1, CKIN2)

CKF Input frequency and clock

multiplication ratio deter-

mined by programming

device PLL dividers. Consult

Silicon Laboratories configu-

ration software DSPLLsim at

www.silabs.com/timing to

determine PLL divider set-

tings for a given input fre-

quency/clock multiplication

ratio combination.

10 — 710 MHz

Output Clock Frequency

(CKOUT1, CKOUT2)

CKOF 10

970

1213

—

945

1134

1417

MHz

Input Clocks (CKIN1, CKIN2)

Differential Voltage Swing CKNDPP 0.25 — 1.9 VPP

Common Mode Voltage CKNVCM 1.8 V ±10% 0.9 — 1.4 V

2.5 V ±10% 1.0 — 1.7 V

3.3 V ±10% 1.1 — 1.95 V

Rise/Fall Time CKNTRF 20–80% — 11 ns

Duty Cycle CKNDC Whichever is less 40 — 60 %

50 — — ns

Output Clocks (CKOUT1, CKOUT2)

Common Mode VOCM LVPECL

100 Ω load

line-to-line

VDD –1.42 — V

DD –1.25 V

Differential Output Swing VOD 1.1 — 1.9 V

Single Ended Output

Swing

VSE 0.5 — 0.93 V

Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision

Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.

Si5325

Preliminary Rev. 0.26 3

Rise/Fall Time CKOTRF 20–80% — 230 350 ps

Duty Cycle CKODC 45 — 55 %

PLL Performance

Jitter Generation JGEN fOUT = 622.08 MHz,

LVPECL output format

50 kHz–80 MHz

— 0.6 TBD ps rms

12 kHz–20 MHz — 0.6 TBD ps rms

800 Hz–80 MHz — TBD TBD ps rms

Jitter Transfer JPK —0.050.1dB

Phase Noise CKOPN fOUT = 622.08 MHz

100 Hz offset

— TBD TBD dBc/Hz

1 kHz offset — TBD TBD dBc/Hz

10 kHz offset — TBD TBD dBc/Hz

100 kHz offset — TBD TBD dBc/Hz

1 MHz offset — TBD TBD dBc/Hz

Subharmonic Noise SPSUBH Phase Noise @ 100 kHz Off-

set

— TBD TBD dBc

Spurious Noise SPSPUR Max spur @ n x F3

(n > 1, n x F3 < 100 MHz)

— TBD TBD dBc

Package

Thermal Resistance

Junction to Ambient

θJA Still Air — 38 — ºC/W

Table 2. Absolute Maximum Ratings

Parameter Symbol Value Unit

DC Supply Voltage VDD –0.5 to 3.6 V

LVCMOS Input Voltage VDIG –0.3 to (VDD + 0.3) V

Operating Junction Temperature TJCT –55 to 150 C

Storage Temperature Range TSTG –55 to 150 C

ESD HBM Tolerance (100 pF, 1.5 kΩ)2kV

ESD MM Tolerance 200 V

Latch-Up Tolerance JESD78 Compliant

Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be

restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum

rating conditions for extended periods of time may affect device reliability.

Table 1. Performance Specifications (Continued)

(VDD = 1.8, 2.5, or 3.3 V ±10%, TA= –40 to 85 ºC)

Parameter Symbol Test Condition Min Typ Max Unit

Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision

Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.

Si5325

4 Preliminary Rev. 0.26

Figure 1. Si5325 Typical Application Circuit (I2C Control Mode)

Figure 2. Si5325 Typical Application Circuit (SPI Control Mode)

Si5325

INT_C1B

C2B

RST

CKOUT1+

CKOUT1–

VDD

GND

Serial Data

Serial Clock

Reset

Interrupt/CKIN_1 Invalid Indicator

CKIN_2 Invalid Indicator

Clock Outputs

CKOUT2+

CKOUT2–

SDA

SCL

I2C Interface

Serial Port AddressA[2:0]

CMODE

Control Mode (L)

CKIN1+

CKIN1–

Input

Clock

Sources*

CKIN2+

CKIN2–

Assumes differential LVPECL termination (3.3 V) on clock inputs.*Note:

Ferrite

Bead

System

Power

Supply

0.1 µF

1 µF

0.1 µF

100 Ω

0.1 µF +

–

0.1 µF

100 Ω

0.1 µF +

–

130 Ω130 Ω

82 Ω82 Ω

VDD = 3.3 V

130 Ω130 Ω

82 Ω82 Ω

VDD = 3.3 V

Si5325 INT_C1B

C2B

SPI Interface

RST

CKOUT1+

CKOUT1–

VDD

GND

Reset

Interrupt/CLKIN_1 Invalid Indicator

CLKIN_2 Invalid Indicator

CKOUT2+

CKOUT2–

Serial Data Out

Serial Data In

SDO

SDI

Serial ClockSCLK

Slave Select

CMODEControl Mode (H)

CKIN1+

CKIN1–

Input

Clock

Sources*

CKIN2+

CKIN2–

Assumes differential LVPECL termination (3.3 V) on clock inputs.

*Note:

Clock Outputs

0.1 µF

100 Ω

0.1 µF +

–

0.1 µF

100 Ω

0.1 µF +

–

Ferrite

Bead

System

Power

Supply

0.1 µF

1 µF

130 Ω130 Ω

82 Ω82 Ω

VDD = 3.3 V

130 Ω130 Ω

82 Ω82 Ω

VDD = 3.3 V

Si5325

Preliminary Rev. 0.26 5

1. Functional Description

The Si5325 is a low jitter, precision clock multiplier for

applications requiring clock multiplication without jitter

attenuation. The Si5325 accepts dual clock inputs

ranging from 10 to 710 MHz and generates two

independent, synchronous clock outputs ranging from

10 to 945 MHz and select frequencies to 1.4 GHz. The

device provides virtually any frequency translation

combination across this operating range. Independent

dividers are available for each input clock and output

clock, so the Si5325 can accept input clocks at different

frequencies and it can generate output clocks at

different frequencies. The Si5325 input clock frequency

and clock multiplication ratio are programmable through

an I2C or SPI interface. Silicon Laboratories offers a

PC-based software utility, DSPLLsim, that can be used

to determine the optimum PLL divider settings for a

given input frequency/clock multiplication ratio

combination that minimizes phase noise and power

consumption. This utility can be downloaded from

www.silabs.com/timing.

The Si5325 is based on Silicon Laboratories' 3rd-

generation DSPLL® technology, which provides any-

rate frequency synthesis in a highly integrated PLL

solution that eliminates the need for external VCXO and

loop filter components. The Si5325 PLL loop bandwidth

is digitally programmable and supports a range from

30 kHz to 1.3 MHz. The DSPLLsim software utility can

be used to calculate valid loop bandwidth settings for a

given input clock frequency/clock multiplication ratio.

In the case when the input clocks enter alarm

conditions, the PLL will freeze the DCO output

frequency near its last value to maintain operation with

an internal state close to the last valid operating state.

The Si5325 has two differential clock outputs. The

electrical format of each clock output is independently

programmable to support LVPECL, LVDS, CML, or

CMOS loads. If not required, the second clock output

can be powered down to minimize power consumption.

The phase difference between the selected input clock

and the output clocks is adjustable in 200 ps increments

for system skew control. In addition, the phase of one

output clock may be adjusted in relation to the phase of

the other output clock. The resolution varies from

800 ps to 2.2 ns depending on the PLL divider settings.

Consult the DSPLLsim configuration software to

determine the phase offset resolution for a given input

clock/clock multiplication ratio combination. For system-

level debugging, a bypass mode is available which

drives the output clock directly from the input clock,

bypassing the internal DSPLL. The device is powered

by a single 1.8, 2.5, or 3.3 V supply.

1.1. Further Documentation

Consult the Silicon Laboratories Any-Rate Precision

Clock Family Reference Manual (FRM) for more

detailed information about the Si5325. The FRM can be

downloaded from www.silabs.com/timing.

Silicon Laboratories has developed a PC-based

software utility called DSPLLsim to simplify device

configuration, including frequency planning and loop

bandwidth selection. This utility can be downloaded

from www.silabs.com/timing.

Si5325

6 Preliminary Rev. 0.26

2. Pin Descriptions: Si5325

Pin numbers are preliminary and subject to change.

2930313233343536

10 11 12 13 14 15 16 17

RST

C2B

INT_C1B

GND

VDD

GND

VDD

CLKIN2+

CLKIN2–

VDD

CLKIN1+

CLKIN1–

CS_CA

SCL

SDA_SDO

A2_SS

SDI

CLKOUT1–

GND

VDD

CLKOUT2–

CLKOUT2+

CMODE

GND

Pad

CLKOUT1+

Table 3. Si5325 Pin Descriptions

Pin # Pin Name I/O Signal Level Description

1RST ILVCMOSExternal Reset.

Active low input that performs external hardware reset of

device. Resets all internal logic to a known state and forces

the device registers to their default value. Clock outputs are

tristated during reset. After rising edge of RST signal, the

Si5325 will perform an internal self-calibration.

This pin has a weak pull-up.

2, 7, 9, 14,

18, 19, 20,

30, 33

NC — — No Connect.

This pin must be left unconnected for normal operation.

3 INT_C1B O LVCMOS Interrupt/CKIN1 Invalid Indicator.

This pin functions as a device interrupt output or an alarm

output for CKIN1. If used as an interrupt output, INT_PIN

must be set to 1. The pin functions as a maskable interrupt

output with active polarity controlled by the INT_POL register

bit.

If used as an alarm output, the pin functions as a LOS (and

optionally FOS) alarm indicator for CKIN1. Set

CK1_BAD_PIN = 1 and INT_PIN =0.

0 = CKIN1 present.

1 = LOS (FOS) on CKIN1.

The active polarity is controlled by CK_BAD_POL. If no func-

tion is selected, the pin tristates.

Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5325 Register Map.

Si5325

Preliminary Rev. 0.26 7

4C2BOLVCMOSCKIN2 Invalid Indicator.

This pin functions as a LOS (and optionally FOS) alarm indi-

cator for CKIN2 if CK2_BAD_PIN =1.

0 = CKIN2 present.

1 = LOS (FOS) on CKIN2.

The active polarity can be changed by CK_BAD_POL. If

CK2_BAD_PIN = 0, the pin tristates.

5, 10, 11,

15, 32

VDD VDD Supply Supply.

The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass

capacitors should be associated with the following Vdd pins:

5 0.1 µF

10 0.1 µF

32 0.1 µF

A 1.0 µF should be placed as close to device as is practical.

6, 8, 31 GND GND Supply Ground.

Must be connected to system ground. Minimize the ground

path impedance for optimal performance of this device.

CKIN2+

CKIN2–

IMultiClock Input 2.

Differential input clock. This input can also be driven with a

single-ended signal. Input frequency range is 10 to 710 MHz.

CKIN1+

CKIN1–

IMultiClock Input 1.

Differential input clock. This input can also be driven with a

single-ended signal. Input frequency range is 10 to 710 MHz.

21 CS_CA I/O LVCMOS Input Clock Select/Active Clock Indicator.

In manual clock selection mode, this pin functions as the

manual input clock selector if the CKSEL_PIN is set to 1.

0 = Select CKIN1.

1 = Select CKIN2.

If CKSEL_PIN =0, the CKSEL_REG register bit controls this

function and this input tristates.

In automatic clock selection mode, this pin indicates which of

the two input clocks is currently the active clock. If alarms

exist on both clocks, CA will indicate the last active clock that

was used before entering the digital hold state. The

CK_ACTV_PIN register bit must be set to 1 to reflect the

active clock status to the CA output pin.

0 = CKIN1 active input clock.

1 = CKIN2 active input clock.

If CK_ACTV_PIN = 0, this pin will tristate. The CA status will

always be reflected in the CK_ACTV_REG read only register

bit.

Table 3. Si5325 Pin Descriptions (Continued)

Pin # Pin Name I/O Signal Level Description

Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5325 Register Map.

Si5325

8 Preliminary Rev. 0.26

22 SCL I LVCMOS Serial Clock/Serial Clock.

This pin functions as the serial clock input for both SPI and

I2C modes.

23 SDA_SDO I/O LVCMOS Serial Data.

In I2C control mode (CMODE = 0), this pin functions as the

bidirectional serial data port.

In SPI control mode (CMODE = 1), this pin functions as the

serial data output.

ILVCMOSSerial Port Address.

In I2C control mode (CMODE = 0), these pins function as

hardware controlled address bits.

In SPI control mode (CMODE = 1), these pins are ignored.

26 A2_SSILVCMOSSerial Port Address/Slave Select.

In I2C control mode (CMODE = 0), this pin functions as a

hardware controlled address bit.

In SPI control mode (CMODE = 1), this pin functions as the

slave select input.

27 SDI I LVCMOS Serial Data In.

In I2C control mode (CMODE = 0), this pin is ignored.

In SPI control mode (CMODE = 1), this pin functions as the

serial data input.

CKOUT1–

CKOUT1+

OMultiOutput Clock 1.

Differential output clock with a frequency range of 10 MHz to

1.4175 GHz. Output signal format is selected by

SFOUT1_REG register bits. Output is differential for

LVPECL, LVDS, and CML compatible modes. For CMOS for-

mat, both output pins drive identical single-ended clock out-

puts.

CKOUT2–

CKOUT2+

OMultiOutput Clock 2.

Differential output clock with a frequency range of 10 MHz to

1.4175 GHz. Output signal format is selected by

SFOUT2_REG register bits. Output is differential for

LVPECL, LVDS, and CML compatible modes. For CMOS for-

mat, both output pins drive identical single-ended clock out-

puts.

36 CMODE I LVCMOS Control Mode.

Selects I2C or SPI control mode for the Si5325.

0 = I2C Control Mode.

1 = SPI Control Mode.

GND PAD GND GND Supply Ground Pad.

The ground pad must provide a low thermal and electrical

impedance to a ground plane.

Table 3. Si5325 Pin Descriptions (Continued)

Pin # Pin Name I/O Signal Level Description

Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5325 Register Map.

Si5325

Preliminary Rev. 0.26 9

3. Ordering Guide

Ordering Part

Number

Output Clock Frequency

Range

Package Temperature Range

Si5325A-B-GM 10–945 MHz

970–1134 MHz

1.213–1.417 GHz

36-Lead 6 x 6 mm QFN –40 to 85 °C

Si5325B-B-GM 10–808 MHz 36-Lead 6 x 6 mm QFN –40 to 85 °C

Si5325C-B-GM 10–346 MHz 36-Lead 6 x 6 mm QFN –40 to 85 °C

Si5325

10 Preliminary Rev. 0.26

4. Package Outline: 36-Pin QFN

Figure 3 illustrates the package details for the Si5325. Table 4 lists the values for the dimensions shown in the

illustration.

Figure 3. 36-Pin Quad Flat No-lead (QFN)

Table 4. Package Dimensions

Symbol Millimeters Symbol Millimeters

Min Nom Max Min Nom Max

A 0.80 0.85 0.90 L 0.50 0.60 0.75

A1 0.00 0.01 0.05 θ——12º

b 0.18 0.23 0.30 aaa — — 0.10

D 6.00 BSC bbb — — 0.10

D2 3.95 4.10 4.25 ccc — — 0.05

e 0.50 BSC ddd — — 0.10

E 6.00 BSC eee — — 0.05

E2 3.95 4.10 4.25

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to JEDEC outline MO-220, variation VJJD.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body

Components.

Si5325

Preliminary Rev. 0.26 11

5. Recommended PCB Layout

Figure 4. PCB Land Pattern Diagram

Si5325

12 Preliminary Rev. 0.26

Table 5. PCB Land Pattern Dimensions

Dimension MIN MAX

e 0.50 BSC.

E5.42 REF.

D5.42 REF.

E2 4.00 4.20

D2 4.00 4.20

GE 4.53 —

GD 4.53 —

X — 0.28

Y0.89 REF.

ZE — 6.31

ZD — 6.31

Notes (General):

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.

3. This Land Pattern Design is based on IPC-SM-782 guidelines.

4. All dimensions shown are at Maximum Material Condition (MMC). Least Material

Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.

Notes (Solder Mask Design):

1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the

solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.

Notes (Stencil Design):

1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be

used to assure good solder paste release.

2. The stencil thickness should be 0.125 mm (5 mils).

3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.

4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the

center ground pad.

Notes (Card Assembly):

1. A No-Clean, Type-3 solder paste is recommended.

2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification

for Small Body Components.

Si5325

Preliminary Rev. 0.26 13

DOCUMENT CHANGE LIST

Revision 0.23 to Revision 0.24

Clarified that the two outputs have a common, higher

frequency source on page 1.

Changed LVTTL to LVCMOS in Table 2, “Absolute

Maximum Ratings,” on page 3.

Added Figure 1, “Typical Phase Noise Plot,” on page

Updated “2. Pin Descriptions: Si5325”.

 Removed references to latency control, INC, and DEC.

 Changed font for register names to underlined italics.

Updated "3. Ordering Guide" on page 9.

Added “5. Recommended PCB Layout”.

Revision 0.24 to Revision 0.25

Updated Section "2. Pin Descriptions: Si5325" on

page 6.

Revision 0.25 to Revision 0.26

Removed Figure 1. “Typical Phase Noise Plot.”

Changed pins 11 and 15 from NC to VDD in “2. Pin

Descriptions: Si5325”.

Si5325

14 Preliminary Rev. 0.26

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Email: Clockinfo@silabs.com

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