Revised April 2002 CD4071BC * CD4081BC Quad 2-Input OR Buffered B Series Gate * Quad 2-Input AND Buffered B Series Gate General Description Features The CD4071BC and CD4081BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outputs which improve transfer characteristics by providing very high gain. Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS 5V-10V-15V parametric ratings Symmetrical output characteristics Maximum input leakage 1 A at 15V over full temperature range All inputs protected against static discharge with diodes to VDD and VSS. Ordering Code: Order Number CD4071BCM Package Number M14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4071BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide CD4081BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4081BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices are also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Connection Diagrams CD4071B CD4081B Top View Top View (c) 2002 Fairchild Semiconductor Corporation DS005977 www.fairchildsemi.com CD4071BC * CD4081BC Quad 2-Input OR Buffered B Series Gate * Quad 2-Input AND Buffered B Series Gate October 1987 CD4071BC * CD4081BC Schematic Diagrams CD4071B 1 /4 of device shown J=A+B Logical "1" = HIGH Logical "0" = LOW *All inputs protected by standard CMOS protection circuit. CD4081B 1 /4 of device shown J=A*B Logical "1" = HIGH Logical "0" = LOW All inputs protected by standard CMOS protection circuit. www.fairchildsemi.com 2 Recommended Operating Conditions (Note 2) -0.5V to VDD +0.5V Voltage at Any Pin Operating Range (VDD) Power Dissipation (PD) 3 VDC to 15 VDC Operating Temperature Range (TA) Dual-In-Line 700 mW Small Outline 500 mW -0.5 VDC to +18 VDC VDD Range -65C to +150C Storage Temperature (TS) Lead Temperature (TL) Note 2: All voltages measured with respect to VSS unless otherwise specified. 260C (Soldering, 10 seconds) DC Electrical Characteristics -55C to +125C CD4071BC, CD4081BC Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation. (Note 2) CD4071BC/CD4081BC Symbol IDD VOL Parameter -55C Conditions Min VIH IOL IOH IIN +125C Typ Max Min VDD = 5V 0.25 0.004 0.25 7.5 VDD = 10V 0.5 0.005 0.5 15 VDD = 15V 1.0 0.006 1.0 30 0.05 0 0.05 0.05 0.05 0 0.05 0.05 0.05 0 0.05 0.05 LOW Level VDD = 5V Output Voltage VDD = 10V |IO| < 1 A HIGH Level VDD = 5V Output Voltage VDD = 10V |IO| < 1 A 4.95 4.95 5 9.95 9.95 10 9.95 14.95 14.95 15 14.95 Units Max Quiescent Device VDD = 15V VIL +25C Min Current VDD = 15V VOH Max A V 4.95 V LOW Level VDD = 5V, VO = 0.5V 1.5 2 1.5 1.5 Input Voltage VDD = 10V, VO = 1.0V 3.0 4 3.0 3.0 VDD = 15V, VO = 1.5V 4.0 6 4.0 4.0 V HIGH Level VDD = 5V, VO = 4.5V 3.5 3.5 3 Input Voltage VDD = 10V, VO = 9.0V 7.0 7.0 6 7.0 VDD = 15V, VO = 13.5V 11.0 11.0 9 11.0 LOW Level Output VDD = 5V, VO = 0.4V 0.64 0.51 0.88 0.36 Current VDD = 10V, VO = 0.5V 1.6 1.3 2.25 0.9 (Note 3) VDD = 15V, VO = 1.5V 4.2 3.4 8.8 2.4 HIGH Level Output VDD = 5V, VO = 4.6V -0.64 -0.51 -0.88 -0.36 Current VDD = 10V, VO = 9.5V -1.6 -1.3 -2.25 -0.9 (Note 3) VDD = 15V, VO = 13.5V -4.2 -3.4 -8.8 -2.4 Input Current VDD = 15V, VIN = 0V -0.1 -10-5 -0.1 -1.0 VDD = 15V, VIN = 15V 0.1 10-5 0.1 1.0 3.5 V mA mA A Note 3: IOH and IOL are tested one output at a time. AC Electrical Characteristics (Note 4) CD4071BC TA = 25C, Input tr; tf = 20 ns, CL = 50 pF, RL = 200 k, Typical temperature coefficient is 0.3%/C Symbol tPHL Parameter Propagation Delay Time, HIGH-to-LOW Level tPLH tTHL, tTLH Conditions Typ Max 100 250 VDD = 10V 40 100 VDD = 15V 30 70 VDD = 5V Propagation Delay Time, VDD = 5V 90 250 LOW-to-HIGH Level VDD = 10V 40 100 VDD = 15V 30 70 Transition Time VDD = 5V 90 200 VDD = 10V 50 100 VDD = 15V 40 80 7.5 CIN Average Input Capacitance Any Input 5 CPD Power Dissipation Capacity Any Gate 18 Units ns ns ns pF pF Note 4: AC Parameters are guaranteed by DC correlated testing. 3 www.fairchildsemi.com CD4071BC * CD4081BC Absolute Maximum Ratings(Note 1) CD4071BC * CD4081BC AC Electrical Characteristics (Note 5) CD4081BC TA = 25C, Input tr; tf = 20 ns, CL = 50 pF, RL = 200 k, Typical temperature coefficient is 0.3%/C Symbol tPHL Parameter Propagation Delay Time, tTHL, tTLH Conditions Max 100 250 VDD = 10V 40 100 VDD = 15V 30 70 Propagation Delay Time, VDD = 5V 120 250 LOW-to-HIGH Level VDD = 10V 50 100 VDD = 15V 35 70 HIGH-to-LOW Level tPLH Typ VDD = 5V Transition Time VDD = 5V 90 200 VDD = 10V 50 100 VDD = 15V 40 80 7.5 CIN Average Input Capacitance Any Input 5 CPD Power Dissipation Capacity Any Gate 18 Note 5: AC Parameters are guaranteed by DC correlated testing. Typical Performance Characteristics Typical Transfer Characteristics Typical Transfer Characteristics Typical Transfer Characteristics Typical Transfer Characteristics www.fairchildsemi.com 4 Units ns ns ns pF pF CD4071BC * CD4081BC Typical Performance Characteristics (Continued) 5 www.fairchildsemi.com CD4071BC * CD4081BC Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A www.fairchildsemi.com 6 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com CD4071BC * CD4081BC Quad 2-Input OR Buffered B Series Gate * Quad 2-Input AND Buffered B Series Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued)