FullFlex FullFlexTM Synchronous SDR Dual-Port SRAM Features * True dual-ported memory allows simultaneous access to the shared array from each port * Synchronous pipelined operation with Single Data Rate (SDR) operation on each port -- SDR interface at 250 MHz -- Up to 36-Gb/s bandwidth (250 MHz * 72 bit * 2 ports) * Selectable pipelined or flow-through mode * 1.5V or 1.8V core power supply * Commercial and Industrial temperature * IEEE 1149.1 JTAG boundary scan * Available in 484-ball PBGA Packages and 256-ball FBGA packages * FullFlex72 family -- 36-Mbit: 512K x 72 (CYD36S72V18) -- Burst counters for sequential memory access -- Mailbox with interrupt flags for message passing -- Dual Chip Enables for easy depth expansion Functional Description The FullFlexTM Dual-Port SRAM families consist of 4-Mbit, 9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual-port static RAMs that are high-speed, low-power 1.8V/1.5V CMOS. Two ports are provided, allowing the array to be accessed simultaneously. Simultaneous access to a location triggers deterministic access control. For FullFlex72 these ports can operate independently with 72-bit bus widths and each port can be independently configured for two pipelined stages. Each port can also be configured to operate in pipelined or flow-through mode. Advanced features include built-in deterministic access control to manage address collisions during simultaneous access to the same memory location, Variable Impedance Matching (VIM) to improve data transmission by matching the output driver impedance to the line impedance, and echo clocks to improve data transfer. -- 18-Mbit: 256K x 72 (CYD18S72V18) -- 9-Mbit: 128K x 72 (CYD09S72V18) -- 4-Mbit: 64K x 72 (CYD04S72V18) * FullFlex36 family -- 36-Mbit: 1M x 36 (CYD36S36V18) To reduce the static power consumption, chip enables can be used to power down the internal circuitry. The number of cycles of latency before a change in CE0 or CE1 will enable or disable the databus matches the number of cycles of read latency selected for the device. In order for a valid write or read to occur, both chip enable inputs on a port must be active. -- 18-Mbit: 512K x 36 (CYD18S36V18) -- 9-Mbit: 256K x 36 (CYD09S36V18) -- 4-Mbit: 128K x 36 (CYD04S36V18) * FullFlex18 family -- 36-Mbit: 2M x 18 (CYD36S18V18) Each port contains an optional burst counter on the input address register. After externally loading the counter with the initial address, the counter will increment the address internally. -- 18-Mbit: 1M x 18 (CYD18S18V18) -- 9-Mbit: 512K x 18 (CYD09S18V18) -- 4-Mbit: 256K x 18 (CYD04S18V18) * Built-in deterministic access control to manage address collisions -- Deterministic flag output upon collision detection -- Collision detection on back-to-back clock cycles -- First Busy Address readback * Advanced features for improved high-speed data transfer and flexibility -- Variable Impedance Matching (VIM) -- Echo clocks Cypress Semiconductor Corporation Document #: 38-06082 Rev. *G -- Selectable LVTTL (3.3V), Extended HSTL (1.4V-1.9V), 1.8V LVCMOS, or 2.5V LVCMOS I/O on each port Additional features of this device include a mask register and a mirror register to control counter increments and wrap-around. The counter-interrupt (CNTINT) flags notify the host that the counter will reach maximum count value on the next clock cycle. The host can read the burst-counter internal address, mask register address, and busy address on the address lines. The host can also load the counter with the address stored in the mirror register by utilizing the retransmit functionality. Mailbox interrupt flags can be used for message passing, and JTAG boundary scan and asynchronous Master Reset (MRST) are also available. The logic block diagram in Figure 1 displays these features. The FullFlex72 is offered in a 484-ball plastic BGA package. The FullFlex36 and FullFlex18 are offered in both 484-ball and 256-ball fine pitch BGA packages. * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised December 21, 2006 FullFlex FTSELL FTSELR CQENL CONFIG Block PORTSTD[1:0]L CONFIG Block CQENR PORTSTD[1:0]R DQ[71:0]L BE [7:0]L CE0L CE1L OEL IO Control IO Control DQ [71:0]R BE [7:0]R CE0R CE1R OER R/WR R/WL CQ1L CQ1L CQ0L CQ0L CQ1R CQ1R CQ0R CQ0R Dual Ported Array BUSYL A [20:0]L CNT/MSKL ADSL CNTENL CNTRSTL RETL CNTINTL CL Collision Detection Logic Address & Counter Logic BUSYR Address & Counter Logic WRPL A [20:0]R CNT/MSKR ADSR CNTENR CNTRSTR RETR CNTINTR CR WRPR Mailboxes INTL INTR ZQ0L ZQ1L READYL LowSPDL JTAG RESET LOGIC TRST TMS TDI TDO TCK ZQ0R ZQ1R MRST READYR LowSPDR Figure 1. FullFlex72 18-Mbit (CYD18S72V18) Block Diagram[1, 2, 3] Notes: 1. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and the CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and the CYD09S18V18 devices have 19 address bits. The CYD18S72V18, CYD09S36V18, and the CYD04S18V18 devices have 18 address bits. The CYD09S72V18 and the CYD04S36V18 devices have 17 address bits. The CYD04S72V18 has 16 address bits. 2. The FullFlex72 family of devices has 72 data lines. The FullFlex36 family of devices has 36 data lines. The FullFlex18 family of devices has 18 data lines. 3. The FullFlex72 family of devices has eight byte enables. The FullFlex36 family of devices has four byte enables. The FullFlex18 family of devices has two byte enables. Document #: 38-06082 Rev. *G Page 2 of 51 FullFlex FullFlex72 SDR 484-ball BGA Pinout (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A DNU DQ61 DQ59 DQ57 DQ54 DQ51 DQ48 DQ45 DQ42 DQ39 DQ36 DQ36 DQ39 DQ42 DQ45 DQ48 DQ51 DQ54 DQ57 DQ59 DQ61 DNU L L L L L L L L L L R R R R R R R R R R B DQ63 DQ62 DQ60 DQ58 DQ55 DQ52 DQ49 DQ46 DQ43 DQ40 DQ37 DQ37 DQ40 DQ43 DQ46 DQ49 DQ52 DQ55 DQ58 DQ60 DQ62 DQ63 L L L L L L L L L L L R R R R R R R R R R R C DQ65 DQ64 VSS L L VSS DQ56 DQ53 DQ50 DQ47 DQ44 DQ41 DQ38 DQ38 DQ41 DQ44 DQ47 DQ50 DQ53 DQ56 VSS L L L L L L L R R R R R R R DQ67 DQ66 VSS L L VSS D VSS CQ1L CQ1L VSS LOW PORT ZQ0L BUSY CNTI PORT DNU CQ1R CQ1R VSS SPDL STD0 [4] L NTL STD1 L L VSS VDDI VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI DNU OL OL OL OL OL OR OR OR OR VSS VSS DQ64 DQ65 R R VSS DQ66 DQ67 R R E DQ69 DQ68 VDDI VSS L L OL VSS VDDI DQ68 DQ69 OR R R F DQ71 DQ70 CE1L CE0L VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CE0R CE1R DQ70 DQ71 L L OL OL OL OL OL RE RE RE RE OR OR OR OR OR R R A0L A1L RETL BE4L VDDI VDDI VREF VSS OL OL L VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI BE4R RETR A1R R OR OR A0R A2L A3L WRP BE5L VDDI VDDI VSS OL OL L VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE5R WRP OR OR R A3R A2R A4L A5L READ BE6L VDDI VDDI VSS YL OL OL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE6R READ A5R OR OR YR A4R A6L A7L VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VDDI BE7R ZQ1R A7R [4] RE OR A6R A8L A9L OEL VTTL VCO RE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL OER RE A8R VSS BE3L VTTL VCO RE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL BE3R VSS A11R A10R RE A12L A13L ADSL BE2L VDDI VCO OL RE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL BE2R ADSR A13R A12R RE A14L A15L CNT/ BE1L VDDI VDDI VSS MSKL OL OL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE1R CNT/ A15R A14R OR OR MSK R R A16L A17L CNTE BE0L VDDI VDDI VSS [7] [6] OL OL NL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE0R CNTE A17R A16R [6] [7] OR OR NR T A18L DNU CNTR INTL VDDI VDDI VREF VSS [5] STL OL OL L VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI INTR CNTR DNU A18R [5] R OR OR STR U DQ35 DQ34 R/WL CQE VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CQE R/WR DQ34 DQ35 L L NL OL OL OL OL OL RE RE RE RE OR OR OR OR OR NR R R V DQ33 DQ32 FTSE VDDI DNU VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI VDDI TRST VDDI FTSE DQ32 DQ33 L L OL OL OL OL OL OR OR OR OR OR OR R R LL LR W DQ31 DQ30 VSS MRST VSS CQ0L CQ0L DNU PORT CNTI BUSY ZQ0R PORT LOW VSS CQ0R CQ0R VSS [4] L L STD1 NTR STD0 SPDR R R R Y DQ29 DQ28 VSS L L G H J K L M N P A10L A11L ZQ1L BE7L VTTL VCO [4] RE CL CR A9R TDI TDO DQ30 DQ31 R R VSS DQ20 DQ17 DQ14 DQ11 DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R DQ11 DQ14 DQ17 DQ20 TMS L L L L R R R R TCK DQ28 DQ29 R R AA DQ27 DQ26 DQ24 DQ22 DQ19 DQ16 DQ13 DQ10 DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R DQ10 DQ13 DQ16 DQ19 DQ22 DQ24 DQ26 DQ27 L L L L L L L L R R R R R R R R AB DNU DQ25 DQ23 DQ21 DQ18 DQ15 DQ12 DQ9L DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R DQ9R DQ12 DQ15 DQ18 DQ21 DQ23 DQ25 DNU L L L L L L R R R R R R Notes: 4. Leaving this pin DNU disables VIM. 5. Leave this ball unconnected for CYD18S72V18, CYD09S72V18 and CYD04S72V18. 6. Leave this ball unconnected for CYD09S72V18 and CYD04S72V18. 7. Leave this ball unconnected for CYD04S72V18. Document #: 38-06082 Rev. *G Page 3 of 51 FullFlex FullFlex36 SDR 484-ball BGA Pinout (Top View)[8] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A DNU DNU DNU DNU DNU DQ33 DQ30 DQ27 DQ24 DQ21 DQ18 DQ18 DQ21 DQ24 DQ27 DQ30 DQ33 DNU DNU DNU DNU DNU L L L L L L R R R R R R B DNU DNU DNU DNU DNU DQ34 DQ31 DQ28 DQ25 DQ22 DQ19 DQ19 DQ22 DQ25 DQ28 DQ31 DQ34 DNU DNU DNU DNU DNU L L L L L L R R R R R R C DNU DNU VSS VSS DNU DQ35 DQ32 DQ29 DQ26 DQ23 DQ20 DQ20 DQ23 DQ26 DQ29 DQ32 DQ35 DNU L L L L L L R R R R R R VSS VSS DNU DNU DNU DNU VSS VSS VSS CQ1L CQ1L VSS VSS VSS DNU DNU D LOW PORT ZQ0L BUSY CNTI PORT DNU CQ1R CQ1R VSS SPDL STD0 [4] L NTL STD1 L L E DNU DNU VDDI VSS OL F DNU DNU CE1L CE0L VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CE0R CE1R DNU DNU OL OL OR OR OR RE RE RE RE OL OL OL OR OR G H J K VSS VDDI VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI DNU OL OR OR OR OR OL OL OL OL VSS VDDI DNU DNU OR A0L A1L RETL BE2L VDDI VDDI VREF VSS OL OL L VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI BE2R RETR A1R R OR OR A0R A2L A3L WRP BE3L VDDI VDDI VSS OL OL L VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE3R WRP OR OR R A3R A2R A4L A5L READ DNU VDDI VDDI VSS YL OL OL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI DNU READ A5R OR OR YR A4R A6L A7L VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VDDI DNU ZQ1R A7R [4] RE OR A6R A8L A9L A8R ZQ1L DNU VTTL VCO [4] RE CL OEL VTTL VCO RE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL OER RE CR VSS DNU VTTL VCO RE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL DNU RE VSS A11R A10R A12L A13L ADSL DNU VDDI VCO OL RE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL DNU ADSR A13R A12R RE A14L A15L CNT/ BE1L VDDI VDDI VSS MSKL OL OL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE1R CNT/ A15R A14R OR OR MSK R R A16L A17L CNTE BE0L VDDI VDDI VSS OL OL NL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE0R CNTE A17R A16R OR OR NR T A18L A19L CNTR INTL VDDI VDDI VREF VSS STL OL OL L VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI INTR CNTR A19R A18R R OR OR STR U DNU DNU R/WL CQE VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CQE R/WR DNU DNU NL OL OL OR OR OR RE RE RE RE OL OL OL OR OR NR V DNU DNU FTSE VDDI DNU VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI VDDI TRST VDDI FTSE DNU DNU OL OR OR OR OR OL OL OL OL OR OR LL LR L M N P A10L A11L DNU DNU VSS MRST VSS CQ0L CQ0L DNU PORT CNTI BUSY ZQ0R PORT LOW VSS CQ0R CQ0R VSS [4] STD1 NTR STD0 SPDR R R R TDI TDO DNU DNU DNU DNU VSS TMS TCK DNU DNU W Y A9R VSS DNU DQ17 DQ14 DQ11 DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R DQ11 DQ14 DQ17 DNU L L L R R R AA DNU DNU DNU DNU DNU DQ16 DQ13 DQ10 DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R DQ10 DQ13 DQ16 DNU DNU DNU DNU DNU L L L R R R AB DNU DNU DNU DNU DNU DQ15 DQ12 DQ9L DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R DQ9R DQ12 DQ15 DNU DNU DNU DNU DNU L L R R Note: 8. Use this pinout only for device CYD36S36V18 of the FullFlex36 family. Document #: 38-06082 Rev. *G Page 4 of 51 FullFlex FullFlex18 SDR 484-ball BGA Pinout (Top View)[9] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A DNU DNU DNU DNU DNU DNU DNU DNU DQ15 DQ12 DQ9L DQ9R DQ12 DQ15 DNU DNU DNU DNU DNU DNU DNU DNU L L R R B DNU DNU DNU DNU DNU DNU DNU DNU DQ16 DQ13 DQ10 DQ10 DQ13 DQ16 DNU DNU DNU DNU DNU DNU DNU DNU L L L R R R C DNU DNU VSS VSS DNU DNU DNU DNU DQ17 DQ14 DQ11 DQ11 DQ14 DQ17 DNU DNU DNU DNU L L L R R R VSS VSS DNU DNU DNU DNU VSS VSS VSS CQ1L CQ1L VSS VSS VSS DNU DNU D LOW PORT ZQ0L BUSY CNTI PORT DNU CQ1R CQ1R VSS SPDL STD0 [4] L NTL STD1 L L E DNU DNU VDDI VSS OL F DNU DNU CE1L CE0L VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CE0R CE1R DNU DNU OL OL OR OR OR RE RE RE RE OL OL OL OR OR G H J K VSS VDDI VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI DNU OL OR OR OR OR OL OL OL OL VSS VDDI DNU DNU OR A0L A1L RETL BE1L VDDI VDDI VREF VSS OL OL L VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI BE1R RETR A1R R OR OR A0R A2L A3L WRP DNU VDDI VDDI VSS L OL OL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI DNU WRP OR OR R A3R A2R A4L A5L READ DNU VDDI VDDI VSS OL OL YL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI DNU READ A5R OR OR YR A4R A6L A7L VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VDDI DNU ZQ1R A7R [4] RE OR A6R A8L A9L A8R ZQ1L DNU VTTL VCO [4] RE CL OEL VTTL VCO RE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL OER RE CR VSS DNU VTTL VCO RE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL DNU RE VSS A11R A10R A12L A13L ADSL DNU VDDI VCO OL RE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCO VTTL DNU ADSR A13R A12R RE A14L A15L CNT/ DNU VDDI VDDI VSS MSKL OL OL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI DNU CNT/ A15R A14R OR OR MSK R R A16L A17L CNTE BE0L VDDI VDDI VSS NL OL OL VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDI VDDI BE0R CNTE A17R A16R OR OR NR T A18L A19L CNTR INTL VDDI VDDI VREF VSS OL OL L STL VSS VSS VSS VSS VSS VSS VSS VREF VDDI VDDI INTR CNTR A19R A18R R OR OR STR U A20L DNU R/WL CQE VDDI VDDI VDDI VDDI VDDI VCO VCO VCO VCO VDDI VDDI VDDI VDDI VDDI CQE R/WR DNU A20R NL OL OL OR OR OR RE RE RE RE OL OL OL OR OR NR V DNU DNU FTSE VDDI DNU VDDI VDDI VDDI VDDI VTTL VTTL VTTL VDDI VDDI VDDI VDDI VDDI TRST VDDI FTSE DNU DNU OL OR OR OR OR OL OL OL OL OR OR LL LR L M N P A10L A11L DNU DNU VSS MRST VSS CQ0L CQ0L DNU PORT CNTI BUSY ZQ0R PORT LOW VSS CQ0R CQ0R VSS [4] STD1 NTR STD0 SPDR R R R TDI TDO DNU DNU DNU DNU VSS TMS TCK DNU DNU W Y A9R VSS DNU DNU DNU DNU DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R DNU DNU DNU DNU AA DNU DNU DNU DNU DNU DNU DNU DNU DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R DNU DNU DNU DNU DNU DNU DNU DNU AB DNU DNU DNU DNU DNU DNU DNU DNU DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R DNU DNU DNU DNU DNU DNU DNU DNU Note: 9. Use this pinout only for device CYD36S18V18 of the FullFlex18 family. Document #: 38-06082 Rev. *G Page 5 of 51 FullFlex FullFlex36 SDR 256-Ball BGA (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A DQ32L DQ30L DQ28L DQ26L DQ24L DQ22L DQ20L DQ18L DQ18R DQ20R DQ22R DQ24R DQ26R DQ28R DQ30R DQ32R B DQ33L DQ31L DQ29L DQ27L DQ25L DQ23L DQ21L DQ19L DQ19R DQ21R DQ23R DQ25R DQ27R DQ29R DQ31R DQ33R C DQ34L DQ35L RETL INTL CQ1L CQ1L DNU TRST MRST ZQ0R[4] CQ1R CQ1R INTR RETR DQ35R DQ34R D A0L A1L WRPL VSS VTTL VTTL VSS E A2L A3L CE0L CE1L VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR F A4L A5L CNTINTL BE3L VDDIOL VSS VSS VSS VSS VSS VSS G A6L A7L BUSYL BE2L ZQ0L[4] VSS VSS VSS VSS VSS H A8L A9L CL VTTL VCORE VSS VSS VSS VSS J A10L A11L VSS PORTST VCORE D1L VSS VSS VSS K A12L A13L OEL BE1L VDDIOL VSS VSS L A14L A15L ADSL BE0L VDDIOL VSS VSS M A16L A17L[11] R/WL N A18L[10] DNU CNT/MS KL P DQ16L DQ17L CNTENL CNTRST L CQ0L CQ0L R DQ15L DQ13L DQ11L DQ9L DQ7L T DQ14L DQ12L DQ10L DQ8L DQ6L VREFL FTSELL LOWSP DL LOWSP FTSELR VREFR DR 16 WRPR A1R A0R CE1R CE0R A3R A2R VDDIOR BE3R CNTINTR A5R A4R VSS VDDIOR BE2R BUSYR A7R A6R VSS VSS VCORE VTTL CR A9R A8R VSS VSS VSS VCORE PORTST D1R VSS A11R A10R VSS VSS VSS VSS VDDIOR BE1R OER A13R A12R VSS VSS VSS VSS VDDIOR BE0R ADSR A15R A14R R/WR A17R[11] A16R DNU A18R[10] CQENL VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CQENR VREFL PORTST READYL ZQ1L[4] D0L 15 ZQ1R[4] READY PORTST VREFR CNT/MS R D0R KR VTTL VTTL TCK TMS TDO TDI CQ0R CQ0R DQ5L DQ3L DQ1L DQ1R DQ3R DQ5R DQ7R DQ9R DQ11R DQ13R DQ15R DQ4L DQ2L DQ0L DQ0R DQ2R DQ4R DQ6R DQ8R DQ10R DQ12R DQ14R CNTRST CNTENR DQ17R DQ16R R Notes: 10. Leave this ball unconnected for CYD09S36V18 and CYD04S36V18. 11. Leave this ball unconnected for CYD04S36V18. Document #: 38-06082 Rev. *G Page 6 of 51 FullFlex FullFlex18 SDR 256-Ball BGA (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A DNU DNU DNU DQ17L DQ16L DQ13L DQ12L DQ9L DQ9R DQ12R DQ13R DQ16R DQ17R DNU DNU DNU B DNU DNU DNU DNU DQ15L DQ14L DQ11L DQ10L DQ10R DQ11R DQ14R DQ15R DNU DNU DNU DNU C DNU DNU RETL INTL CQ1L CQ1L DNU TRST MRST ZQ0R[4] CQ1R CQ1R INTR RETR DNU DNU D A0L A1L WRPL VSS VTTL VTTL VSS WRPR A1R A0R E A2L A3L CE0L CE1L VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CE1R CE0R A3R A2R F A4L A5L CNTINTL DNU VDDIOL VSS VSS VSS VSS VSS VSS VDDIOR DNU CNTINTR A5R A4R G A6L A7L BUSYL DNU ZQ0L[4] VSS VSS VSS VSS VSS VSS VDDIOR DNU BUSYR A7R A6R H A8L A9L CL VTTL VCORE VSS VSS VSS VSS VSS VSS VCORE VTTL CR A9R A8R J A10L A11L VSS PORTST VCORE D1L VSS VSS VSS VSS VSS VSS VCORE PORTST D1R VSS A11R A10R K A12L A13L OEL BE1L VDDIOL VSS VSS VSS VSS VSS VSS VDDIOR BE1R OER A13R A12R L A14L A15L ADSL BE0L VDDIOL VSS VSS VSS VSS VSS VSS VDDIOR BE0R ADSR A15R A14R M A16L A17L R/WL R/WR A17R A16R N VREFL FTSELL LOWSP DL CQENL VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CQENR A18L[13] A19L[12] CNT/MS VREFL PORTST READYL ZQ1L[4] KL D0L P DNU DNU R DNU DNU DNU T DNU DNU DNU LOWSP FTSELR VREFR DR CNTENL CNTRST L VTTL VTTL ZQ1R[4] READY PORTST VREFR CNT/MS A19R[12] A18R[13] R D0R KR CQ0L CQ0L TCK TMS TDO TDI CQ0R CQ0R CNTRST CNTENR R DNU DQ6L DQ5L DQ2L DQ1L DQ1R DQ2R DQ5R DQ6R DNU DQ8L DQ7L DQ4L DQ3L DQ0L DQ0R DQ3R DQ4R DQ7R DQ8R DNU DNU DNU DNU DNU DNU DNU DNU Notes: 12. Leave this ball unconnected for CYD09S18V18 and CYD04S18V18. 13. Leave this ball unconnected for CYD04S18V18. Document #: 38-06082 Rev. *G Page 7 of 51 FullFlex Table 1. Selection Guide fMAX[15] Max. Access Time (Clock to Data) -250 -200 -167 Unit 250 200 167 MHz 2.64 3.3 4.0 ns Typical Operating Current ICC 930[14] 800[14] 700[14] mA Typical Standby Current for ISB3 (Both Ports CMOS Level) 210[14] 210[14] 210[14] mA Pin Definitions Left Port Right Port Description [1] A[20:0]L A[20:0]R Address Inputs. DQ[71:0]L DQ[71:0]R Data Bus Input/Output.[2] BE[7:0]L BE[7:0]R Byte Select Inputs.[3] Asserting these signals enables Read and Write operations to the corresponding bytes of the memory array. BUSYL BUSYR Port Busy Output. When there is an address match and both chip enables are active for both ports, an external BUSY signal is asserted on the fifth clock cycles from when the collision occurs. CL CR Clock Signal. Maximum clock input rate is fMAX. CE0L CE0R Active LOW Chip Enable Input. CE1L CE1R Active HIGH Chip Enable Input. CQENL CQENR Echo Clock Enable Input. Assert HIGH to enable echo clocking on respective port. CQ0L CQ0R Echo Clock Signal Output for DQ[35:0] for FullFlex72 devices. Echo Clock Signal Output for DQ[17:0] for FullFlex36 devices. Echo Clock Signal Output for DQ[8:0] for FullFlex18 devices. CQ0L CQ0R Inverted Echo Clock Signal Output for DQ[35:0] for FullFlex72 devices. Inverted Echo Clock Signal Output for DQ[17:0] for FullFlex36 devices. Inverted Echo Clock Signal Output for DQ[8:0] for FullFlex18 devices. CQ1L CQ1R Echo Clock Signal Output for DQ[71:36] for FullFlex72 devices. Echo Clock Signal Output for DQ[35:18] for FullFlex36 devices. Echo Clock Signal Output for DQ[17:9] for FullFlex18 devices. CQ1L CQ1R Inverted Echo Clock Signal Output for DQ[71:36] for FullFlex72 devices. Inverted Echo Clock Signal Output for DQ[35:18] for FullFlex36 devices. Inverted Echo Clock Signal Output for DQ[17:9] forFullFlex18 devices. ZQ[1:0]L ZQ[1:0]R VIM Output Impedance Matching Input. To use, connect a calibrating resistor between ZQ and ground. The resistor must be five times larger than the intended line impedance driven by the dual-port. Assert HIGH or leave DNU to disable Variable Impedance Matching. OEL OER Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ data pins during Read operations. INTL INTR Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The upper two memory locations can be used for message passing. INTL is asserted LOW when the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is deasserted HIGH when it reads the contents of its mailbox. LowSPDL LowSPDR Port Low Speed Select Input. Assert this pin LOW to disable the DLL. For operation at less than 100 MHz, assert this pin LOW. PORTSTD[1:0]L[16] PORTSTD[1:0]R[16] Port Clock/Address/Control/Data/Echo Clock/I/O Standard Select Input. Assert these pins LOW/LOW for LVTTL, LOW/HIGH for HSTL, HIGH/LOW for 2.5V LVCMOS, and HIGH/HIGH for 1.8V LVCMOS, respectively. These pins must be driven by VTTL referenced levels. Notes: 14. For 18-Mbit x72 commercial configuration only, please refer to the electrical characteristics section for complete information. 15. SDR mode with two pipelined stages. 16. PORTSTD[1:0]L and PORTSTD[1:0]R have internal pull-down resistors. Document #: 38-06082 Rev. *G Page 8 of 51 FullFlex Pin Definitions (continued) Left Port Right Port Description R/WL R/WR Read/Write Enable Input. Assert this pin LOW to Write to, or HIGH to Read from the dual-port memory array. READYL READYR Port DLL Ready Output. This signal will be asserted LOW when the DLL and Variable Impedance Matching circuits have completed calibration. This is a wired OR capable output. CNT/MSKL CNT/MSKR Port Counter/Mask Select Input. Counter control input. ADSL ADSR Port Counter Address Load Strobe Input. Counter control input. CNTENL CNTENR Port Counter Enable Input. Counter control input. CNTRSTL CNTRSTR Port Counter Reset Input. Counter control input. CNTINTL CNTINTR Port Counter Interrupt Output. This pin is asserted LOW one cycle before the unmasked portion of the counter is incremented to all "1s". WRPL WRPR Port Counter Wrap Input. When the burst counter reaches the maximum count, on the next counter increment WRP can be set LOW to load the unmasked counter bits to 0 or set HIGH to load the counter with the value stored in the mirror register. RETL RETR Port Counter Retransmit Input. Assert this pin LOW to reload the initial address for repeated access to the same segment of memory. VREFL VREFR Port External HSTL I/O Reference Input. This pin is left DNU when HSTL is not used. VDDIOL VDDIOR Port Data I/O Power Supply. FTSELL FTSELR Port Flow-through Mode Select Input. Assert this pin LOW to select Flow-through mode. Assert this pin HIGH to select Pipelined mode. MRST Master Reset Input. MRST is an asynchronous input signal and affects both ports. Asserting MRST LOW performs all of the reset functions as described in the text. A MRST operation is required at power-up. This pin must be driven by a VDDIOL referenced signal. TMS JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State machine transitions occur on the rising edge of TCK. Operation for LVTTL or 2.5V LVCMOS. TDI JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers. Operation for LVTTL or 2.5V LVCMOS. TRST JTAG Reset Input. Operation for LVTTL or 2.5V LVCMOS. TCK JTAG Test Clock Input. Operation for LVTTL or 2.5V LVCMOS. TDO JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally three-stated except when captured data is shifted out of the JTAG TAP. Operation for LVTTL or 2.5V LVCMOS. VSS Ground Inputs. VCORE VTTL Device Core Power Supply. LVTTL Power Supply. Selectable I/O Standard The FullFlex device families also offer the option of choosing one of four port standards for the device. Each port can independently select standards from single-ended HSTL class I, single-ended LVTTL, 2.5V LVCMOS, or 1.8V LVCMOS. The selection of the standard is determined by the PORTSTD pins for each port. These pins should be connected to either an LVTTL or 2.5V LVCMOS power suppy. This will determine the input clock, address, control, data, and Echo clock standard for each port as shown in Table 2. Please note that only 1.8V LVCMOS and HSTL are supported for 4-Mbit, 9-Mbit, 18-Mbit devices running at 250 MHz, and for 36-Mbit devices running at 200 MHz. Document #: 38-06082 Rev. *G Table 2. Port Standard Selection PORTSTD1 PORTSTD0 I/O Standard VSS VSS LVTTL VSS VTTL HSTL VTTL VSS 2.5V LVCMOS VTTL VTTL 1.8V LVCMOS Clocking Separate clocks synchronize the operations on each port. Each port has one clock input C. In this mode, all the transactions on the address, control, and data will be on the C rising Page 9 of 51 FullFlex edge. All transactions on the address, control, data input, output, and byte enables will occur on the C rising edge. clock is associated with half the data bits. The output clock will match the corresponding ports I/O configuration. Table 3. Data Pin Assignment To enable Echo clock outputs, tie CQEN HIGH. To disable Echo clock outputs, tie CQEN LOW. BE Pin Name Data Pin Name BE[7] DQ[71:63] BE[6] DQ[62:54] BE[5] DQ[53:45] BE[4] DQ[44:36] BE[3] DQ[35:27] BE[2] DQ[26:18] BE[1] DQ[17:9] BE[0] DQ[8:0] Input Clock Data Out Echo Clock Echo Clock Figure 2. SDR Echo Clock Delay Deterministic Access Control Selectable Pipelined/Flow-through Mode To meet data rate and throughput requirements, the FullFlex families offer selectable pipelined or flow-through mode. Echo clocks are not supported in flow-through mode and the DLL must be disabled. Flow-through mode is selected by the FTSEL pin. Strapping this pin HIGH selects pipelined mode. Strapping this pin LOW selects flow-through mode. DLL The FullFlex familes of devices have an on-chip DLL. Enabling the DLL reduces the clock to data valid (tCD) time allowing more set-up time for the receiving device. For operation below 100 MHz, the DLL must be disabled. This is selectable by strapping LowSPD low. Whenever the operating frequency is altered beyond the Clock Input Cycle to Cycle Jitter spec, the DLL is required to be reset followed by 1024 clocks before any valid operation. LowSPD pins can be used to reset the DLL(s) for a single port independent of all other circuitry. MRST can be used to reset all DLLs on the chip, for information on DLL lock and reset time, please see the Master Reset section below. Echo Clocking As the speed of data increases, on-board delays caused by parasitics make providing accurate clock trees extremely difficult. To counter this problem, the FullFlex families incorporate Echo Clocks. Echo Clocks are enabled on a per port basis. The dual-port receives input clocks that are used to clock in the address and control signals for a read operation. The dual-port retransmits the input clocks relative to the data output. The buffered clocks are provided on the CQ1/CQ1 and CQ0/CQ0 outputs. Each port has a pair of Echo clocks. Each Deterministic Access Control is provided for ease of design. The circuitry detects when both ports are accessing the same location and provides an external BUSY flag to the port on which data may be corrupted. The collision detection logic saves the address in conflict (Busy Address) to a readable register. In the case of multiple collisions, the first Busy address will be written to the Busy Address register. If both ports are accessing the same location at the same time and only one port is doing a write, if tCCS is met, then the data being written to and read from the address is valid data. For example, if the right port is reading and the left port is writing and the left ports clock meets tCCS, then the data being read from the address by the right port will be the old data. In the same case, if the right ports clock meets tCCS, then the data being read out of the address from the right port will be the new data. In the above case, if tCCS is violated by the either ports clock with respect to the other port and the right port gets the external BUSY flag, the data from the right port is corrupted. Table 4 shows the tCCS timing that must be met to guarantee the data. Table 5 shows that, in the case of the left port writing and the right port reading, when an external BUSY flag is asserted on the right port, the data read out of the device will not be guaranteed. The value in the busy address register can be read back to the address lines. The required input control signals for this function are shown in Table 8. The value in the busy address register will be read out to the address lines tCA after the same amount of latency as a data read operation. After an initial address match, the BUSY flag is asserted and the address under contention is saved in the busy address register. All following address matches cause the BUSY flag to be generated, however, none of the addresses are saved into the busy address register. Once a busy readback is performed, the address of the first match that happens at least two clocks cycles after the busy readback is saved into the busy address register. Table 4. tCCS Timing for All Operating Modes Port A--Early Arriving Port Port B--Late Arriving Port Mode Active Edge Mode Active Edge SDR C SDR C Document #: 38-06082 Rev. *G tCCS C Rise to Opposite C Rise Set-up Time for Non-corrupt Data tCYC(min) - 0.5 Unit ns Page 10 of 51 FullFlex Table 5. Deterministic Access Control Logic Left Port Right Port Left Clock Right Clock BUSYL BUSYR X H H No Collision Description Read Read X Write Read >tCCS 0 H H Read OLD Data 0 >tCCS H H Read NEW Data <tCCS 0 H H Read OLD Data H L Data Not Guaranteed H H Read NEW Data H L Data Not Guaranteed 0 Read Write <tCCS >tCCS 0 H H Read NEW Data 0 >tCCS H H Read OLD Data <tCCS 0 H H Read NEW Data L H Data Not Guaranteed H H Read OLD Data L H Data Not Guaranteed 0 Write <tCCS 0 >-tCCS & <tCCS L L Array Data Corrupted 0 >tCCS L H Array Stores Right Port Data >tCCS 0 H L Array Stores Left Port Data Write Variable Impedance Matching (VIM) Table 7. Variable Impedance Matching Operation Each port contains a Variable Impedance Matching circuit to set the impedance of the I/O driver to match the impedance of the on-board traces. The impedance is set for all outputs except JTAG and is done on a per port basis. To take advantage of the VIM feature, connect a calibrating resistor (RQ) that is five times the value of the intended line impedance from the ZQ pin to VSS. The output impedance is then adjusted to account for drifts in supply voltage and temperature every 1024 clock cycles. If a port's clock is suspended, the VIM circuit will retain its last setting until the clock is restarted. On restart, it will then resume periodic adjustment. In the case of a significant change in device temperature or supply voltage, recalibration will happen every 1024 clock cycles. A Master Reset will initialize the VIM circuitry. Table 6 shows the VIM parameters and Table 7 describes the VIM operation modes. In order to disable VIM, the ZQ pin must be connected to VDDIO of the relative supply for the I/Os before a Master Reset. Table 6. Variable Impedance Matching Parameters Parameter Min. Max. Unit RQ Value 100 275 2% Output Impedance 20 55 15% Reset Time N/A 1024 Cycles N/A Update Time N/A 1024 Cycles N/A Document #: 38-06082 Rev. *G Tolerance RQ Connection Output Configuration 100 - 275 to VSS Output Driver Impedance = RQ/5 15% at Vout = VDDIO/2 ZQ to VDDIO VIM Disabled. Rout < 20 at Vout = VDDIO/2 Address Counter and Mask Register Operations[1] Each port of the FullFlex family contains a programmable burst address counter. The burst counter contains four registers: a counter register, a mask register, a mirror register, and a busy address register. The counter register contains the address used to access the RAM array. It is changed only by the master reset (MRST), Counter Reset, Counter Load, Retransmit, and Counter Increment operations. The mask register value affects the Counter Increment and Counter Reset operations by preventing the corresponding bits of the counter register from changing. It also affects the counter interrupt output (CNTINT). The mask register is only changed by Mask Reset, Mask Load, and MRST. The Mask Load operation loads the value of the address bus into the mask register. The mask register defines the counting range of the counter register. The mask register is divided into two or three consecutive regions. Zero or more "0s" define the masked region and one or more "1s" define the unmasked portion of the counter register. The counter register may only be divided into up to three regions. The region containing the least significant bits must be no more than two "0s". Bits one and zero may be "10" respectively, masking the least significant counter bit and causing the counter to increment by two instead of one. If bits one and zero are "00", the two least significant bits are masked and the counter will increment by four instead of one. For example, in the case of a 256Kx72 Page 11 of 51 FullFlex configuration, a mask register value of 003FC divides the mask register into three regions. With bit 0 being the least significant bit and bit 17 being the most significant bit, the two least significant bits are masked, the next eight bits are unmasked, and the remaining bits are masked. The mirror register is used to reload the counter register on retransmit operations (see "retransmit" below) and wrap functions (see "counter increment" below). The last value loaded into the counter register is stored in the mirror register. The mirror register is only changed by master reset (MRST), Counter Reset, and Counter Load. Table 8 summarizes the operations of these registers and the required input control signals. All signals except MRST are synchronized to the ports clock. Counter Load Operation[1] The address counter and mirror registers are both loaded with the address value presented on the address lines. This value ranges from 0 to 1FFFFF. Mask Load Operation[1] The mask register is loaded with the address value presented on the address bus. This value ranges from 0 to 1FFFFF though not all values permit correct increment operations. Permitted values are in the form of 2n-1, 2n-2, or 2n-4. The counter register can only be segmented in up to three regions. From the most significant bit to the least significant bit, permitted values have zero or more "0s", one or more "1s", and the least significant two bits can be "11", "10", or "00". Thus Document #: 38-06082 Rev. *G 1FFFFE, 07FFFF, and 003FFC are permitted values but 02FFFF, 003FFA, and 07FFE4 are not. Counter Readback Operation The internal value of the counter register can be read out on the address lines. The address will be valid tCA after the selected number of latency cycles configured by FTSEL. The data bus (DQ) is tri-stated on the cycle that the address is presented on the address lines. Figure 3 shows a block diagram of this logic. Mask Readback Operation The internal value of the mask register can be read out on the address lines. The address will be valid tCA after the selected number of latency cycles configured by FTSEL. The data bus (DQ) is tri-stated on the cycle that the address is presented on the address lines. Figure 3 shows a block diagram of the operation. Counter Reset Operation All unmasked bits of the counter and mirror registers are reset to "0". All masked bits remain unchanged. A mask reset followed by a counter reset will reset the counter and mirror registers to 00000. Mask Reset Operation The mask register is reset to all "1s", which unmasks every bit of the burst counter. Page 12 of 51 FullFlex Table 8. Burst Counter and Mask Register Control Operation (Any Port) [17, 18] C MRST CNTRST CNT/MSK CNTEN ADS RET X L X X X X X Master Reset Operation Description H L H X X X Counter Reset Reset counter and mirror unmasked portion to all 0s. H L L X X X Mask Reset Reset mask register to all 1s. H H H L L X Counter Load Load burst counter and mirror with external address value presented on address lines. H H L L L X Mask Load Load mask register with value presented on the address lines. H H H L H L Retransmit Load counter with value in the mirror register H H H L H H Counter Increment Internally increment address counter value. H H H H H H Counter Hold Constantly hold the address value for multiple clock cycles. H H H H L H Counter Readback Read out counter internal value on address lines. H H L H L H Mask Readback Read out mask register value on address lines. H H L H H L Busy Address Readback Read out first busy address after last busy address readback H H L L H X Reserved H H L H L L Reserved H H L H H H Reserved H H H H L L Reserved H H H H H L Reserved Reset address counter to all 0s, mask register to all 1s, and busy address to all 0's. Notes: 17. "X" = "Don't Care", "H" = HIGH, "L" = LOW. 18. Counter operation and mask register operation is independent of chip enables. Document #: 38-06082 Rev. *G Page 13 of 51 FullFlex Increment Operation[1] Retransmit Once the address counter is initially loaded with an external address, the counter can internally increment the address value and address the entire memory array. Only the unmasked bits of the counter register are incremented. In order for a counter bit to change, the corresponding bit in the mask register must be "1". If the two least significant bits of the mask register are "11", the burst counter will increment by one. If the two least significant bits are "10", the burst counter will increment by two, and if they are "00", the burst counter will increment by four. If all unmasked counter bits are incremented to "1" and WRP is deasserted, the next increment will wrap the counter back to the initially loaded value. The cycle before the increment that results in all unmasked counter bits to become "1s", a counter interrupt flag (CNTINT) is asserted if the counter is incremented again. This increment will cause the counter to reach its maximum value and the next increment will return the counter register to its initial value that was stored in the mirror register if WRP is deasserted. If WRP is asserted, the unmasked portion of the counter is filled with "0" instead. The example shown in Figure 4 shows an example of the CYDD36S18V18 device with the mask register loaded with a mask value of 00007F unmasking the seven least significant bits. Setting the mask register to this value allows the counter to access the entire memory space. The address counter is then loaded with an initial value of 000005 assuming WRP is deasserted. The masked bits, the seventh address through the twenty-first address, do not increment in an increment operation. The counter address will start at address 000005 and will increment its internal address value until it reaches the mask register value of 00007F. The counter wraps around the memory block to location 000005 at the next count. CNTINT is issued when the counter reaches the maximum -1 count. Retransmit allows repeated access to the same block of memory without the need to reload the initial address. An internal mirror register stores the address counter value last loaded. While RET is asserted low, the counter will continue to wrap back to the value in the mirror register independent of the state of WRP. Hold Operation The value of all three registers can be constantly maintained unchanged for an unlimited number of clock cycles. Such operation is useful in applications where wait states are needed, or when address is available a few cycles ahead of data in a shared bus interface. Document #: 38-06082 Rev. *G Counter Interrupt The counter interrupt (CNTINT) is asserted LOW one clock cycle before an increment operation that results in the unmasked portion of the counter register being all "1s". It is deasserted by counter reset, counter load, mask reset, mask load, and MRST. Counting by Two When the two least significant bits of the mask register are "10," the counter increments by two. Counting by Four When the two least significant bits of the mask register are "00", the counter increments by four. Mailbox Interrupts The upper two memory locations can be used for message passing and permit communications between ports. Table 9 shows the interrupt operation for both ports. The highest memory location is the mailbox for the right port and the maximum address - 1 is the mailbox for the left port. When one port Writes to the other port's mailbox, the INT flag of the port that the mailbox belongs to is asserted LOW. The INT flag remains asserted until the mailbox location is read by the other port. When a port reads its mailbox, the INT flag is deasserted high after one cycle of latency with respect to the input clock of the port to which the mailbox belongs and is independent of OE. Table 9 shows that in order to set the INTR flag, a Write operation by the left port to address 1FFFFF will assert INTR LOW. A valid Read of the 1FFFFF location by the right port will reset INTR HIGH after one cycle of latency with respect to the right port's clock. At least one byte enable has to be activated to set or reset the mailbox interrupt. Page 14 of 51 FullFlex CNT/MSK CNTEN Decode Logic A CNTRST RET MRST A Mask Register Counter/ Address Register Address Decode RAM Array C From Address Lines Load/Increment 20 Mirror From Mask Register Increment Logic Wrap 20 From Mask From Counter 20 To Readback and Address Decode 0 0 20 Counter 1 1 20 20 Bit 0 and 1 +1 Wrap Detect 1 +2 Wrap 0 1 +4 20 To Counter 0 Figure 3. Counter, Mask, and Mirror Logic Block Diagram[1] Document #: 38-06082 Rev. *G Page 15 of 51 FullFlex CNTINT Example: Load Counter-Mask H Register = 00007F 0 0 0s 220 219 0 1 1 1 H X X Xs 220 219 Max Address Value L H 1 1 Unmasked Address X 0 0 0 0 1 0 X X Xs X 1 1 1 1 Mask Register LSB 1 6 5 4 3 2 1 0 27 2 2 2 2 2 2 2 220 219 Max + 1 Address Value 1 6 5 4 3 2 1 0 27 2 2 2 2 2 2 2 Masked Address Load Address Counter = 000005 1 1 1 1 Address Counter LSB 6 5 4 3 2 1 0 27 2 2 2 2 2 2 2 X X Xs X 0 0 0 0 1 0 1 220 219 6 5 4 3 2 1 0 27 2 2 2 2 2 2 2 Figure 4. Programmable Counter-Mask Register Operation with WRP deasserted[1, 22] Table 9. Interrupt Operation Example[1, 17, 19, 20, 21] Left Port Function R/WL Right Port CEL A0L-20L INTL R/WR CER A0R-20R INTR Set Right INTR Flag L L Max. Address X X X X L Reset Right INTR Flag X X X X H L Max. Address H Set Left INTL Flag X X X L L L Max. Address-1 X Reset Left INTL Flag H L Max. Address-1 H X X X X Master Reset The FullFlex family of Dual-Ports undergo a complete reset when MRST is asserted. MRST must be driven by VDDIOL referenced levels. The MRST can be asserted asynchronously to the clocks and must remain asserted for at least tRS. Once asserted MRST deasserts READY, initializes the internal burst counters, internal mirror registers, and internal Busy Addresses to zero, and initializes the internal mask register to all "1s". All mailbox interrupts (INT), Busy Address Outputs (BUSY), and burst counter interrupts (CNTINT) are deasserted upon master reset. Additionally, MRST must not be released until all power supplies including VREF are fully ramped, all port clocks and mode select inputs (LOWSPD, ZQ, CQEN, DDRON, FTSEL, and PORTSTD) are valid and stable. This begins calibration of the DLL and VIM circuits. READY will be asserted within 1024 clock cycles. READY is a wired OR capable output with a strong pull-up and weak pull-down. Up to four outputs may be connected together. For faster pull-down of the signal, connect a 250 Ohm resistor to VSS. If the DLL and VIM circuits are disabled for a port, the port will be operational within five clock cycles. However, the READY will be asserted within 160 clock cycles. IEEE 1149.1 Serial Boundary Scan (JTAG) The FullFlex families incorporate an IEEE 1149.1 serial boundary scan test access port (TAP). The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels depending on the VTTL power supply. It is composed of four input connections and one output connection required by the test logic defined by the standard. Notes: 19. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the C and can be deasserted after that. Data will be out after the following C edge and will be tri-stated after the next C edge. 20. OE is "Don't Care" for mailbox operation. 21. At least one of BE0, BE1, BE2, BE3, BE4, BE5, BE6, or BE7 must be LOW. 22. The "X" in this diagram represents the counter's upper bits. Document #: 38-06082 Rev. *G Page 16 of 51 FullFlex Table 10.JTAG IDCODE Register Definitions Part Number Table 11.Scan Registers Sizes Register Name Bit Size Configuration Value CYD36S72V18 512Kx72 0C026069h (x2) CYD36S36V18 1024Kx36 0C023069h Bypass 1 CYD36S18V18 2048Kx36 0C024069h Identification 32 CYD18S72V18 256Kx72 0C025069h Boundary Scan CYD18S36V18 512Kx36 0C026069h CYD18S18V18 1024Kx18 0C027069h CYD09S72V18 128Kx72 0C028069h CYD09S36V18 256Kx36 0C029069h CYD09S18V18 512Kx18 0C02A069h CYD04S72V18 64Kx72 0C02B069h CYD04S36V18 128Kx36 0C02C069h CYD04S18V18 256Kx18 0C02D069h Instruction 4 n[23] Table 12.Instruction Identification Codes Instruction Code Description EXTEST 0000 Captures the Input/Output ring contents. Places the BSR between the TDI and TDO. BYPASS 1111 Places the BYR between TDI and TDO. IDCODE 1011 Loads the IDR with the vendor ID code and places the register between TDI and TDO. HIGHZ 0111 Places BYR between TDI and TDO. Forces all FullFlex72 and FullFlex36 output drivers to a High-Z state. CLAMP 0100 Controls boundary to 1/0. Places BYR between TDI and TDO. SAMPLE/PRELOAD 1000 Captures the input/output ring contents. Places BSR between TDI and TDO. RESERVED All other codes Other combinations are reserved. Do not use other than the above. Note: 23. Details of the boundary scan length can be found in the BSDL file for the device. Document #: 38-06082 Rev. *G Page 17 of 51 FullFlex Maximum Ratings Operating Range (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ -65C to + 150C Ambient Temperature with Power Applied............................................ -55C to + 125C Supply Voltage to Ground Potential .............. -0.5V to + 4.1V DC Voltage Applied to Outputs in High-Z State.......................-0.5V to VDDIO + 0.5V Range Ambient Temperature VCORE Commercial 0C to +70C 1.8V 100 mV 1.5V 80 mV Industrial -40C to +85C 1.8V 100 mV 1.5V 80 mV Power Supply Requirements Min. Typ. Max. LVTTL VDDIO 3.0V 3.3V 3.6V 2.5V LVCMOS VDDIO 2.3V 2.5V 2.7V Static Discharge Voltage ...........................................> 2200V HSTL VDDIO 1.4V 1.5V 1.9V (JEDEC JESD8-6, JESD8-B) 1.8V LVCMOS VDDIO 1.7V 1.8V 1.9V Latch-up Current .....................................................> 200 mA 3.3V VTTL 3.0V 3.3V 3.6V 2.5V VTTL 2.3V 2.5V 2.7V HSTL VREF 0.68V 0.75V 0.95V DC Input Voltage.................................-0.5V to VDDIO + 0.5V Output Current into Outputs (LOW) ............................ 20 mA Electrical Characteristics Over the Operating Range All Speed Bins[24] Parameter VOH Description Configuration Min. Output HIGH Voltage (VDDIO = Min., IOH = -8 mA) LVTTL 2.4[25] V (VDDIO = Min., IOH = -4 mA) HSTL (DC)[26] VDDIO - 0.4[25] V (VDDIO = Min., IOH = -4 mA) HSTL (AC)[26] 0.5[25] V (VDDIO = Min., IOH = -6 mA) 2.5V LVCMOS (VDDIO = Min., IOH = -4 mA) VOL VIL Max. 1.7[25] VDDIO - V 0.45[25] V Output HIGH Voltage (VDDIO = Min., IOL = 8 mA) LVTTL 0.4[25] V (VDDIO = Min., IOL = 4 mA) HSTL(DC)[26] 0.4[25] V (VDDIO = Min., IOL = 4 mA) HSTL (AC)[26] 0.5[25] V (VDDIO = Min., IOL = 6 mA) 2.5V LVCMOS 0.7[25] V (VDDIO = Min., IOL = 4 mA) VIH 1.8V LVCMOS VDDIO - Typ. Unit Input HIGH Voltage Input LOW Voltage 1.8V LVCMOS 0.45 [25] V LVTTL 2 VDDIO + 0.3 V HSTL(DC)[26] VREF + 0.1 VDDIO + 0.3 V 2.5V LVCMOS 1.7 V 1.8V LVCMOS 1.26 LVTTL -0.3 0.8 V V HSTL(DC)[26] -0.3 VREF - 0.1 V 2.5V LVCMOS 0.7 V 1.8V LVCMOS 0.36 V Notes: 24. LVTTL and 2.5V LVCMOS are not available for 4-Mbit, 9-Mbit, 18-Mbit devices running at 250 MHz and 36-Mbit devices running at 200 MHz. 25. These parameters are met with VIM disabled. 26. The (DC) specifications are measured under steady state conditions. The (AC) specifications are measured while switching at speed. AC VIH/VIL in HSTL mode are measured with 1V/ns input edge rates Document #: 38-06082 Rev. *G Page 18 of 51 FullFlex Electrical Characteristics Over the Operating Range (continued) All Speed Bins[24] Parameter READY VOH READY VOL Configuration Min. Output HIGH Voltage (VDDIO = Min., IOH = -24 mA) LVTTL 2.7[25] V (VDDIO = Min., IOH = -12 mA) HSTL(DC)[26] VDDIO - 0.4[25] V (VDDIO = Min., IOH = -12 mA) HSTL (AC)[26] VDDIO - 0.5[25] V (VDDIO = Min., IOH = -15 mA) 2.5V LVCMOS (VDDIO = Min., IOH = -12 mA) 1.8V LVCMOS 2.0 Typ. Unit Description Max. [25] V VDDIO - 0.45[25] V [25] V Output HIGH Voltage (VDDIO = Min., IO = 0.12 mA) LVTTL (VDDIO = Min., IOL = 0.12 mA) HSTL(DC)[26] 0.4[25] V (VDDIO = Min., IOL = 0.12 mA) HSTL (AC)[26] 0.5[25] V (VDDIO = Min., IOL = 0.15 mA) 2.5V LVCMOS 0.7 [25] V (VDDIO = Min., IOL = 0.08 mA) 1.8V LVCMOS 0.45[25] 0.4 V IOZ Output Leakage Current -10 10 A IIX1 Input Leakage Current Except TDI, TMS, MRST -10 10 A IIX2 Input Leakage Current TDI, TMS, MRST -300 10 A IIX3 Input Leakage Current PORTSTD, DDRON -10 300 A Document #: 38-06082 Rev. *G Page 19 of 51 FullFlex Electrical Characteristics Over the Operating Range -250[24] Parameter ICC -200[24] -167 -133 Description Configuration Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit Operating Current (VCORE = Max.,IOUT = 0 mA) Outputs Disabled 512Kx72 Com. N/A N/A 1440 1800 1280 1620 1120 1430 mA N/A N/A N/A N/A 1330 1730 1170 1550 mA N/A N/A 1180 1500 1050 1350 930 1220 mA Ind. 1024Kx36 Com. Ind. 2048Kx18 Com. Ind. 256Kx72 Com. Ind. 512Kx36 Com. Ind. 1024Kx18 Com. Ind. 128Kx72 Com. N/A N/A 1110 1470 980 1330 mA 1130 1430 1000 1290 890 1160 mA N/A N/A N/A N/A 1060 1410 940 1280 mA 930 1140 800 980 700 880 N/A N/A mA N/A N/A 820 1030 730 930 N/A N/A mA 750 920 640 800 570 720 N/A N/A mA N/A N/A 670 860 590 780 N/A N/A mA 710 880 610 770 540 690 N/A N/A mA N/A N/A 640 830 570 750 N/A N/A mA 770 930 640 790 560 700 N/A N/A mA N/A 660 830 580 740 N/A N/A mA 630 740 540 640 470 570 N/A N/A mA N/A N/A 550 670 490 600 N/A N/A mA 660 770 550 660 480 580 N/A N/A mA Ind. N/A N/A 570 690 500 610 N/A N/A mA Com. 740 880 620 740 540 650 N/A N/A mA Ind. N/A N/A 630 770 550 680 N/A N/A mA 610 690 510 590 450 520 N/A N/A mA N/A N/A 520 600 460 530 N/A N/A mA 630 720 530 610 460 530 N/A N/A mA N/A N/A 540 620 470 550 N/A N/A mA 256Kx36 Com. Ind. 512Kx18 Com. 128Kx36 Com. Ind. 256Kx18 Com. Ind. Document #: 38-06082 Rev. *G N/A N/A N/A Ind. 64Kx72 N/A N/A Page 20 of 51 FullFlex Electrical Characteristics Over the Operating Range (continued) -250[24] Parameter ISB1 -200[24] -167 -133 Description Configuration Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit Standby Current (Both Ports TTL Level) CEL and CER VIH, f = fMAX 512Kx72 Com. N/A N/A 1000 1250 920 1160 830 1060 mA N/A N/A N/A N/A 970 1260 880 1170 mA N/A N/A 910 1140 820 1050 740 960 mA Ind. 1024Kx36 Com. Ind. 2048Kx18 Com. Ind. 256Kx72 Com. Ind. 512Kx36 Com. Ind. 1024Kx18 Com. Ind. 128Kx72 Com. Ind. 256Kx36 Com. Ind. 512Kx18 Com. Ind. 64Kx72 N/A N/A N/A 880 1160 790 1080 mA N/A 890 1110 810 1030 730 940 mA N/A N/A N/A N/A 860 1140 780 1050 mA 570 700 500 630 460 580 N/A N/A mA N/A N/A 530 680 490 630 N/A N/A mA 520 640 460 570 410 530 N/A N/A mA N/A N/A 480 630 440 580 N/A N/A mA 500 620 450 560 410 520 N/A N/A mA N/A N/A 470 610 430 570 N/A N/A mA 460 560 400 490 360 450 N/A N/A mA N/A N/A 420 540 380 490 N/A N/A mA 430 500 380 440 340 400 N/A N/A mA N/A N/A 390 470 360 430 N/A N/A mA 450 520 390 460 350 410 N/A N/A mA N/A N/A 410 480 370 440 N/A N/A mA Com. 440 520 380 450 340 400 N/A N/A mA Ind. N/A N/A 390 480 350 430 N/A N/A mA 410 450 360 400 320 360 N/A N/A mA N/A N/A 360 410 330 370 N/A N/A mA 420 470 370 410 320 370 N/A N/A mA N/A N/A 370 420 330 380 N/A N/A mA 128Kx36 Com. Ind. 256Kx18 Com. Ind. Document #: 38-06082 Rev. *G N/A N/A Page 21 of 51 FullFlex Electrical Characteristics Over the Operating Range (continued) -250[24] Parameter ISB2 Description Standby Current (One Port TTL or CMOS Level) CEL | CER VIH, f = fMAX -167 -133 Configuration Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit 512Kx72 Com. N/A N/A 1300 1570 1160 1410 1020 1260 mA N/A N/A N/A N/A 1210 1520 1070 1370 mA N/A N/A 1090 1330 980 1210 870 1100 mA Ind. 1024Kx36 Com. Ind. 2048Kx18 Com. Ind. 256Kx72 Com. Ind. 512Kx36 Com. Ind. 1024Kx18 Com. Ind. 128Kx72 Com. Ind. 256Kx36 Com. Ind. 512Kx18 Com. Ind. 64Kx72 N/A N/A N/A N/A 1030 1330 920 1210 mA N/A N/A 1040 1270 930 1160 830 1050 mA N/A N/A N/A N/A 980 1270 880 1160 mA 760 890 650 790 580 710 N/A N/A mA N/A N/A 680 840 610 760 N/A N/A mA 630 760 550 670 490 610 N/A N/A mA N/A N/A 570 730 520 670 N/A N/A mA 600 730 520 640 470 580 N/A N/A mA N/A N/A 550 690 490 640 N/A N/A mA 620 730 520 630 460 560 N/A N/A mA N/A N/A 550 670 480 610 N/A N/A mA 540 610 460 530 400 470 N/A N/A mA N/A N/A 480 560 430 500 N/A N/A mA 550 620 460 530 410 480 N/A N/A mA N/A N/A 480 560 430 510 N/A N/A mA Com. 590 680 500 580 440 510 N/A N/A mA Ind. N/A N/A 510 610 450 550 N/A N/A mA 510 560 440 480 380 420 N/A N/A mA N/A N/A 450 500 390 440 N/A N/A mA 520 570 440 490 390 430 N/A N/A mA N/A N/A 450 500 400 450 N/A N/A mA 128Kx36 Com. Ind. 256Kx18 Com. Ind. Document #: 38-06082 Rev. *G -200[24] Page 22 of 51 FullFlex Electrical Characteristics Over the Operating Range All Speed Bins[24] Parameter ISB3 Description Standby Current (Both Ports CMOS Level) CEL and CER VCORE - 0.2V, f = 0 Typ. Max. Com. 410 590 mA Ind. 460 700 mA Com. 410 590 mA Ind. 460 700 mA Com. 410 590 mA Ind. 460 700 mA Com. 210 300 mA Ind. 230 350 mA Com. 210 300 mA Ind. 230 350 mA Com. 210 300 mA Ind. 230 350 mA Com. 150 200 mA Ind. 170 220 mA Com. 150 200 mA Ind. 170 220 mA Com. 150 200 mA Ind. 170 220 mA Com. 130 150 mA Ind. 140 170 mA Com. 130 150 mA Ind. 140 170 mA Com. 130 150 mA Ind. 140 170 mA Configuration 512Kx72 1024Kx36 2048Kx18 256Kx72 512Kx36 1024Kx18 128Kx72 256Kx36 512Kx18 64Kx72 128Kx36 256Kx18 Unit Table 13.Capacitance Signals Packages CYDD18S72V18 CYDD09S72V18 CYDD04S72V18 CYDD18S36V18 CYDD09S36V18 CYDD04S36V18 CYDD18S18V18 CYDD09S18V18 CYDD04S18V18 CYDD36S72V18 CYDD36S36V18 CYDD36S18V18 12 pF 12 pF 20 pF 20 pF OE BE, DQ 10 pF 18 pF 16 pF 30 pF All other signals 10 pF 10 pF 16 pF 16 pF Document #: 38-06082 Rev. *G Page 23 of 51 FullFlex AC Test Load and Waveforms V V REF V T H = 1 .5 V fo r L V T T L V T H = 5 0 % V D D IO fo r 2 .5 V C M O S V T H = 5 0 % V D D IO fo r 1 .8 V C M O S = NC REF 50 O hm 50 O hm O u tp u t T e s t P o in t R =250 O hm VTH ZQ READY D e v ic e u n d e r te s t C = 10pF RQ =250 O hm Figure 5. Output Test Load for LVTTL/CMOS V T H V V R E F = 5 0 % V D D IO = 0 .7 5 V R E F 5 0 O h m 5 0 O h m O u tp u t R = 2 5 0 O h m T e s t P o in t R E A D Y Z Q D e v ic e u n d e r te s t V T H C = 1 0 p F fo r S D R R Q = 2 5 0 O h m Figure 6. Output Test Load for HSTL Figure 7. HSTL Input Waveform Document #: 38-06082 Rev. *G Page 24 of 51 FullFlex Switching Characteristics Over the Operating Range Table 14.SDR Mode, Signals effected by DLL DLL ON (LOWSPD=1)[29] -250[24] Parameter Description tCD2[33] C Rise to DQ Valid for Pipelined Mode tCCQ[33] C Rise to CQ Rise Min. Max. Min. 2.64[28, 1.00 2.64[32] 2.64[28, 32] C Rise to DQ Output High Z in Pipelined Mode 1.00 tCKLZ2[27, 33] C Rise to DQ Output Low Z in Pipelined Mode 1.00 -167 Max. Min. 3.30[28, 32] [27, 33] tCKHZ2 -200[24] DLL OFF (LOWSPD=0)[29] 3.30[32] 1.00 3.30[28, 32] 1.00 Min. Max. 4.00[28, 4.50[28, 1.00 4.00[32] 1.00 4.50[32] 1.00 4.00[28, 32] 4.50[28, 32] 32] 1.00 -133 Max. 32] 1.00 Max. Uni t 6.00[28, ns 1.00 6.00[32 ns 1.00 6.00[28, 32] ns Min. 32] 1.00 1.00 32] 1.00 ns Table 15.SDR Mode -250[24] Parameter Description fMAX Maximum Operating (PIPELINED) Frequency for Pipelined Mode fMAX (FLOW- THROUGH) -167 -133 Min. Max. Min. Max. Min. Max. Min. Max. Unit 100 250 100 200 100 167 100 133 MHz 55.6 MHz 10.00 ns Maximum Operating Frequency for Flow-through Mode 100 tCYC C Clock Cycle Time for (PIPELINED) Pipelined Mode 4.00[32] tCYC (FLOW- C Clock Cycle Time for Flow-through Mode 10.00[32] tCKD C Clock Duty Time tSD Data Input HSTL 1.20[28,32] Set-up Time 1.8V LVCMOS to C Rise 2.5V LVCMOS 1.45[28,32] 3.3V LVTTL THROUGH) -200[24] 45 10.00 77 5.00[32] 10.00 13.00[32] 55 45 66.7 6.00[32] 10.00 15.00[32] 55 45 7.00[32] 18.00[32] 55 45 ns 55 % 1.50[28,32] 1.70[28,32] 1.80[28,32] ns 1.75[28,32] 1.95[28,32] 2.05[28,32] ns 0.5 0.5 0.5 ns HSTL 1.20[28,30, 32] 1.8V LVCMOS 1.50[28,30, 1.70[28,30, 1.80[28,30, ns 2.5V LVCMOS 1.45[28,30, 32] 3.3V LVTTL 1.75[28,30, 1.95[28,30, 2.05[28,30, ns 0.50 0.60 0.70 ns tHD[30, 31] Data Input Hold Time after C Rise tSAC Address & Control Input Setup Time to C Rise tHAC[30] Address & Control Input Hold Time after C Rise tOE Output Enable to Data Valid tOLZ[27] OE to Low Z 0.5 32] 32] 32] 0.50 3.40[28,32] 1.00 32] 4.40[28, 32] 5.00[28 32] 1.00 32] 5.50[28, ,32] 1.00 32] 1.00 ns ns Notes: 27. Parameters specified with the load capacitance in Figure 5 and Figure 6. 28. For the x18 devices, add 200 ps to this parameter in the table above. 29. Test conditions assume a signal transition time of 2 V/ns. 30. add 100ps to this timing for 36M devices. 31. add 200ps to this timing for 36M x72 devices 32. Add 15% to this parameter if a VCORE of 1.5V is used. 33. This parameter assumes input clock cycle to cycle jitter of +/- 0ps. Document #: 38-06082 Rev. *G Page 25 of 51 FullFlex Table 15.SDR Mode -250[24] Parameter Description tOHZ[27] OE to High Z tCD1 C Rise to DQ Valid for Flow-through Mode (LowSPD = 1) tCA1 Min. 1.00 -200[24] Max. [28,32] 3.40 -167 Min. Max. 1.00 4.40[28, 32] -133 Min. Max. 1.00 5.00[28 ,32] Min. Max. Unit 1.00 5.50[28, 32] ns 7.20[28,32] 9.00[28, 32] [28,32] 11.00 13.00 ns C Rise to Address Readback Valid for Flow-through Mode 7.20[32] 9.00[32] 11.00 13.00 ns tCA2 C Rise to Address Readback Valid for Pipelined Mode 4.00[32] 5.00[32] 6.00[32 7.50[32] ns tDC[33] DQ Output Hold after C Rise tJIT Clock Input Cycle to Cycle Jitter 1.00 tCQHQV[33] Echo Clock HSTL (CQ) High to 1.8V LVCMOS Output Valid 2.5V LVCMOS 3.3V LVTTL 1.00 [28,32] [32] [32] ] 1.00 1.00 ns +/- 200 +/- 200 +/- 200 +/- 200 ps 0.60[28] 0.70[28] 0.80[28 0.90[28] ns 0.70[28] 0.80[28] 0.90[28 1.00[28] ns ] ] tCQHQX[33] Echo Clock HSTL (CQ) High to 1.8V LVCMOS Output Hold 2.5V LVCMOS 3.3V LVTTL -0.60 -0.70 -0.80 -0.90 ns -0.75 -0.85 -0.95 -1.05 ns tCKHZ1[27] C Rise to DQ Output High Z in Flow-through Mode 1.00 tCKLZ1[27] C Rise to DQ Output Low Z in Flow-through Mode 1.00 1.00 1.00 1.00 ns tAC Address Output Hold after C Rise 1.00 1.00 1.00 1.00 ns 7.20[28,32] 9.00[28, 1.00 32] 1.00 11.00 1.00 [28,32] 13.00 [28,32] ns tCKHZA1[27] C Rise to Address Output High Z for Flow-through Mode 1.00 7.20[32] 1.00 9.00[32] 1.00 11.00 1.00 13.00 ns tCKHZA2[27] C Rise to Address Output High Z for Pipelined Mode 1.00 4.00[32] 1.00 5.00[32] 1.00 6.00[32 1.00 7.50[32] ns tCKLZA[27] C Rise to Address Output Low Z 1.00 tSCINT C Rise to CNTINT Low 1.00 2.64[32] 1.00 3.30[32] 1.00 4.00[32 1.00 4.50[32] ns tRCINT C Rise to CNTINT High 1.00 2.64[32] 1.00 3.30[32] 1.00 4.00[32 1.00 4.50[32] ns tSINT C Rise to INT Low 0.50 6.00[32] 0.50 7.00[32] 0.50 8.00[32 0.50 8.50[32] ns tRINT C Rise to INT High 0.50 6.00[32] 0.50 7.00[32] 0.50 8.00[32 0.50 8.50[32] ns tBSY C Rise to BUSY Valid 1.00 2.64[32] 1.00 3.30[32] 1.00 4.00[32 1.00 4.50[32] ns 1.00 [32] ] 1.00 [32] 1.00 ] ] ] ] ] ns Table 16.Master Reset Timing -250[24] Parameter Description Min. Max. -200[24] Min. Max. -167 Min. Max. -133 Min. Max. Unit tPUP Power-Up Time 1 1 1 1 ms tRS Master Reset Pulse Width 5 5 5 5 cycles Document #: 38-06082 Rev. *G Page 26 of 51 FullFlex Table 16.Master Reset Timing -250[24] Parameter Description Min. -200[24] Max. 5 Min. Max. 5 -167 Min. -133 Max. 5 Min. Max. 5 Unit tRSR Master Reset Recovery Time cycles tRSF Master Reset to Outputs Inactive/Hi Z 12 15 18 22.50 ns tRDY[34] Master Reset Release to Port Ready 1024 1024 1024 1024 cycles tCORDY[35] C Rise to Port Ready 8[32] 9.5[32] 11[32] 13[32] ns Table 17.JTAG Timing -250[24] Parameter Description Min. -200[24] Max. Min. Max. -167 Min. -133 Max. Min. Max. Unit 20 MHz fJTAG JTAG TAP Controller Frequency tTCYC TCK Cycle Time 50 50 50 50 ns tTH TCK High Time 20 20 20 20 ns tTL TCK Low Time 20 20 20 20 ns tTMSS TMS Set-up to TCK Rise 10 10 10 10 ns tTMSH TMS Hold to TCK Rise 10 10 10 10 ns tTDIS TDI Set-up to TCK Rise 10 10 10 10 ns tTDIH TDI Hold to TCK Rise 10 10 10 10 ns tTDOV TCK Low to TDO Valid tTDOX TCK Low to TDO Invalid tJXZ TCK Low to TDO High Z 15 15 15 15 ns tJZX TCK Low to TDO Active 15 15 15 15 ns 15 ns 20 20 10 20 10 0 0 10 0 10 0 tJZX TCK Low to TDO Active 15 15 15 Notes: 34. READY is a wired OR capable output with a weak pull-down. For a decreased falling delay, connect a 250- resistor to VSS. 35. Add this propagation delay after tRDY for all Master Reset Operations. ns ns Switching Waveforms JTAG Timing tTH Test Clock TCK tTMSS tTL tTCYC tTMSH Test Mode Select TMS tTDIS tTDIH Test Data-In TDI Test Data-Out TDO Document #: 38-06082 Rev. *G tTDOX tTDOV Page 27 of 51 FullFlex Switching Waveforms (continued) Master Reset[34] ~ VCORE tPUP tRS MRST ~ C ~ tRDY READY tCORDY ~ tRSF All Address & Data ~ tRSR All Other Inputs ~ READ Cycle for Pipelined Mode tCYC C CE OE tSAC tHAC R/W A An 2 Pipelined stages DQ DQx-1 An+1 An+2 DQx DQn tDC Document #: 38-06082 Rev. *G An+3 DQn+1 An+4 DQn+2 An+5 DQn+3 An+6 DQn+4 tCD2 Page 28 of 51 FullFlex Switching Waveforms (continued) WRITE Cycle for Pipelined and Flow-through Modes tCYC C CE R/W An A An+1 An+2 An+3 An+4 An+5 An+6 DQn+1 DQn+2 DQn+3 DQn+4 DQn+5 DQn+6 2 Pipelined stages DQ DQn tSD tHD READ with Address Counter Advance for Pipelined Mode tCYC C A An Internal Address An An+1 An+2 An+3 ADS CNTEN DQ DQx-1 DQx Document #: 38-06082 Rev. *G DQn DQn+1 DQn+2 DQn+3 Page 29 of 51 FullFlex Switching Waveforms (continued) READ with Address Counter Advance for Flow-through Mode tCYC C tSAC tHAC A An ADS tSAC tHAC CNTEN tCD1 DQ DQx DQn DQn + 1 DQn + 2 DQn + 3 DQn + 4 tDC READ EXTERNAL ADDRESS Document #: 38-06082 Rev. *G READ WITH COUNTER COUNTER HOLD READ WITH COUNTER Page 30 of 51 FullFlex Switching Waveforms (continued) Port-to-Port WRITE-READ for Pipelined Mode tCYC Left Port CL An AL R/WL DQL DQn Right Port CR tCCS tCYC AR An R/WR tSAC tHAC DQR DQn tCD2 tDC Chip Enable READ for Pipelined Mode tCYC C CE0 CE1 R/W tSAC tHAC A An An+1 An+3 An+4 tCD2 An+5 An+6 DQn+3 DQn DQ Document #: 38-06082 Rev. *G An+2 tDC tCKLZ2 Page 31 of 51 FullFlex Switching Waveforms (continued) OE Controlled WRITE for Pipelined Mode tCYC C A Ax+1 Ax+2 Ax+3 An An+1 An+2 An+3 DQn DQn+1 DQn+2 DQn+3 An An+1 An+2 An+3 DQn DQn+1 DQn+2 DQn+3 R/W OE tOHZ DQx+1 DQ DQx-1 DQx OE Controlled WRITE for Flow-through Mode tCYC C A Ax+1 Ax+2 Ax+3 R/W OE tOHZ DQx+2 DQ DQx DQx+1 Document #: 38-06082 Rev. *G Page 32 of 51 FullFlex Switching Waveforms (continued) Byte-Enable READ for Pipelined Mode tCYC C A An An+1 An+2 An+3 R/W BE7 BE6 BE5 BE4 BE3 BE2 BE1 BE0 tCKLZ2 t DQn+1(63:71) CKHZ2 DQ63:71 DQ54:62 DQn+1(54:62) DQn+2(45:53) DQ45:53 DQn+2(36:44) DQ36:44 DQn+1(27:35) DQ27:35 DQ18:26 DQ9:17 DQ0:8 Document #: 38-06082 Rev. *G DQn+2(18:26) DQn+3(9:17) DQn+3(0:8) Page 33 of 51 FullFlex Switching Waveforms (continued) Port-to-Port WRITE-to-READ for Flow-through Mode CL R /W L tS A C AL tH A C M A TC H NO MATCH tS D DQL tH D V A LID tC C S CR tCD1 R /W R tH A C tS A C AR NO MATCH M A TC H tC D 1 VA LID DQR V A L ID tDC tD C Busy Address Readback for Pipelined and Flow-through Modes, DDRON = CNT/MSK = RET = LOW[36] tCYC ~ C Internal Amatch+2 Address Amatch+3 BUSY CNTEN ADS Amatch+4 ~ ~ ~ ~ External Address Pipelined ~ External Address Flow-through ~ Amatch tCA2 tAC Amatch tCA1 tAC Note: 36. Amatch is the matching address which will be reported on the address bus of the losing port. The counter operation selected for reporting the address is "Busy Address Readback." Document #: 38-06082 Rev. *G Page 34 of 51 FullFlex Switching Waveforms (continued) Read Cycle for Flow-through Mode t CY C C CE 0 t SAC t H AC CE 1 BEn R /W t S AC A t H AC An + 1 An tC D 1 An + 2 An + 3 t C KH Z 1 tD C DQ DQ n D Qn + 1 t C KLZ 1 tO H Z DQ n + 2 tD C t O LZ OE tO E READ-to-WRITE for Pipelined Mode (OE = VIL)[37,38,39] tCYC tCL C A tCH Ax An An+1 tSAC tHAC R/W DQ An+2 tSAC tHAC tCKLZ2 DQx-2 DQx-1 tCD2 DQx tDC DQn tCKHZ2 DQn+1 DQn+2 tSD tHD Notes: 37. When OE = VIL, the last read operation is allowed to complete before the DQ bus is tri-stated and the user is allowed to drive write data. 38. Two dummy writes should be issued to accomplish bus turnaround. The 3rd instruction is the first valid write. 39. Chip enable or all byte enables should be held inactive during the two dummy writes to avoid data corruption. Document #: 38-06082 Rev. *G Page 35 of 51 FullFlex Switching Waveforms (continued) READ-to-WRITE for Pipelined Mode (OE Controlled)[40,41] tCYC C A Ax Ax+1 Ax+2 An An+1 An+2 An+3 DQn+1 DQn+2 DQn+3 tSAC tHAC R/W OE DQ tOHZ DQx-2 DQx-1 DQx tSD tHD DQn Notes: 40. OE should be deasserted and tOHZ allowed to elapse before the first write operation is issued. 41. Any write scheduled to complete after OE is deasserted will be preempted. Document #: 38-06082 Rev. *G Page 36 of 51 FullFlex Switching Waveforms (continued) Read-to-Write-to-Read for Flow-through Mode (OE = LOW) t CYC C t SAC t HAC CE0 CE 1 B En t SAC t HAC R/W A An An + 1 An + 2 An + 2 t SD DQ IN An + 3 An + 4 tH D DQn + 2 t CD1 t C D1 DQ n D Q O UT t C D1 DQn + 1 t CD1 DQ n + 3 t CKHZ1 t CKLZ1 tD C READ Document #: 38-06082 Rev. *G tD C NO P W RITE R EAD Page 37 of 51 FullFlex Switching Waveforms (continued) Read-to-Write-to-Read for Flow-through Mode (OE Controlled) t C YC C t SA C t H AC CE0 CE1 BEn t SA C t H A C R /W A An An + 1 An + 2 tS D D Q IN D Q O UT An + 4 An + 5 tH D DQn + 2 tC D 1 An + 3 DQn + 3 tD C tO E tC D 1 tC D 1 DQn DQn + 4 t C KL Z 1 tO H Z tD C OE READ Document #: 38-06082 Rev. *G W R IT E R EA D Page 38 of 51 FullFlex Switching Waveforms (continued) BUSY Timing, WRITE-WRITE Collision for Pipelined and Flow-through Modes, Clock Timing Violates tCCS. (Flag Both Ports) Port A C A R/W BUSY < tCCS tBSY tBSY Port B C A R/W tBSY BUSY tBSY BUSY Timing, WRITE-WRITE Collision for Pipelined and Flow-through Modes, Clock Timing Meets tCCS. (Flag Losing Port) Losing Port C A R/W BUSY tccs tBSY tBSY Winning Port C A Match R/W BUSY Document #: 38-06082 Rev. *G Page 39 of 51 FullFlex Switching Waveforms (continued) Read with Echo Clock for Pipelined Mode (CQEN = HIGH) C tSAC tHAC R/W A An An+1 An+2 An+3 An+4 An+5 An+6 CQ0 CQ0 tCCQ CQ1 CQ1 tCQHQX tCQHQV DQ DQx-1 DQx Document #: 38-06082 Rev. *G DQn DQn+1 DQn+2 DQn+3 DQn+4 Page 40 of 51 FullFlex Switching Waveforms (continued) Mailbox Interrupt Output tCYC CL AL AMAX R/WL DQL INTR tSINT tRINT CR AR AMAX R/WR DQR Document #: 38-06082 Rev. *G DQMAX Page 41 of 51 FullFlex Ordering Information 512K x 72 (36 Mbit) 1.8V/1.5V Synchronous CYD36S72V18 Dual-Port SRAM Speed (MHz) Ordering Code 200 CYD36S72V18-200BGXC BY0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Lead-Free) Commercial CYD36S72V18-200BGC BG0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Leaded) Commercial CYD36S72V18-167BGXC BY0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Lead-Free) Commercial CYD36S72V18-167BGC BG0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Leaded) Commercial CYD36S72V18-167BGXI BY0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Lead-Free) Industrial CYD36S72V18-167BGI BG0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Leaded) Industrial CYD36S72V18-133BGXC BY0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Lead-Free) Commercial CYD36S72V18-133BGC BG0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Leaded) Commercial CYD36S72V18-133BGXI BY0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Lead-Free) Industrial CYD36S72V18-133BGI BG0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Leaded) Industrial 167 133 Package Name Package Type Operating Range 256K x 72 (18 Mbit) 1.8V/1.5V Synchronous CYD18S72V18 Dual-Port SRAM Speed (MHz) Ordering Code 250 CYD18S72V18-250BGXC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Commercial CYD18S72V18-250BGC BG484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Commercial CYD18S72V18-200BGXC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Commercial CYD18S72V18-200BGC BG484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Commercial CYD18S72V18-200BGXI BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Industrial CYD18S72V18-200BGI BG484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Industrial CYD18S72V18-167BGXC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Commercial CYD18S72V18-167BGC BG484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Commercial CYD18S72V18-167BGXI BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Industrial CYD18S72V18-167BGI BG484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Industrial 200 167 Package Name Package Type Operating Range 128K x 72 (9 Mbit) 1.8V/1.5V Synchronous CYD09S72V18 Dual-Port SRAM Speed (MHz) Ordering Code Package Name 250 CYD09S72V18-250BGXC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Commercial CYD09S72V18-250BGC BG484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Commercial 200 CYD09S72V18-200BGXC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Commercial CYD09S72V18-200BGC BG484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Commercial CYD09S72V18-200BGXI BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Industrial 167 Package Type Operating Range CYD09S72V18-200BGI BG484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Industrial CYD09S72V18-167BGXC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Commercial CYD09S72V18-167BGC BG484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Commercial CYD09S72V18-167BGXI BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Industrial CYD09S72V18-167BGI BG484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Industrial Document #: 38-06082 Rev. *G Page 42 of 51 FullFlex Ordering Information (continued) 64K x 72 (4 Mbit) 1.8V/1.5V Synchronous CYD04S72V18 Dual-Port SRAM Speed (MHz) Ordering Code Package Name 250 CYD04S72V18-250BGXC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Commercial CYD04S72V18-250BGC BG484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Commercial 200 CYD04S72V18-200BGXC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Commercial CYD04S72V18-200BGC BG484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Commercial CYD04S72V18-200BGXI BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Industrial 167 Package Type Operating Range CYD04S72V18-200BGI BG484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Industrial CYD04S72V18-167BGXC BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Commercial CYD04S72V18-167BGC BG484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Commercial CYD04S72V18-167BGXI BY484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Lead-Free) Industrial CYD04S72V18-167BGI BG484 484-ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Leaded) Industrial 1024K x 36 (36 Mbit) 1.8V/1.5V Synchronous CYD36S36V18 Dual-Port SRAM Speed (MHz) Ordering Code Package Name 200 CYD36S36V18-200BGXC BY0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Lead-Free) Commercial CYD36S36V18-200BGC BG0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Leaded) Commercial 167 CYD36S36V18-167BGXC BY0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Lead-Free) Commercial CYD36S36V18-167BGC BG0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Leaded) Commercial CYD36S36V18-167BGXI BY0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Lead-Free) Industrial 133 Package Type Operating Range CYD36S36V18-167BGI BG0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Leaded) Industrial CYD36S36V18-133BGXC BY0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Lead-Free) Commercial CYD36S36V18-133BGC BG0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Leaded) Commercial CYD36S36V18-133BGXI BY0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Lead-Free) Industrial CYD36S36V18-133BGI BG0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Leaded) Industrial 512K x 36 (18 Mbit) 1.8V/1.5V Synchronous CYD18S36V18 Dual-Port SRAM Speed (MHz) Ordering Code Package Name 250 CYD18S36V18-250BBXC BW0BC 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Lead-Free) Commercial CYD18S36V18-250BBC BB0BC 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Leaded) Commercial CYD18S36V18-200BBXC BW0BC 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Lead-Free) Commercial CYD18S36V18-200BBC BB0BC 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Leaded) Commercial CYD18S36V18-200BBXI BW0BC 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Lead-Free) Industrial CYD18S36V18-200BBI BB0BC 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Leaded) Industrial CYD18S36V18-167BBXC BW0BC 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Lead-Free) Commercial CYD18S36V18-167BBC BB0BC 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Leaded) Commercial CYD18S36V18-167BBXI BW0BC 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Lead-Free) Industrial CYD18S36V18-167BBI BB0BC 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Leaded) Industrial 200 167 Document #: 38-06082 Rev. *G Package Type Operating Range Page 43 of 51 FullFlex Ordering Information (continued) 256K x 36 (9 Mbit) 1.8V/1.5V Synchronous CYD09S36V18 Dual-Port SRAM Speed (MHz) Ordering Code Package Name 250 CYD09S36V18-250BBXC BW0BD 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Commercial CYD09S36V18-250BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Commercial 200 CYD09S36V18-200BBXC BW0BD 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Commercial CYD09S36V18-200BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Commercial CYD09S36V18-200BBXI BW0BD 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Industrial CYD09S36V18-200BBI BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Industrial CYD09S36V18-167BBXC BW0BD 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Commercial CYD09S36V18-167BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Commercial CYD09S36V18-167BBXI BW0BD 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Industrial CYD09S36V18-167BBI BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Industrial 167 Package Type Operating Range 128K x 36 (4 Mbit) 1.8V/1.5V Synchronous CYD04S36V18 Dual-Port SRAM Speed (MHz) Ordering Code Package Name 250 CYD04S36V18-250BBXC BW0BD 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Commercial CYD04S36V18-250BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Commercial 200 CYD04S36V18-200BBXC BW0BD 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Commercial CYD04S36V18-200BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Commercial CYD04S36V18-200BBXI BW0BD 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Industrial CYD04S36V18-200BBI BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Industrial CYD04S36V18-167BBXC BW0BD 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Commercial CYD04S36V18-167BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Commercial CYD04S36V18-167BBXI BW0BD 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Industrial CYD04S36V18-167BBI BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Industrial 167 Package Type Operating Range 2048K x 18 (36 Mbit) 1.8V/1.5V Synchronous CYD36S18V18 Dual-Port SRAM Speed (MHz) Ordering Code 200 CYD36S18V18-200BGXC BY0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Lead-Free) Commercial CYD36S18V18-200BGC BG0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Leaded) Commercial CYD36S18V18-167BGXC BY0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Lead-Free) Commercial CYD36S18V18-167BGC BG0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Leaded) Commercial CYD36S18V18-167BGXI BY0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Lead-Free) Industrial CYD36S18V18-167BGI BG0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Leaded) Industrial CYD36S18V18-133BGXC BY0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Lead-Free) Commercial CYD36S18V18-133BGC BG0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Leaded) Commercial CYD36S18V18-133BGXI BY0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Lead-Free) Industrial CYD36S18V18-133BGI BG0DA 484-ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Leaded) Industrial 167 133 Document #: 38-06082 Rev. *G Package Name Package Type Operating Range Page 44 of 51 FullFlex Ordering Information (continued) 1024K x 18 (18 Mbit) 1.8V/1.5V Synchronous CYD18S18V18 Dual-Port SRAM Speed MHz) Ordering Code Package Name 250 CYD18S18V18-250BBXC BW0BC 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Lead-Free) Commercial CYD18S18V18-250BBC BB0BC 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Leaded) Commercial 200 CYD18S18V18-200BBXC BW0BC 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Lead-Free) Commercial CYD18S18V18-200BBC BB0BC 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Leaded) Commercial CYD18S18V18-200BBXI BW0BC 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Lead-Free) Industrial CYD18S18V18-200BBI BB0BC 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Leaded) Industrial CYD18S18V18-167BBXC BW0BC 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Lead-Free) Commercial CYD18S18V18-167BBC BB0BC 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Leaded) Commercial CYD18S18V18-167BBXI BW0BC 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Lead-Free) Industrial CYD18S18V18-167BBI BB0BC 256-ball Grid Array 19 mm x 19 mm with 1.0 mm pitch (Leaded) Industrial 167 Package Type Operating Range 512K x 18 (9 Mbit) 1.8V/1.5V Synchronous CYD09S18V18 Dual-Port SRAM Speed (MHz) Ordering Code Package Name 250 CYD09S18V18-250BBXC BW0BD 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Commercial CYD09S18V18-250BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Commercial 200 CYD09S18V18-200BBXC BW0BD 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Commercial CYD09S18V18-200BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Commercial CYD09S18V18-200BBXI BW0BD 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Industrial CYD09S18V18-200BBI BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Industrial CYD09S18V18-167BBXC BW0BD 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Commercial CYD09S18V18-167BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Commercial CYD09S18V18-167BBXI BW0BD 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Industrial CYD09S18V18-167BBI BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Industrial 167 Package Type Operating Range 256K x 18 (4 Mbit) 1.8V/1.5V Synchronous CYD04S18V18 Dual-Port SRAM Speed (MHz) Ordering Code Package Name 250 CYD04S18V18-250BBXC BW0BD 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Commercial CYD04S18V18-250BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Commercial CYD04S18V18-200BBXC BW0BD 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Commercial CYD04S18V18-200BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Commercial CYD04S18V18-200BBXI BW0BD 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Industrial CYD04S18V18-200BBI BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Industrial CYD04S18V18-167BBXC BW0BD 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Commercial CYD04S18V18-167BBC BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Commercial CYD04S18V18-167BBXI BW0BD 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Lead-Free) Industrial CYD04S18V18-167BBI BB256 256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Leaded) Industrial 200 167 Document #: 38-06082 Rev. *G Package Type Operating Range Page 45 of 51 FullFlex Package Diagrams TOP VIEW 256-ball Lead-Free FBGA (17 x 17 mm) BW256 256-ball Leaded FBGA (17 x 17 mm) BB256 BOTTOM VIEW O0.05 M C O0.25 M C A B PIN 1 CORNER O0.450.05(256X)-CPLD DEVICES (37K & 39K) PIN 1 CORNER +0.10 -0.05 O0.50 (256X)-ALL OTHER DEVICES 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B B C C D D 1.00 A E E F F G H J K H 15.00 17.000.10 G J K L M 7.50 L M N N P P R R T T 1.00 7.50 0.15 C 0.700.05 0.25 C B 15.00 A 17.000.10 A 0.20(4X) SEATING PLANE +0.10 -0.05 C A1 0.36 0.56 REFERENCE JEDEC MO-192 51-85108-*F 0.35 A1 A 1.40 MAX. 1.70 MAX. Document #: 38-06082 Rev. *G Page 46 of 51 FullFlex Package Diagrams (continued) 256-ball Lead-Free FBGA (19 x 19 x 1.7 mm) BW256 256-ball Leaded FBGA (19 x 19 x 1.7 mm) BB256 BOTTOM VIEW TOP VIEW A1 CORNER O0.05 M C O0.25 M C A B PIN A1 CORNER 1 O0.50 (256 X) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 B C C D D E E F F G G 19.00 +/- 0.10 H J K L 1.00 (REF) A B 15.00 (REF) A H J K L M M N N P P R R T T 1.00 (REF) -B- 15.00 (REF) -A- 19.00 +/- 0.10 Package Weight - 1.1 grams 0.15 C 0.70 (REF) 0.25 C 0.15(4X) 001-00915-*A Document #: 38-06082 Rev. *G 1.70 MAX. 0.35 +0.10/-0.05 SEATING PLANE 0.56 (REF) -C- Jedec Outline - Design Guide 4.14 Page 47 of 51 FullFlex Package Diagrams (continued) 484-ball Lead-Free PBGA (23 mm x 23 mm x 2.03 mm) BY484 484-ball Leaded PBGA (23 mm x 23 mm x 2.03 mm) BG484 O0.50~O0.70(484X) PIN #1 CORNER 1 3 2 5 4 7 6 9 8 10 15 13 11 12 14 19 17 16 18 21 20 21 22 22 O1.00(3X) REF. 19 20 18 16 14 9 11 13 15 12 10 7 8 1 3 5 6 4 2 A B C D E F G H J K L M N P R T U V W Y AA AB 21.00 23.000.20 20.00 REF. 1.00 A B C D E F G H J K L M N P R T U V W Y AA AB 17 1.00 -B- 21.00 3.20*45(4x) -A20.00 REF. 23.000.20 0.35 C 0.20 C f 0.25 C 30 TYP. f 0.97 REF. 0.20(4X) Document #: 38-06082 Rev. *G 2.03 0.13 0.40~0.60 SEATING PLANE 0.56 REF. -C- Package Weight - 2.0 grams Jedec Outline - Design Guide 4.14 51-85218-** Page 48 of 51 FullFlex Package Diagrams (continued) 484-ball Lead-Free PBGA (27 mm x 27 mm x 2.33 mm) BY484S 484-ball Leaded PBGA (27 mm x 27 mm x 2.33 mm) BG484S 001-07825-** FullFlex is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are trademarks of their respective holders. Document #: 38-06082 Rev. *G Page 49 of 51 FullFlex Document History Page Document Title: FullFlexTM Synchronous SDR Dual-Port SRAM Document Number: 38-06082 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 302411 See ECN YDT New data sheet *A 334036 See ECN YDT Corrected typo on page 1 Reproduced PDF file to fix formatting errors *B 395800 See ECN SPN Added statement about no echo clocks for flow-through mode Updated electrical characteristics Added note 16 and 17 (1.5V timing) Added note 33 (timing for x18 devices) Updated input edge rate (note 34) Updated table 5 on deterministic access control logic Added description of busy readback in deterministic access control section Changed dummy write descriptions Updated ZQ pins connection details Updated note 24, B0 to BE0 Added power supply requirements to MRST and VC_SEL Added note 4 (VIM disable) Updated supply voltage to ground potential to 4.1V Updated parameters on table 15 Updated and added parameters to table 16 Updated x72 pinout to SDR only pinout Updated 484 PBGA pin diagram Updated the pin definition of MRST Updated the pin definition of VC_SEL Updated READY description to include Wired OR note Updated master reset to include wired OR note for READY Updated minimum VOH value for the 1.8V LVCMOS configuration Updated electrical characteristics to include IOH and IOL values Updated electrical characteristics to include READY Added IIX3 Updated maximum input capacitance Added Notes 33 and 34Removed Notes 15 and 17 Updated Pin Definitions for CQ0, CQ0, CQ1, and CQ1 Removed -100 Speed bin from Table.1 Selection Guide Changed voltage name from VDDQ to VDDIO Changed voltage name from VDD to VCORE Moved the Mailbox Interrupt Timing Diagram to be the final timing diagram Updated the Package Type for the CYD36S18V18 parts Updated the Package Type for the CYD36S18V18 parts Updated the Package Type for the CYD18S18V18 parts Updated the Package Type for the CYD18S36V18 parts Included the Package Diagram for the 256-Ball FBGA (19 x 19 mm) BW256 Included an OE Controlled Write for Flow-through Mode Switching Waveform Included a Read with Echo Clock Switching Waveform Updated Figure 5 and Figure 6 Updated Electrical Characteristics for READY VOH and READY V Updated Electrical Characteristics for VOH and VOL for the -167 and -133 speeds Included a Unit column for Table 5 Removed Switching Characteristic tCA from chart Included tOHZ in Switching Waveform OE Controlled Write for Pipelined Mode Included tCKLZ2 in Waveform Read-to-Write-to-Read for Flow-through Mode *C 402238 SEE ECN KGH Updated AC Test Load and Waveforms Included FullFlex36 SDR 484-ball BGA Pinout (Top View) Included FullFlex18 SDR 484-ball BGA Pinout (Top View) Included Timing Parameter tCORDY Document #: 38-06082 Rev. *G Page 50 of 51 (c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. FullFlex Document Title: FullFlexTM Synchronous SDR Dual-Port SRAM Document Number: 38-06082 REV. ECN NO. Issue Date Orig. of Change *D 458131 SEE ECN YDT Changed ordering information with lead-free part numbers Removed VC_SEL Added I/O and core voltage adders Removed references to bin drop for LVTTL/2.5V LVCMOS and 1.5V core modes Updated Cin and Cout Updated ICC, ISB1, ISB2 and ISB3 tables Updated busy address read back timing diagram Added HTSL input waveform Removed HSTL (AC) from DC tables Added 484-ball 27 mmx27 mmx2.33 mm PBGA package *E 470031 SEE ECN YDT Changed VOL of 1.8V LVCMOS to 0.45V Updated tRSF VREF is DNU when HSTL is not used Formatted pin description table Changed VDDIO pins for 36M x 36 and 36M x 18 pinouts Changed 36Mx72 JTAG IDCODE *F 500001 SEE ECN YDT DLL Change, added Clock Input Cycle to Cycle Jitter Modified DLL description Changed Input Capaciance Table Changed tCCS number Added note 31 *G 627539 SEE ECN QSL change all NC to DNU corrected switching waveform for (CQEN = High) from both Pipeline and Flowthrough mode to only pipeline mode Modified Master Reset Description Modified switching characteristics tables, extraced signals effected by the DLL into one table and combine all other signals into one table updated package name Added footnote for tHD, tHAC and tSAC changed note 26 description Document #: 38-06082 Rev. *G Description of Change Page 51 of 51