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FSBB15CH60F Motion SPM® 3 Series
January 2014
©2006 Fairchild Semiconductor Corporation 1www.fairchildsemi.com
FSBB15CH60F Rev. C6
FSBB15CH60F
Motion SPM® 3 Series
Features
• UL Certified No. E209204 (UL1557)
• 600 V - 15 A 3-Phase IGBT Inverter with Integral Gate
Drivers and Protection
• Built-In Thermal Shutdown Function
• Low-Loss, Short-Circuit Rated IGBTs
• Very Low Thermal Resistance Using Al2O3 DBC Sub-
strate
• Dedicated Vs Pins Simplify PCB Layout
• Separate Open-Emitter Pins from Low-Side IGBTs for
Three-Phase Current Sensing
• Single-Grounded Power Supply
• Isolation Rating: 2500 Vrms / min.
Applications
• Motion Control - Home Appliance / Industrial Motor
Related Resources
• AN-9035 - Motion SPM 3 Series Ver.2 User’s Guide
General Description
FSBB15CH60F is a Motion SPM® 3 module providing a
fully-featured, high-performance inverter output stage
for AC Induction, BLDC, and PMSM motors. These mod-
ules integrate optimized gate drive of the built-in IGBTs
to minimize EMI and losses, while also providing multi-
ple on-module protection features including under-volt-
age lockouts, over-current shutdown, and fault reporting.
The built-in, high-speed HVIC requires only a single sup-
ply voltage and translates the incoming logic-level gate
inputs to the high-voltage, high-current drive signals
required to properly drive the module's internal IGBTs.
Separate negative IGBT terminals are availabl e for each
phase to support the widest variety of control algorithms.
Package Mark ing and Ordering Information
Figure 1. Package Overview
Device Device Marking Package Packing Type Quantity
FSBB15CH60F FSBB15CH60F SPMCA-027 Rail 10
FSBB15CH60F Motion SPM® 3 Series
©2006 Fairchild Semiconductor Corporation 2www.fairchildsemi.com
FSBB15CH60F Rev. C6
Integrated Power Functions
• 600 V - 15 A IGBT inverter for three-phase DC / AC power conversion (please refer to Figure 3)
Integrated Drive, Protection and System Control Functions
• For inverter high-side IGBTs: gate drive circuit, high-voltage isolated high-speed level shifting
control circuit Under-Voltage Lock-Out Protection (UVLO)
Note: Available bootstrap circuit example is given in Figures 10 and 11.
• For inverter low-side IGBTs: gate drive circuit, Short-Circuit Protection (SCP)
control supply circuit Under-Voltage Lock-Out Protection (UVLO)
• Fault signaling: corresponding to UVLO (low-side supply) and SC faults
• Input interface: active-HIGH interface, works with 3.3 / 5 V logic, Schmitt-trigger input
Pin Configuration
Figure 2. Top View
(21) N U
(22) N V
(23) N W
(27) P
U
(25) V
(26) W
Case Temperature (T
C)
Detecting Point
DBC Substrate
(21) N U
(22) N V
(23) N W
(27) P
(24)
(25) V
(26) W
Case Temperature (T
C)
Detecting Point
(1) VCC(L)
(2) COM
(3) IN (UL)
(4) IN (VL)
(5) IN (WL)
(6) VFO
(15) VB(V)
(16) V S(V)
(17) IN (WH)
(18) VCC(WH)
(19) V B(W)
(20) V S(W)
(7) C FOD
(8) C SC
(9) I N (UH)
(10) VCC(UH)
(11) VB(U)
(12) V S(U)
(13) IN(VH)
(14) V CC(VH)
(1) VCC(L)
(2) COM
(3) IN (UL)
(4) IN (VL)
(5) IN (WL)
(6) VFO
(15) VB(V)
(16) V S(V)
(17) IN (WH)
(18) VCC(WH)
(19) V B(W)
(20) V S(W)
(7) C FOD
(8) C SC
(9) I N (UH)
(10) VCC(UH)
(11) VB(U)
(12) V S(U)
(13) IN(VH)
(14) V CC(VH)
13.7
19.2
(21) N U
(22) N V
(23) N W
(27) P
U
(25) V
(26) W
Case Temperature (T
C)
Detecting Point
DBC Substrate
(21) N U
(22) N V
(23) N W
(27) P
(24)
(25) V
(26) W
Case Temperature (T
C)
Detecting Point
(1) VCC(L)
(2) COM
(3) IN (UL)
(4) IN (VL)
(5) IN (WL)
(6) VFO
(15) VB(V)
(16) V S(V)
(17) IN (WH)
(18) VCC(WH)
(19) V B(W)
(20) V S(W)
(7) C FOD
(8) C SC
(9) I N (UH)
(10) VCC(UH)
(11) VB(U)
(12) V S(U)
(13) IN(VH)
(14) V CC(VH)
(1) VCC(L)
(2) COM
(3) IN (UL)
(4) IN (VL)
(5) IN (WL)
(6) VFO
(15) VB(V)
(16) V S(V)
(17) IN (WH)
(18) VCC(WH)
(19) V B(W)
(20) V S(W)
(7) C FOD
(8) C SC
(9) I N (UH)
(10) VCC(UH)
(11) VB(U)
(12) V S(U)
(13) IN(VH)
(14) V CC(VH)
(1) VCC(L)
(2) COM
(3) IN (UL)
(4) IN (VL)
(5) IN (WL)
(6) VFO
(15) VB(V)
(16) V S(V)
(17) IN (WH)
(18) VCC(WH)
(19) V B(W)
(20) V S(W)
(7) C FOD
(8) C SC
(9) I N (UH)
(10) VCC(UH)
(11) VB(U)
(12) V S(U)
(13) IN(VH)
(14) V CC(VH)
(1) VCC(L)
(2) COM
(3) IN (UL)
(4) IN (VL)
(5) IN (WL)
(6) VFO
(15) VB(V)
(16) V S(V)
(17) IN (WH)
(18) VCC(WH)
(19) V B(W)
(20) V S(W)
(7) C FOD
(8) C SC
(9) I N (UH)
(10) VCC(UH)
(11) VB(U)
(12) V S(U)
(13) IN(VH)
(14) V CC(VH)
13.7
19.2
13.7
19.2
FSBB15CH60F Motion SPM® 3 Series
©2006 Fairchild Semiconductor Corporation 3www.fairchildsemi.com
FSBB15CH60F Rev. C6
Pin Descriptions
Pin Number Pin Name Pin Description
1V
CC(L) Low-Side Common Bias Voltage for IC and IGBTs Driving
2 COM Common Supply Ground
3IN
(UL) Signal Inpu t for Low-Side U-Phase
4IN
(VL) Signal Input for Low-Side V-Phase
5IN
(WL) Signal Input for Low-Side W-Phase
6V
FO Fault Output
7C
FOD Capacitor for Fault Output Duration Selection
8C
SC Capacitor (Low-pass Filter) for Short-Circuit Current Detection Input
9IN
(UH) Signal Input for High-Side U-Phase
10 VCC(UH) High-Side Bias Voltage for U-Phase IC
11 VB(U) High-Side Bias Voltage for U-Phase IGBT Driving
12 VS(U) High-Side Bias Voltage Ground for U-Phase IGBT Driving
13 IN(VH) Signal Input for High-Side V-Phase
14 VCC(VH) High-Side Bias Voltage for V-Phase IC
15 VB(V) High-Side Bias Voltage for V-Phase IGBT Driving
16 VS(V) High-Side Bias Voltage Ground for V-Phase IGBT Driving
17 IN(WH) Signal Input for High-Side W Phase
18 VCC(WH) High-Side Bias Voltage for W-Phase IC
19 VB(W) High-Side Bias Voltage for W-Phase IGBT Driving
20 VS(W) High-Side Bias Voltage Ground for W-Phase IGBT Driving
21 NUNegative DC-Link Input for U-Phase
22 NVNegative DC-Link Input for V-Phase
23 NWNegative DC-Link Input for W-Phase
24 U Output for U-Phase
25 V Output for V-Phase
26 W Output for W-Phase
27 P Positive DC-Link Input
FSBB15CH60F Motion SPM® 3 Series
©2006 Fairchild Semiconductor Corporation 4www.fairchildsemi.com
FSBB15CH60F Rev. C6
Internal Equivalent Circuit and Input/Output Pins
Figure 3. Internal Block Diagram
1st Notes:
1. Inverter low-side is composed of three IGBTs, freewheeling diodes for each IGBT, and one control IC. It has gate drive and protection functions.
2. Inverter power side is composed of four inverter DC-link input terminals and three inverter output terminals.
3. Inverter high-side is composed of three IGBTs, freewheeling diodes, and three drive ICs for each IGBT.
COM
VCC
IN(UL)
IN(VL)
IN(WL)
VFO
C(FOD)
C(SC)
OUT(UL)
OUT(VL)
OUT(WL)
NU (21)
NV (22)
NW (23)
U (24)
V (25)
W (26)
P (27)
(20) VS(W)
(19) VB(W)
(16) VS(V)
(15) VB(V)
(8) C SC
(7) CFOD
(6) VFO
(5) IN(W L)
(4) IN(VL)
(3) IN(UL)
(2) C OM
(1) VCC(L)
VCC
VB
OUT
COM
VS
IN
VB
VS
OUT
IN
COM
VCC
VCC
VB
OUT
COM VS
IN
(18) VCC(WH)
(17) IN(WH)
(14) VCC(VH)
(13) IN(VH)
(12) VS(U)
(11) VB(U)
(10) VCC(UH)
(9) IN(UH)
VSL
FSBB15CH60F Motion SPM® 3 Series
©2006 Fairchild Semiconductor Corporation 5www.fairchildsemi.com
FSBB15CH60F Rev. C6
Absolute Maximum Ratings (TJ = 25°C, unless otherwise specified.)
Inverter Part
2nd Notes:
1. The maximum junction temperature rating of the power chips integrated within the Motion SPM® 3 product is 150C (at TC 100C). However, to insure safe operation of the
Motion SPM 3 product, the average junction temperature should be limited to TJ(ave) 125C (at TC 100C)
Control Part
Total System
Thermal Resistance
2nd Notes:
2. For the measurement point of case temperature(TC), please refer to Figure 2.
Symbol Parameter Conditions Rating Unit
VPN Supply Voltage Applied between P- NU, NV, NW450 V
VPN(Surge) Supply Voltage (Surge) Applied between P- NU, NV, NW500 V
VCES Collector - Emitter Voltage 600 V
± ICEach IGBT Collector Current TC = 25°C 15 A
± ICP Each IGBT Collector Current (Peak) TC = 25°C, Under 1ms Pulse Width 30 A
PCCollector Dissipation TC = 25°C per Chip 50 W
TJOperating Junction Tem perature (2nd Note 1) -20 ~ 125 °C
Symbol Parameter Conditions Rating Unit
VCC Control Supply Voltage Applied between VCC(UH), VCC(VH), VCC(WH), VCC(L) -
COM 20 V
VBS High-Side Control Bias
Voltage Applied between VB(U) - VS(U), VB(V) - VS(V), VB(W) -
VS(W)
20 V
VIN Input Signal Voltage Applied between IN(UH), IN(VH), IN(WH), IN(UL), IN(VL),
IN(WL) - COM -0.3 ~ 17 V
VFO Fault Output Supply Voltage Applied between VFO - COM -0.3 ~ VCC+0.3 V
IFO Fault Output Current Sink Current at VFO Pin 5 mA
VSC Current-Sensing Input Voltage Applied between CSC - COM -0.3 ~ VCC+0.3 V
Symbol Parameter Conditions Rating Unit
VPN(PROT) Self-Protection Supply Voltage Limit
(Short-Circuit Protection Capability) VCC = VBS = 13.5 ~ 16.5 V
TJ = 125°C, Non-Repetitive, < 2 s400 V
TCModule Case Operation Temperature -20CTJ 125C, See Figure 2 -20 ~ 100 °C
TSTG Storage Temperature -40 ~ 125 °C
VISO Isolation Voltage 60 Hz, Sinusoidal, AC 1 Minute, Connect
Pins to Heat Sink Plate 2500 Vrms
Symbol Parameter Condition Min. Typ. Max. Unit
Rth(j-c)Q Junction to Case Thermal
Resistance Inverter IGBT Part (per 1 / 6 module) - - 2.02 °C/W
Rth(j-c)F Inverter FWD Part (per 1 / 6 module) - - 3.15 °C/W
FSBB15CH60F Motion SPM® 3 Series
©2006 Fairchild Semiconductor Corporation 6www.fairchildsemi.com
FSBB15CH60F Rev. C6
Electrical Characteristics (TJ = 25°C, unless otherwise specified.)
Inverter Part
2nd Notes:
3. tON and tOFF include the propagation delay of the internal drive IC. tC(ON) and tC(OFF) are the switchin g time of IGBT itself under the give n gate driv ing condition inte rnally. Fo r
the detailed information, please see Figure 4.
Figure 4. Switching Time Definition
Symbol Parameter Conditions Min. Typ. Max. Unit
VCE(SAT) Collector - Emitter
Saturation Voltage VCC = VBS = 15 V
VIN = 5 V IC = 15 A, TJ = 25°C - - 2.3 V
VFFWDi Forward Voltage VIN = 0 V IC = 15 A, TJ = 25°C - - 2.1 V
HS tON Switching Times VPN = 300 V, VCC = VBS = 15 V
IC = 15 A
VIN = 0 V 5 V, Ind uctive Load
(2nd Note 3)
-0.4- s
tC(ON) -0.28- s
tOFF -0.67- s
tC(OFF) -0.35- s
trr -0.10- s
LS tON VPN = 300 V, VCC = VBS = 15 V
IC = 15 A
VIN = 0 V 5 V, Ind uctive Load
(2nd Note 3)
-0.55- s
tC(ON) -0.24- s
tOFF -0.73- s
tC(OFF) -0.34- s
trr -0.10- s
ICES Collector - Emitter
Leakage Current VCE = VCES - - 250 A
VCE IC
VIN
tON tC(ON)
VIN(ON) 10% IC10% VCE
90% IC
100% IC
trr
100% IC
0
VCE
IC
VIN
tOFF tC(OFF)
VIN(OFF) 10% VCE 10% IC
(a) tu rn-o n (b ) tu rn -of f
FSBB15CH60F Motion SPM® 3 Series
©2006 Fairchild Semiconductor Corporation 7www.fairchildsemi.com
FSBB15CH60F Rev. C6
Electrical Characteristics (TJ = 25°C, unless otherwise specified.)
Control Part
2nd Notes:
4. Short-circuit protection is functioning only at the low-sides.
5. The fault-out pulse width tFOD depends on the capacitance value of CFOD according to the following approximate equation: CFOD = 18.3 x 10-6 x tFOD [F]
Recommended Operating Conditions
Symbol Parameter Conditions Min. Typ. Max. Unit
IQCCL Quiescent VCC Supply
Current VCC = 15 V
IN(UL, VL, WL) = 0 V VCC(L) - COM - - 23 mA
IQCCH VCC = 15 V
IN(UH, VH, WH) = 0 V VCC(UH), VCC(VH), VCC(WH)
- COM - - 100 A
IQBS Quiescent VBS Supply Current VBS = 15 V
IN(UH, VH, WH) = 0 V VB(U) - VS(U), VB(V) - VS(V),
VB(W) - VS(W)
- - 500 A
VFOH Fault Output Voltage VSC = 0 V, VFO Circuit: 4.7 k to 5 V Pull-up 4.5 - - V
VFOL VSC = 1 V, VFO Circuit: 4.7 k to 5 V Pull-up - - 0.8 V
VSC(ref) Short Circuit Current Trip Level VCC = 15 V (2nd Note 4) 0.45 0.50 0.55 V
TSD Over-Temperature Protection Temperature at LVIC 125 145 175 V
TSD Over-Temperature Protection
Hysterisis Temperature at LVIC - 18 - V
UVCCD Supply Circuit Under-Voltage
Protection Detection Level 10.7 11.9 13.0 V
UVCCR Reset Level 11.2 12.4 13.2 V
UVBSD Detection Level 10.1 11.3 12.5 V
UVBSR Reset Level 10.5 11.7 12.9 V
tFOD Fault-out Pulse Width CFOD = 33 nF (2nd Note 5) 1.0 1.8 - ms
VIN(ON) ON Threshold Voltage Applied between IN(UH), IN(VH), IN(WH), IN(UL),
IN(VL), IN(WL) - COM 3.0 - - V
VIN(OFF) OFF Threshold Voltage - - 0.8 V
Symbol Parameter Conditions Min. Typ. Max. Unit
VPN Supply Voltage Applied between P - NU, NV, NW- 300 400 V
VCC Control Supply Voltage Applied between VCC(UH), VCC(VH), VCC(WH),
VCC(L) - COM 13.5 15 16.5 V
VBS High-Side Bias Voltage Applied between VB(U) - VS(U), VB(V) - VS(V),
VB(W) - VS(W)
13.0 15 18.5 V
dVCC / d t,
dVBS / dt Control Supply Variation -1 - 1 V / s
tdead Blanking Time for Preventing
Arm-Short For Each Input Signal 2.0 - - s
fPWM PWM Input Signal -20C TC 100°C, -20C TJ 125°C - - 20 kHz
VSEN Voltage for Current Sensing Applied between NU, NV, NW - COM
(Including Surge Voltage) -4 4 V
FSBB15CH60F Motion SPM® 3 Series
©2006 Fairchild Semiconductor Corporation 8www.fairchildsemi.com
FSBB15CH60F Rev. C6
Mechanical Characteristics and Ratings
Figure 5. Flatness Measurement Position
Parameter Conditions Min. Typ. Max. Unit
Mounting Torque Mounting Screw: M3 Recommended 0.62 N•m 0.51 0.62 0.72 N•m
Device Flatness See Figure 5 0 - +120 m
Weight - 15.00 - g
( + )
( + )
( + )
( + )
FSBB15CH60F Motion SPM® 3 Series
©2006 Fairchild Semiconductor Corporation 9www.fairchildsemi.com
FSBB15CH60F Rev. C6
Time Charts of Protective Function
a1 : Control supply voltage rises: after the voltage rises UVCCR, the circuits start to operate when next input is applied.
a2 : Normal operation: IGBT ON and carrying current.
a3 : Under-Voltage detection (UVCCD).
a4 : IGBT OFF in spite of control input condition.
a5 : Fault output operation starts.
a6 : Under-Voltage reset (UVCCR).
a7 : Normal operation: IGBT ON and carrying current.
Figure 6. Under-Voltage Protection (Low-Side)
b1 : Control supply voltage rises: after the voltage reaches UVBSR, the circuits start to operate when next input is applied.
b2 : Normal operation: IGBT ON and carrying current.
b3 : Under-Voltage detection (UVBSD).
b4 : IGBT OFF in spite of control input condition, but there is no fault output signal.
b5 : Under-Voltage reset (UVBSR).
b6 : Normal operation: IGBT ON and carrying current.
Figure 7. Under-Voltage Protection (High-Side)
Input Signal
Output Current
Fault Output Signal
Control
Supply Voltage
RESET
UVCCR
Protection
Circuit State SET RESET
UVCCD
a1 a3
a2 a4
a6
a5
a7
Input Signal
Output Current
Fault Output Signal
Control
Supply Voltage
RESET
UVBSR
Protection
Circuit State SET RESET
UVBSD
b1 b3
b2 b4 b6
b5
High-level (no fault output)
FSBB15CH60F Motion SPM® 3 Series
©2006 Fairchild Semiconductor Corporation 10 www.fairchildsemi.com
FSBB15CH60F Rev. C6
(with the external shunt resistance and CR connection)
c1 : Normal operation: IGBT ON and carrying current.
c2 : Short-Circuit current detection (SC trigger).
c3 : Hard IGBT gate interrupt.
c4 : IGBT turns OFF.
c5 : Fault output timer operation starts: the pulse width of the fault output signal is set by the external capacitor CFO.
c6 : Input “LOW”: IGBT OFF state.
c7 : Input “HIGH”: IGBT ON state, but during the active period of fault output, the IGBT doesn’t turn ON.
c8 : IGBT OFF state.
Figure 8. Short-Circuit Protection (Low-Side Operation Only)
FSBB15CH60F Motion SPM® 3 Series
©2006 Fairchild Semiconductor Corporation 11 www.fairchildsemi.com
FSBB15CH60F Rev. C6
Figure 9. Recommended MCU I/O Interface Circuit
3rd Notes:
1. RC coupling at each input (parts shown dotted) might change depending on the PWM control scheme in the application and the wiring impedance of the application’s printed
circuit bo ar d. Th e M ot io n S P M® 3 Product input signal section integrates a 3.3 k(typ.) pull-down resistor. Therefore, when using an external filtering resistor, pay attention to
the signal voltage drop at input terminal.
2. The logic input works with standard CM OS or LSTTL outputs.
Figure 10. Recommended Bootstrap Operation Circuit and Parameters
3rd Notes:
3. It would be recommended that the bootstrap diode, DBS, has soft and fast recovery characteristics.
4. The bootstrap resistor (RBS) should be three times greater than RE(H). The recommended value of RE(H) is 5.6 , but it can be increased up to 20 (maximum ) for a slow er dv/
dt of high-side.
5. The ceramic capacitor placed between VCC - COM should be over 1 F and mounted as close t o the pins of the Motion SPM 3 product as possible.
MCU
SPM
COM
+5 V
1 nF
4.7 k
,,
IN(UL) IN(VL) IN(WL)
,,
IN(UH) IN(VH) IN(WH)
VFO
100
1 nF
RPF =
CPF=
+15 V
22 µF0.1 µF
1000 µF1 µF
One-Leg Diagram of
Motion SPM 3 Product
Vcc
IN
COM
VB
HO
VS
Vcc
IN
COM
OUT
Inverter
Output
P
N
These values depend on PWM control algorithm.
DBS
RBS
RE(H)
VSL
FSBB15CH60F Motion SPM® 3 Series
©2006 Fairchild Semiconductor Corporation 12 www.fairchildsemi.com
FSBB15CH60F Rev. C6
Figure 11. Typical Application Circuit
4th Notes:
1. To avoid malfunction, the wiring of each input should be as short as possible (less than 2 - 3 cm).
2. By virtue of integrating an application-specific type of HVIC inside the Moti on SPM® 3 product, direct coupling to MCU terminals without any optocoupler or transformer isola-
tion is possible.
3. VFO output is open-collector type. This signal line should be pulled up to the positive side of the 5 V power supply with approximately 4.7 k resistance (please refer to Figure
9).
4. CSP15 of around seven times larger than bootstrap capacitor CBS is recommended.
5. VFO output pulse width sho uld be deter mined by connecting an externa l capa citor (C FOD) be tween CFOD (pin 7) and COM (pi n 2). (E xam ple : if CFOD = 33 nF, then tFO = ms
(typ.)) Please refer to the 2nd note 5 for calculation method.
6. Input signal is active-HIG H type . Ther e is a 3.3 kresistor inside the IC to pull do wn ea ch inp ut signal line t o GN D. Wh en em ploying R C couplin g circuits, set up such RC cou-
ple that input signal agree with turn-off / turn-on threshold voltage.
7. To prevent errors of the protection function, the wiring around RF and CSC should be as short as possible.
8. In the short-circuit protection circuit, please select the RFCSC time constant in the range 1.5 ~ 2 s.
9. Each capacitor should be mounted as close to the pins of the Motion SPM 3 product as possible.
10. To prevent surge destr uction, the wiring between the smoothing capacitor and the P & GND pins should be as short as possible. The use of a high-frequency non-inductive
capacitor of around 0.1 ~ 0.22 F between the P & GND pins is recommended.
11. Relays are used in almost every systems of electrical equipment in home appliances. In these cases, th ere should be sufficient distance between the MCU and the relays.
12. CSPC15 should be over 1 F and mounted as c lose to the pi ns of the Motion SPM 3 product as possible.
Fault
+15 V
CBS CBSC
RBS DBS
CBS CBSC
RBS DBS
CBS CBSC
RBS DBS
CSP15 CSPC15
CFOD
+5 V
RPF
CBPF
RS
M
Vdc
CDCS
Gating UH
Gating V H
Gating WH
Gating WL
Gating V L
Gating UL
CPF
M
C
U
RFU
RFV
RFW
RSU
RSV
RSW
CFU
CFV
CFW
W-Phase Current
V-Phase Current
U-Phase Curr en t
RF
COM
VCC
IN(UL)
IN(VL)
IN(WL)
VFO
C(FOD)
C(SC)
OUT(UL)
OUT(VL)
OUT(WL)
NU(21)
NV(22)
NW(23)
U (24)
V (25)
W (26)
P (27)
(20) VS(W)
(19) VB(W)
(16) VS(V)
(15) VB(V)
(8) CSC
(7) CFOD
(6) VFO
(5) IN(WL)
(4) IN(VL)
(3) IN(UL)
(2) COM
(1) VCC(L)
VCC
VB
OUT
COM VS
IN
VB
VS
OUT
IN
COM
VCC
VCC
VB
OUT
COM VS
IN
(18) VCC(WH)
(17) I N(WH)
(14) VCC(VH)
(13) IN(VH)
(12) VS(U)
(11) VB(U)
(10) VCC(UH)
(9) IN(UH)
Input Signal for Short-
Circuit Protection
CSC
RE(UH)
VSL
RE(VH)
RE(WH)
FSBB15CH60F Motion SPM® 3 Series
©2006 Fairchild Semiconductor Corporation 13 www.fairchildsemi.com
FSBB15CH60F Rev. C6
Detailed Package Outline Drawings
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or data on the drawing and contact a FairchildSemiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide therm and conditions,
specifically the the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/MO/MOD27BA.pdf
FSBB15CH60F Motion SPM® 3 Series
©2006 Fairchild Semiconductor Corporation 14 www.fairchildsemi.com
FSBB15CH60F Rev. C6
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