LTC2941IMS8E#PBF - ANALOG DEVICES

LTC2941

Rev. C

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TYPICAL APPLICATION

DESCRIPTION

Battery Gas Gauge with I2C Interface

The LT C

2941 measures battery charge state in battery-

supplied handheld PC and portable product applications.

Its operating range is perfectly suited for single-cell Li-Ion

batteries. A precision coulomb counter integrates current

through a sense resistor between the battery’s positive

terminal and the load or charger. The measured charge

is stored in internal registers. An SMBus/I

C interface

accesses and configures the device.

The LTC2941 features programmable high and low

thresholds for accumulated charge. If a threshold is

exceeded, the device communicates an alert using either

the SMBus alert protocol or by setting a flag in the inter-

nal status register.

The LTC2941 requires only a single low value external

sense resistor to set the current range.

FEATURES

APPLICATIONS

n Indicates Accumulated Battery Charge

andDischarge

n High Accuracy Analog Integration

n High Side Sense

n 1% Charge Accuracy

n ±50mV Sense Voltage Range

n SMBus/I2C Interface

n Configurable Alert Output/Charge Complete Input

n 2.7V to 5.5V Operating Range

n Quiescent Current Less Than 100µA

n Small 6-Pin 2mm × 3mm DFN and 8-Lead

MSOPPackages

n Low Power Handheld Products

n Cellular Phones

n MP3 Player

n Cameras

n GPS

Total Charge Error vs

Differential Sense Voltage

SENSE+

I2C/SMBus

TO HOST SENSE–

CHARGER

LTC2941

AL/CC

SDA

LOAD

0.1µF

2941 TA01a

1-CELL

Li-Ion

RSENSE

100mΩ

SCL

GND

VSENSE (mV)

0.1

–1.0

CHARGE ERROR (%)

–0.5

–1.5

0.5

1.0

1 10 100

2941 TA01b

–2.0

VSENSE+ = 3.6V

2.0

1.5

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LTC2941

Rev. C

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Supply Voltage (SENSE+) ............................. –0.3V to 6V

SCL, SDA, AL/CC ......................................... –0.3V to 6V

SENSE– .................................. –0.3V to (VSENSE+ + 0.3V)

(Notes 1, 2)

TOP VIEW

SENSE–

AL/CC

SDA

SENSE+

GND

SCL

DCB PACKAGE

6-LEAD (2mm × 3mm) PLASTIC DFN

TJMAX = 150°C, θJA = 120°C/W

EXPOSED PAD (PIN 7), DO NOT CONNECT

SENSE+

GND

SCL

DNC

SENSE–

AL/CC

SDA

DNC

TOP VIEW

MSE PACKAGE

8-LEAD PLASTIC MSOP

PIN 4, PIN 5 AND EXPOSED PAD (PIN 9), DO NOT CONNECT

ORDER INFORMATION

PIN CONFIGURATION

ABSOLUTE MAXIMUM RATINGS

Lead Free Finish

TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2941CDCB#TRMPBF LTC2941CDCB#TRPBF LFKQ 6-Lead (2mm × 3mm) Plastic DFN 0°C to 70°C

LTC2941IDCB#TRMPBF LTC2941IDCB#TRPBF LFKQ 6-Lead (2mm × 3mm) Plastic DFN –40°C to 85°C

TUBE TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2941CMS8E#PBF LTC2941CMS8E#TRPBF LTGVY 8-Lead Plastic MSOP 0°C to 70°C

LTC2941IMS8E#PBF LTC2941IMS8E#TRPBF LTGVY 8-Lead Plastic MSOP –40°C to 85°C

TRM = 500 pieces.

Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

Operating Ambient Temperature Range

LTC2941C ................................................ 0°C to 70°C

LTC2941I..............................................–40°C to 85°C

Storage Temperature Range .................... –65°C to 150°

LTC2941

Rev. C

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ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 2)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Power Requirements

VSENSE+Supply Voltage 2.7 5.5 V

ISUPPLY Supply Current (Note 3) Device On l70 100 µA

Shutdown l2.5 µA

Shutdown, VSENSE+ ≤ 4.2V 1 µA

VUVLO Undervoltage Lockout Threshold VSENSE+ Falling, DCB Package

VSENSE+ Falling, MSE Package

2.5

2.45

2.6

2.7

Coulomb Counter

VSENSE Sense Voltage Differential Input Range VSENSE+ – VSENSE–l±50 mV

Differential Input Resistance, Across

SENSE+ and SENSE– (Note 7)

400 kΩ

qLSB Charge LSB (Note 4) Prescaler M = 128 (Default),

RSENSE = 50mΩ

0.085 mAh

TCE Total Charge Error (Note 5) 10mV ≤ |VSENSE | ≤ 50mV DC ±1 %

10mV ≤ |VSENSE | ≤ 50mV, DC VSENSE+ ≤ 4.2V l±1.5 %

1mV ≤ |VSENSE | ≤ 50mV DC (Note 7) l±3.5 %

VBAT Alert VBAT Alert Threshold VSENSE+ Falling, B[7:6] = 01 l2.75 2.8 2.85 V

VSENSE+ Falling, B[7:6] = 10 l2.85 2.9 2.95 V

VSENSE+ Falling, B[7:6] = 11 l2.95 3 3.05 V

Digital Inputs and Digital Outputs

VITH Logic Input Threshold, AL/CC,

SCL,SDA

l0.3 •

VSENSE+

0.7 •

VSENSE+

VOL Low Level Output Voltage, AL/CC, SDA I = 3mA l0.4 V

IIN Input Leakage, AL/CC, SCL, SDA VIN = VSENSE+/2 l1 µA

CIN Input Capacitance, AL/CC, SCL, SDA (Note 7) l10 pF

tPCC Minimum Charge Complete (CC)

PulseWidth

1 µs

I2C Timing Characteristics

fSCL(MAX) Maximum SCL Clock Frequency l400 900 kHz

tBUF(MIN) Bus Free Time Between STOP/START l1.3 µs

tSU,STA(MIN) Minimum Repeated START

Set-UpTime

l600 ns

tHD,STA(MIN) Minimum Hold Time (Repeated)

START Condition

l600 ns

tSU,STO(MIN) Minimum Set-Up Time for

STOPCondition

l600 ns

LTC2941

Rev. C

For more information www.analog.com

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 2)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

tSU,DAT(MIN) Minimum Data Set-Up Time Input l100 ns

tHD,DATI(MIN) Minimum Data Hold Time Input l0 µs

tHD,DATO Data Hold Time Output l0.3 0.9 µs

tOf Data Output Fall Time (Notes 6, 7) l20 + 0.1

• CB

300 ns

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All currents into pins are positive, all voltages are referenced to

GND unless otherwise specified

Note 3: ISUPPLY = ISENSE+ + ISENSE–

Note 4: The equivalent charge of an LSB in the accumulated charge

registers (C, D) depends on the value of RSENSE and the setting of the

internal prescaling factor M. It is calculated by:

LSB =0.085mAh • 50mΩ

SENSE

•M

128

See Choosing RSENSE and Coulomb Counter Prescaler“M”B[5:3] section

for more information.

1mAh = 3.6A • s = 3.6C (coulomb), 0.085mAh = 306mC.

Note 5: Deviation of qLSB from its nominal value.

Note 6: CB = capacitance of one bus line in pF (10pF ≤ CB ≤ 400pF).

Note 7: Guaranteed by design, not subject to test.

TIMING DIAGRAM

tSU, DAT

tSU, STO

tSU, STA tBUF

tHD, STA

tHD, DATO,

tHD, DATI

tHD, STA

START

CONDITION

STOP

CONDITION

REPEATED START

CONDITION

START

CONDITION

SDA

SCL 2941 F01

tof

Figure1. Definition of Timing on I2C Bus

LTC2941

Rev. C

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TYPICAL PERFORMANCE CHARACTERISTICS

Total Charge Error

vs Differential Sense Voltage

Total Charge Error

vs Supply Voltage Total Charge Error vs Temperature

Supply Current vs Supply Voltage

Shutdown Supply Current

vs Supply Voltage

VSENSE (mV)

0.1

–1

CHARGE ERROR (%)

–2

1 10 100

2941 G01

–3

VSENSE+ = 2.7V

VSENSE+ = 4.2V

VSENSE+ (V)

2.5

CHARGE ERROR (%)

–1.00

–0.50

–0.25

1.00

0.25

3.5 4.5 5.0

2941 G02

–0.75

0.50

0.75

3.0 4.0 5.5 6.0

VSENSE = –50mV

VSENSE = –10mV

TEMPERATURE (°C)

–50

CHARGE ERROR (%)

–1.00

–0.50

–0.25

0.50

25 50

2941 G03

–0.75

0.75

1.00

0.25

–25 0 75 100

VSENSE = –50mV

VSENSE = –10mV

VSENSE+ (V)

2.5

SUPPLY

(µA)

100

4.0 5.0

2941 G04

3.0 3.5 4.5 5.5 6.0

TA = 25°C

TA = –40°C

TA = 85°C

VSENSE+ (V)

2.5

ISHUTDOWN (µA)

1.0

2.0

3.5 4.5 5.0

2941 G05

0.5

1.5

3.0 4.0 5.5 6.0

TA = 25°C

TA = –40°C

TA = 85°C

LTC2941

Rev. C

For more information www.analog.com

PIN FUNCTIONS

SENSE+ (Pin 1): Positive Current Sense Input and Power

Supply. Connect to the load/charger side of the sense

resistor. VSENSE+ operating range is 2.7V to 5.5V.

GND (Pin 2): Device Ground. Connect directly to the nega-

tive battery terminal.

SCL (Pin 3): Serial Bus Clock Input.

SDA (Pin 4/Pin 6): Serial Bus Data Input and Output.

AL/CC (Pin 5/Pin 7): Alert Output or Charge Complete

Input. Configured either as an SMBus alert output or

charge complete input by control register bits B[2:1].

At power-up, the pin defaults to alert mode conforming

to the SMBus alert response protocol. It behaves as an

open-drain logic output that pulls to GND when a value

in the threshold registers is exceeded.

When configured as a charge complete input, connect to

the charge complete output from the battery charger cir-

cuit. A high level at CC sets the value of the accumulated

charge (registers C, D) to FFFFh.

SENSE– (Pin 6/Pin 8): Negative Current Sense Input.

Connect SENSE– to the positive battery terminal side

of the sense resistor. The voltage between SENSE– and

SENSE+ must remain within ±50mV in normal operation.

Exposed Pad (Pin 7/Pin 9): Do not connect.

BLOCK DIAGRAM

REF CLK

BIDIRECTIONAL

INTEGRATOR

SENSE–

INTERNAL

REFERENCE

GENERATOR

ACCUMULATED

CHARGE

PRESCALER

STATUS/

CONTROL

INTERNAL

OSCILLATOR

SENSE+

VSUPPLY

AL/CC

GND I2C/

SMBus

SCL

SDA

2941 F02

Figure2. Block Diagram of the LTC2941

LTC2941

Rev. C

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OPERATION

Overview

The LTC2941 is a battery gas gauge device designed for

use with single Li-Ion cells and other battery types with

a terminal voltage between 2.7V and 5.5V. A precision

coulomb counter integrates current through a sense

resistor between the battery’s positive terminal and the

load orcharger.

Coulomb Counter

Charge is the time integral of current. The LTC2941 mea-

sures battery current by monitoring the voltage developed

across a sense resistor and then integrates this infor-

mation to infer charge. The differential voltage between

SENSE+ and SENSE– is applied to an auto-zeroed differ-

ential analog integrator to convert the measured current

to charge.

When the integrator output ramps to REFHI or REFLO

levels, switches S1, S2, S3 and S4 toggle to reverse the

ramp direction. By observing the condition of the switches

and the ramp direction, polarity is determined.

A programmable prescaler is incremented or decre-

mented every time the integrator changes ramp direc-

tion. The prescaler effectively increases integration time

by a factor M programmable from 1 to 128. At each under

or overflow of the prescaler, the accumulated charge is

incremented or decremented one count. The value of

accumulated charge is read via the I2C interface.

Power-Up Sequence

When VSENSE+ rises above a threshold of approximately

2.45V, the LTC2941 generates an internal power-on reset

(POR) signal and sets all registers to their default state.

In the default state, the coulomb counter is active. The

accumulated charge is set to mid-scale (7FFFh), the low

threshold registers are set to 0000h and all the high

threshold registers are set to FFFFh. The alert mode is

enabled and the coulomb counter prescaling factor M is

set to 128.

–

REFHI

REFLO

LOADCHARGER

SENSE+

RSENSE

BATTERY

IBAT

SENSE–

GND

POLARITY

DETECTION

CONTROL

LOGIC

PRE-

SCALER

I2C/

SMBus

REGISTERS

AL/CC

SCL

SDA

2941 F03

STATUS

CONTROL

ACR

THRESHOLDS

VSUPPLY

Figure3. Coulomb Counter Section of the LTC2941

LTC2941

Rev. C

For more information www.analog.com

APPLICATIONS INFORMATION

I2C/SMBus Interface

The LTC2941 communicates with a bus master using a

2-wire interface compatible with I

C and SMBus. The 7-bit

hard-coded I2C address of LTC2941 is 1100100.

The LTC2941 is a slave-only device. Therefore the

serial clock line (SCL) is input only while the data line

(SDA) is bidirectional. For more details refer to the I

Protocolsection.

Internal Registers

The LTC2941 integrates current through a sense resistor

and stores a 16-bit result, accumulated charge, as two

bytes in registers C and D. Two byte high and low limits

programmed in registers E, F, G and H are continuously

compared against the accumulated charge. If either limit

is exceeded, a corresponding flag is set in the status reg-

ister bits A[2] or A[3]. If the alert mode is enabled, the

AL/CC pin pulls low.

The internal eight registers are organized as shown in

Table1:

Table1. Register Map

ADDRESS NAME REGISTER DESCRIPTION R/W DEFAULT

00h A Status R See Below

01h B Control R/W 3Ch

02h C Accumulated Charge MSB R/W 7Fh

03h D Accumulated Charge LSB R/W FFh

04h E Charge Threshold High MSB R/W FFh

05h F Charge Threshold High LSB R/W FFh

06h G Charge Threshold Low MSB R/W 00h

07h H Charge Threshold Low LSB R/W 00h

R = Read, W = Write

Status Register (A)

Table 2 shows the details of the status register

(address00h):

Table2. Status Register A (Read Only)

BIT NAME OPERATION DEFAULT

A[7] Chip Identification 1: LTC2941

0: LTC2942

A[6] Reserved Not Used. 0

A[5] Accumulated Charge

Overflow/Underflow

Indicates that the value of the

accumulated charge hit either

top or bottom.

A[4] Reserved Not used. 0

A[3] Charge Alert High Indicates that the accumulated

charge value exceeded the

charge threshold high limit.

A[2] Charge Alert Low Indicates that the accumulated

charge value dropped below

the charge threshold low limit.

A[1] VBAT Alert Indicates that the battery

voltage (at SENSE–) dropped

below selected VBAT threshold.

A[0] Undervoltage

Lockout Alert

Indicates recovery from

undervoltage. If equal to 1,

a UVLO has occurred and

the content of registers is

uncertain.

The AL/CC pin can be configured to pull low whenever

any status register bit is set (except for bit A[7] and A[0]),

using control register bits B[2] and B[1]. All status regis-

ter bits except A[7] are cleared after being read by the host

if the conditions which set these bits have been removed.

As soon as one of the measured quantities exceeds the

programmed limits, the corresponding bit A[3], A[2] or

A[1] in the status register is set.

LTC2941

Rev. C

For more information www.analog.com

APPLICATIONS INFORMATION

Bit A[5] is set if the LTC2941’s accumulated charge over-

flows or underflows the combined total in registers C and D.

Note that the counting process does not roll over, but sim-

ply stops at FFFFh or 0000h until the direction is reversed.

The LTC2941 includes a battery undervoltage moni-

tor, which sets bit A1 if the limit is exceeded. Limits are

selected in the control register.

The undervoltage lockout (UVLO) bit A[0] is set if, dur-

ing operation, the voltage on SENSE+ drops below 2.7V

without reaching the POR level. The analog parts of the

coulomb counter are switched off while the digital register

values are retained. After recovery of the supply voltage

the coulomb counter resumes integrating with the stored

value in the accumulated charge registers (C, D) but it has

missed any charge flowing while VSENSE+ < 2.7V.

The hard coded bit A[7] of the status register enables the

host to distinguish the LTC2941 from the pin compatible

LTC2942, allowing the same software to be used with

both devices.

Control Register (B)

The operation of the LTC2941 can be controlled by pro-

gramming the control register at address 01h. Table3

shows the organization of the 8-bit control register B[7:0]

Table3. Control Register B

BIT NAME OPERATION DEFAULT

B[7:6] VBAT Alert [11] Threshold Value = 3.0V.

[10] Threshold Value = 2.9V.

[01] Threshold Value = 2.8V.

[00] VBAT Alert Off.

[00]

B[5:3] Prescaler M Sets coulomb counter prescaling

factor M between 1 and 128.

Default is 128.

M = 2(4 • B[5] + 2 • B[4] + B[3]).

[111]

B[2:1] AL/CC

Configure

Configures the AL/CC pin.

[10] Alert Mode.

Alert functionality enabled.

Pin becomes logic output.

[01] Charge Complete Mode.

Pin becomes logic input and accepts

“charge complete” signal (e.g., from

a charger) to set accumulated charge

[00] AL/CC pin disabled.

[11] Not allowed.

[10]

B[0] Shutdown Shut down analog section to reduce

ISUPPLY.

[0]

Power Down B[0]

Programming the last bit B[0] of the control register to 1

sets the analog parts of the LTC2941 in power down and

the current consumption drops typically below 1µA. All

analog circuits are disabled while the values in the regis-

ters are retained. Note that any charge flowing while B[0]

is 1 is not measured and the charge information below 1

LSB of the accumulated charge register is lost.

Alert/Charge Complete Configuration B[2:1]

The AL/CC pin is a dual function pin configured by the

control register. By setting bits B[2:1] to [10] (default)

the AL/CC pin is configured as an alert pin following the

SMBus protocol. In this alert mode the AL/CC pin is a

digital output and is pulled low if one of the measured

quantities exceeds its high or low threshold or if the an

overflow/underflow occurs in the accumulated charge

registers C and D. An alert response procedure started

by the master resets the alert at the AL/CC pin. For further

information see the Alert Response Protocol section.

Setting the control bits B[2:1] to [01] configures the AL/

CC pin as a digital input. In this mode, a high input on

the AL/CC pin communicates to the LTC2941 that the

battery is full and the accumulated charge is set to its

maximum value FFFFh. The AL/CC pin would typically be

connected to the “charge complete” output from the bat-

tery chargercircuitry.

If neither the alert nor the charge complete functionality

is desired, bits B[2:1] should be set to [00]. The AL/CC

pin is then disabled and should be tied to GND. Avoid set-

ting B[2:1] to [11] as it enables the alert and the charge

complete modes simultaneously.

Choosing RSENSE and Coulomb Counter

Prescaler“M”B[5:3]

To achieve the specified precision of the coulomb counter

the differential voltage between SENSE+ and SENSE– must

stay within ±50mV. For differential input signals up to

±300mV the LTC2941 will remain functional but the preci-

sion of the coulomb counter is not guaranteed.

LTC2941

Rev. C

For more information www.analog.com

APPLICATIONS INFORMATION

The value of the external sense resistor is determined by

the maximum input range of VSENSE and the maximum

current of the application:

RSENSE ≤

50mV

MAX

The choice of the external sense resistor value influences

the gain of the coulomb counter. A larger sense resis-

tor gives a larger differential voltage between SENSE+

and SENSE– for the same current which results in more

precise coulomb counting. Thus the amount of charge

represented by the least significant bit (q

LSB

) of the accu-

mulated charge (registers C, D) is given by:

qLSB =0.085mAh •

50m

RSENSE

•

128

qLSB =0.085mAh • 50mΩ

SENSE

when the prescaler is set to its default value of M=128.

Note that 1mAh = 3.6A • s = 3.6C (coulombs).

Choosing RSENSE = 50mV/IMAX is not sufficient in

applications where:

A. the battery capacity (QBAT) is very large compared to

the maximum current (IMAX):

QBAT > IMAX • 5.5 hours

B. the battery capacity (QBAT) is very small compared to

the maximum current (IMAX):

QBAT < IMAX • 0.1 hours

For case A: In low current applications using a large bat-

tery, choosing RSENSE according to RSENSE = 50mV/IMAX

can lead to a qLSB smaller than QBAT/216 and the 16-bit

accumulated charge may underflow before the battery is

exhausted or overflow during charge. Choose in this case

a maximum RSENSE of:

RSENSE ≤0.085mAh • 2

QBAT

• 50mΩ

In an example application where the maximum current is

MAX

= 100mA, calculating R

SENSE

= 50mV/I

MAX

would

lead to a sense resistor of 500mΩ. This gives a qLSB

of 8.5µAh and the accumulated charge register can rep-

resent a maximum battery capacity of QBAT = 8.5µAh •

65535 = 557mAh. If the battery is larger, RSENSE must be

lowered. For example, RSENSE must be reduced to 150mΩ

if a battery with a capacity of 1800mAh is used.

For case B: In applications using a small battery but hav-

ing a high maximum current, qLSB can get quite large with

respect to the battery capacity. For example, if the battery

capacity is 100mAh and the maximum current is 1A, the

standard equation leads to choose a sense resistor value

of 50mΩ, resulting in:

qLSB = 0.085mAh = 306mC

The battery capacity then corresponds to only 1176 q

LSB

and less than 2% of the accumulated charge register

isutilized.

To preserve digital resolution in this case, the LTC2941

includes a programmable prescaler. Lowering the pres-

caler factor M allows reducing qLSB to better match the

accumulated charge registers C and D to the capacity

of the battery. The prescaling factor M can be chosen

between 1 and its default value 128. The charge LSB

thenbecomes:

qLSB =0.085mAh • 50mΩ

SENSE

•M

128

LTC2941

Rev. C

For more information www.analog.com

To use as much of the range of the accumulated charge

registers C and D as possible the prescaler factor M

should be chosen for a given battery capacity QBAT and a

sense resistor RSENSE as:

M≥128 • QBAT

• 0.085mAh

•RSENSE

50mΩ

M can be set to 1, 2, 4, 8, …128 by programming

B[5:3] of the control register as M = 2(4 • B[5] + 2 • B[4]

+ B[3])

. The default value after power up is M = 128 = 2

(B[5:3]=111).

In the above example of a 100mAh battery and a RSENSE

of 50mΩ, the prescaler should be programmed to M = 4.

The qLSB then becomes 2.656µAh and the battery capacity

corresponds to roughly 37650 qLSBs.

Note that the internal digital resolution of the coulomb

counter is higher than indicated by q

LSB

. The digitized

charge qINTERNAL is M • 8 smaller than qLSB. qINTERNAL is

typically 299µAs for a 50mΩ sense resistor.

VBAT Alert B[7:6]

The VBAT alert function allows the LTC2941 to monitor

the voltage at SENSE–. If enabled, a drop of the voltage

at the SENSE– pin below a preset threshold is detected

and bit A[1] in the status register is set. If the alert mode

is enabled by setting B[2] to one, an alert is generated at

the AL/CC pin. The threshold for the VBAT alert function

is selectable according to Table3.

Accumulated Charge Registers (C, D)

The coulomb counter of the LTC2941 integrates current

through the sense resistor. The 16-bit result of this charge

integration is stored in the accumulated charge registers C

and D. As the LTC2941 does not know the actual battery

status after initial power-up, the accumulated charge is

set to mid-scale (7FFFh). If the host knows the status of

the battery, the accumulated charge registers C[7:0] and

D[7:0] can be either programmed to the correct value

via I2C or it can be set after charging to FFFFh (full) by

pulling the AL/CC pin high (if charge complete mode is

enabled via bits B[2:1]). Before writing the accumulated

charge registers, the analog section should be shut down

by setting B[0] to 1. In order to avoid a change in the

accumulated charge registers between reading MSBs

C[7:0] and LSBs D[7:0], it is recommended to read them

sequentially, as shown in Figure8.

Threshold Registers (E, F), (G, H)

For battery charge, the LTC2941 features a high and a

low threshold register. At power-up the high threshold

is set to FFFFh while the low threshold is set to 0000h.

Both thresholds can be programmed to a desired value via

C. As soon as the accumulated charge exceeds the high

threshold or falls below the low threshold, the LTC2941

sets the corresponding flag in the status register and pulls

the AL/CC pin low if alert mode is enabled.

I2C Protocol

The LTC2941 uses an I2C/SMBus compatible 2-wire open-

drain interface supporting multiple devices and masters

on a single bus. The connected devices can only pull the

bus wires LOW and they never drive the bus HIGH. The

bus wires should be externally connected to a positive

supply voltage via a current source or pull-up resistor.

When the bus is idle, both SDA and SCL are HIGH. Data on

the I2C-bus can be transferred at rates of up to 100kbit/s

in standard mode and up to 400kbit/s in fast mode.

Each device on the I2C/SMBus is recognized by a unique

address stored in that device and can operate as either a

transmitter or receiver, depending on the function of the

device. In addition to transmitters and receivers, devices

can also be classified as masters or slaves when perform-

ing data transfers. A master is the device which initiates

a data transfer on the bus and generates the clock sig-

nals to permit that transfer. At the same time any device

addressed is considered a slave. The LTC2941 always

acts as a slave. Figure4 shows an overview of the data

transmission on the I2C bus.

APPLICATIONS INFORMATION

LTC2941

Rev. C

For more information www.analog.com

APPLICATIONS INFORMATION

START and STOP Conditions

When the bus is idle, both SCL and SDA must be HIGH. A

bus master signals the beginning of a transmission with a

START condition by transitioning SDA from HIGH to LOW

while SCL is HIGH. When the master has ﬁnished com-

municating with the slave, it issues a STOP condition by

transitioning SDA from LOW to HIGH while SCL is HIGH.

The bus is then free for another transmission. When the

bus is in use, it stays busy if a repeated START (Sr) is gen-

erated instead of a STOP condition. The repeated START

(Sr) conditions are functionally identical to the START (S).

Data Transmission

After a START condition, the I2C bus is considered busy

and data transfer begins between a master and a slave. As

data is transferred over I2C in groups of nine bits (eight

data bits followed by an acknowledge bit), each group

takes nine SCL cycles. The transmitter releases the SDA

line during the acknowledge clock pulse and the receiver

issues an acknowledge (ACK) by pulling SDA LOW or

leaves SDA HIGH to indicate a not-acknowledge (NACK)

condition. Change of data state can only happen while

SCL is LOW.

Write Protocol

The master begins communication with a START condi-

tion followed by the seven bit slave address 1100100

and the R/W bit set to zero, as shown in Figure5. The

LTC2941 acknowledges this by pulling SDA LOW and then

the master sends a command byte which indicates which

internal register the master is to write. The LTC2941

acknowledges and then latches the command byte into

its internal register address pointer. The master delivers

the data byte, the LTC2941 acknowledges once more and

latches the data into the desired register. The transmission

is ended when the master sends a STOP condition. If the

master continues by sending a second data byte instead

of a STOP, the LTC2941 acknowledges again, increments

its address pointer and latches the second data byte in

the following register, as shown in Figure6.

Read Protocol

The master begins a read operation with a START condi-

tion followed by the seven bit slave address 1100100 and

the R/W bit set to zero, as shown in Figure7. The LTC2941

acknowledges and then the master sends a command

byte which indicates which internal register the master is

to read. The LTC2941 acknowledges and then latches the

command byte into its internal register address pointer.

The master then sends a repeated START condition fol-

lowed by the same seven bit address with the R/W bit

now set to one. The LTC2941 acknowledges and sends

the contents of the requested register. The transmission

is ended when the master sends a STOP condition. If

the master acknowledges the transmitted data byte, the

LTC2941 increments its address pointer and sends the

contents of the following register, as shown in Figure8.

SCL

SDA

START

CONDITION

STOP

CONDITION

ADDRESS R/W ACK DATA ACK DATA ACK

1 - 7 8 9

2941 F04

a6 - a0 b7 - b0 b7 - b0

1 - 7 8 9 1 - 7 8 9

Figure4. Data Transfer Over I2C or SMBus

LTC2941

Rev. C

For more information www.analog.com

APPLICATIONS INFORMATION

Alert Response Protocol

In a system where several slaves share a common inter-

rupt line, the master can use the alert response address

(ARA) to determine which device initiated the interrupt

(Figure9).

FROM MASTER TO SLAVE

ADDRESS REGISTER DATA

FROM SLAVE TO MASTER

2941 F05

A: ACKNOWLEDGE (LOW)

A: NOT-ACKNOWLEDGE (HIGH)

R: READ BIT (HIGH)

W: WRITE BIT (LOW)

S: START CONDITION

P: STOP CONDITION

A A A

1100100 01h FCh

0 0 0

Figure5. Writing FCh to LTC2941 Control Register (B)

ADDRESS REGISTER DATA

2941 F06

A A A

1100100 02h F0h 01h

0 0 0 0

DATA A

Figure6. Writing F001h to the LTC2941 Accumulated Charge Registers (C, D)

ADDRESS REGISTER S

2941 F07

A A ADDRESS

1100100 00h 1

0 0 1100100 0

81h

DATA

Figure7. Reading the LTC2941 Status Register (A)

ADDRESS REGISTER S

2941 F08

A A ADDRESS

1100100 02h 1

0 0 1100100 0

80h

DATA

01h

DATA

Figure8. Reading the LTC2941 Accumulated Charge Registers (C, D)

S R

ALERT RESPONSE ADDRESS DEVICE ADDRESS

2941 F09

0001100 11001001

0 1

Figure9. LTC2941 Serial Bus SDA Alert Response Protocol

The master initiates the ARA procedure with a START con-

dition and the special 7-bit ARA bus address (0001100)

followed by the read bit (R) = 1. If the LTC2941 is assert-

ing the AL/CC pin in alert mode, it acknowledges and

responds by sending its 7-bit bus address (1100100)

LTC2941

Rev. C

For more information www.analog.com

APPLICATIONS INFORMATION

and a 1. While it is sending its address, it monitors the

SDA pin to see if another device is sending an address at

the same time using standard I2C bus arbitration. If the

LTC2941 is sending a 1 and reads a 0 on the SDA pin on

the rising edge of SCL, it assumes another device with a

lower address is sending and the LTC2941 immediately

aborts its transfer and waits for the next ARA cycle to try

again. If transfer is successfully completed, the LTC2941

will stop pulling down the AL/CC pin and will not respond

to further ARA requests until a new alert event occurs.

PC Board Layout Recommendations

Keep all traces as short as possible to minimize noise and

inaccuracy. Use a 4-wire Kelvin sense connection for the

sense resistor, locating the LTC2941 close to the resis-

tor with short sense traces to SENSE+ and SENSE–. Use

wider traces from the resistor to the battery, load and/or

charger (see Figure10). Put the bypass capacitor close

to SENSE+ and GND.

LTC2941

2941 F10

RSENSE TO BATTERY

CHARGER/LOAD

Figure10. Kelvin Connection on Sense Resistor

LTC2941

Rev. C

For more information www.analog.com

PACKAGE DESCRIPTION

3.00 ±0.10

(2 SIDES)

2.00 ±0.10

(2 SIDES)

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

0.40 ± 0.10

BOTTOM VIEW—EXPOSED PAD

1.65 ± 0.10

(2 SIDES)

0.75 ±0.05

R = 0.115

TYP

R = 0.05

TYP

1.35 ±0.10

(2 SIDES)

PIN 1 BAR

TOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DCB6) DFN 0405

0.25 ± 0.05

0.50 BSC

PIN 1 NOTCH

R0.20 OR 0.25

× 45° CHAMFER

0.25 ± 0.05

1.35 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

1.65 ±0.05

(2 SIDES)

2.15 ±0.05

0.70 ±0.05

3.55 ±0.05

PACKAGE

OUTLINE

0.50 BSC

DCB Package

6-Lead Plastic DFN (2mm × 3mm)

(Reference LTC DWG # 05-08-1715 Rev A)

LTC2941

Rev. C

For more information www.analog.com

PACKAGE DESCRIPTION

MSOP (MS8E) 0213 REV K

0.53 ±0.152

(.021 ±.006)

SEATING

PLANE

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD

SHALL NOT EXCEED 0.254mm (.010") PER SIDE.

0.18

(.007)

0.254

(.010)

1.10

(.043)

MAX

0.22 – 0.38

(.009 – .015)

TYP

0.86

(.034)

REF

0.65

(.0256)

BSC

0° – 6° TYP

DETAIL “A”

GAUGE PLANE

1 2 34

4.90 ±0.152

(.193 ±.006)

BOTTOM VIEW OF

EXPOSED PAD OPTION

765

3.00 ±0.102

(.118 ±.004)

(NOTE 3)

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

0.52

(.0205)

REF

1.68

(.066)

1.88

(.074)

5.10

(.201)

MIN

3.20 – 3.45

(.126 – .136)

1.68 ±0.102

(.066 ±.004)

1.88 ±0.102

(.074 ±.004) 0.889 ±0.127

(.035 ±.005)

RECOMMENDED SOLDER PAD LAYOUT

0.65

(.0256)

BSC

0.42 ±0.038

(.0165 ±.0015)

TYP

0.1016 ±0.0508

(.004 ±.002)

DETAIL “B”

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

NO MEASUREMENT PURPOSE

0.05 REF

0.29

REF

MS8E Package

8-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1662 Rev K)

LTC2941

Rev. C

For more information www.analog.com

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

A 8/10 Revised Exposed Pad description in the Pin Configuration and Pin Functions sections 2, 5

B 02/16 Added MSOP Package option 1–18

C 11/18 Updated MSE Package description to include DNC (Do Not Connect) for MSE Package

Corrected equation for external sense resistor calculation

Note added to explain status output timing following internal self test operation

LTC2941

Rev. C

For more information www.analog.com

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AL/CC

SDA

RSENSE

100mΩ

1-CELL

Li-Ion

0.1µF

LOAD

SCL

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GND

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(CHARGER)

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Pin Compatible with LTC2942-1

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LTC4059 900mA Linear Lithium-Ion Battery Charger 2mm × 2mm DFN Package, Thermal Regulation, Charge Current

MonitorOutput

LTC4061 Standalone Linear Li-Ion Battery Charger with

Thermistor Input

4.2V, ±0.35% Float Voltage, Up to 1A Charge Current, 3mm × 3mm

DFNPackage

LTC4063 Li-Ion Charger with Linear Regulator Up to 1A Charge Current, 100mA, 125mV LDO, 3mm × 3mm DFN Package

LTC4080 500mA Standalone Li-Ion Charger with Integrated

300mA Synchronous Buck

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Operation, 1.5A Max Charge Current, 180mΩ Ideal Diode with <50mΩ

Option, 3.3V/25mA Always-On LDO, 4mm × 3mm DFN-14 Package

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