MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
MIXED SIGNAL MICROCONTROLLER
1FEATURES
• Low Supply Voltage Range: 1.8 V to 3.6 V • Unified Clock System
• Ultralow Power Consumption – FLL Control Loop for Frequency
Stabilization
– Active Mode (AM):
All System Clocks Active – Low-Power/Low-Frequency Internal Clock
230 µA/MHz at 8 MHz, 3.0 V, Flash Program Source (VLO)
Execution (Typical) – Low-Frequency Trimmed Internal Reference
110 µA/MHz at 8 MHz, 3.0 V, RAM Program Source (REFO)
Execution (Typical) – 32-kHz Crystals
– Standby Mode (LPM3): – High-Frequency Crystals up to 32 MHz
Real-Time Clock With Crystal , Watchdog, • 16-Bit Timer TA0, Timer_A With Five
and Supply Supervisor Operational, Full Capture/Compare Registers
RAM Retention, Fast Wake-Up: • 16-Bit Timer TA1, Timer_A With Three
1.7 µA at 2.2 V, 2.1 µA at 3.0 V (Typical) Capture/Compare Registers
Low-Power Oscillator (VLO),
General-Purpose Counter, Watchdog, and • 16-Bit Timer TB0, Timer_B With Seven
Supply Supervisor Operational, Full RAM Capture/Compare Shadow Registers
Retention, Fast Wake-Up: • Up to Four Universal Serial Communication
1.2 µA at 3.0 V (Typical) Interfaces
– Off Mode (LPM4): – USCI_A0, USCI_A1, USCI_A2, and USCI_A3
Full RAM Retention, Supply Supervisor Each Supporting
Operational, Fast Wake-Up: – Enhanced UART supporting
1.2 µA at 3.0 V (Typical) Auto-Baudrate Detection
– Shutdown Mode (LPM4.5): – IrDA Encoder and Decoder
0.1 µA at 3.0 V (Typical) – Synchronous SPI
• Wake-Up From Standby Mode in Less Than – USCI_B0, USCI_B1, USCI_B2, and USCI_B3
5 µs Each Supporting
• 16-Bit RISC Architecture – I2CTM
– Extended Memory – Synchronous SPI
– Up to 25-MHz System Clock • 12-Bit Analog-to-Digital (A/D) Converter
• Flexible Power Management System – Internal Reference
– Fully Integrated LDO With Programmable – Sample-and-Hold
Regulated Core Supply Voltage – Autoscan Feature
– Supply Voltage Supervision, Monitoring, – 14 External Channels, 2 Internal Channels
and Brownout • Hardware Multiplier Supporting 32-Bit
Operations
• Serial Onboard Programming, No External
Programming Voltage Needed
• Three Channel Internal DMA
• Basic Timer With Real-Time Clock Feature
• Family Members are Summarized in Table 1
• For Complete Module Descriptions, See the
MSP430x5xx Family User's Guide (SLAU208)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
DESCRIPTION
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with extensive
low-power modes, is optimized to achieve extended battery life in portable measurement applications. The
device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to
maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to
active mode in less than 5 µs.
The MSP430F543xA and MSP430F541xA series are microcontroller configurations with three 16-bit timers, a
high performance 12-bit analog-to-digital (A/D) converter, up to four universal serial communication interfaces
(USCI), hardware multiplier, DMA, real-time clock module with alarm capabilities, and up to 87 I/O pins.
Typical applications for this device include analog and digital sensor systems, digital motor control, remote
controls, thermostats, digital timers, hand-held meters, etc.
Family members available are summarized in Table 1.
Table 1. Family Members
USCI
Flash SRAM ADC12_A Package
Channel A: Channel B:
Device Timer_A(1) Timer_B(2) I/O
(KB) (KB) (Ch) Type
UART/IrDA/ SPI/I2C
SPI
100 PZ,
MSP430F5438A 256 16 5, 3 7 4 4 14 ext / 2 int 87 113 ZQW
MSP430F5437A 256 16 5, 3 7 2 2 14 ext / 2 int 67 80 PN
100 PZ,
MSP430F5436A 192 16 5, 3 7 4 4 14 ext / 2 int 87 113 ZQW
MSP430F5435A 192 16 5, 3 7 2 2 14 ext / 2 int 67 80 PN
100 PZ,
MSP430F5419A 128 16 5, 3 7 4 4 14 ext / 2 int 87 113 ZQW
MSP430F5418A 128 16 5, 3 7 2 2 14 ext / 2 int 67 80 PN
(1) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(2) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
Table 2. Ordering Information(1)
PACKAGED DEVICES(2)
TAPLASTIC 100-PIN LQFP PLASTIC 80-PIN LQFP PLASTIC 113-BALL BGA
(PZ) (PN) (ZQW)
MSP430F5438AIPZ MSP430F5437AIPN MSP430F5438AIZQW
–40°C to 85°C MSP430F5436AIPZ MSP430F5435AIPN MSP430F5436AIZQW
MSP430F5419AIPZ MSP430F5418AIPN MSP430F5419AIZQW
(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
2Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
PZPACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7
P7.4/A12
P7.5/A13
P7.6/A14
P7.7/A15
P5.0/A8/VREF+/VeREF+
P5.1/A9/VREF−/VeREF−
AVCC
AVSS
P7.0/XIN
P7.1/XOUT
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/SMCLK
P1.7
P2.0/TA1CLK/MCLK
P9.7
P9.6
P9.5/UCA2RXDUCA2SOMI
P9.4/UCA2TXD/UCA2SIMO
P9.3/UCB2CLK/UCA2STE
P9.2/UCB2SOMI/UCB2SCL
P9.1/UCB2SIMO/UCB2SDA
P9.0/UCB2STE/UCA2CLK
P8.7
P8.6/TA1.1
P8.5/TA1.0
DVCC2
DVSS2
VCORE
P8.4/TA0.4
P8.3/TA0.3
P8.2/TA0.2
P8.1/TA0.1
P8.0/TA0.0
P7.3/TA1.2
P7.2/TB0OUTH/SVMOUT
P5.7/UCA1RXD/UCA1SOMI
P5.6/UCA1TXD/UCA1SIMO
P5.5/UCB1CLK/UCA1STE
P5.4/UCB1SOMI/UCB1SCL
MSP430F5438AIPZ
MSP430F5436AIPZ
MSP430F5419AIPZ
P6.3/A3
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
P5.3/XT2OUT
P5.2/XT2IN
DVSS4
DVCC4
P11.2/SMCLK
P11.1/MCLK
P11.0/ACLK
P10.7
P10.6
P10.5/UCA3RXDUCA3SOMI
P10.4/UCA3TXD/UCA3SIMO
P10.3/UCB3CLK/UCA3STE
P10.2/UCB3SOMI/UCB3SCL
P10.1/UCB3SIMO/UCB3SDA
P10.0/UCB3STE/UCA3CLK
P2.1/TA1.0
P2.2/TA1.1
P2.3/TA1.2
P2.4/RTCCLK
P2.5
P2.6/ACLK
P2.7/ADC12CLK/DMAE0
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
DVSS3
DVCC3
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/UCB1STE/UCA1CLK
P3.7/UCB1SIMO/UCB1SDA
P4.0/TB0.0
P4.1/TB0.1
P4.2/TB0.2
P4.3/TB0.3
P4.4/TB0.4
P4.5/TB0.5
P4.6/TB0.6
P4.7/TB0CLK/SMCLK
DVSS1
DVCC1
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Pin Designation, MSP430F5438AIPZ, MSP430F5436AIPZ, MSP430F5419AIPZ
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 3
P8.0/TA0.0
P7.3/TA1.2
P7.2/TB0OUTH/SVMOUT
P5.7/UCA1RXD/UCA1SOMI
P5.6/UCA1TXD/UCA1SIMO
P5.5/UCB1CLK/UCA1STE
P5.4/UCB1SOMI/UCB1SCL
P4.7/TB0CLK/SMCLK
P4.6/TB0.6
DVCC2
DVSS2
VCORE
P4.5/TB0.5
P4.4/TB0.4
P4.3/TB0.3
P4.2/TB0.2
P4.1/TB0.1
P4.0/TB0.0
P3.7/UCB1SIMO/UCB1SDA
P3.6/UCB1STE/UCA1CLK
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7
P7.4/A12
P7.5/A13
P7.6/A14
P7.7/A15
P5.0/A8/VREF+/VeREF+
P5.1/A9/VREF−/VeREF−
AVCC
AVSS
P7.0/XIN
P7.1/XOUT
DVSS1
DVCC1
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
PNPACKAGE
(TOP VIEW)
22 23
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
25 26 27 28
79 78 77 76 7580 74 72 71 7073
29 30 31 32 33
69 68
21
67 66 65 64
34 35 36 37 38 39 40
63 62 61
MSP430F5437AIPN
MSP430F5435AIPN
MSP430F5418AIPN
P6.3/A3
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCLK
P5.3/XT2OUT
P5.2/XT2IN
DVSS4
DVCC4
P8.6/TA1.1
P8.5/TA1.0
P8.4/TA0.4
P8.3/TA0.3
P8.2/TA0.2
P8.1/TA0.1
P1.4/TA0.3
P1.5/TA0.4
P1.6/SMCLK
P1.7
P2.0/TA1CLK/MCLK
P2.1/TA1.0
P2.2/TA1.1
P2.3/TA1.2
P2.4/RTCCLK
DVSS3
DVCC3
P2.5
P2.6/ACLK
P2.7/ADC12CLK/DMAE0
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Pin Designation, MSP430F5437AIPN, MSP430F5435AIPN, MSP430F5418AIPN
4Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12
C1 C2 C3 C11 C12
D1 D2 D4 D5 D6 D7 D8 D9 D11 D12
E1 E2 E4 E5 E6 E7 E8 E9 E11 E12
F1 F2 F4 F5 F8 F9 F11 F12
G1 G2 G4 G5 G8 G9 G11 G12
J1 J2 J4 J5 J6 J7 J8 J9 J11 J12
H1 H2 H4 H5 H6 H7 H8 H9 H11 H12
K1 K2 K11 K12
L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12
M1 M2 M3 M5 M6 M7 M8 M9 M10 M11 M12
M4
ZQWPACKAGE
(TOP VIEW)
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Pin Designation, MSP430F5438AIZQW, MSP430F5436AIZQW, MSP430F5419AIZQW
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Unified
Clock
System
256KB
192KB
128KB
Flash
16KB
RAM
MCLK
ACLK
SMCLK
I/OPorts
P1/P2
2×8I/Os
Interrupt
Capability
PA
1×16I/Os
CPUXV2
and
Working
Registers
EEM
(L:8+2)
XIN XOUT
JTAG/
Interface
SBW
PA PB PC PD
DMA
3Channel
XT2IN
XT OUT2
PE
Power
Management
LDO
SVM/
Brownout
SVS
SYS
Watchdog
PF
I/OPorts
P3/P4
2×8I/Os
PB
1×16I/Os
I/OPorts
P5/P6
2×8I/Os
PC
1×16I/Os
I/OPorts
P7/P8
2×8I/Os
PD
1×16I/Os
I/OPorts
P9/P10
2×8I/Os
PE
1×16I/Os
I/OPorts
P11
1×3I/Os
PF
1×3I/Os
MPY32
TA0
Timer_A
5CC
Registers
TA1
Timer_A
3CC
Registers
TB0
Timer_B
7CC
Registers
RTC_A CRC16
USCI0,1,2,3
USCI_Ax:
UART,
IrDA,SPI
UCSI_Bx:
SPI,I2C
ADC12_A
200KSPS
16Channels
(14ext/2int)
Autoscan
12Bit
DVCC DVSS AVCC AVSS
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x P10.x P11.x
RST/NMI
MAB
MDB
REF
Unified
Clock
System
256KB
192KB
128KB
Flash
16KB
RAM
MCLK
ACLK
SMCLK
I/OPorts
P1/P2
2×8I/Os
Interrupt
Capability
PA
1×16I/Os
CPUXV2
and
Working
Registers
EEM
(L:8+2)
XIN XOUT
JTAG/
Interface
SBW
PA PB PC PD
DMA
3Channel
XT2IN
XT OUT2
Power
Management
LDO
SVM/
Brownout
SVS
SYS
Watchdog
I/OPorts
P3/P4
2×8I/Os
PB
1×16I/Os
I/OPorts
P5/P6
2×8I/Os
PC
1×16I/Os
I/OPorts
P7/P8
2×8I/Os
PD
1×16I/Os
MPY32
TA0
Timer_A
5CC
Registers
TA1
Timer_A
3CC
Registers
TB0
Timer_B
7CC
Registers
RTC_A CRC16
USCI0,1
UCSI_Ax:
UART,
IrDA,SPI
USCI_Bx:
SPI,I2C
DVCC DVSS AVCC AVSS
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x
RST/NMI
ADC12_A
200KSPS
16Channels
(14ext/2int)
Autoscan
12Bit
MAB
MDB
REF
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Functional Block Diagram
MSP430F5438AIPZ, MSP430F5436AIPZ, MSP430F5419AIPZ,
MSP430F5438AIZQW, MSP430F5436AIZQW, MSP430F5419AIZQW
Functional Block Diagram
MSP430F5437AIPN, MSP430F5435AIPN, MSP430F5418AIPN
6Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Table 3. TERMINAL FUNCTIONS
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ PN ZQW
General-purpose digital I/O
P6.4/A4 1 1 A1 I/O Analog input A4 – ADC
General-purpose digital I/O
P6.5/A5 2 2 E4 I/O Analog input A5 – ADC
General-purpose digital I/O
P6.6/A6 3 3 B1 I/O Analog input A6 – ADC
General-purpose digital I/O
P6.7/A7 4 4 C2 I/O Analog input A7 – ADC
General-purpose digital I/O
P7.4/A12 5 5 F4 I/O Analog input A12 –ADC
General-purpose digital I/O
P7.5/A13 6 6 C1 I/O Analog input A13 – ADC
General-purpose digital I/O
P7.6/A14 7 7 D2 I/O Analog input A14 – ADC
General-purpose digital I/O
P7.7/A15 8 8 G4 I/O Analog input A15 – ADC
General-purpose digital I/O
Analog input A8 – ADC
P5.0/A8/VREF+/VeREF+ 9 9 D1 I/O Output of reference voltage to the ADC
Input for an external reference voltage to the ADC
General-purpose digital I/O
Analog input A9 – ADC
P5.1/A9/VREF-/VeREF- 10 10 E1 I/O Negative terminal for the ADC's reference voltage for both sources, the
internal reference voltage, or an external applied reference voltage
AVCC 11 11 E2 Analog power supply
AVSS 12 12 F2 Analog ground supply
General-purpose digital I/O
P7.0/XIN 13 13 F1 I/O Input terminal for crystal oscillator XT1
General-purpose digital I/O
P7.1/XOUT 14 14 G1 I/O Output terminal of crystal oscillator XT1
DVSS1 15 15 G2 Digital ground supply
DVCC1 16 16 H2 Digital power supply
General-purpose digital I/O with port interrupt
P1.0/TA0CLK/ACLK 17 17 H1 I/O TA0 clock signal TACLK input
ACLK output (divided by 1, 2, 4, or 8)
General-purpose digital I/O with port interrupt
P1.1/TA0.0 18 18 H4 I/O TA0 CCR0 capture: CCI0A input, compare: Out0 output
BSL transmit output
General-purpose digital I/O with port interrupt
P1.2/TA0.1 19 19 J4 I/O TA0 CCR1 capture: CCI1A input, compare: Out1 output
BSL receive input
General-purpose digital I/O with port interrupt
P1.3/TA0.2 20 20 J1 I/O TA0 CCR2 capture: CCI2A input, compare: Out2 output
General-purpose digital I/O with port interrupt
P1.4/TA0.3 21 21 J2 I/O TA0 CCR3 capture: CCI3A input compare: Out3 output
General-purpose digital I/O with port interrupt
P1.5/TA0.4 22 22 K1 I/O TA0 CCR4 capture: CCI4A input, compare: Out4 output
General-purpose digital I/O with port interrupt
P1.6/SMCLK 23 23 K2 I/O SMCLK output
P1.7 24 24 L1 I/O General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
P2.0/TA1CLK/MCLK 25 25 M1 I/O TA1 clock signal TA1CLK input
MCLK output
(1) I = input, O = output, N/A = not available on this package offering
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 7
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Table 3. TERMINAL FUNCTIONS (continued)
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ PN ZQW
General-purpose digital I/O with port interrupt
P2.1/TA1.0 26 26 L2 I/O TA1 CCR0 capture: CCI0A input, compare: Out0 output
General-purpose digital I/O with port interrupt
P2.2/TA1.1 27 27 M2 I/O TA1 CCR1 capture: CCI1A input, compare: Out1 output
General-purpose digital I/O with port interrupt
P2.3/TA1.2 28 28 L3 I/O TA1 CCR2 capture: CCI2A input, compare: Out2 output
General-purpose digital I/O with port interrupt
P2.4/RTCCLK 29 29 M3 I/O RTCCLK output
P2.5 30 32 L4 I/O General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
P2.6/ACLK 31 33 M4 I/O ACLK output (divided by 1, 2, 4, 8, 16, or 32)
General-purpose digital I/O with port interrupt
P2.7/ADC12CLK/DMAE0 32 34 J5 I/O Conversion clock output ADC
DMA external trigger input
General-purpose digital I/O
Slave transmit enable – USCI_B0 SPI mode
P3.0/UCB0STE/UCA0CLK 33 35 L5 I/O Clock signal input – USCI_A0 SPI slave mode
Clock signal output – USCI_A0 SPI master mode
General-purpose digital I/O
P3.1/UCB0SIMO/UCB0SDA 34 36 M5 I/O Slave in, master out – USCI_B0 SPI mode
I2C data – USCI_B0 I2C mode
General-purpose digital I/O
P3.2/UCB0SOMI/UCB0SCL 35 37 J6 I/O Slave out, master in – USCI_B0 SPI mode
I2C clock – USCI_B0 I2C mode
General-purpose digital I/O
Clock signal input – USCI_B0 SPI slave mode
P3.3/UCB0CLK/UCA0STE 36 38 L6 I/O Clock signal output – USCI_B0 SPI master mode
Slave transmit enable – USCI_A0 SPI mode
DVSS3 37 30 M6 Digital ground supply
DVCC3 38 31 M7 Digital power supply
General-purpose digital I/O
P3.4/UCA0TXD/UCA0SIMO 39 39 L7 I/O Transmit data – USCI_A0 UART mode
Slave in, master out – USCI_A0 SPI mode
General-purpose digital I/O
P3.5/UCA0RXD/UCA0SOMI 40 40 J7 I/O Receive data – USCI_A0 UART mode
Slave out, master in – USCI_A0 SPI mode
General-purpose digital I/O
Slave transmit enable – USCI_B1 SPI mode
P3.6/UCB1STE/UCA1CLK 41 41 M8 I/O Clock signal input – USCI_A1 SPI slave mode
Clock signal output – USCI_A1 SPI master mode
General-purpose digital I/O
P3.7/UCB1SIMO/UCB1SDA 42 42 L8 I/O Slave in, master out – USCI_B1 SPI mode
I2C data – USCI_B1 I2C mode
General-purpose digital I/O
P4.0/TB0.0 43 43 J8 I/O TB0 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
General-purpose digital I/O
P4.1/TB0.1 44 44 M9 I/O TB0 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
General-purpose digital I/O
P4.2/TB0.2 45 45 L9 I/O TB0 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
General-purpose digital I/O
P4.3/TB0.3 46 46 L10 I/O TB0 capture CCR3: CCI3A/CCI3B input, compare: Out3 output
General-purpose digital I/O
P4.4/TB0.4 47 47 M10 I/O TB0 capture CCR4: CCI4A/CCI4B input, compare: Out4 output
General-purpose digital I/O
P4.5/TB0.5 48 48 L11 I/O TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output
8Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Table 3. TERMINAL FUNCTIONS (continued)
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ PN ZQW
General-purpose digital I/O
P4.6/TB0.6 49 52 M11 I/O TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output
General-purpose digital I/O
P4.7/TB0CLK/SMCLK 50 53 M12 I/O TB0 clock input
SMCLK output
General-purpose digital I/O
P5.4/UCB1SOMI/UCB1SCL 51 54 L12 I/O Slave out, master in – USCI_B1 SPI mode
I2C clock – USCI_B1 I2C mode
General-purpose digital I/O
Clock signal input – USCI_B1 SPI slave mode
P5.5/UCB1CLK/UCA1STE 52 55 J9 I/O Clock signal output – USCI_B1 SPI master mode
Slave transmit enable – USCI_A1 SPI mode
General-purpose digital I/O
P5.6/UCA1TXD/UCA1SIMO 53 56 K11 I/O Transmit data – USCI_A1 UART mode
Slave in, master out – USCI_A1 SPI mode
General-purpose digital I/O
P5.7/UCA1RXD/UCA1SOMI 54 57 K12 I/O Receive data – USCI_A1 UART mode
Slave out, master in – USCI_A1 SPI mode
General-purpose digital I/O
P7.2/TB0OUTH/SVMOUT 55 58 J11 I/O Switch all PWM outputs high impedance – Timer TB0
SVM output
General-purpose digital I/O
P7.3/TA1.2 56 59 J12 I/O TA1 CCR2 capture: CCI2B input, compare: Out2 output
General-purpose digital I/O
P8.0/TA0.0 57 60 H9 I/O TA0 CCR0 capture: CCI0B input, compare: Out0 output
General-purpose digital I/O
P8.1/TA0.1 58 61 H11 I/O TA0 CCR1 capture: CCI1B input, compare: Out1 output
General-purpose digital I/O
P8.2/TA0.2 59 62 H12 I/O TA0 CCR2 capture: CCI2B input, compare: Out2 output
General-purpose digital I/O
P8.3/TA0.3 60 63 G9 I/O TA0 CCR3 capture: CCI3B input, compare: Out3 output
General-purpose digital I/O
P8.4/TA0.4 61 64 G11 I/O TA0 CCR4 capture: CCI4B input, compare: Out4 output
Regulated core power supply output (internal usage only, no external current
VCORE(2) 62 49 G12 loading)
DVSS2 63 50 F12 Digital ground supply
DVCC2 64 51 E12 Digital power supply
General-purpose digital I/O
P8.5/TA1.0 65 65 F11 I/O TA1 CCR0 capture: CCI0B input, compare: Out0 output
General-purpose digital I/O
P8.6/TA1.1 66 66 E11 I/O TA1 CCR1 capture: CCI1B input, compare: Out1 output
P8.7 67 N/A D12 I/O General-purpose digital I/O
General-purpose digital I/O
Slave transmit enable – USCI_B2 SPI mode
P9.0/UCB2STE/UCA2CLK 68 N/A D11 I/O Clock signal input – USCI_A2 SPI slave mode
Clock signal output – USCI_A2 SPI master mode
General-purpose digital I/O
P9.1/UCB2SIMO/UCB2SDA 69 N/A F9 I/O Slave in, master out – USCI_B2 SPI mode
I2C data – USCI_B2 I2C mode
General-purpose digital I/O
P9.2/UCB2SOMI/UCB2SCL 70 N/A C12 I/O Slave out, master in – USCI_B2 SPI mode
I2C clock – USCI_B2 I2C mode
(2) VCORE is for internal usage only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 9
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Table 3. TERMINAL FUNCTIONS (continued)
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ PN ZQW
General-purpose digital I/O
Clock signal input – USCI_B2 SPI slave mode
P9.3/UCB2CLK/UCA2STE 71 N/A E9 I/O Clock signal output – USCI_B2 SPI master mode
Slave transmit enable – USCI_A2 SPI mode
General-purpose digital I/O
P9.4/UCA2TXD/UCA2SIMO 72 N/A C11 I/O Transmit data – USCI_A2 UART mode
Slave in, master out – USCI_A2 SPI mode
General-purpose digital I/O
P9.5/UCA2RXD/UCA2SOMI 73 N/A B12 I/O Receive data – USCI_A2 UART mode
Slave out, master in – USCI_A2 SPI mode
P9.6 74 N/A B11 I/O General-purpose digital I/O
P9.7 75 N/A A12 I/O General-purpose digital I/O
General-purpose digital I/O
Slave transmit enable – USCI_B3 SPI mode
P10.0/UCB3STE/UCA3CLK 76 N/A D9 I/O Clock signal input – USCI_A3 SPI slave mode
Clock signal output – USCI_A3 SPI master mode
General-purpose digital I/O
P10.1/UCB3SIMO/UCB3SDA 77 N/A A11 I/O Slave in, master out – USCI_B3 SPI mode
I2C data – USCI_B3 I2C mode
General-purpose digital I/O
P10.2/UCB3SOMI/UCB3SCL 78 N/A D8 I/O Slave out, master in – USCI_B3 SPI mode
I2C clock – USCI_B3 I2C mode
General-purpose digital I/O
Clock signal input – USCI_B3 SPI slave mode
P10.3/UCB3CLK/UCA3STE 79 N/A B10 I/O Clock signal output – USCI_B3 SPI master mode
Slave transmit enable – USCI_A3 SPI mode
General-purpose digital I/O
P10.4/UCA3TXD/UCA3SIMO 80 N/A A10 I/O Transmit data – USCI_A3 UART mode
Slave in, master out – USCI_A3 SPI mode
General-purpose digital I/O
P10.5/UCA3RXD/UCA3SOMI 81 N/A B9 I/O Receive data – USCI_A3 UART mode
Slave out, master in – USCI_A3 SPI mode
P10.6 82 N/A A9 I/O General-purpose digital I/O
P10.7 83 N/A B8 I/O General-purpose digital I/O
General-purpose digital I/O
P11.0/ACLK 84 N/A A8 I/O ACLK output (divided by 1, 2, 4, 8, 16, or 32)
General-purpose digital I/O
P11.1/MCLK 85 N/A D7 I/O MCLK output
General-purpose digital I/O
P11.2/SMCLK 86 N/A A7 I/O SMCLK output
DVCC4 87 67 B7 Digital power supply
DVSS4 88 68 B6 Digital ground supply
General-purpose digital I/O
P5.2/XT2IN 89 69 A6 I/O Input terminal for crystal oscillator XT2
General-purpose digital I/O
P5.3/XT2OUT 90 70 A5 I/O Output terminal of crystal oscillator XT2
Test mode pin – Selects four wire JTAG operation.
TEST/SBWTCK(3) 91 71 D6 I Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated
General-purpose digital I/O
PJ.0/TDO(4) 92 72 B5 I/O JTAG test data output port
General-purpose digital I/O
PJ.1/TDI/TCLK(4) 93 73 A4 I/O JTAG test data input or test clock input
(3) Please refer to Bootstrap Loader (BSL) and JTAG Operation for usage with BSL and JTAG functions
(4) Please refer to JTAG Operation for usage with JTAG function.
10 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Table 3. TERMINAL FUNCTIONS (continued)
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ PN ZQW
General-purpose digital I/O
PJ.2/TMS(4) 94 74 D5 I/O JTAG test mode select
General-purpose digital I/O
PJ.3/TCK(4) 95 75 B4 I/O JTAG test clock
Reset input active low
RST/NMI/SBWTDIO(3) 96 76 A3 I/O Non-maskable interrupt input
Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated.
General-purpose digital I/O
P6.0/A0 97 77 D4 I/O Analog input A0 – ADC
General-purpose digital I/O
P6.1/A1 98 78 B3 I/O Analog input A1 – ADC
General-purpose digital I/O
P6.2/A2 99 79 A2 I/O Analog input A2 – ADC
General-purpose digital I/O
P6.3/A3 100 80 B2 I/O Analog input A3 – ADC
Reserved N/A N/A (5)
(5) G5, E8, F8, G8, H8, E7, H7, E6, H6, E5, F5, H5, C3 are reserved and should be connected to ground.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 11
Program Counter PC/R0
Stack Pointer SP/R1
Status Register SR/CG1/R2
Constant Generator CG2/R3
General-Purpose Register R4
General-Purpose Register R5
General-Purpose Register R6
General-Purpose Register R7
General-Purpose Register R8
General-Purpose Register R9
General-Purpose Register R10
General-Purpose Register R11
General-Purpose Register R12
General-Purpose Register R13
General-Purpose Register R15
General-Purpose Register R14
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
SHORT-FORM DESCRIPTION
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The
register-to-register operation execution time is one
cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator, respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data.
12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Operating Modes
The MSP430 has one active mode and six software selectable low-power modes of operation. An interrupt event
can wake up the device from any of the low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
The following seven operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active
• Low-power mode 1 (LPM1)
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK and FLL loop control and DCOCLK are disabled
– DCO's dc-generator remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc generator is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc generator is disabled
– Crystal oscillator is stopped
– Complete data retention
• Low-power mode 4.5 (LPM4.5)
– Internal regulator disabled
– No data retention
– Wakeup from RST, digital I/O
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 13
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 4. Interrupt Sources, Flags, and Vectors
SYSTEM WORD
INTERRUPT SOURCE INTERRUPT FLAG PRIORITY
INTERRUPT ADDRESS
System Reset
Power-Up
External Reset
Watchdog Timeout, Password WDTIFG, KEYV (SYSRSTIV)(1) (2) Reset 0FFFEh 63, highest
Violation
Flash Memory Password Violation
PMM Password Violation
System NMI SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
PMM VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, (Non)maskable 0FFFCh 62
Vacant Memory Access JMBOUTIFG (SYSSNIV)(1)
JTAG Mailbox
User NMI
NMI NMIIFG, OFIFG, ACCVIFG (SYSUNIV)(1) (2) (Non)maskable 0FFFAh 61
Oscillator Fault
Flash Memory Access Violation
TB0 TBCCR0 CCIFG0 (3) Maskable 0FFF8h 60
TBCCR1 CCIFG1 ... TBCCR6 CCIFG6,
TB0 Maskable 0FFF6h 59
TBIFG (TBIV)(1) (3)
Watchdog Timer_A Interval Timer WDTIFG Maskable 0FFF4h 58
Mode
USCI_A0 Receive/Transmit UCA0RXIFG, UCA0TXIFG (UCA0IV)(1) (3) Maskable 0FFF2h 57
USCI_B0 Receive/Transmit UCB0RXIFG, UCB0TXIFG (UCAB0IV)(1) (3) Maskable 0FFF0h 56
ADC12_A ADC12IFG0 ... ADC12IFG15 (ADC12IV)(1) (3) Maskable 0FFEEh 55
TA0 TA0CCR0 CCIFG0(3) Maskable 0FFECh 54
TA0CCR1 CCIFG1 ... TA0CCR4 CCIFG4,
TA0 Maskable 0FFEAh 53
TA0IFG (TA0IV)(1) (3)
USCI_A2 Receive/Transmit UCA2RXIFG, UCA2TXIFG (UCA2IV)(1) (3) Maskable 0FFE8h 52
USCI_B2 Receive/Transmit UCB2RXIFG, UCB2TXIFG (UCB2IV)(1) (3) Maskable 0FFE6h 51
DMA DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)(1) (3) Maskable 0FFE4h 50
TA1 TA1CCR0 CCIFG0(3) Maskable 0FFE2h 49
TA1CCR1 CCIFG1 ... TA1CCR2 CCIFG2,
TA1 Maskable 0FFE0h 48
TA1IFG (TA1IV)(1) (3)
I/O Port P1 P1IFG.0 to P1IFG.7 (P1IV)(1) (3) Maskable 0FFDEh 47
USCI_A1 Receive/Transmit UCA1RXIFG, UCA1TXIFG (UCA1IV)(1) (3) Maskable 0FFDCh 46
USCI_B1 Receive/Transmit UCB1RXIFG, UCB1TXIFG (UCB1IV)(1) (3) Maskable 0FFDAh 45
USCI_A3 Receive/Transmit UCA3RXIFG, UCA3TXIFG (UCA3IV)(1) (3) Maskable 0FFD8h 44
USCI_B3 Receive/Transmit UCB3RXIFG, UCB3TXIFG (UCB3IV)(1) (3) Maskable 0FFD6h 43
I/O Port P2 P2IFG.0 to P2IFG.7 (P2IV)(1) (3) Maskable 0FFD4h 42
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RTC_A Maskable 0FFD2h 41
RT0PSIFG, RT1PSIFG (RTCIV)(1) (3)
0FFD0h 40
Reserved Reserved(4) ⋮ ⋮
0FF80h 0, lowest
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(3) Interrupt flags are located in the module.
(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, it is recommended to reserve these locations.
14 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Memory Organization
MSP430F5419A MSP430F5436A MSP430F5438A
MSP430F5418A MSP430F5435A MSP430F5437A
Memory (flash) Total Size 128 KB 192 KB 256 KB
Main: interrupt vector Flash 00FFFFh–00FF80h 00FFFFh–00FF80h 00FFFFh–00FF80h
Main: code memory Flash 025BFFh–005C00h 035BFFh–005C00h 045BFFh–005C00h
Bank 3 N/A 23 KB 64 KB
035BFFh–030000h 03FFFFh–030000h
Bank 2 23 KB 64 KB 64 KB
025BFFh–020000h 02FFFFh–020000h 02FFFFh–020000h
Main: code memory Bank 1 64 KB 64 KB 64 KB
01FFFFh–010000h 01FFFFh–010000h 01FFFFh–010000h
Bank 0 41 KB 41 KB 64 KB
00FFFFh–005C00h 00FFFFh–005C00h 045BFFh–040000h
00FFFFh–005C00h
Size 16 KB 16 KB 16 KB
Sector 3 4 KB 4 KB 4 KB
005BFFh–004C00h 005BFFh–004C00h 005BFFh–004C00h
Sector 2 4 KB 4 KB 4 KB
RAM 004BFFh–003C00h 004BFFh–003C00h 004BFFh–003C00h
Sector 1 4 KB 4 KB 4 KB
003BFFh–002C00h 003BFFh–002C00h 003BFFh–002C00h
Sector 0 4 KB 4 KB 4 KB
002BFFh–001C00h 002BFFh–001C00h 002BFFh–001C00h
Info A 128 B 128 B 128 B
0019FFh–001980h 0019FFh–001980h 0019FFh–001980h
Info B 128 B 128 B 128 B
00197Fh–001900h 00197Fh–001900h 00197Fh–001900h
Information memory
(flash) Info C 128 B 128 B 128 B
0018FFh–001880h 0018FFh–001880h 0018FFh–001880h
Info D 128 B 128 B 128 B
00187Fh–001800h 00187Fh–001800h 00187Fh–001800h
BSL 3 512 B 512 B 512 B
0017FFh–001600h 0017FFh–001600h 0017FFh–001600h
BSL 2 512 B 512 B 512 B
0015FFh–001400h 0015FFh–001400h 0015FFh–001400h
Bootstrap loader (BSL)
memory (Flash) BSL 1 512 B 512 B 512 B
0013FFh–001200h 0013FFh–001200h 0013FFh–001200h
BSL 0 512 B 512 B 512 B
0011FFh–001000h 0011FFh–001000h 0011FFh–001000h
Size 4KB 4KB 4KB
Peripherals 000FFFh–000000h 000FFFh–000000h 000FFFh–000000h
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 15
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Bootstrap Loader (BSL)
The BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the
device memory via the BSL is protected by an user-defined password. Usage of the BSL requires four pins as
shown in Table 5. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK
pins. For complete description of the features of the BSL and its implementation, see the MSP430 Memory
Programming User's Guide, literature number SLAU265.
Table 5. BSL Pin Requirements and Functions
DEVICE SIGNAL BSL FUNCTION
RST/NMI/SBWTDIO Entry sequence signal
TEST/SBWTCK Entry sequence signal
P1.1 Data transmit
P1.2 Data receive
VCC Power supply
VSS Ground supply
JTAG Operation
JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430
development tools and device programmers. The JTAG pin requirements are shown in Table 6. For further
details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's
Guide, literature number SLAU278.
Table 6. JTAG Pin Requirements and Functions
DEVICE SIGNAL DIRECTION FUNCTION
PJ.3/TCK IN JTAG clock input
PJ.2/TMS IN JTAG state control
PJ.1/TDI/TCLK IN JTAG data input/TCLK input
PJ.0/TDO OUT JTAG data output
TEST/SBWTCK IN Enable JTAG pins
RST/NMI/SBWTDIO IN External reset
VCC Power supply
VSS Ground supply
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface.
Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire
interface pin requirements are shown in Table 7. For further details on interfacing to development tools and
device programmers, see the MSP430 Hardware Tools User's Guide, literature number SLAU278.
Table 7. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL DIRECTION FUNCTION
TEST/SBWTCK IN Spy-Bi-Wire clock input
RST/NMI/SBWTDIO IN, OUT Spy-Bi-Wire data input/output
VCC Power supply
VSS Ground supply
16 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Flash Memory
The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the
flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually. Segments A to D are also called information memory.
• Segment A can be locked separately.
RAM Memory
The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage,
however all data is lost. Features of the RAM memory include:
• RAM memory has n sectors. The size of a sector can be found in Memory Organization.
• Each sector 0 to n can be complete disabled; however, data retention is lost.
• Each sector 0 to n automatically enters low-power retention mode when possible.
• For devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 17
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x5xx Family User's Guide, literature number
SLAU208.
Digital I/O
There are up to ten 8-bit I/O ports implemented: For 100-pin options, P1 through P10 are complete. P11 contains
three individual I/O ports. For 80-pin options, P1 through P7 are complete. P8 contains seven individual I/O ports.
P9 through P11 do not exist. Port PJ contains four individual I/O ports, common to all devices.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Pullup or pulldown on all ports is programmable.
• Drive strength on all ports is programmable.
• Edge-selectable interrupt and LPM4.5 wakeup input capability is available for all bits of ports P1 and P2.
• Read/write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise (P1 through P11) or word-wise in pairs (PA through PF).
Oscillator and System Clock
The clock system in the MSP430x5xx family of devices is supported by the Unified Clock System (UCS) module
that includes support for a 32-kHz watch crystal oscillator (XT1 LF mode), an internal very-low-power
low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an integrated internal
digitally controlled oscillator (DCO), and a high-frequency crystal oscillator (XT1 HF mode or XT2). The UCS
module is designed to meet the requirements of both low system cost and low power consumption. The UCS
module features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator,
stabilizes the DCO frequency to a programmable multiple of the selected FLL reference frequency. The internal
DCO provides a fast turn-on clock source and stabilizes in less than 5 µs. The UCS module provides the
following clock signals:
• Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal, a high-frequency crystal, the internal
low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitally controlled
oscillator DCO.
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by
same sources made available to ACLK.
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
Power Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains
programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor
(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is
implemented to provide the proper internal reset signal to the device during power-on and power-off. The
SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply
voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not
automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.
Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs operations with
32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations.
18 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Real-Time Clock (RTC_A)
The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated
real-time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers
that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Calendar
mode integrates an internal calendar which compensates for months with less than 31 days and includes leap
year correction. The RTC_A also supports flexible alarm functions and offset-calibration hardware.
Watchdog Timer (WDT_A)
The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 19
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
System Module (SYS)
The SYS module handles many of the system functions within the device. These include power on reset and
power up clear handling, NMI source selection and management, reset interrupt vector generators, boot strap
loader entry mechanisms, as well as, configuration management (device descriptors). It also includes a data
exchange mechanism via JTAG called a JTAG mailbox that can be used in the application.
Table 8. System Module Interrupt Vector Registers
INTERRUPT VECTOR REGISTER ADDRESS INTERRUPT EVENT VALUE PRIORITY
SYSRSTIV , System Reset 019Eh No interrupt pending 00h
Brownout (BOR) 02h Highest
RST/NMI (POR) 04h
PMMSWBOR (BOR) 06h
Wakeup from LPMx.5 08h
Security violation (BOR) 0Ah
SVSL (POR) 0Ch
SVSH (POR) 0Eh
SVML_OVP (POR) 10h
SVMH_OVP (POR) 12h
PMMSWPOR (POR) 14h
WDT timeout (PUC) 16h
WDT password violation (PUC) 18h
KEYV flash password violation (PUC) 1Ah
FLL unlock (PUC) 1Ch
Peripheral area fetch (PUC) 1Eh
PMM password violation (PUC) 20h
Reserved 22h to 3Eh Lowest
SYSSNIV , System NMI 019Ch No interrupt pending 00h
SVMLIFG 02h Highest
SVMHIFG 04h
SVSMLDLYIFG 06h
SVSMHDLYIFG 08h
VMAIFG 0Ah
JMBINIFG 0Ch
JMBOUTIFG 0Eh
SVMLVLRIFG 10h
SVMHVLRIFG 12h
Reserved 14h to 1Eh Lowest
SYSUNIV, User NMI 019Ah No interrupt pending 00h
NMIFG 02h Highest
OFIFG 04h
ACCVIFG 06h
Reserved 08h
Reserved 0Ah to 1Eh Lowest
20 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU intervention. For
example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or
from a peripheral.
Table 9. DMA Trigger Assignments (1)
Channel
Trigger 0 1 2
0 DMAREQ DMAREQ DMAREQ
1 TA0CCR0 CCIFG TA0CCR0 CCIFG TA0CCR0 CCIFG
2 TA0CCR2 CCIFG TA0CCR2 CCIFG TA0CCR2 CCIFG
3 TA1CCR0 CCIFG TA1CCR0 CCIFG TA1CCR0 CCIFG
4 TA1CCR2 CCIFG TA1CCR2 CCIFG TA1CCR2 CCIFG
5 TB0CCR0 CCIFG TB0CCR0 CCIFG TB0CCR0 CCIFG
6 TB0CCR2 CCIFG TB0CCR2 CCIFG TB0CCR2 CCIFG
7 Reserved Reserved Reserved
8 Reserved Reserved Reserved
9 Reserved Reserved Reserved
10 Reserved Reserved Reserved
11 Reserved Reserved Reserved
12 Reserved Reserved Reserved
13 Reserved Reserved Reserved
14 Reserved Reserved Reserved
15 Reserved Reserved Reserved
16 UCA0RXIFG UCA0RXIFG UCA0RXIFG
17 UCA0TXIFG UCA0TXIFG UCA0TXIFG
18 UCB0RXIFG UCB0RXIFG UCB0RXIFG
19 UCB0TXIFG UCB0TXIFG UCB0TXIFG
20 UCA1RXIFG UCA1RXIFG UCA1RXIFG
21 UCA1TXIFG UCA1TXIFG UCA1TXIFG
22 UCB1RXIFG UCB1RXIFG UCB1RXIFG
23 UCB1TXIFG UCB1TXIFG UCB1TXIFG
24 ADC12IFGx ADC12IFGx ADC12IFGx
25 Reserved Reserved Reserved
26 Reserved Reserved Reserved
27 Reserved Reserved Reserved
28 Reserved Reserved Reserved
29 MPY ready MPY ready MPY ready
30 DMA2IFG DMA0IFG DMA1IFG
31 DMAE0 DMAE0 DMAE0
(1) Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers will not
cause any DMA trigger event when selected.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 21
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Universal Serial Communication Interface (USCI)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as
UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module contains two portions,
A and B.
The USCI_An module provides support for SPI (3 pin or 4 pin), UART, enhanced UART, or IrDA.
The USCI_Bn module provides support for SPI (3 pin or 4 pin) or I2C.
The MSP430F5438A, MSP430F5436A, and MSP430F5419A include four complete USCI modules (n = 0 to 3).
The MSP430F5437A, MSP430F5435A, and MSP430F5418A include two complete USCI modules (n = 0 to 1).
TA0
TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. It can support multiple
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may
be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 10. TA0 Signal Connections
INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER
MODULE
INPUT INPUT OUTPUT OUTPUT
BLOCK
PZ/ZQW PN PZ/ZQW PN
SIGNAL SIGNAL SIGNAL SIGNAL
17/H1-P1.0 17-P1.0 TA0CLK TACLK
ACLK ACLK Timer NA NA
SMCLK SMCLK
17/H1-P1.0 17-P1.0 TA0CLK TACLK
18/H4-P1.1 18-P1.1 TA0.0 CCI0A 18/H4-P1.1 18-P1.1
57/H9-P8.0 60-P8.0 TA0.0 CCI0B 57/H9-P8.0 60-P8.0
CCR0 TA0 TA0.0 ADC12 (internal) ADC12 (internal)
DVSS GND ADC12SHSx = {1} ADC12SHSx = {1}
DVCC VCC
19/J4-P1.2 19-P1.2 TA0.1 CCI1A 19/J4-P1.2 19-P1.2
58/H11-P8.1 61-P8.1 TA0.1 CCI1B 58/H11-P8.1 61-P8.1
CCR1 TA1 TA0.1
DVSS GND
DVCC VCC
20/J1-P1.3 20-P1.3 TA0.2 CCI2A 20/J1-P1.3 20-P1.3
59/H12-P8.2 62-P8.2 TA0.2 CCI2B 59/H12-P8.2 62-P8.2
CCR2 TA2 TA0.2
DVSS GND
DVCC VCC
21/J2-P1.4 21-P1.4 TA0.3 CCI3A 21/J2-P1.4 21-P1.4
60/G9-P8.3 63-P8.3 TA0.3 CCI3B 60/G9-P8.3 63-P8.3
CCR3 TA3 TA0.3
DVSS GND
DVCC VCC
22/K1-P1.5 22-P1.5 TA0.4 CCI4A 22/K1-P1.5 22-P1.5
61/G11-P8.4 64-P8.4 TA0.4 CCI4B 61/G11-P8.4 64-P8.4
CCR4 TA4 TA0.4
DVSS GND
DVCC VCC
22 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
TA1
TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It can support multiple
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may
be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 11. TA1 Signal Connections
INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER
MODULE
INPUT INPUT OUTPUT OUTPUT
BLOCK
PZ/ZQW PN PZ/ZQW PN
SIGNAL SIGNAL SIGNAL SIGNAL
25/M1-P2.0 25-P2.0 TA1CLK TACLK
ACLK ACLK Timer NA NA
SMCLK SMCLK
25/M1-P2.0 25-P2.0 TA1CLK TACLK
26/L2-P2.1 26-P2.1 TA1.0 CCI0A 26/L2-P2.1 26-P2.1
65/F11-P8.5 65-P8.5 TA1.0 CCI0B 65/F11-P8.5 65-P8.5
CCR0 TA0 TA1.0
DVSS GND
DVCC VCC
27/M2-P2.2 27-P2.2 TA1.1 CCI1A 27/M2-P2.2 27-P2.2
66/E11-P8.6 66-P8.6 TA1.1 CCI1B 66/E11-P8.6 66-P8.6
CCR1 TA1 TA1.1
DVSS GND
DVCC VCC
28/L3-P2.3 28-P2.3 TA1.2 CCI2A 28/L3-P2.3 28-P2.3
56/J12-P7.3 59-P7.3 TA1.2 CCI2B 56/J12-P7.3 59-P7.3
CCR2 TA2 TA1.2
DVSS GND
DVCC VCC
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 23
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
TB0
TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. It can support multiple
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may
be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 12. TB0 Signal Connections
INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER
MODULE
INPUT INPUT OUTPUT OUTPUT
BLOCK
PZ/ZQW PN PZ/ZQW PN
SIGNAL SIGNAL SIGNAL SIGNAL
50/M12-P4.7 53-P4.7 TB0CLK TBCLK
ACLK ACLK Timer NA NA
SMCLK SMCLK
50/M12-P4.7 53-P4.7 TB0CLK TBCLK
43/J8-P4.0 43-P4.0 TB0.0 CCI0A 43/J8-P4.0 43-P4.0
ADC12 (internal) ADC12 (internal)
43/J8-P4.0 43-P4.0 TB0.0 CCI0B ADC12SHSx = {2} ADC12SHSx = {2}
CCR0 TB0 TB0.0
DVSS GND
DVCC VCC
44/M9-P4.1 44-P4.1 TB0.1 CCI1A 44/M9-P4.1 44-P4.1
ADC12 (internal) ADC12 (internal)
44/M9-P4.1 44-P4.1 TB0.1 CCI1B ADC12SHSx = {3} ADC12SHSx = {3}
CCR1 TB1 TB0.1
DVSS GND
DVCC VCC
45/L9-P4.2 45-P4.2 TB0.2 CCI2A 45/L9-P4.2 45-P4.2
45/L9-P4.2 45-P4.2 TB0.2 CCI2B CCR2 TB2 TB0.2
DVSS GND
DVCC VCC
46/L10-P4.3 46-P4.3 TB0.3 CCI3A 46/L10-P4.3 46-P4.3
46/L10-P4.3 46-P4.3 TB0.3 CCI3B CCR3 TB3 TB0.3
DVSS GND
DVCC VCC
47/M10-P4.4 47-P4.4 TB0.4 CCI4A 47/M10-P4.4 47-P4.4
47/M10-P4.4 47-P4.4 TB0.4 CCI4B CCR4 TB4 TB0.4
DVSS GND
DVCC VCC
48/L11-P4.5 48-P4.5 TB0.5 CCI5A 48/L11-P4.5 48-P4.5
48/L11-P4.5 48-P4.5 TB0.5 CCI5B CCR5 TB5 TB0.5
DVSS GND
DVCC VCC
49/M11-P4.6 52-P4.6 TB0.6 CCI6A 49/M11-P4.6 52-P4.6
ACLK CCI6B
(internal) CCR6 TB6 TB0.6
DVSS GND
DVCC VCC
24 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
ADC12_A
The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any
CPU intervention.
CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used for data
checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
REF Voltage Reference
The reference module (REF) is responsible for generation of all critical reference voltages that can be used by
the various analog peripherals in the device.
Embedded Emulation Module (EEM, L Version)
The Embedded Emulation Module (EEM) supports real-time in-system debugging. The L version of the EEM
implemented on all devices has the following features:
• Eight hardware triggers/breakpoints on memory access
• Two hardware trigger/breakpoint on CPU register write access
• Up to ten hardware triggers can be combined to form complex triggers/breakpoints
• Two cycle counters
• Sequencer
• State storage
• Clock control on module level
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 25
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Peripheral File Map
Table 13. Peripherals
OFFSET ADDRESS
MODULE NAME BASE ADDRESS RANGE
Special Functions (refer to Table 14) 0100h 000h - 01Fh
PMM (refer to Table 15) 0120h 000h - 010h
Flash Control (refer to Table 16) 0140h 000h - 00Fh
CRC16 (refer to Table 17) 0150h 000h - 007h
RAM Control (refer to Table 18) 0158h 000h - 001h
Watchdog (refer to Table 19) 015Ch 000h - 001h
UCS (refer to Table 20) 0160h 000h - 01Fh
SYS (refer to Table 21) 0180h 000h - 01Fh
Shared Reference (refer to Table 22) 01B0h 000h - 001h
Port P1/P2 (refer to Table 23) 0200h 000h - 01Fh
Port P3/P4 (refer to Table 24) 0220h 000h - 00Bh
Port P5/P6 (refer to Table 25) 0240h 000h - 00Bh
Port P7/P8 (refer to Table 26) 0260h 000h - 00Bh
Port P9/P10 (refer to Table 27) 0280h 000h - 00Bh
Port P11 (refer to Table 28) 02A0h 000h - 00Ah
Port PJ (refer to Table 29) 0320h 000h - 01Fh
TA0 (refer to Table 30) 0340h 000h - 02Eh
TA1 (refer to Table 31) 0380h 000h - 02Eh
TB0 (refer to Table 32) 03C0h 000h - 02Eh
Real Timer Clock (RTC_A) (refer to Table 33) 04A0h 000h - 01Bh
32-bit Hardware Multiplier (refer to Table 34) 04C0h 000h - 02Fh
DMA General Control (refer to Table 35) 0500h 000h - 00Fh
DMA Channel 0 (refer to Table 35) 0510h 000h - 00Ah
DMA Channel 1 (refer to Table 35) 0520h 000h - 00Ah
DMA Channel 2 (refer to Table 35) 0530h 000h - 00Ah
USCI_A0 (refer to Table 36) 05C0h 000h - 01Fh
USCI_B0 (refer to Table 37) 05E0h 000h - 01Fh
USCI_A1 (refer to Table 38) 0600h 000h - 01Fh
USCI_B1 (refer to Table 39) 0620h 000h - 01Fh
USCI_A2 (refer to Table 40) 0640h 000h - 01Fh
USCI_B2 (refer to Table 41) 0660h 000h - 01Fh
USCI_A3 (refer to Table 42) 0680h 000h - 01Fh
USCI_B3 (refer to Table 43) 06A0h 000h - 01Fh
ADC12_A (refer to Table 44) 0700h 000h - 03Eh
26 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Table 14. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION REGISTER OFFSET
SFR interrupt enable SFRIE1 00h
SFR interrupt flag SFRIFG1 02h
SFR reset pin control SFRRPCR 04h
Table 15. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION REGISTER OFFSET
PMM Control 0 PMMCTL0 00h
PMM control 1 PMMCTL1 02h
SVS high side control SVSMHCTL 04h
SVS low side control SVSMLCTL 06h
PMM interrupt flags PMMIFG 0Ch
PMM interrupt enable PMMIE 0Eh
PMM power mode 5 control PM5CTL0 10h
Table 16. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION REGISTER OFFSET
Flash control 1 FCTL1 00h
Flash control 3 FCTL3 04h
Flash control 4 FCTL4 06h
Table 17. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION REGISTER OFFSET
CRC data input CRC16DI 00h
CRC data input reverse byte CRCDIRB 02h
CRC initialization and result CRCINIRES 04h
CRC result reverse byte CRCRESR 06h
Table 18. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION REGISTER OFFSET
RAM control 0 RCCTL0 00h
Table 19. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION REGISTER OFFSET
Watchdog timer control WDTCTL 00h
Table 20. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTION REGISTER OFFSET
UCS control 0 UCSCTL0 00h
UCS control 1 UCSCTL1 02h
UCS control 2 UCSCTL2 04h
UCS control 3 UCSCTL3 06h
UCS control 4 UCSCTL4 08h
UCS control 5 UCSCTL5 0Ah
UCS control 6 UCSCTL6 0Ch
UCS control 7 UCSCTL7 0Eh
UCS control 8 UCSCTL8 10h
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 27
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Table 21. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION REGISTER OFFSET
System control SYSCTL 00h
Bootstrap loader configuration area SYSBSLC 02h
JTAG mailbox control SYSJMBC 06h
JTAG mailbox input 0 SYSJMBI0 08h
JTAG mailbox input 1 SYSJMBI1 0Ah
JTAG mailbox output 0 SYSJMBO0 0Ch
JTAG mailbox output 1 SYSJMBO1 0Eh
Bus Error vector generator SYSBERRIV 18h
User NMI vector generator SYSUNIV 1Ah
System NMI vector generator SYSSNIV 1Ch
Reset vector generator SYSRSTIV 1Eh
Table 22. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION REGISTER OFFSET
Shared reference control REFCTL 00h
Table 23. Port P1/P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION REGISTER OFFSET
Port P1 input P1IN 00h
Port P1 output P1OUT 02h
Port P1 direction P1DIR 04h
Port P1 pullup/pulldown enable P1REN 06h
Port P1 drive strength P1DS 08h
Port P1 selection P1SEL 0Ah
Port P1 interrupt vector word P1IV 0Eh
Port P1 interrupt edge select P1IES 18h
Port P1 interrupt enable P1IE 1Ah
Port P1 interrupt flag P1IFG 1Ch
Port P2 input P2IN 01h
Port P2 output P2OUT 03h
Port P2 direction P2DIR 05h
Port P2 pullup/pulldown enable P2REN 07h
Port P2 drive strength P2DS 09h
Port P2 selection P2SEL 0Bh
Port P2 interrupt vector word P2IV 1Eh
Port P2 interrupt edge select P2IES 19h
Port P2 interrupt enable P2IE 1Bh
Port P2 interrupt flag P2IFG 1Dh
28 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Table 24. Port P3/P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION REGISTER OFFSET
Port P3 input P3IN 00h
Port P3 output P3OUT 02h
Port P3 direction P3DIR 04h
Port P3 pullup/pulldown enable P3REN 06h
Port P3 drive strength P3DS 08h
Port P3 selection P3SEL 0Ah
Port P4 input P4IN 01h
Port P4 output P4OUT 03h
Port P4 direction P4DIR 05h
Port P4 pullup/pulldown enable P4REN 07h
Port P4 drive strength P4DS 09h
Port P4 selection P4SEL 0Bh
Table 25. Port P5/P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION REGISTER OFFSET
Port P5 input P5IN 00h
Port P5 output P5OUT 02h
Port P5 direction P5DIR 04h
Port P5 pullup/pulldown enable P5REN 06h
Port P5 drive strength P5DS 08h
Port P5 selection P5SEL 0Ah
Port P6 input P6IN 01h
Port P6 output P6OUT 03h
Port P6 direction P6DIR 05h
Port P6 pullup/pulldown enable P6REN 07h
Port P6 drive strength P6DS 09h
Port P6 selection P6SEL 0Bh
Table 26. Port P7/P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTION REGISTER OFFSET
Port P7 input P7IN 00h
Port P7 output P7OUT 02h
Port P7 direction P7DIR 04h
Port P7 pullup/pulldown enable P7REN 06h
Port P7 drive strength P7DS 08h
Port P7 selection P7SEL 0Ah
Port P8 input P8IN 01h
Port P8 output P8OUT 03h
Port P8 direction P8DIR 05h
Port P8 pullup/pulldown enable P8REN 07h
Port P8 drive strength P8DS 09h
Port P8 selection P8SEL 0Bh
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 29
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Table 27. Port P9/P10 Registers (Base Address: 0280h)
REGISTER DESCRIPTION REGISTER OFFSET
Port P9 input P9IN 00h
Port P9 output P9OUT 02h
Port P9 direction P9DIR 04h
Port P9 pullup/pulldown enable P9REN 06h
Port P9 drive strength P9DS 08h
Port P9 selection P9SEL 0Ah
Port P10 input P10IN 01h
Port P10 output P10OUT 03h
Port P10 direction P10DIR 05h
Port P10 pullup/pulldown enable P10REN 07h
Port P10 drive strength P10DS 09h
Port P10 selection P10SEL 0Bh
Table 28. Port P11 Registers (Base Address: 02A0h)
REGISTER DESCRIPTION REGISTER OFFSET
Port P11 input P11IN 00h
Port P11 output P11OUT 02h
Port P11 direction P11DIR 04h
Port P11 pullup/pulldown enable P11REN 06h
Port P11 drive strength P11DS 08h
Port P11 selection P11SEL 0Ah
Table 29. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION REGISTER OFFSET
Port PJ input PJIN 00h
Port PJ output PJOUT 02h
Port PJ direction PJDIR 04h
Port PJ pullup/pulldown enable PJREN 06h
Port PJ drive strength PJDS 08h
30 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Table 30. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION REGISTER OFFSET
TA0 control TA0CTL 00h
Capture/compare control 0 TA0CCTL0 02h
Capture/compare control 1 TA0CCTL1 04h
Capture/compare control 2 TA0CCTL2 06h
Capture/compare control 3 TA0CCTL3 08h
Capture/compare control 4 TA0CCTL4 0Ah
TA0 counter register TA0R 10h
Capture/compare register 0 TA0CCR0 12h
Capture/compare register 1 TA0CCR1 14h
Capture/compare register 2 TA0CCR2 16h
Capture/compare register 3 TA0CCR3 18h
Capture/compare register 4 TA0CCR4 1Ah
TA0 expansion register 0 TA0EX0 20h
TA0 interrupt vector TA0IV 2Eh
Table 31. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION REGISTER OFFSET
TA1 control TA1CTL 00h
Capture/compare control 0 TA1CCTL0 02h
Capture/compare control 1 TA1CCTL1 04h
Capture/compare control 2 TA1CCTL2 06h
TA1 counter register TA1R 10h
Capture/compare register 0 TA1CCR0 12h
Capture/compare register 1 TA1CCR1 14h
Capture/compare register 2 TA1CCR2 16h
TA1 expansion register 0 TA1EX0 20h
TA1 interrupt vector TA1IV 2Eh
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 31
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Table 32. TB0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION REGISTER OFFSET
TB0 control TB0CTL 00h
Capture/compare control 0 TB0CCTL0 02h
Capture/compare control 1 TB0CCTL1 04h
Capture/compare control 2 TB0CCTL2 06h
Capture/compare control 3 TB0CCTL3 08h
Capture/compare control 4 TB0CCTL4 0Ah
Capture/compare control 5 TB0CCTL5 0Ch
Capture/compare control 6 TB0CCTL6 0Eh
TB0 register TB0R 10h
Capture/compare register 0 TB0CCR0 12h
Capture/compare register 1 TB0CCR1 14h
Capture/compare register 2 TB0CCR2 16h
Capture/compare register 3 TB0CCR3 18h
Capture/compare register 4 TB0CCR4 1Ah
Capture/compare register 5 TB0CCR5 1Ch
Capture/compare register 6 TB0CCR6 1Eh
TB0 expansion register 0 TB0EX0 20h
TB0 interrupt vector TB0IV 2Eh
Table 33. Real Time Clock Registers (Base Address: 04A0h)
REGISTER DESCRIPTION REGISTER OFFSET
RTC control 0 RTCCTL0 00h
RTC control 1 RTCCTL1 01h
RTC control 2 RTCCTL2 02h
RTC control 3 RTCCTL3 03h
RTC prescaler 0 control RTCPS0CTL 08h
RTC prescaler 1 control RTCPS1CTL 0Ah
RTC prescaler 0 RTCPS0 0Ch
RTC prescaler 1 RTCPS1 0Dh
RTC interrupt vector word RTCIV 0Eh
RTC seconds/counter register 1 RTCSEC/RTCNT1 10h
RTC minutes/counter register 2 RTCMIN/RTCNT2 11h
RTC hours/counter register 3 RTCHOUR/RTCNT3 12h
RTC day of week/counter register 4 RTCDOW/RTCNT4 13h
RTC days RTCDAY 14h
RTC month RTCMON 15h
RTC year low RTCYEARL 16h
RTC year high RTCYEARH 17h
RTC alarm minutes RTCAMIN 18h
RTC alarm hours RTCAHOUR 19h
RTC alarm day of week RTCADOW 1Ah
RTC alarm days RTCADAY 1Bh
32 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Table 34. 32-bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION REGISTER OFFSET
16-bit operand 1 – multiply MPY 00h
16-bit operand 1 – signed multiply MPYS 02h
16-bit operand 1 – multiply accumulate MAC 04h
16-bit operand 1 – signed multiply accumulate MACS 06h
16-bit operand 2 OP2 08h
16 × 16 result low word RESLO 0Ah
16 × 16 result high word RESHI 0Ch
16 × 16 sum extension register SUMEXT 0Eh
32-bit operand 1 – multiply low word MPY32L 10h
32-bit operand 1 – multiply high word MPY32H 12h
32-bit operand 1 – signed multiply low word MPYS32L 14h
32-bit operand 1 – signed multiply high word MPYS32H 16h
32-bit operand 1 – multiply accumulate low word MAC32L 18h
32-bit operand 1 – multiply accumulate high word MAC32H 1Ah
32-bit operand 1 – signed multiply accumulate low word MACS32L 1Ch
32-bit operand 1 – signed multiply accumulate high word MACS32H 1Eh
32-bit operand 2 – low word OP2L 20h
32-bit operand 2 – high word OP2H 22h
32 × 32 result 0 – least significant word RES0 24h
32 × 32 result 1 RES1 26h
32 × 32 result 2 RES2 28h
32 × 32 result 3 – most significant word RES3 2Ah
MPY32 control register 0 MPY32CTL0 2Ch
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 33
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Table 35. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)
REGISTER DESCRIPTION REGISTER OFFSET
DMA channel 0 control DMA0CTL 00h
DMA channel 0 source address low DMA0SAL 02h
DMA channel 0 source address high DMA0SAH 04h
DMA channel 0 destination address low DMA0DAL 06h
DMA channel 0 destination address high DMA0DAH 08h
DMA channel 0 transfer size DMA0SZ 0Ah
DMA channel 1 control DMA1CTL 00h
DMA channel 1 source address low DMA1SAL 02h
DMA channel 1 source address high DMA1SAH 04h
DMA channel 1 destination address low DMA1DAL 06h
DMA channel 1 destination address high DMA1DAH 08h
DMA channel 1 transfer size DMA1SZ 0Ah
DMA channel 2 control DMA2CTL 00h
DMA channel 2 source address low DMA2SAL 02h
DMA channel 2 source address high DMA2SAH 04h
DMA channel 2 destination address low DMA2DAL 06h
DMA channel 2 destination address high DMA2DAH 08h
DMA channel 2 transfer size DMA2SZ 0Ah
DMA module control 0 DMACTL0 00h
DMA module control 1 DMACTL1 02h
DMA module control 2 DMACTL2 04h
DMA module control 3 DMACTL3 06h
DMA module control 4 DMACTL4 08h
DMA interrupt vector DMAIV 0Eh
Table 36. USCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION REGISTER OFFSET
USCI control 1 UCA0CTL1 00h
USCI control 0 UCA0CTL0 01h
USCI baud rate 0 UCA0BR0 06h
USCI baud rate 1 UCA0BR1 07h
USCI modulation control UCA0MCTL 08h
USCI status UCA0STAT 0Ah
USCI receive buffer UCA0RXBUF 0Ch
USCI transmit buffer UCA0TXBUF 0Eh
USCI LIN control UCA0ABCTL 10h
USCI IrDA transmit control UCA0IRTCTL 12h
USCI IrDA receive control UCA0IRRCTL 13h
USCI interrupt enable UCA0IE 1Ch
USCI interrupt flags UCA0IFG 1Dh
USCI interrupt vector word UCA0IV 1Eh
34 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Table 37. USCI_B0 Registers (Base Address: 05E0h)
REGISTER DESCRIPTION REGISTER OFFSET
USCI synchronous control 1 UCB0CTL1 00h
USCI synchronous control 0 UCB0CTL0 01h
USCI synchronous bit rate 0 UCB0BR0 06h
USCI synchronous bit rate 1 UCB0BR1 07h
USCI synchronous status UCB0STAT 0Ah
USCI synchronous receive buffer UCB0RXBUF 0Ch
USCI synchronous transmit buffer UCB0TXBUF 0Eh
USCI I2C own address UCB0I2COA 10h
USCI I2C slave address UCB0I2CSA 12h
USCI interrupt enable UCB0IE 1Ch
USCI interrupt flags UCB0IFG 1Dh
USCI interrupt vector word UCB0IV 1Eh
Table 38. USCI_A1 Registers (Base Address: 0600h)
REGISTER DESCRIPTION REGISTER OFFSET
USCI control 1 UCA1CTL1 00h
USCI control 0 UCA1CTL0 01h
USCI baud rate 0 UCA1BR0 06h
USCI baud rate 1 UCA1BR1 07h
USCI modulation control UCA1MCTL 08h
USCI status UCA1STAT 0Ah
USCI receive buffer UCA1RXBUF 0Ch
USCI transmit buffer UCA1TXBUF 0Eh
USCI LIN control UCA1ABCTL 10h
USCI IrDA transmit control UCA1IRTCTL 12h
USCI IrDA receive control UCA1IRRCTL 13h
USCI interrupt enable UCA1IE 1Ch
USCI interrupt flags UCA1IFG 1Dh
USCI interrupt vector word UCA1IV 1Eh
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 35
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Table 39. USCI_B1 Registers (Base Address: 0620h)
REGISTER DESCRIPTION REGISTER OFFSET
USCI synchronous control 1 UCB1CTL1 00h
USCI synchronous control 0 UCB1CTL0 01h
USCI synchronous bit rate 0 UCB1BR0 06h
USCI synchronous bit rate 1 UCB1BR1 07h
USCI synchronous status UCB1STAT 0Ah
USCI synchronous receive buffer UCB1RXBUF 0Ch
USCI synchronous transmit buffer UCB1TXBUF 0Eh
USCI I2C own address UCB1I2COA 10h
USCI I2C slave address UCB1I2CSA 12h
USCI interrupt enable UCB1IE 1Ch
USCI interrupt flags UCB1IFG 1Dh
USCI interrupt vector word UCB1IV 1Eh
Table 40. USCI_A2 Registers (Base Address: 0640h)
REGISTER DESCRIPTION REGISTER OFFSET
USCI control 1 UCA2CTL1 00h
USCI control 0 UCA2CTL0 01h
USCI baud rate 0 UCA2BR0 06h
USCI baud rate 1 UCA2BR1 07h
USCI modulation control UCA2MCTL 08h
USCI status UCA2STAT 0Ah
USCI receive buffer UCA2RXBUF 0Ch
USCI transmit buffer UCA2TXBUF 0Eh
USCI LIN control UCA2ABCTL 10h
USCI IrDA transmit control UCA2IRTCTL 12h
USCI IrDA receive control UCA2IRRCTL 13h
USCI interrupt enable UCA2IE 1Ch
USCI interrupt flags UCA2IFG 1Dh
USCI interrupt vector word UCA2IV 1Eh
Table 41. USCI_B2 Registers (Base Address: 0660h)
REGISTER DESCRIPTION REGISTER OFFSET
USCI synchronous control 1 UCB2CTL1 00h
USCI synchronous control 0 UCB2CTL0 01h
USCI synchronous bit rate 0 UCB2BR0 06h
USCI synchronous bit rate 1 UCB2BR1 07h
USCI synchronous status UCB2STAT 0Ah
USCI synchronous receive buffer UCB2RXBUF 0Ch
USCI synchronous transmit buffer UCB2TXBUF 0Eh
USCI I2C own address UCB2I2COA 10h
USCI I2C slave address UCB2I2CSA 12h
USCI interrupt enable UCB2IE 1Ch
USCI interrupt flags UCB2IFG 1Dh
USCI interrupt vector word UCB2IV 1Eh
36 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Table 42. USCI_A3 Registers (Base Address: 0680h)
REGISTER DESCRIPTION REGISTER OFFSET
USCI control 1 UCA3CTL1 00h
USCI control 0 UCA3CTL0 01h
USCI baud rate 0 UCA3BR0 06h
USCI baud rate 1 UCA3BR1 07h
USCI modulation control UCA3MCTL 08h
USCI status UCA3STAT 0Ah
USCI receive buffer UCA3RXBUF 0Ch
USCI transmit buffer UCA3TXBUF 0Eh
USCI LIN control UCA3ABCTL 10h
USCI IrDA transmit control UCA3IRTCTL 12h
USCI IrDA receive control UCA3IRRCTL 13h
USCI interrupt enable UCA3IE 1Ch
USCI interrupt flags UCA3IFG 1Dh
USCI interrupt vector word UCA3IV 1Eh
Table 43. USCI_B3 Registers (Base Address: 06A0h)
REGISTER DESCRIPTION REGISTER OFFSET
USCI synchronous control 1 UCB3CTL1 00h
USCI synchronous control 0 UCB3CTL0 01h
USCI synchronous bit rate 0 UCB3BR0 06h
USCI synchronous bit rate 1 UCB3BR1 07h
USCI synchronous status UCB3STAT 0Ah
USCI synchronous receive buffer UCB3RXBUF 0Ch
USCI synchronous transmit buffer UCB3TXBUF 0Eh
USCI I2C own address UCB3I2COA 10h
USCI I2C slave address UCB3I2CSA 12h
USCI interrupt enable UCB3IE 1Ch
USCI interrupt flags UCB3IFG 1Dh
USCI interrupt vector word UCB3IV 1Eh
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 37
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Table 44. ADC12_A Registers (Base Address: 0700h)
REGISTER DESCRIPTION REGISTER OFFSET
Control register 0 ADC12CTL0 00h
Control register 1 ADC12CTL1 02h
Control register 2 ADC12CTL2 04h
Interrupt-flag register ADC12IFG 0Ah
Interrupt-enable register ADC12IE 0Ch
Interrupt-vector-word register ADC12IV 0Eh
ADC memory-control register 0 ADC12MCTL0 10h
ADC memory-control register 1 ADC12MCTL1 11h
ADC memory-control register 2 ADC12MCTL2 12h
ADC memory-control register 3 ADC12MCTL3 13h
ADC memory-control register 4 ADC12MCTL4 14h
ADC memory-control register 5 ADC12MCTL5 15h
ADC memory-control register 6 ADC12MCTL6 16h
ADC memory-control register 7 ADC12MCTL7 17h
ADC memory-control register 8 ADC12MCTL8 18h
ADC memory-control register 9 ADC12MCTL9 19h
ADC memory-control register 10 ADC12MCTL10 1Ah
ADC memory-control register 11 ADC12MCTL11 1Bh
ADC memory-control register 12 ADC12MCTL12 1Ch
ADC memory-control register 13 ADC12MCTL13 1Dh
ADC memory-control register 14 ADC12MCTL14 1Eh
ADC memory-control register 15 ADC12MCTL15 1Fh
Conversion memory 0 ADC12MEM0 20h
Conversion memory 1 ADC12MEM1 22h
Conversion memory 2 ADC12MEM2 24h
Conversion memory 3 ADC12MEM3 26h
Conversion memory 4 ADC12MEM4 28h
Conversion memory 5 ADC12MEM5 2Ah
Conversion memory 6 ADC12MEM6 2Ch
Conversion memory 7 ADC12MEM7 2Eh
Conversion memory 8 ADC12MEM8 30h
Conversion memory 9 ADC12MEM9 32h
Conversion memory 10 ADC12MEM10 34h
Conversion memory 11 ADC12MEM11 36h
Conversion memory 12 ADC12MEM12 38h
Conversion memory 13 ADC12MEM13 3Ah
Conversion memory 14 ADC12MEM14 3Ch
Conversion memory 15 ADC12MEM15 3Eh
38 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
Voltage applied at VCC to VSS –0.3 V to 4.1 V
Voltage applied to any pin (excluding VCORE)(2) –0.3 V to VCC + 0.3 V
Diode current at any device pin ±2 mA
Storage temperature range, Tstg (3) –55°C to 105°C
Maximum junction temperature, TJ95°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. VCORE is for internal device usage only. No external DC loading or voltage should be applied.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Thermal Packaging Characteristics VALUE UNIT
QFP (PZ) 50.1
Low-K board (JESD51-3) QFP (PN) 57.9
BGA (ZQW) 60
qJA Junction-to-ambient thermal resistance, still air °C/W
QFP (PZ) 40.8
High-K board (JESD51-7) QFP (PN) 37.9
BGA (ZQW) 42
QFP (PZ) 8.9
qJC Junction-to-case thermal resistance QFP (PN) 10.3 °C/W
BGA (ZQW) 8
Recommended Operating Conditions MIN NOM MAX UNIT
Supply voltage during program execution and flash programming
VCC 1.8 3.6 V
(AVCC = DVCC1/2/3/4 = DVCC)(1)
VSS Supply voltage (AVSS = DVSS1/2/3/4 = DVSS) 0 V
TAOperating free-air temperature I version –40 85 °C
TJOperating junction temperature I version –40 85 °C
CVCORE Recommended capacitor at VCORE 470 nF
CDVCC/C Capacitor ratio of DVCC to VCORE 10
VCORE PMMCOREVx = 0, 1.8 V ≤VCC ≤3.6 V 0 8.0
PMMCOREVx = 1, 2.0 V ≤VCC ≤3.6 V 0 12.0
Processor frequency (maximum MCLK
fSYSTEM MHz
frequency)(2) (3) (see Figure 1)PMMCOREVx = 2, 2.2 V ≤VCC ≤3.6 V 0 20.0
PMMCOREVx = 3, 2.4 V ≤VCC ≤3.6 V 0 25.0
(1) It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
(2) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
(3) Modules may have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 39
2.01.8
8
0
12
20
25
SystemFrequency-MHz
SupplyVoltage-V
ThenumberswithinthefieldsdenotethesupportedPMMCOREVxsettings.
2.2 2.4 3.6
0,1,2,30,1,20,10
1,2,3
1,2
1
2,3
3
2
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Figure 1. Frequency vs Supply Voltage
40 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Electrical Characteristics
Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted)(1) (2) (3)
FREQUENCY (fDCO = fMCLK = fSMCLK)
EXECUTION
PARAMETER VCC PMMCOREVx 1 MHz 8 MHz 12 MHz 20 MHz 25 MHz UNIT
MEMORY TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX
0 0.29 0.33 1.84 2.08
1 0.32 2.08 3.10
IAM, Flash Flash 3.0 V mA
2 0.33 2.24 3.50 6.37
3 0.35 2.36 3.70 6.75 8.90 9.60
0 0.17 0.19 0.88 0.99
1 0.18 1.00 1.47
IAM, RAM RAM 3.0 V mA
2 0.19 1.13 1.68 2.82
3 0.20 1.20 1.78 3.00 4.50 4.90
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
(3) Characterized with program executing typical data processing.
fACLK = 32768 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 41
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
-40°C 25°C 60°C 85°C
PARAMETER VCC PMMCOREVx UNIT
TYP MAX TYP MAX TYP MAX TYP MAX
2.2 V 0 69 93 69 93 69 93 69 93
Low-power
ILPM0,1MHz µA
mode 0(3) (4) 3.0 V 3 73 100 73 100 73 100 73 100
2.2 V 0 11 15.5 11 15.5 11 15.5 11 15.5
Low-power
ILPM2 µA
mode 2(5) (4) 3.0 V 3 11.7 17.5 11.7 17.5 11.7 17.5 11.7 17.5
0 1.4 1.7 2.6 6.6
2.2 V 1 1.5 1.8 2.9 9.9
2 1.5 2.0 3.3 10.1
Low-power mode 3,
ILPM3,XT1LF 0 1.8 2.1 2.4 2.8 7.1 13.6 µA
crystal mode(6) (4) 1 1.8 2.3 3.1 10.5
3.0 V 2 1.9 2.4 3.5 10.6
3 2.0 2.3 2.6 3.9 11.8 14.8
0 1.0 1.2 1.42 2.0 5.8 12.9
1 1.0 1.3 2.3 6.0
Low-power mode 3,
ILPM3,VLO 3.0 V µA
VLO mode(7) (4) 2 1.1 1.4 2.8 6.2
3 1.2 1.4 1.62 3.0 6.2 13.9
0 1.1 1.2 1.35 1.9 5.7 12.9
1 1.2 1.2 2.2 5.9
Low-power
ILPM4 3.0 V µA
mode 4(8) (4) 2 1.3 1.3 2.6 6.1
3 1.3 1.3 1.52 2.9 6.2 13.9
ILPM4.5 Low-power mode 4.5(9) 3.0 V 0.10 0.10 0.13 0.20 0.50 1.14 µA
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
(4) Current for brownout, high side supervisor (SVSH) normal mode included. Low side supervisor and monitors disabled (SVSL, SVML).
High side monitor disabled (SVMH). RAM retention enabled.
(5) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz; DCO setting = 1
MHz operation, DCO bias generator enabled.
(6) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
(7) Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz
(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
(9) Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
42 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Schmitt-Trigger Inputs – General Purpose I/O(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
1.8 V 0.80 1.40
VIT+ Positive-going input threshold voltage V
3 V 1.50 2.10
1.8 V 0.45 1.00
VIT– Negative-going input threshold voltage V
3 V 0.75 1.65
1.8 V 0.3 0.85
Vhys Input voltage hysteresis (VIT+ – VIT–) V
3 V 0.4 1.0
For pullup: VIN = VSS
RPull Pullup/pulldown resistor(2) 20 35 50 kΩ
For pulldown: VIN = VCC
CIInput capacitance VIN = VSS or VCC 5 pF
(1) Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).
(2) Also applies to RST pin when pullup/pulldown resistor is enabled.
Inputs – Ports P1 and P2(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
Port P1, P2: P1.x to P2.x, External trigger pulse width to
t(int) External interrupt timing(2) 2.2 V/3 V 20 ns
set interrupt flag
(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
(2) An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set by trigger signals shorter
than t(int).
Leakage Current – General Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
Ilkg(Px.x) High-impedance leakage current (1) (2) 1.8 V/3 V ±50 nA
(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 43
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Outputs – General Purpose I/O (Full Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
I(OHmax) = –3 mA(1) VCC – 0.25 VCC
1.8 V
I(OHmax) = –10 mA(2) VCC – 0.60 VCC
VOH High-level output voltage V
I(OHmax) = –5 mA(1) VCC – 0.25 VCC
3 V
I(OHmax) = –15 mA(2) VCC – 0.60 VCC
I(OLmax) = 3 mA(1) VSS VSS + 0.25
1.8 V
I(OLmax) = 10 mA(2) VSS VSS + 0.60
VOL Low-level output voltage V
I(OLmax) = 5 mA(1) VSS VSS + 0.25
3 V
I(OLmax) = 15 mA(2) VSS VSS + 0.60
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
Outputs – General Purpose I/O (Reduced Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
I(OHmax) = –1 mA(2) VCC – 0.25 VCC
1.8 V
I(OHmax) = –3 mA(3) VCC – 0.60 VCC
VOH High-level output voltage V
I(OHmax) = –2 mA(2) VCC – 0.25 VCC
3.0 V
I(OHmax) = –6 mA(3) VCC – 0.60 VCC
I(OLmax) = 1 mA(2) VSS VSS + 0.25
1.8 V
I(OLmax) = 3 mA(3) VSS VSS + 0.60
VOL Low-level output voltage V
I(OLmax) = 2 mA(2) VSS VSS + 0.25
3.0 V
I(OLmax) = 6 mA(3) VSS VSS + 0.60
(1) Selecting reduced drive strength may reduce EMI.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
(3) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
Output Frequency – General Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
VCC = 1.8 V 16
PMMCOREVx = 0
Port output frequency
fPx.y P1.6/SMCLK (1) (2) MHz
(with load) VCC = 3 V 25
PMMCOREVx = 3
VCC = 1.8 V
P1.0/TA0CLK/ACLK 16
PMMCOREVx = 0
P1.6/SMCLK
fPort_CLK Clock output frequency MHz
P2.0/TA1CLK/MCLK VCC = 3 V 25
CL= 20 pF(2) PMMCOREVx = 3
(1) A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL= 20 pF is connected to the output to VSS.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
44 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
0.0 0.5 1.0 1.5 2.0
T = 25°C
A
T = 85°C
A
V = 1.8 V
Px.y
CC
V – Low-Level Output Voltage – V
OL
I – Typical Low-Level Output Current – mA
OL
-8.0
-7.0
-6.0
-5.0
-4.0
-3.0
-2.0
-1.0
0.0
0.0 0.5 1.0 1.5 2.0
T = 25°C
A
T = 85°C
A
V = 1.8 V
Px.y
CC
V – High-Level Output Voltage – V
OH
I – Typical High-Level Output Current – mA
OH
-25.0
-20.0
-15.0
-10.0
-5.0
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
T = 25°C
A
T = 85°C
A
V = 3.0 V
Px.y
CC
V – High-Level Output Voltage – V
OH
I – Typical High-Level Output Current – mA
OH
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TYPICAL LOW-LEVEL OUTPUT CURRENT TYPICAL LOW-LEVEL OUTPUT CURRENT
vs vs
LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE
Figure 2. Figure 3.
TYPICAL HIGH-LEVEL OUTPUT CURRENT TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs vs
HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE
Figure 4. Figure 5.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 45
0
4
8
12
16
20
24
0.0 0.5 1.0 1.5 2.0
T = 25°C
A
T = 85°C
A
V = 1.8 V
Px.y
CC
V – Low-Level Output Voltage – V
OL
I – Typical Low-Level Output Current – mA
OL
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
40.0
45.0
50.0
55.0
60.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
T = 25°C
A
T = 85°C
A
V = 3.0 V
Px.y
CC
V – Low-Level Output Voltage – V
OL
I – Typical Low-Level Output Current – mA
OL
-60.0
-55.0
-50.0
-45.0
-40.0
-35.0
-30.0
-25.0
-20.0
-15.0
-10.0
-5.0
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
T = 25°C
A
T = 85°C
A
V = 3.0 V
Px.y
CC
V – High-Level Output Voltage – V
OH
I – Typical High-Level Output Current – mA
OH
-20
-16
-12
-8
-4
0
0.0 0.5 1.0 1.5 2.0
T = 25°C
A
T = 85°C
A
V = 1.8 V
Px.y
CC
V – High-Level Output Voltage – V
OH
I – Typical High-Level Output Current – mA
OH
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TYPICAL LOW-LEVEL OUTPUT CURRENT TYPICAL LOW-LEVEL OUTPUT CURRENT
vs vs
LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE
Figure 6. Figure 7.
TYPICAL HIGH-LEVEL OUTPUT CURRENT TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs vs
HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE
Figure 8. Figure 9.
46 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Crystal Oscillator, XT1, Low-Frequency Mode(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1, 0.075
TA= 25°C
Differential XT1 oscillator crystal fOSC = 32768 Hz, XTS = 0,
ΔIDVCC.LF current consumption from lowest XT1BYPASS = 0, XT1DRIVEx = 2, 3.0 V 0.170 µA
drive setting, LF mode TA= 25°C
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3, 0.290
TA= 25°C
XT1 oscillator crystal frequency,
fXT1,LF0 XTS = 0, XT1BYPASS = 0 32768 Hz
LF mode
XT1 oscillator logic-level
fXT1,LF,SW square-wave input frequency, XTS = 0, XT1BYPASS = 1(2) (3) 10 32.768 50 kHz
LF mode XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0, 210
fXT1,LF = 32768 Hz, CL,eff = 6 pF
Oscillation allowance for
OALF kΩ
LF crystals(4) XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1, 300
fXT1,LF = 32768 Hz, CL,eff = 12 pF
XTS = 0, XCAPx = 0(6) 2
XTS = 0, XCAPx = 1 5.5
Integrated effective load
CL,eff pF
capacitance, LF mode(5) XTS = 0, XCAPx = 2 8.5
XTS = 0, XCAPx = 3 12.0
XTS = 0, Measured at ACLK,
Duty cycle LF mode 30 70 %
fXT1,LF = 32768 Hz
Oscillator fault frequency,
fFault,LF XTS = 0(8) 10 10000 Hz
LF mode(7)
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0, 1000
TA= 25°C,
CL,eff = 6 pF
tSTART,LF Startup time, LF mode 3.0 V ms
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3, 500
TA= 25°C,
CL,eff = 12 pF
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(2) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this datasheet.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
(a) For XT1DRIVEx = 0, CL,ef f ≤6 pF.
(b) For XT1DRIVEx = 1, 6 pF ≤CL,ef f ≤9 pF.
(c) For XT1DRIVEx = 2, 6 pF ≤CL,ef f ≤10 pF.
(d) For XT1DRIVEx = 3, CL,ef f ≥6 pF.
(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
(6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(8) Measured with logic-level input frequency but also applies to operation with crystals.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 47
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Crystal Oscillator, XT1, High-Frequency Mode(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fOSC = 4 MHz,
XTS = 1, XOSCOFF = 0, 200
XT1BYPASS = 0, XT1DRIVEx = 0,
TA= 25°C
fOSC = 12 MHz,
XTS = 1, XOSCOFF = 0, 260
XT1BYPASS = 0, XT1DRIVEx = 1,
TA= 25°C
XT1 oscillator crystal current,
IDVCC.HF 3.0 V µA
HF mode fOSC = 20 MHz,
XTS = 1, XOSCOFF = 0, 325
XT1BYPASS = 0, XT1DRIVEx = 2,
TA= 25°C
fOSC = 32 MHz,
XTS = 1, XOSCOFF = 0, 450
XT1BYPASS = 0, XT1DRIVEx = 3,
TA= 25°C
XT1 oscillator crystal frequency, XTS = 1,
fXT1,HF0 4 8 MHz
HF mode 0 XT1BYPASS = 0, XT1DRIVEx = 0(2)
XT1 oscillator crystal frequency, XTS = 1,
fXT1,HF1 8 16 MHz
HF mode 1 XT1BYPASS = 0, XT1DRIVEx = 1(2)
XT1 oscillator crystal frequency, XTS = 1,
fXT1,HF2 16 24 MHz
HF mode 2 XT1BYPASS = 0, XT1DRIVEx = 2(2)
XT1 oscillator crystal frequency, XTS = 1,
fXT1,HF3 24 32 MHz
HF mode 3 XT1BYPASS = 0, XT1DRIVEx = 3(2)
XT1 oscillator logic-level XTS = 1,
fXT1,HF,SW square-wave input frequency, 0.7 32 MHz
XT1BYPASS = 1(3) (2)
HF mode, bypass mode XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 0, 450
fXT1,HF = 6 MHz, CL,eff = 15 pF
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 1, 320
fXT1,HF = 12 MHz, CL,eff = 15 pF
Oscillation allowance for
OAHF Ω
HF crystals(4) XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 2, 200
fXT1,HF = 20 MHz, CL,eff = 15 pF
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 3, 200
fXT1,HF = 32 MHz, CL,eff = 15 pF
fOSC = 6 MHz, XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 0, 0.5
TA= 25°C,
CL,eff = 15 pF
tSTART,HF Startup time, HF mode 3.0 V ms
fOSC = 20 MHz, XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 2, 0.3
TA= 25°C,
CL,eff = 15 pF
(1) To improve EMI on the XT1 oscillator the following guidelines should be observed.
(a) Keep the traces between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(2) This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device
operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation.
(3) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this datasheet.
(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals.
48 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Crystal Oscillator, XT1, High-Frequency Mode(1) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Integrated effective load
CL,eff XTS = 1 1 pF
capacitance, HF mode(5) (6)
XTS = 1, Measured at ACLK,
Duty cycle HF mode 40 50 60 %
fXT1,HF2 = 20 MHz
Oscillator fault frequency,
fFault,HF XTS = 1(8) 30 300 kHz
HF mode(7)
(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
(6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(8) Measured with logic-level input frequency but also applies to operation with crystals.
Crystal Oscillator, XT2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fOSC = 4 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 0, 200
TA= 25°C
fOSC = 12 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 1, 260
TA= 25°C
XT2 oscillator crystal current
IDVCC.XT2 3.0 V µA
consumption fOSC = 20 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 2, 325
TA= 25°C
fOSC = 32 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 3, 450
TA= 25°C
XT2 oscillator crystal frequency,
fXT2,HF0 XT2DRIVEx = 0, XT2BYPASS = 0(3) 4 8 MHz
mode 0
XT2 oscillator crystal frequency,
fXT2,HF1 XT2DRIVEx = 1, XT2BYPASS = 0(3) 8 16 MHz
mode 1
XT2 oscillator crystal frequency,
fXT2,HF2 XT2DRIVEx = 2, XT2BYPASS = 0(3) 16 24 MHz
mode 2
XT2 oscillator crystal frequency,
fXT2,HF3 XT2DRIVEx = 3, XT2BYPASS = 0(3) 24 32 MHz
mode 3
XT2 oscillator logic-level
fXT2,HF,SW square-wave input frequency, XT2BYPASS = 1(4) (3) 0.7 32 MHz
bypass mode
(1) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(2) To improve EMI on the XT2 oscillator the following guidelines should be observed.
(a) Keep the traces between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
(d) Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(3) This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device
operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation.
(4) When XT2BYPASS is set, the XT2 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined
in the Schmitt-trigger Inputs section of this datasheet.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 49
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Crystal Oscillator, XT2 (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
XT2DRIVEx = 0, XT2BYPASS = 0, 450
fXT2,HF0 = 6 MHz, CL,eff = 15 pF
XT2DRIVEx = 1, XT2BYPASS = 0, 320
fXT2,HF1 = 12 MHz, CL,eff = 15 pF
Oscillation allowance for
OAHF Ω
HF crystals(5) XT2DRIVEx = 2, XT2BYPASS = 0, 200
fXT2,HF2 = 20 MHz, CL,eff = 15 pF
XT2DRIVEx = 3, XT2BYPASS = 0, 200
fXT2,HF3 = 32 MHz, CL,eff = 15 pF
fOSC = 6 MHz
XT2BYPASS = 0, XT2DRIVEx = 0, 0.5
TA= 25°C,
CL,eff = 15 pF
tSTART,HF Startup time 3.0 V ms
fOSC = 20 MHz
XT2BYPASS = 0, XT2DRIVEx = 2, 0.3
TA= 25°C,
CL,eff = 15 pF
Integrated effective load
CL,eff 1 pF
capacitance, HF mode(6) (1)
Duty cycle Measured at ACLK, fXT2,HF2 = 20 MHz 40 50 60 %
fFault,HF Oscillator fault frequency(7) XT2BYPASS = 1(8) 30 300 kHz
(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.
(6) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(8) Measured with logic-level input frequency but also applies to operation with crystals.
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fVLO VLO frequency Measured at ACLK 1.8 V to 3.6 V 6 9.4 14 kHz
dfVLO/dTVLO frequency temperature drift Measured at ACLK(1) 1.8 V to 3.6 V 0.5 %/°C
dfVLO/dVCC VLO frequency supply voltage drift Measured at ACLK(2) 1.8 V to 3.6 V 4 %/V
Duty cycle Measured at ACLK 1.8 V to 3.6 V 40 50 60 %
(1) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)
Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
IREFO REFO oscillator current consumption TA= 25°C 1.8 V to 3.6 V 3 µA
REFO frequency calibrated Measured at ACLK 1.8 V to 3.6 V 32768 Hz
fREFO Full temperature range 1.8 V to 3.6 V ±3.5
REFO absolute tolerance calibrated %
TA= 25°C 3 V ±1.5
dfREFO/dTREFO frequency temperature drift Measured at ACLK(1) 1.8 V to 3.6 V 0.01 %/°C
dfREFO/dVCC REFO frequency supply voltage drift Measured at ACLK(2) 1.8 V to 3.6 V 1.0 %/V
Duty cycle Measured at ACLK 1.8 V to 3.6 V 40 50 60 %
tSTART REFO startup time 40%/60% duty cycle 1.8 V to 3.6 V 25 µs
(1) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)
50 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
01 2 34567
Typical DCO Frequency, V = 3.0 V,T = 25°C
CC A
DCORSEL
100
10
1
0.1
f – MHz
DCO
DCOx = 31
DCOx = 0
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fDCO(0,0) DCO frequency (0, 0) DCORSELx = 0, DCOx = 0, MODx = 0 0.07 0.20 MHz
fDCO(0,31) DCO frequency (0, 31) DCORSELx = 0, DCOx = 31, MODx = 0 0.70 1.70 MHz
fDCO(1,0) DCO frequency (1, 0) DCORSELx = 1, DCOx = 0, MODx = 0 0.15 0.36 MHz
fDCO(1,31) DCO frequency (1, 31) DCORSELx = 1, DCOx = 31, MODx = 0 1.47 3.45 MHz
fDCO(2,0) DCO frequency (2, 0) DCORSELx = 2, DCOx = 0, MODx = 0 0.32 0.75 MHz
fDCO(2,31) DCO frequency (2, 31) DCORSELx = 2, DCOx = 31, MODx = 0 3.17 7.38 MHz
fDCO(3,0) DCO frequency (3, 0) DCORSELx = 3, DCOx = 0, MODx = 0 0.64 1.51 MHz
fDCO(3,31) DCO frequency (3, 31) DCORSELx = 3, DCOx = 31, MODx = 0 6.07 14.0 MHz
fDCO(4,0) DCO frequency (4, 0) DCORSELx = 4, DCOx = 0, MODx = 0 1.3 3.2 MHz
fDCO(4,31) DCO frequency (4, 31) DCORSELx = 4, DCOx = 31, MODx = 0 12.3 28.2 MHz
fDCO(5,0) DCO frequency (5, 0) DCORSELx = 5, DCOx = 0, MODx = 0 2.5 6.0 MHz
fDCO(5,31) DCO frequency (5, 31) DCORSELx = 5, DCOx = 31, MODx = 0 23.7 54.1 MHz
fDCO(6,0) DCO frequency (6, 0) DCORSELx = 6, DCOx = 0, MODx = 0 4.6 10.7 MHz
fDCO(6,31) DCO frequency (6, 31) DCORSELx = 6, DCOx = 31, MODx = 0 39.0 88.0 MHz
fDCO(7,0) DCO frequency (7, 0) DCORSELx = 7, DCOx = 0, MODx = 0 8.5 19.6 MHz
fDCO(7,31) DCO frequency (7, 31) DCORSELx = 7, DCOx = 31, MODx = 0 60 135 MHz
Frequency step between range
SDCORSEL SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO) 1.2 2.3 ratio
DCORSEL and DCORSEL + 1
Frequency step between tap
SDCO SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO) 1.02 1.12 ratio
DCO and DCO + 1
Duty cycle Measured at SMCLK 40 50 60 %
dfDCO/dT DCO frequency temperature drift fDCO = 1 MHz, 0.1 %/°C
dfDCO/dVCC DCO frequency voltage drift fDCO = 1 MHz 1.9 %/V
Figure 10. Typical DCO frequency
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 51
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
PMM, Brown-Out Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BORHon voltage,
V(DVCC_BOR_IT–) | dDVCC/dt| < 3 V/s 1.45 V
DVCC falling level
BORHoff voltage,
V(DVCC_BOR_IT+) | dDVCC/dt| < 3 V/s 0.80 1.30 1.50 V
DVCC rising level
V(DVCC_BOR_hys) BORHhysteresis 60 250 mV
Pulse length required at RST/NMI pin to
tRESET 2 µs
accept a reset
PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Core voltage, active
VCORE3(AM) 2.4 V ≤DVCC ≤3.6 V 1.90 V
mode, PMMCOREV = 3
Core voltage, active
VCORE2(AM) 2.2 V ≤DVCC ≤3.6 V 1.80 V
mode, PMMCOREV = 2
Core voltage, active
VCORE1(AM) 2.0 V ≤DVCC ≤3.6 V 1.60 V
mode, PMMCOREV = 1
Core voltage, active
VCORE0(AM) 1.8 V ≤DVCC ≤3.6 V 1.40 V
mode, PMMCOREV = 0
Core voltage, low-current
VCORE3(LPM) 2.4 V ≤DVCC ≤3.6 V 1.94 V
mode, PMMCOREV = 3
Core voltage, low-current
VCORE2(LPM) 2.2 V ≤DVCC ≤3.6 V 1.84 V
mode, PMMCOREV = 2
Core voltage, low-current
VCORE1(LPM) 2.0 V ≤DVCC ≤3.6 V 1.64 V
mode, PMMCOREV = 1
Core voltage, low-current
VCORE0(LPM) 1.8 V ≤DVCC ≤3.6 V 1.44 V
mode, PMMCOREV = 0
52 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
PMM, SVS High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SVSHE = 0, DVCC = 3.6 V 0 nA
I(SVSH) SVS current consumption SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0 200 nA
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1 1.5 µA
SVSHE = 1, SVSHRVL = 0 1.57 1.68 1.78
SVSHE = 1, SVSHRVL = 1 1.79 1.88 1.98
V(SVSH_IT–) SVSHon voltage level(1) V
SVSHE = 1, SVSHRVL = 2 1.98 2.08 2.21
SVSHE = 1, SVSHRVL = 3 2.10 2.18 2.31
SVSHE = 1, SVSMHRRL = 0 1.62 1.74 1.85
SVSHE = 1, SVSMHRRL = 1 1.88 1.94 2.07
SVSHE = 1, SVSMHRRL = 2 2.07 2.14 2.28
SVSHE = 1, SVSMHRRL = 3 2.20 2.30 2.42
V(SVSH_IT+) SVSHoff voltage level(1) V
SVSHE = 1, SVSMHRRL = 4 2.32 2.40 2.55
SVSHE = 1, SVSMHRRL = 5 2.52 2.70 2.88
SVSHE = 1, SVSMHRRL = 6 2.90 3.10 3.23
SVSHE = 1, SVSMHRRL = 7 2.90 3.10 3.23
SVSHE = 1, dVDVCC/dt = 10 mV/µs, 2.5
SVSHFP = 1
tpd(SVSH) SVSHpropagation delay µs
SVSHE = 1, dVDVCC/dt = 1 mV/µs, 20
SVSHFP = 0
SVSHE = 0 →1, dVDVCC/dt = 10 mV/µs, 12.5
SVSHFP = 1
t(SVSH) SVSHon/off delay time µs
SVSHE = 0 →1, dVDVCC/dt = 1 mV/µs, 100
SVSHFP = 0
dVDVCC/dt DVCC rise time 0 1000 V/s
(1) The SVSHsettings available depend on the VCORE (PMMCOREVx) setting. Please refer to the Power Management Module and Supply
Voltage Supervisor chapter in the MSP430x5xx Family User's Guide (SLAU208) on recommended settings and usage.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 53
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
PMM, SVM High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SVMHE = 0, DVCC = 3.6 V 0 nA
I(SVMH) SVMHcurrent consumption SVMHE= 1, DVCC = 3.6 V, SVMHFP = 0 200 nA
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1 1.5 µA
SVMHE = 1, SVSMHRRL = 0 1.62 1.74 1.85
SVMHE = 1, SVSMHRRL = 1 1.88 1.94 2.07
SVMHE = 1, SVSMHRRL = 2 2.07 2.14 2.28
SVMHE = 1, SVSMHRRL = 3 2.20 2.30 2.42
V(SVMH) SVMHon/off voltage level(1) SVMHE = 1, SVSMHRRL = 4 2.32 2.40 2.55 V
SVMHE = 1, SVSMHRRL = 5 2.52 2.70 2.88
SVMHE = 1, SVSMHRRL = 6 2.90 3.10 3.23
SVMHE = 1, SVSMHRRL = 7 2.90 3.10 3.23
SVMHE = 1, SVMHOVPE = 1 3.75
SVMHE = 1, dVDVCC/dt = 10 mV/µs, 2.5
SVMHFP = 1
tpd(SVMH) SVMHpropagation delay µs
SVMHE = 1, dVDVCC/dt = 1 mV/µs, 20
SVMHFP = 0
SVMHE = 0 →1, dVDVCC/dt = 10 mV/µs, 12.5
SVMHFP = 1
t(SVMH) SVMHon/off delay time µs
SVMHE = 0 →1, dVDVCC/dt = 1 mV/µs, 100
SVMHFP = 0
(1) The SVMHsettings available depend on the VCORE (PMMCOREVx) setting. Please refer to the Power Management Module and
Supply Voltage Supervisor chapter in the MSP430x5xx Family User's Guide (SLAU208) on recommended settings and usage.
54 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SVSLE = 0, PMMCOREV = 2 0 nA
I(SVSL) SVSLcurrent consumption SVSLE = 1, PMMCOREV = 2, SVSLFP = 0 200 nA
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1 1.5 µA
SVSLE = 1, dVCORE/dt = 10 mV/µs, 2.5
SVSLFP = 1
tpd(SVSL) SVSLpropagation delay µs
SVSLE = 1, dVCORE/dt = 1 mV/µs, 20
SVSLFP = 0
SVSLE = 0 →1, dVCORE/dt = 10 mV/µs, 12.5
SVSLFP = 1
t(SVSL) SVSLon/off delay time µs
SVSLE = 0 →1, dVCORE/dt = 1 mV/µs, 100
SVSLFP = 0
PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SVMLE = 0, PMMCOREV = 2 0 nA
I(SVML) SVMLcurrent consumption SVMLE= 1, PMMCOREV = 2, SVMLFP = 0 200 nA
SVMLE= 1, PMMCOREV = 2, SVMLFP = 1 1.5 µA
SVMLE = 1, dVCORE/dt = 10 mV/µs, 2.5
SVMLFP = 1
tpd(SVML) SVMLpropagation delay µs
SVMLE = 1, dVCORE/dt = 1 mV/µs, 20
SVMLFP = 0
SVMLE = 0 →1, dVCORE/dt = 10 mV/µs, 12.5
SVMLFP = 1
t(SVML) SVMLon/off delay time µs
SVMLE = 0 →1, dVCORE/dt = 1 mV/µs, 100
SVMLFP = 0
Wake-up from Low Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Wake-up time from PMMCOREV = SVSMLRRL = n, fMCLK ≥4.0 MHz 5
tWAKE-UP- LPM2, LPM3, or LPM4 where n = 0, 1, 2, or 3 µs
FAST fMCLK < 4.0 MHz 6
to active mode(1) SVSLFP = 1
Wake-up time from
tWAKE-UP- PMMCOREV = SVSMLRRL = n, where n = 0, 1, 2, or 3
LPM2, LPM3 or LPM4 to 150 165 µs
SLOW SVSLFP = 0
active mode(2)
Wake-up time from
tWAKE-UP- LPM4.5 to active 2 3 ms
LPM5 mode(3)
Wake-up time from RST
tWAKE-UP- or BOR event to active 2 3 ms
RESET mode(3)
(1) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVSL) and low side monitor (SVML). Fastest wakeup times are possible with SVSLand SVMLin full
performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVMLwhile
operating in LPM2, LPM3, and LPM4. Please refer to the Power Management Module and Supply Voltage Supervisor chapter in the
MSP430x5xx Family User's Guide (SLAU208).
(2) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVSL) and low side monitor (SVML). In this case, the SVSLand SVMLare in normal mode (low current)
mode when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVMLwhile operating in LPM2, LPM3, and
LPM4. Please refer to the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx Family User's Guide
(SLAU208).
(3) This value represents the time from the wakeup event to the reset vector execution.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 55
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Internal: SMCLK, ACLK 1.8 V/
fTA Timer_A input clock frequency External: TACLK 25 MHz
3.0 V
Duty cycle = 50% ± 10%
All capture inputs. 1.8 V/
tTA,cap Timer_A capture timing Minimum pulse width required for 20 ns
3.0 V
capture.
Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Internal: SMCLK, ACLK 1.8 V/
fTB Timer_B input clock frequency External: TBCLK 25 MHz
3.0 V
Duty cycle = 50% ± 10%
All capture inputs. 1.8 V/
tTB,cap Timer_B capture timing Minimum pulse width required for 20 ns
3.0 V
capture.
USCI (UART Mode) - recommended operating conditions
PARAMETER CONDITIONS VCC MIN TYP MAX UNIT
Internal: SMCLK, ACLK
fUSCI USCI input clock frequency External: UCLK fSYSTEM MHz
Duty cycle = 50% ± 10%
BITCLK clock frequency
fBITCLK 1 MHz
(equals baud rate in MBaud)
USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
2.2 V 50 600
ttUART receive deglitch time(1) ns
3 V 50 600
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
56 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
tSU,MI
tHD,MI
UCLK
SOMI
SIMO
tVALID,MO
tHD,MO
CKPL =0
CKPL =1
tLO/HI tLO/HI
1/fUCxCLK
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
USCI (SPI Master Mode) - recommended operating conditions
PARAMETER CONDITIONS VCC MIN TYP MAX UNIT
Internal: SMCLK, ACLK
fUSCI USCI input clock frequency fSYSTEM MHz
Duty cycle = 50% ± 10%
USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note (1),Figure 11 and Figure 12)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
SMCLK, ACLK
fUSCI USCI input clock frequency fSYSTEM MHz
Duty cycle = 50% ± 10% 1.8 V 55
PMMCOREV = 0 ns
3.0 V 38
tSU,MI SOMI input data setup time 2.4 V 30
PMMCOREV = 3 ns
3.0 V 25
1.8 V 0
PMMCOREV = 0 ns
3.0 V 0
tHD,MI SOMI input data hold time 2.4 V 0
PMMCOREV = 3 ns
3.0 V 0
UCLK edge to SIMO valid, 1.8 V 20
CL= 20 pF ns
3.0 V 18
PMMCOREV = 0
tVALID,MO SIMO output data valid time(2) UCLK edge to SIMO valid, 2.4 V 16
CL= 20 pF ns
3.0 V 15
PMMCOREV = 3 1.8 V -10
CL= 20 pF ns
PMMCOREV = 0 3.0 V -8
tHD,MO SIMO output data hold time(3) 2.4 V -10
CL= 20 pF ns
PMMCOREV = 3 3.0 V -8
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave) refer to the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 11 and Figure 12.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams in
Figure 11 and Figure 12.
Figure 11. SPI Master Mode, CKPH = 0
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 57
tSU,MI
tHD,MI
UCLK
SOMI
SIMO
tVALID,MO
CKPL =0
CKPL =1
1/fUCxCLK
tHD,MO
tLO/HI tLO/HI
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Figure 12. SPI Master Mode, CKPH = 1
58 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note (1),Figure 13 and Figure 14)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
1.8 V 11
PMMCOREV = 0 ns
3.0 V 8
tSTE,LEAD STE lead time, STE low to clock 2.4 V 7
PMMCOREV = 3 ns
3.0 V 6
1.8 V 3
PMMCOREV = 0 ns
3.0 V 3
tSTE,LAG STE lag time, Last clock to STE high 2.4 V 3
PMMCOREV = 3 ns
3.0 V 3
1.8 V 66
PMMCOREV = 0 ns
3.0 V 50
tSTE,ACC STE access time, STE low to SOMI data out 2.4 V 36
PMMCOREV = 3 ns
3.0 V 30
1.8 V 30
PMMCOREV = 0 ns
3.0 V 23
STE disable time, STE high to SOMI high
tSTE,DIS impedance 2.4 V 16
PMMCOREV = 3 ns
3.0 V 13
1.8 V 5
PMMCOREV = 0 ns
3.0 V 5
tSU,SI SIMO input data setup time 2.4 V 2
PMMCOREV = 3 ns
3.0 V 2
1.8 V 5
PMMCOREV = 0 ns
3.0 V 5
tHD,SI SIMO input data hold time 2.4 V 5
PMMCOREV = 3 ns
3.0 V 5
UCLK edge to SOMI valid, 1.8 V 76
CL= 20 pF ns
3.0 V 60
PMMCOREV = 0
tVALID,SO SOMI output data valid time(2) UCLK edge to SOMI valid, 2.4 V 44
CL= 20 pF ns
3.0 V 40
PMMCOREV = 3 1.8 V 18
CL= 20 pF ns
PMMCOREV = 0 3.0 V 12
tHD,SO SOMI output data hold time(3) 2.4 V 10
CL= 20 pF ns
PMMCOREV = 3 3.0 V 8
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).
For the master's parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 11 and Figure 12.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams in
Figure 11 and Figure 12.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 59
STE
UCLK
CKPL =0
CKPL =1
SOMI
SIMO
tSU,SI
tHD,SI
tVALID,SO
tSTE,LEAD
1/fUCxCLK
tLO/HI tLO/HI
tSTE,LAG
tSTE,DIS
tSTE,ACC
tHD,SO
STE
UCLK
CKPL =0
CKPL =1
SOMI
SIMO
tSU,SI
tHD,SI
tVALID,SO
tSTE,LEAD
1/fUCxCLK
tSTE,LAG
tSTE,DIS
tSTE,ACC
tHD,MO
tLO/HI tLO/HI
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Figure 13. SPI Slave Mode, CKPH = 0
Figure 14. SPI Slave Mode, CKPH = 1
60 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
SDA
SCL
tHD,DAT
tSU,DAT
tHD,STA
tHIGH
tLOW
tBUF
tHD,STA
tSU,STA
tSP
tSU,STO
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 15)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Internal: SMCLK, ACLK
fUSCI USCI input clock frequency External: UCLK fSYSTEM MHz
Duty cycle = 50% ± 10%
fSCL SCL clock frequency 2.2 V/3 V 0 400 kHz
fSCL ≤100 kHz 4.0
tHD,STA Hold time (repeated) START 2.2 V/3 V µs
fSCL > 100 kHz 0.6
fSCL ≤100 kHz 4.7
tSU,STA Setup time for a repeated START 2.2 V/3 V µs
fSCL > 100 kHz 0.6
tHD,DAT Data hold time 2.2 V/3 V 0 ns
tSU,DAT Data setup time 2.2 V/3 V 250 ns
fSCL ≤100 kHz 4.0
tSU,STO Setup time for STOP 2.2 V/3 V µs
fSCL > 100 kHz 0.6
2.2 V 50 600
tSP Pulse width of spikes suppressed by input filter ns
3 V 50 600
Figure 15. I2C Mode Timing
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 61
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
AVCC and DVCC are connected together,
Analog supply voltage
AVCC AVSS and DVSS are connected together, 2.2 3.6 V
Full performance V(AVSS) = V(DVSS) = 0 V
V(Ax) Analog input voltage range(2) All ADC12 analog input pins Ax 0 AVCC V
fADC12CLK = 5.0 MHz, ADC12ON = 1, 2.2 V 125 155
Operating supply current into
IADC12_A REFON = 0, SHT0 = 0, SHT1 = 0, µA
AVCC terminal(3) 3 V 150 220
ADC12DIV = 0
Only one terminal Ax can be selected at one
CIInput capacitance 2.2 V 20 25 pF
time
RIInput MUX ON resistance 0 V ≤VAx ≤AVCC 10 200 1900 Ω
(1) The leakage current is specified by the digital I/O input leakage.
(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. If the
reference voltage is supplied by an external source or if the internal reference voltage is used and REFOUT = 1, then decoupling
capacitors are required. See REF, External Reference andREF, Built-In Reference.
(3) The internal reference supply current is not included in current consumption parameter IADC12_A.
12-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
For specified performance of ADC12 linearity
fADC12CLK 2.2 V/3 V 0.45 4.8 5.4 MHz
parameters
Internal ADC12
fADC12OSC ADC12DIV = 0, fADC12CLK = fADC12OSC 2.2 V/3 V 4.2 4.8 5.4 MHz
oscillator(1)
REFON = 0, Internal oscillator, 2.2 V/3 V 2.4 3.1
fADC12OSC = 4.2 MHz to 5.4 MHz
tCONVERT Conversion time µs
External fADC12CLK from ACLK, MCLK or SMCLK, (2)
ADC12SSEL ≠0
RS= 400 Ω, RI= 1000 Ω, CI= 20 pF,
tSample Sampling time 2.2 V/3 V 1000 ns
t= [RS+ RI] × CI(3)
(1) The ADC12OSC is sourced directly from MODOSC inside the UCS.
(2) 13 × ADC12DIV × 1/fADC12CLK
(3) Approximately ten Tau (t) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) x (RS+ RI) × CI+ 800 ns, where n = ADC resolution = 12, RS= external source resistance
12-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
1.4 V ≤(VeREF+ – VREF–/VeREF–)min ≤1.6 V ±2
Integral
EI2.2 V/3 V LSB
linearity error (INL) 1.6 V < (VeREF+ – VREF–/VeREF–)min ≤VAVCC ±1.7
Differential (VeREF+ – VREF–/VeREF–)min ≤(VeREF+ – VREF–/VeREF–),
ED2.2 V/3 V ±1.0 LSB
linearity error (DNL) CVREF+ = 20 pF
(VeREF+ – VREF–/VeREF–)min ≤(VeREF+ – VREF–/VeREF–),
EOOffset error 2.2 V/3 V ±1.0 ±2.0 LSB
Internal impedance of source RS< 100 Ω, CVREF+ = 20 pF
(VeREF+ – VREF–/VeREF–)min ≤(VeREF+ – VREF–/VeREF–),
EGGain error 2.2 V/3 V ±1.0 ±2.0 LSB
CVREF+ = 20 pF
Total unadjusted (VeREF+ – VREF–/VeREF–)min ≤(VeREF+ – VREF–/VeREF–),
ET2.2 V/3 V ±1.4 ±3.5 LSB
error CVREF+ = 20 pF
62 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
500
550
600
650
700
750
800
850
900
950
1000
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
Typical Temperature Sensor Voltage - mV
AmbientTemperature- ˚C
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
12-Bit ADC, Temperature Sensor and Built-In VMID (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
2.2 V 680
ADC12ON = 1, INCH = 0Ah,
VSENSOR See (2) mV
TA= 0°C 3 V 680
2.2 V 2.25
TCSENSOR ADC12ON = 1, INCH = 0Ah mV/°C
3 V 2.25
2.2 V 30
Sample time required if ADC12ON = 1, INCH = 0Ah,
tSENSOR(sample) µs
channel 10 is selected(3) Error of conversion result ≤1 LSB 3 V 30
AVCC divider at channel 11, ADC12ON = 1, INCH = 0Bh 0.48 0.5 0.52 VAVCC
VAVCC factor
VMID 2.2 V 1.06 1.1 1.14
AVCC divider at channel 11 ADC12ON = 1, INCH = 0Bh V
3 V 1.44 1.5 1.56
Sample time required if ADC12ON = 1, INCH = 0Bh,
tVMID(sample) 2.2 V/3 V 1000 ns
channel 11 is selected(4) Error of conversion result ≤1 LSB
(1) The temperature sensor is provided by the REF module. Please refer to the REF module parametric, IREF+, regarding the current
consumption of the temperature sensor.
(2) The temperature sensor offset can be as much as ±20°C. A single-point calibration is recommended in order to minimize the offset error
of the built-in temperature sensor. The TLV structure contains calibration values for 30°C ± 3°C and 85°C ± 3°C for each of the available
reference voltage levels. The sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature,°C) + VSENSOR, where TCSENSOR
and VSENSOR can be computed from the calibration values for higher accuracy. See also the MSP430x5xx Family User's Guide
(SLAU208).
(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
(4) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
Figure 16. Typical Temperature Sensor Voltage
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 63
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
REF, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VeREF+ Positive external reference voltage input VeREF+ > VREF–/VeREF– (2) 1.4 AVCC V
VREF–/VeREF– Negative external reference voltage input VeREF+ > VREF–/VeREF– (3) 0 1.2 V
(VeREF+ – Differential external reference voltage VeREF+ > VREF–/VeREF– (4) 1.4 AVCC V
VREF–/VeREF–) input 1.4 V ≤VeREF+ ≤VAVCC ,
VeREF– = 0 V
fADC12CLK = 5 2.2 V/3 V ±8.5 ±26 µA
MHz,ADC12SHTx = 1h,
Conversion rate 200ksps
IVeREF+, Static input current
IVREF–/VeREF– 1.4 V ≤VeREF+ ≤VAVCC ,
VeREF– = 0 V
fADC12CLK = 5 2.2 V/3 V ±1 µA
MHz,ADC12SHTx = 8h,
Conversion rate 20ksps
CVREF+/- Capacitance at VREF+/- terminal (5)10 µF
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
(5) Two decoupling capacitors, 10µF and 100nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC12_A. See also the MSP430x5xx Family User's Guide (SLAU208).
REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
REFVSEL = {2} for 2.5 V
REFON = REFOUT = 1 3 V 2.50 ±1.5%
IVREF+= 0 A
REFVSEL = {1} for 2.0 V
Positive built-in reference
VREF+ REFON = REFOUT = 1 3 V 1.98 ±1.5% V
voltage output IVREF+= 0 A
REFVSEL = {0} for 1.5 V
REFON = REFOUT = 1 2.2 V/ 3 V 1.49 ±1.5%
IVREF+= 0 A
REFVSEL = {0} for 1.5 V, reduced 1.8
performance
AVCC minimum voltage, REFVSEL = {0} for 1.5 V 2.2
AVCC(min) Positive built-in reference V
active REFVSEL = {1} for 2.0 V 2.3
REFVSEL = {2} for 2.5 V 2.8
REFON = 1, REFOUT = 0, REFBURST = 0 3 V 100 140 µA
Operating supply current into
IREF+ AVCC terminal(2) (3) REFON = 1, REFOUT = 1, REFBURST = 0 3 V 0.9 1.5 mA
(1) The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers, one
smaller and one larger for driving the VREF+ terminal. When REFOUT = 1, the reference is available at the VREF+ terminal, as well as,
used as the reference for the conversion and utilizes the larger buffer. When REFOUT = 0, the reference is only used as the reference
for the conversion and utilizes the smaller buffer.
(2) The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. REFOUT = 0 represents the current contribution of the smaller buffer. REFOUT = 1 represents the current
contribution of the larger buffer without external load.
(3) The temperature sensor is provided by the REF module. Its current is supplied via terminal AVCC and is equivalent to IREF+ with REFON
=1 and REFOUT = 0.
64 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
REF, Built-In Reference (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
REFVSEL = (0, 1, 2}
Load-current regulation, IVREF+ = +10 µA/–1000 µA
IL(VREF+) 2500 µV/mA
VREF+ terminal(4) AVCC = AVCC (min) for each reference level.
REFVSEL = (0, 1, 2}, REFON = REFOUT = 1
Capacitance at VREF+/-
CVREF+/- REFON = REFOUT = 1(5) 20 100 pF
terminals IVREF+ = 0 A
Temperature coefficient of ppm/°
TCREF+ REFVSEL = (0, 1, 2}, REFON = 1, 30 50
built-in reference(6) C
REFOUT = 0 or 1
AVCC = AVCC (min) - AVCC(max)
Power supply rejection ratio TA= 25°C
PSRR_DC 120 300 µV/V
(DC) REFVSEL = (0, 1, 2}, REFON = 1,
REFOUT = 0 or 1
AVCC = AVCC (min) - AVCC(max)
TA= 25°C
Power supply rejection ratio
PSRR_AC f = 1 kHz, ΔVpp = 100 mV 6.4 mV/V
(AC) REFVSEL = (0, 1, 2}, REFON = 1,
REFOUT = 0 or 1
AVCC = AVCC (min) - AVCC(max)
REFVSEL = (0, 1, 2}, REFOUT = 0, 75
REFON = 0 →1
Settling time of reference
tSETTLE µs
AVCC = AVCC (min) - AVCC(max)
voltage(7) CVREF = CVREF(max) 75
REFVSEL = (0, 1, 2}, REFOUT = 1,
REFON = 0 →1
(4) Contribution only due to the reference and buffer including package. This does not include resistance due to PCB trace, etc.
(5) Two decoupling capacitors, 10µF and 100nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC12_A. See also the MSP430x5xx Family User's Guide (SLAU208).
(6) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C)/(85°C – (–40°C)).
(7) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load when REFOUT = 1.
Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
DVCC(PGM/ERASE) Program and erase supply voltage 1.8 3.6 V
IPGM Average supply current from DVCC during program 3 5 mA
IERASE Average supply current from DVCC during erase 2 mA
IMERASE, IBANK Average supply current from DVCC during mass erase or bank erase 2 mA
tCPT Cumulative program time See (1) 16 ms
Program/erase endurance 104105cycles
tRetention Data retention duration TJ= 25°C 100 years
tWord Word or byte program time See (2) 64 85 µs
tBlock, 0 Block program time for first byte or word See (2) 49 65 µs
Block program time for each additional byte or word, except for last
tBlock, 1–(N–1) See (2) 37 49 µs
byte or word
tBlock, N Block program time for last byte or word See (2) 55 73 µs
Erase time for segment, mass erase, and bank erase when
tErase See (2) 23 32 ms
available.
MCLK frequency in marginal read mode
fMCLK,MGR 0 1 MHz
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)
(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
(2) These values are hardwired into the flash controller's state machine.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 65
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
fSBW Spy-Bi-Wire input frequency 2.2 V/3 V 0 20 MHz
tSBW,Low Spy-Bi-Wire low clock pulse length 2.2 V/3 V 0.025 15 µs
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
tSBW, En 2.2 V/3 V 1 µs
edge)(1)
tSBW,Rst Spy-Bi-Wire return to normal operation time 15 100 µs
2.2 V 0 5 MHz
fTCK TCK input frequency, 4-wire JTAG(2) 3 V 0 10 MHz
Rinternal Internal pull-down resistance on TEST 2.2 V/3 V 45 60 80 kΩ
(1) Tools accessing the Spy-Bi-Wire interface need to wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
66 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/SMCLK
P1.7
Direction
0: Input
1: Output
P1SEL.x
1
0
P1DIR.x
P1IN.x
P1IRQ.x
EN
Module X IN
1
0
Module X OUT
P1OUT.x
Interrupt
Edge
Select
Q
EN
Set
P1SEL.x
P1IES.x
P1IFG.x
P1IE.x
1
0
DVSS
DVCC
P1REN.x Pad Logic
1
P1DS.x
0: Low drive
1: High drive
D
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
INPUT/OUTPUT SCHEMATICS
Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 67
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Table 45. Port P1 (P1.0 to P1.7) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P1.x) x FUNCTION P1DIR.x P1SEL.x
P1.0/TA0CLK/ACLK 0 P1.0 (I/O) I: 0; O: 1 0
TA0.TA0CLK 0 1
ACLK 1 1
P1.1/TA0.0 1 P1.1 (I/O) I: 0; O: 1 0
TA0.CCI0A 0 1
TA0.0 1 1
P1.2/TA0.1 2 P1.2 (I/O) I: 0; O: 1 0
TA0.CCI1A 0 1
TA0.1 1 1
P1.3/TA0.2 3 P1.3 (I/O) I: 0; O: 1 0
TA0.CCI2A 0 1
TA0.2 1 1
P1.4/TA0.3 4 P1.4 (I/O) I: 0; O: 1 0
TA0.CCI3A 0 1
TA0.3 1 1
P1.5/TA0.4 5 P1.5 (I/O) I: 0; O: 1 0
TA0.CCI4A 0 1
TA0.4 1 1
P1.6/SMCLK 6 P1.6 (I/O) I: 0; O: 1 0
SMCLK 1 1
P1.7 7 P1.7 (I/O) I: 0; O: 1 0
68 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
P2.0/TA1CLK/MCLK
P2.1/TA1.0
P2.2/TA1.1
P2.3/TA1.2
P2.4/RTCCLK
P2.5
P2.6/ACLK
P2.7/ADC12CLK/DMAE0
Direction
0: Input
1: Output
P2SEL.x
1
0
P2DIR.x
P2IN.x
P2IRQ.x
EN
Module X IN
1
0
Module X OUT
P2OUT.x
Interrupt
Edge
Select
Q
EN
Set
P2SEL.x
P2IES.x
P2IFG.x
P2IE.x
1
0
DVSS
DVCC
P2REN.x Pad Logic
1
P2DS.x
0: Low drive
1: High drive
D
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 69
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Table 46. Port P2 (P2.0 to P2.7) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P2.x) x FUNCTION P2DIR.x P2SEL.x
P2.0/TA1CLK/MCLK 0 P2.0 (I/O) I: 0; O: 1 0
TA1CLK 0 1
MCLK 1 1
P2.1/TA1.0 1 P2.1 (I/O) I: 0; O: 1 0
TA1.CCI0A 0 1
TA1.0 1 1
P2.2/TA1.1 2 P2.2 (I/O) I: 0; O: 1 0
TA1.CCI1A 0 1
TA1.1 1 1
P2.3/TA1.2 3 P2.3 (I/O) I: 0; O: 1 0
TA1.CCI2A 0 1
TA1.2 1 1
P2.4/RTCCLK 4 P2.4 (I/O) I: 0; O: 1 0
RTCCLK 1 1
P2.5 5 P2.5 (I/O I: 0; O: 1 0
P2.6/ACLK 6 P2.6 (I/O) I: 0; O: 1 0
ACLK 1 1
P2.7/ADC12CLK/DMAE0 7 P2.7 (I/O) I: 0; O: 1 0
DMAE0 0 1
ADC12CLK 1 1
70 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
P3.0/UB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/USC0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/UCB1STE/UCA1CLK
P3.7/UCB1SIMO/UCB1SDA
Direction
0: Input
1: Output
P3SEL.x
1
0
P3DIR.x
P3IN.x
EN
Module X IN
1
0
Module X OUT
P3OUT.x
1
0
DVSS
DVCC
P3REN.x Pad Logic
1
P3DS.x
0: Low drive
1: High drive
D
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
Table 47. Port P3 (P3.0 to P3.7) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P3.x) x FUNCTION P3DIR.x P3SEL.x
P3.0/UCB0STE/UCA0CLK 0 P3.0 (I/O) I: 0; O: 1 0
UCB0STE/UCA0CLK(2) (3) X 1
P3.1/UCB0SIMO/UCB0SDA 1 P3.1 (I/O) I: 0; O: 1 0
UCB0SIMO/UCB0SDA(2) (4) X 1
P3.2/UCB0SOMI/UCB0SCL 2 P3.2 (I/O) I: 0; O: 1 0
UCB0SOMI/UCB0SCL(2) (4) X 1
P3.3/UCB0CLK/UCA0STE 3 P3.3 (I/O) I: 0; O: 1 0
UCB0CLK/UCA0STE(2) X 1
P3.4/UCA0TXD/UCA0SIMO 4 P3.4 (I/O) I: 0; O: 1 0
UCA0TXD/UCA0SIMO(2) X 1
P3.5/UCA0RXD/UCA0SOMI 5 P3.5 (I/O) I: 0; O: 1 0
UCA0RXD/UCA0SOMI(2) X 1
P3.6/UCB1STE/UCA1CLK 6 P3.6 (I/O) I: 0; O: 1 0
UCB1STE/UCA1CLK(2) (5) X 1
P3.7/UCB1SIMO/UCB1SDA 7 P3.7 (I/O) I: 0; O: 1 0
UCB1SIMO/UCB1SDA(2) (4) X 1
(1) X = Don't care
(2) The pin direction is controlled by the USCI module.
(3) UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI A0/B0 is forced
to 3-wire SPI mode if 4-wire SPI mode is selected.
(4) If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
(5) UCA1CLK function takes precedence over UCB1STE function. If the pin is required as UCA1CLK input or output, USCI A1/B1 is forced
to 3-wire SPI mode if 4-wire SPI mode is selected.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 71
P4.0/TB0.0
P4.1/TB0.1
P4.2/TB0.2
P4.3/TB0.3
P4.4/TB0.4
P4.5/TB0.5
P4.6/TB0.6
P4.7/TB0CLK/SMCLK
Direction
0:Input
1:Output
P4SEL.x
1
0
P4DIR.x
P4IN.x
EN
ModuleXIN
1
0
ModuleXOUT
P4OUT.x
1
0
DVSS
DVCC
P4REN.x PadLogic
1
P4DS.x
0:Lowdrive
1:Highdrive
D
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
72 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Table 48. Port P4 (P4.0 to P4.7) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P4.x) x FUNCTION P4DIR.x P4SEL.x
P4.0/TB0.0 0 4.0 (I/O) I: 0; O: 1 0
TB0.CCI0A and TB0.CCI0B 0 1
TB0.0(1) 1 1
P4.1/TB0.1 1 4.1 (I/O) I: 0; O: 1 0
TB0.CCI1A and TB0.CCI1B 0 1
TB0.1(1) 1 1
P4.2/TB0.2 2 4.2 (I/O) I: 0; O: 1 0
TB0.CCI2A and TB0.CCI2B 0 1
TB0.2(1) 1 1
P4.3/TB0.3 3 4.3 (I/O) I: 0; O: 1 0
TB0.CCI3A and TB0.CCI3B 0 1
TB0.3(1) 1 1
P4.4/TB0.5 4 4.4 (I/O) I: 0; O: 1 0
TB0.CCI4A and TB0.CCI4B 0 1
TB0.4(1) 1 1
P4.5/TB0.5 5 4.5 (I/O) I: 0; O: 1 0
TB0.CCI5A and TB0.CCI5B 0 1
TB0.5(1) 1 1
P4.6/TB0.6 6 4.6 (I/O) I: 0; O: 1 0
TB0.CCI6A and TB0.CCI6B 0 1
TB0.6(1) 1 1
P4.7/TB0CLK/SMCLK 7 4.7 (I/O) I: 0; O: 1 0
TB0CLK 0 1
SMCLK 1 1
(1) Setting TBOUTH causes all Timer_B configured outputs to be set to high impedance.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 73
P5.0/A8/VREF+/VeREF+
P5.1/A9/VREF–/VeREF–
P5SEL.x
1
0
P5DIR.x
P5IN.x
EN
ModuleXIN
1
0
ModuleXOUT
P5OUT.x
1
0
DVSS
DVCC
P5REN.x
1
P5DS.x
0:Lowdrive
1:Highdrive
D
Bus
Keeper
To/From
ADC12Reference
PadLogic
To ADC12
INCHx=y
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
74 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Table 49. Port P5 (P5.0 and P5.1) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P5.x) x FUNCTION P5DIR.x P5SEL.x REFOUT
P5.0/A8/VREF+/VeREF+ 0 P5.0 (I/O)(2) I: 0; O: 1 0 X
A8/VeREF+(3) X 1 0
A8/VREF+(4) X 1 1
P5.1/A9/VREF–/VeREF– 1 P5.1 (I/O)(2) I: 0; O: 1 0 X
A9/VeREF–(5) X 1 0
A9/VREF–(6) X 1 1
(1) X = Don't care
(2) Default condition
(3) Setting the P5SEL.0 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC12_A. Channel A8, when selected
with the INCHx bits, is connected to the VREF+/VeREF+ pin.
(4) Setting the P5SEL.0 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. The ADC12_A, VREF+ reference is available at the pin. Channel A8, when selected with the INCHx bits, is connected to
the VREF+/VeREF+ pin.
(5) Setting the P5SEL.1 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. An external voltage can be applied to VeREF- and used as the reference for the ADC12_A. Channel A9, when selected
with the INCHx bits, is connected to the VREF-/VeREF- pin.
(6) Setting the P5SEL.1 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. The ADC12_A, VREF– reference is available at the pin. Channel A9, when selected with the INCHx bits, is connected to
the VREF-/VeREF- pin.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 75
P5.2/XT2IN
P5SEL.2
1
0
P5DIR.2
P5IN.2
EN
ModuleXIN
1
0
ModuleXOUT
P5OUT.2
1
0
DVSS
DVCC
P5REN.2
PadLogic
1
P5DS.2
0:Lowdrive
1:Highdrive
D
Bus
Keeper
ToXT2
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Port P5, P5.2, Input/Output With Schmitt Trigger
76 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
P5.3/XT2OUT
P5SEL.3
1
0
P5DIR.3
P5IN.3
EN
Module X IN
1
0
Module X OUT
P5OUT.3
1
0
DVSS
DVCC
P5REN.3
Pad Logic
1
P5DS.3
0: Low drive
1: High drive
D
Bus
Keeper
To XT2
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Port P5, P5.3, Input/Output With Schmitt Trigger
Table 50. Port P5 (P5.2) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P5.x) x FUNCTION P5DIR.x P5SEL.2 P5SEL.3 XT2BYPASS
P5.2/XT2IN 2 P5.2 (I/O) I: 0; O: 1 0 X X
XT2IN crystal mode(2) X 1 X 0
XT2IN bypass mode(2) X 1 X 1
P5.3/XT2OUT 3 P5.3 (I/O) I: 0; O: 1 0 X X
XT2OUT crystal mode(3) X 1 X 0
P5.3 (I/O)(3) X 1 X 1
(1) X = Don't care
(2) Setting P5SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P5.2 is configured for crystal
mode or bypass mode.
(3) Setting P5SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.3 can be used as
general-purpose I/O.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 77
P5.4/UCB1SOMI/UCB1SCL
P5.5/UCB1CLK/UCA1STE
P5.6/UCA1TXD/UCA1SIMO
P5.7/UCA1RXD/UCA1SOMI
Direction
0: Input
1: Output
P5SEL.x
1
0
P5DIR.x
P5IN.x
EN
Module X IN
1
0
Module X OUT
P5OUT.x
1
0
DVSS
DVCC
P5REN.x Pad Logic
1
P5DS.x
0: Low drive
1: High drive
D
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Port P5, P5.4 to P5.7, Input/Output With Schmitt Trigger
Table 51. Port P5 (P5.4 to P5.7) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P5.x) x FUNCTION P5DIR.x P5SEL.x
P5.4/UCB1SOMI/UCB1SCL 4 P5.4 (I/O) I: 0; O: 1 0
UCB1SOMI/UCB1SCL(2) (3) X 1
P5.5/UCB1CLK/UCA1STE 5 P5.5 (I/O) I: 0; O: 1 0
UCB1CLK/UCA1STE(2) X 1
P5.6/UCA1TXD/UCA1SIMO 6 P5.6 (I/O) I: 0; O: 1 0
UCA1TXD/UCA1SIMO(2) X 1
P5.7/UCA1RXD/UCA1SOMI 7 P5.7 (I/O) I: 0; O: 1 0
UCA1RXD/UCA1SOMI(2) X 1
(1) X = Don't care
(2) The pin direction is controlled by the USCI module.
(3) If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
78 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
P6SEL.x
1
0
P6DIR.x
P6IN.x
EN
Module X IN
1
0
Module X OUT
P6OUT.x
1
0
DVSS
DVCC
P6REN.x
Pad Logic
1
P6DS.x
0: Low drive
1: High drive
D
Bus
Keeper
To ADC12
P6.0/A0
P6.1/A1
P6.2/A2
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7
INCHx = y
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 79
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Table 52. Port P6 (P6.0 to P6.7) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P6.x) x FUNCTION P6DIR.x P6SEL.x INCHx
P6.0/A0 0 P6.0 (I/O) I: 0; O: 1 0 X
A0(2) (3) X X 0
P6.1/A1 1 P6.1 (I/O) I: 0; O: 1 0 X
A1(2) (3) X X 1
P6.2/A2 2 P6.2 (I/O) I: 0; O: 1 0 X
A2(2) (3) X X 2
P6.3/A3 3 P6.3 (I/O) I: 0; O: 1 0 X
A3(2) (3) X X 3
P6.4/A4 4 P6.4 (I/O) I: 0; O: 1 0 X
A4(2) (3) X X 4
P6.5/A5 5 P6.5 (I/O) I: 0; O: 1 0 X
A5(1) (2) (3) X X 5
P6.6/A6 6 P6.6 (I/O) I: 0; O: 1 0 X
A6(2) (3) X X 6
P6.7/A7 7 P6.7 (I/O) I: 0; O: 1 0 X
A7(2) (3) X X 7
(1) X = Don't care
(2) Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals.
(3) The ADC12_A channel Ax is connected internally to AVSS if not selected via the respective INCHx bits.
80 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
P7.0/XIN
P7SEL.0
1
0
P7DIR.0
P7IN.0
EN
Module X IN
1
0
Module X OUT
P7OUT.0
1
0
DVSS
DVCC
P7REN.0
Pad Logic
1
P7DS.0
0: Low drive
1: High drive
D
Bus
Keeper
To XT1
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Port P7, P7.0, Input/Output With Schmitt Trigger
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 81
P7.1/XOUT
P7SEL.0
1
0
P7DIR.1
P7IN.1
EN
Module X IN
1
0
Module X OUT
P7OUT.1
1
0
DVSS
DVCC
P7REN.1
Pad Logic
1
P7DS.1
0: Low drive
1: High drive
D
Bus
Keeper
To XT1
XT1BYPASS
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Port P7, P7.1, Input/Output With Schmitt Trigger
Table 53. Port P7 (P7.0 and P7.1) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P7.x) x FUNCTION P7DIR.x P7SEL.0 P7SEL.1 XT1BYPASS
P7.0/XIN 0 P7.0 (I/O) I: 0; O: 1 0 X X
XIN crystal mode(2) X 1 X 0
XIN bypass mode(2) X 1 X 1
P7.1/XOUT 1 P7.1 (I/O) I: 0; O: 1 0 X X
XOUT crystal mode(3) X 1 X 0
P7.1 (I/O)(3) X 1 X 1
(1) X = Don't care
(2) Setting P7SEL.0 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P7.0 is configured for crystal
mode or bypass mode.
(3) Setting P7SEL.0 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P7.1 can be used as
general-purpose I/O.
82 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
P7.2/TB0OUTH/SVMOUT
P7.3/TA1.2
Direction
0:Input
1:Output
P7SEL.x
1
0
P7DIR.x
P7IN.x
EN
ModuleXIN
1
0
ModuleXOUT
P7OUT.x
1
0
DVSS
DVCC
P7REN.x PadLogic
1
P7DS.x
0:Lowdrive
1:Highdrive
D
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Port P7, P7.2 and P7.3, Input/Output With Schmitt Trigger
Table 54. Port P7 (P7.2 and P7.3) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P7.x) x FUNCTION P7DIR.x P7SEL.x
P7.2/TB0OUTH/SVMOUT 2 P7.2 (I/O) I: 0; O: 1 0
TB0OUTH 0 1
SVMOUT 1 1
P7.3/TA1.2 3 P7.3 (I/O) I: 0; O: 1 0
TA1.CCI2B 0 1
TA1.2 1 1
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 83
P7SEL.x
1
0
P7DIR.x
P7IN.x
EN
Module X IN
1
0
Module X OUT
P7OUT.x
1
0
DVSS
DVCC
P7REN.x
Pad Logic
1
P7DS.x
0: Low drive
1: High drive
D
Bus
Keeper
To ADC12
P7.4/A12
P7.5/A13
P7.6/A14
P7.7/A15
INCHx = y
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
Table 55. Port P7 (P7.4 to P7.7) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P7.x) x FUNCTION P7DIR.x P7SEL.x INCHx
P7.4/A12 4 P7.4 (I/O) I: 0; O: 1 0 X
A12(2) (3) X X 12
P7.5/A13 5 P7.5 (I/O) I: 0; O: 1 0 X
A13(4) (5) X X 13
P7.6/A14 6 P7.6 (I/O) I: 0; O: 1 0 X
A14(4) (5) X X 14
P7.7/A15 7 P7.7 (I/O) I: 0; O: 1 0 X
A15(4) (5) X X 15
(1) X = Don't care
(2) Setting the P7SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals.
(3) The ADC12_A channel Ax is connected internally to AVSS if not selected via the respective INCHx bits.
(4) Setting the P7SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals.
(5) The ADC12_A channel Ax is connected internally to AVSS if not selected via the respective INCHx bits.
84 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
P8.0/TA0.0
P8.1/TA0.1
P8.2/TA0.2
P8.3/TA0.3
P8.4/TA0.4
P8.5/TA1.0
P8.6/TA1.1
P8.7
Direction
0: Input
1: Output
P8SEL.x
1
0
P8DIR.x
P8IN.x
EN
Module X IN
1
0
Module X OUT
P8OUT.x
1
0
DVSS
DVCC
P8REN.x Pad Logic
1
P8DS.x
0: Low drive
1: High drive
D
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
Table 56. Port P8 (P8.0 to P8.7) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P8.x) x FUNCTION P8DIR.x P8SEL.x
P8.0/TA0.0 0 P8.0 (I/O) I: 0; O: 1 0
TA0.CCI0B 0 1
TA0.0 1 1
P8.1/TA0.1 1 P8.1 (I/O) I: 0; O: 1 0
TA0.CCI1B 0 1
TA0.1 1 1
P8.2/TA0.2 2 P8.2 (I/O) I: 0; O: 1 0
TA0.CCI2B 0 1
TA0.2 1 1
P8.3/TA0.3 3 P8.3 (I/O) I: 0; O: 1 0
TA0.CCI3B 0 1
TA0.3 1 1
P8.4/TA0.4 4 P8.4 (I/O) I: 0; O: 1 0
TA0.CCI4B 0 1
TA0.4 1 1
P8.5/TA1.0 5 P8.5 (I/O) I: 0; O: 1 0
TA1.CCI0B 0 1
TA1.0 1 1
P8.6/TA1.1 6 P8.6 (I/O) I: 0; O: 1 0
TA1.CCI1B 0 1
TA1.1 1 1
P8.7 7 P8.7 (I/O) I: 0; O: 1 0
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 85
P9.0/UCB2STE/UCA2CLK
P9.1/UCB2SIMO/UCB2SDA
P9.2/UCB2SOMI/UCB2SCL
P9.3/UCB2CLK/UCA2STE
P9.4/UCA2TXD/UCA2SIMO
P9.5/UCA2RXD/UCA2SOMI
P9.6
P9.7
Direction
0: Input
1: Output
P9SEL.x
1
0
P9DIR.x
P9IN.x
EN
Module X IN
1
0
Module X OUT
P9OUT.x
1
0
DVSS
DVCC
P9REN.x Pad Logic
1
P9DS.x
0: Low drive
1: High drive
D
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
Table 57. Port P9 (P9.0 to P9.7) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P9.x) x FUNCTION P9DIR.x P9SEL.x
P9.0/UCB2STE/UCA2CLK 0 P9.0 (I/O) I: 0; O: 1 0
UCB2STE/UCA2CLK(2) (3) X 1
P9.1/UCB2SIMO/UCB2SDA 1 P9.1 (I/O) I: 0; O: 1 0
UCB2SIMO/UCB2SDA(2) (4) X 1
P9.2/UCB2SOMI/UCB2SCL 2 P9.2 (I/O) I: 0; O: 1 0
UCB2SOMI/UCB2SCL(2) (4) X 1
P9.3/UCB2CLK/UCA2STE 3 P9.3 (I/O) I: 0; O: 1 0
UCB2CLK/UCA2STE(2) X 1
P9.4/UCA2TXD/UCA2SIMO 4 P9.4 (I/O) I: 0; O: 1 0
UCA2TXD/UCA2SIMO(2) X 1
P9.5/UCA2RXD/UCA2SOMI 5 P9.5 (I/O) I: 0; O: 1 0
UCA2RXD/UCA2SOMI(2) X 1
P9.6 6 P9.6 (I/O) I: 0; O: 1 0
P9.7 7 P9.7 (I/O) I: 0; O: 1 0
(1) X = Don't care
(2) The pin direction is controlled by the USCI module.
(3) UCA2CLK function takes precedence over UCB2STE function. If the pin is required as UCA2CLK input or output, USCI A2/B2 is forced
to 3-wire SPI mode if 4-wire SPI mode is selected.
(4) If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
86 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
P10.0/UCB3STE/UCA3CLK
P10.1/UCB3SIMO/UCB3SDA
P10.2/UCB3SOMI/UCB3SCL
P10.3/UCB3CLK/UCA3STE
P10.4/UCA3TXD/UCA3SIMO
P10.5/UCA3RXD/UCA3SOMI
P10.6
P10.7
Direction
0: Input
1: Output
P10SEL.x
1
0
P10DIR.x
P10IN.x
EN
Module X IN
1
0
Module X OUT
P10OUT.x
1
0
DVSS
DVCC
P10REN.x Pad Logic
1
P10DS.x
0: Low drive
1: High drive
D
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Port P10, P10.0 to P10.7, Input/Output With Schmitt Trigger
Table 58. Port P10 (P10.0 to P10.7) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P10.x) x FUNCTION P10DIR.x P10SEL.x
P10.0/UCB3STE/UCA3CLK 0 P10.0 (I/O) I: 0; O: 1 0
UCB3STE/UCA3CLK(2) (3) X 1
P10.1/UCB3SIMO/UCB3SDA 1 P10.1 (I/O) I: 0; O: 1 0
UCB3SIMO/UCB3SDA(2) (4) X 1
P10.2/UCB3SOMI/UCB3SCL 2 P10.2 (I/O) I: 0; O: 1 0
UCB3SOMI/UCB3SCL(2) (4) X 1
P10.3/UCB3CLK/UCA3STE 3 P10.3 (I/O) I: 0; O: 1 0
UCB3CLK/UCA3STE(2) X 1
P10.4/UCA3TXD/UCA3SIMO 4 P10.4 (I/O) I: 0; O: 1 0
UCA3TXD/UCA3SIMO(2) X 1
P10.5/UCA3RXD/UCA3SOMI 5 P10.5 (I/O) I: 0; O: 1 0
UCA3RXD/UCA3SOMI(2) X 1
P10.6 6 P10.6 (I/O) I: 0; O: 1 0
Reserved(5) X 1
P10.7 7 P10.7 (I/O) I: 0; O: 1 0
Reserved(5) x 1
(1) X = Don't care
(2) The pin direction is controlled by the USCI module.
(3) UCA3CLK function takes precedence over UCB3STE function. If the pin is required as UCA3CLK input or output, USCI A3/B3 is forced
to 3-wire SPI mode if 4-wire SPI mode is selected.
(4) If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
(5) The secondary function on these pins are reserved for factory test purposes. Application should keep the P10SEL.x of these ports
cleared to prevent potential conflicts with the application.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 87
P11.0/ACLK
P11.1/MCLK
P11.2/SMCLK
Direction
0: Input
1: Output
P11SEL.x
1
0
P11DIR.x
P11IN.x
EN
Module X IN
1
0
Module X OUT
P11OUT.x
1
0
DVSS
DVCC
P11REN.x Pad Logic
1
P11DS.x
0: Low drive
1: High drive
D
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Port P11, P11.0 to P11.2, Input/Output With Schmitt Trigger
Table 59. Port P11 (P11.0 to P11.2) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P11.x) x FUNCTION P11DIR.x P11SEL.x
P11.0/ACLK 0 P11.0 (I/O) I: 0; O: 1 0
ACLK 1 1
P11.1/MCLK 1 P11.1 (I/O) I: 0; O: 1 0
MCLK 1 1
P11.2/SMCLK 2 P11.2 (I/O) I: 0; O: 1 0
SMCLK 1 1
88 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
PJ.0/TDO
From JTAG
1
0
PJDIR.0
PJIN.0
EN
1
0
From JTAG
PJOUT.0
1
0
DVSS
DVCC
PJREN.0 Pad Logic
1
PJDS.0
0: Low drive
1: High drive
D
DVCC
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
From JTAG
1
0
PJDIR.x
PJIN.x
EN
1
0
From JTAG
PJOUT.x
1
0
DVSS
DVCC
PJREN.x Pad Logic
1
PJDS.x
0: Low drive
1: High drive
D
DVSS
To JTAG
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output
Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 89
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Table 60. Port PJ (PJ.0 to PJ.3) Pin Functions
CONTROL BITS/
SIGNALS(1)
PIN NAME (PJ.x) x FUNCTION PJDIR.x
PJ.0/TDO 0 PJ.0 (I/O)(2) I: 0; O: 1
TDO(3) X
PJ.1/TDI/TCLK 1 PJ.1 (I/O)(2) I: 0; O: 1
TDI/TCLK(3) (4) X
PJ.2/TMS 2 PJ.2 (I/O)(2) I: 0; O: 1
TMS(3) (4) X
PJ.3/TCK 3 PJ.3 (I/O)(2) I: 0; O: 1
TCK(3) (4) X
(1) X = Don't care
(2) Default condition
(3) The pin direction is controlled by the JTAG module.
(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.
90 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
DEVICE DESCRIPTORS (TLV)
Table 61 lists the complete contents of the device descriptor tag-length-value (TLV) structure for each device
type.
Table 61. Device Descriptor Table(1)
'F5438A 'F5437A 'F5436A 'F5435A 'F5419A 'F5418A
Size
Description Address bytes Value Value Value Value Value Value
Info Block Info length 01A00h 1 06h 06h 06h 06h 06h 06h
CRC length 01A01h 1 06h 06h 06h 06h 06h 06h
CRC value 01A02h 2 per unit per unit per unit per unit per unit per unit
Device ID 01A04h 1 05h 04h 03h 02h 01h 00h
Device ID 01A05h 1 80h 80h 80h 80h 80h 80h
Hardware revision 01A06h 1 per unit per unit per unit per unit per unit per unit
Firmware revision 01A07h 1 per unit per unit per unit per unit per unit per unit
Die Record Die Record Tag 01A08h 1 08h 08h 08h 08h 08h 08h
Die Record length 01A09h 1 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah
Lot/Wafer ID 01A0Ah 4 per unit per unit per unit per unit per unit per unit
Die X position 01A0Eh 2 per unit per unit per unit per unit per unit per unit
Die Y position 01A10h 2 per unit per unit per unit per unit per unit per unit
Test results 01A12h 2 per unit per unit per unit per unit per unit per unit
ADC12 ADC12 01A14h 1 11h 11h 11h 11h 11h 11h
Calibration Calibration Tag
ADC12 01A15h 1 10h 10h 10h 10h 10h 10h
Calibration length
ADC Gain Factor 01A16h 2 per unit per unit per unit per unit per unit per unit
ADC Offset 01A18h 2 per unit per unit per unit per unit per unit per unit
ADC 1.5-V
Reference 01A1Ah 2 per unit per unit per unit per unit per unit per unit
Temp. Sensor
30°C
ADC 1.5-V
Reference 01A1Ch 2 per unit per unit per unit per unit per unit per unit
Temp. Sensor
85°C
ADC 2.0-V
Reference 01A1Eh 2 per unit per unit per unit per unit per unit per unit
Temp. Sensor
30°C
ADC 2.0-V
Reference 01A20h 2 per unit per unit per unit per unit per unit per unit
Temp. Sensor
85°C
ADC 2.5-V
Reference 01A22h 2 per unit per unit per unit per unit per unit per unit
Temp. Sensor
30°C
ADC 2.5-V
Reference 01A24h 2 per unit per unit per unit per unit per unit per unit
Temp. Sensor
85°C
REF REF Calibration 01A26h 1 12h 12h 12h 12h 12h 12h
Calibration Tag
REF Calibration 01A27h 1 06h 06h 06h 06h 06h 06h
length
(1) NA = Not applicable
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 91
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Table 61. Device Descriptor Table(1) (continued)
'F5438A 'F5437A 'F5436A 'F5435A 'F5419A 'F5418A
Size
Description Address bytes Value Value Value Value Value Value
REF 1.5-V 01A28h 2 per unit per unit per unit per unit per unit per unit
Reference
REF 2.0-V 01A2Ah 2 per unit per unit per unit per unit per unit per unit
Reference
REF 2.5-V 01A2Ch 2 per unit per unit per unit per unit per unit per unit
Reference
Peripheral Peripheral 01A2Eh 1 02h 02h 02h 02h 02h 02h
Descriptor Descriptor Tag
Peripheral 01A2Fh 1 61h 059h 62h 5Ah 61h 59h
Descriptor Length 08h 08h 08h 08h 08h 08h
Memory 1 2 8Ah 8Ah 8Ah 8Ah 8Ah 8Ah
0Ch 0Ch 0Ch 0Ch 0Ch 0Ch
Memory 2 2 86h 86h 86h 86h 86h 86h
0Eh 0Eh 0Eh 0Eh 0Eh 0Eh
Memory 3 2 30h 30h 30h 30h 30h 30h
2Eh 2Eh 2Eh 2Eh 2Eh 2Eh
Memory 4 2 98h 98h 97h 97h 96h 96h
Memory 5 0/1 NA NA 94h 94h NA NA
delimiter 1 00h 00h 00h 00h 00h 00h
Peripheral count 1 21h 1Dh 21h 1Dh 21h 1Dh
00h 00h 00h 00h 00h 00h
MSP430CPUXV2 2 23h 23h 23h 23h 23h 23h
00h 00h 00h 00h 00h 00h
SBW 2 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh
00h 00h 00h 00h 00h 00h
EEM-8 2 05h 05h 05h 05h 05h 05h
00h 00h 00h 00h 00h 00h
TI BSL 2 FCh FCh FCh FCh FCh FCh
00h 00h 00h 00h 00h 00h
Package 2 1Fh 1Fh 1Fh 1Fh 1Fh 1Fh
10h 10h 10h 10h 10h 10h
SFR 2 41h 41h 41h 41h 41h 41h
02h 02h 02h 02h 02h 02h
PMM 2 30h 30h 30h 30h 30h 30h
02h 02h 02h 02h 02h 02h
FCTL 2 38h 38h 38h 38h 38h 38h
01h 01h 01h 01h 01h 01h
CRC16-straight 2 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch
CRC16-bit 00h 00h 00h 00h 00h 00h
2
reversed 3Dh 3Dh 3Dh 3Dh 3Dh 3Dh
00h 00h 00h 00h 00h 00h
RAMCTL 2 44h 44h 44h 44h 44h 44h
00h 00h 00h 00h 00h 00h
WDT_A 2 40h 40h 40h 40h 40h 40h
01h 01h 01h 01h 01h 01h
UCS 2 48h 48h 48h 48h 48h 48h
02h 02h 02h 02h 02h 02h
SYS 2 42h 42h 42h 42h 42h 42h
03h 03h 03h 03h 03h 03h
REF 2 A0h A0h A0h A0h A0h A0h
05h 05h 05h 05h 05h 05h
Port 1/2 2 51h 51h 51h 51h 51h 51h
92 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Table 61. Device Descriptor Table(1) (continued)
'F5438A 'F5437A 'F5436A 'F5435A 'F5419A 'F5418A
Size
Description Address bytes Value Value Value Value Value Value
02h 02h 02h 02h 02h 02h
Port 3/4 2 52h 52h 52h 52h 52h 52h
02h 02h 02h 02h 02h 02h
Port 5/6 2 53h 53h 53h 53h 53h 53h
02h 02h 02h 02h 02h 02h
Port 7/8 2 54h 54h 54h 54h 54h 54h
02h 02h 02h
Port 9/10 2 NA NA NA
55h 55h 55h
02h 02h 02h
Port 11/12 2 NA NA NA
56h 56h 56h
08h 0Ch 08h 0Ch 08h 0Ch
JTAG 2 5Fh 5Fh 5Fh 5Fh 5Fh 5Fh
02h 02h 02h 02h 02h 02h
TA0 2 62h 62h 62h 62h 62h 62h
04h 04h 04h 04h 04h 04h
TA1 2 61h 61h 61h 61h 61h 61h
04h 04h 04h 04h 04h 04h
TB0 2 67h 67h 67h 67h 67h 67h
0Eh 0Eh 0Eh 0Eh 0Eh 0Eh
RTC 2 68h 68h 68h 68h 68h 68h
02h 02h 02h 02h 02h 02h
MPY32 2 85h 85h 85h 85h 85h 85h
04h 04h 04h 04h 04h 04h
DMA-3 2 47h 47h 47h 47h 47h 47h
0Ch 0Ch 0Ch 0Ch 0Ch 0Ch
USCI_A/B 2 90h 90h 90h 90h 90h 90h
04h 04h 04h 04h 04h 04h
USCI_A/B 2 90h 90h 90h 90h 90h 90h
04h 04h 04h
USCI_A/B 2 NA NA NA
90h 90h 90h
04h 04h 04h
USCI_A/B 2 NA NA NA
90h 90h 90h
08h 10h 08h 10h 08h 10h
ADC12_A 2 D1h D1h D1h D1h D1h D1h
Interrupts TB0.CCIFG0 1 64h 64h 64h 64h 64h 64h
TB0.CCIFG1..6 1 65h 65h 65h 65h 65h 65h
WDTIFG 1 40h 40h 40h 40h 40h 40h
USCI_A0 1 90h 90h 90h 90h 90h 90h
USCI_B0 1 91h 91h 91h 91h 91h 91h
ADC12_A 1 D0h D0h D0h D0h D0h D0h
TA0.CCIFG0 1 60h 60h 60h 60h 60h 60h
TA0.CCIFG1..4 1 61h 61h 61h 61h 61h 61h
USCI_A2 1 94h 01h 94h 01h 94h 01h
USCI_B2 1 95h 01h 95h 01h 95h 01h
DMA 1 46h 46h 46h 46h 46h 46h
TA1.CCIFG0 1 62h 62h 62h 62h 62h 62h
TA1.CCIFG1..2 1 63h 63h 63h 63h 63h 63h
P1 1 50h 50h 50h 50h 50h 50h
USCI_A1 1 92h 92h 92h 92h 92h 92h
USCI_B1 1 93h 93h 93h 93h 93h 93h
USCI_A3 1 96h 01h 96h 01h 96h 01h
USCI_B3 1 97h 01h 97h 01h 97h 01h
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 93
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Table 61. Device Descriptor Table(1) (continued)
'F5438A 'F5437A 'F5436A 'F5435A 'F5419A 'F5418A
Size
Description Address bytes Value Value Value Value Value Value
P2 1 51h 51h 51h 51h 51h 51h
RTC_A 1 68h 68h 68h 68h 68h 68h
delimiter 1 00h 00h 00h 00h 00h 00h
94 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
REVISION HISTORY
REVISION DESCRIPTION
SLAS655 Product Preview release
SLAS655A Production Data release
Changed fXT1,HF,SW MIN from 1.5 MHz to 0.7 MHz, page 48
SLAS655B Changed fXT2,HF,SW MIN from 1.5 MHz to 0.7 MHz, page 49
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 95
PACKAGE OPTION ADDENDUM
www.ti.com 23-May-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
MSP430F5418AIPN ACTIVE LQFP PN 80 119 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F5418AIPNR ACTIVE LQFP PN 80 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F5419AIPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F5419AIPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F5419AIZQW OBSOLETE BGA
MICROSTAR
JUNIOR
ZQW 113 TBD Call TI Call TI
MSP430F5419AIZQWR ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 2500 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
MSP430F5419AIZQWT ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 250 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
MSP430F5435AIPN ACTIVE LQFP PN 80 119 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F5435AIPNR ACTIVE LQFP PN 80 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F5436AIPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F5436AIPZR ACTIVE LQFP PZ 100 1 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F5436AIZQW OBSOLETE BGA
MICROSTAR
JUNIOR
ZQW 113 TBD Call TI Call TI
MSP430F5436AIZQWR ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 2500 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
MSP430F5436AIZQWT ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 250 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
PACKAGE OPTION ADDENDUM
www.ti.com 23-May-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
MSP430F5437AIPN ACTIVE LQFP PN 80 119 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F5437AIPNR ACTIVE LQFP PN 80 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F5438ACY ACTIVE DIESALE Y 0 64 Green (RoHS
& no Sb/Br) Call TI N / A for Pkg Type
MSP430F5438ACYS ACTIVE WAFERSALE YS 0 1 TBD Call TI Call TI
MSP430F5438AGACYS ACTIVE WAFERSALE YS 0 1 TBD Call TI Call TI
MSP430F5438AIPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F5438AIPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F5438AIZQWR ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 2500 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
MSP430F5438AIZQWT ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 250 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
XMS430F5438AIPZ OBSOLETE LQFP PZ 100 TBD Call TI Call TI
XMS430F5438AIPZR OBSOLETE LQFP PZ 100 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 23-May-2012
Addendum-Page 3
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
MSP430F5418AIPNR LQFP PN 80 1000 330.0 24.4 14.6 14.6 1.9 20.0 24.0 Q2
MSP430F5419AIZQWT BGA MI
CROSTA
R JUNI
OR
ZQW 113 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1
MSP430F5436AIZQWT BGA MI
CROSTA
R JUNI
OR
ZQW 113 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1
MSP430F5438AIZQWT BGA MI
CROSTA
R JUNI
OR
ZQW 113 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
MSP430F5418AIPNR LQFP PN 80 1000 367.0 367.0 45.0
MSP430F5419AIZQWT BGA MICROSTAR
JUNIOR ZQW 113 250 336.6 336.6 28.6
MSP430F5436AIZQWT BGA MICROSTAR
JUNIOR ZQW 113 250 336.6 336.6 28.6
MSP430F5438AIZQWT BGA MICROSTAR
JUNIOR ZQW 113 250 336.6 336.6 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PN (S-PQFP-G80) PLASTIC QUAD FLATPACK
4040135 /B 11/96
0,17
0,27
0,13 NOM
40
21
0,25
0,45
0,75
0,05 MIN
Seating Plane
Gage Plane
41
60
61
80
20
SQ
SQ
1
13,80
14,20
12,20
9,50 TYP
11,80
1,45
1,35
1,60 MAX 0,08
0,50 M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK
4040149/B 11/96
50
26 0,13 NOM
Gage Plane
0,25
0,45
0,75
0,05 MIN
0,27
51
25
75
1
12,00 TYP
0,17
76
100
SQ
SQ
15,80
16,20
13,80
1,35
1,45
1,60 MAX
14,20
0°–7°
Seating Plane
0,08
0,50 M
0,08
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated