MSP430F543xA, MSP430F541xA
www.ti.com
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
MIXED SIGNAL MICROCONTROLLER
1FEATURES
• Low Supply Voltage Range: 1.8 V to 3.6 V • Unified Clock System
• Ultralow Power Consumption – FLL Control Loop for Frequency
Stabilization
– Active Mode (AM):
All System Clocks Active – Low-Power/Low-Frequency Internal Clock
230 µA/MHz at 8 MHz, 3.0 V, Flash Program Source (VLO)
Execution (Typical) – Low-Frequency Trimmed Internal Reference
110 µA/MHz at 8 MHz, 3.0 V, RAM Program Source (REFO)
Execution (Typical) – 32-kHz Crystals
– Standby Mode (LPM3): – High-Frequency Crystals up to 32 MHz
Real-Time Clock With Crystal , Watchdog, • 16-Bit Timer TA0, Timer_A With Five
and Supply Supervisor Operational, Full Capture/Compare Registers
RAM Retention, Fast Wake-Up: • 16-Bit Timer TA1, Timer_A With Three
1.7 µA at 2.2 V, 2.1 µA at 3.0 V (Typical) Capture/Compare Registers
Low-Power Oscillator (VLO),
General-Purpose Counter, Watchdog, and • 16-Bit Timer TB0, Timer_B With Seven
Supply Supervisor Operational, Full RAM Capture/Compare Shadow Registers
Retention, Fast Wake-Up: • Up to Four Universal Serial Communication
1.2 µA at 3.0 V (Typical) Interfaces
– Off Mode (LPM4): – USCI_A0, USCI_A1, USCI_A2, and USCI_A3
Full RAM Retention, Supply Supervisor Each Supporting
Operational, Fast Wake-Up: – Enhanced UART supporting
1.2 µA at 3.0 V (Typical) Auto-Baudrate Detection
– Shutdown Mode (LPM4.5): – IrDA Encoder and Decoder
0.1 µA at 3.0 V (Typical) – Synchronous SPI
• Wake-Up From Standby Mode in Less Than – USCI_B0, USCI_B1, USCI_B2, and USCI_B3
5 µs Each Supporting
• 16-Bit RISC Architecture – I2CTM
– Extended Memory – Synchronous SPI
– Up to 25-MHz System Clock • 12-Bit Analog-to-Digital (A/D) Converter
• Flexible Power Management System – Internal Reference
– Fully Integrated LDO With Programmable – Sample-and-Hold
Regulated Core Supply Voltage – Autoscan Feature
– Supply Voltage Supervision, Monitoring, – 14 External Channels, 2 Internal Channels
and Brownout • Hardware Multiplier Supporting 32-Bit
Operations
• Serial Onboard Programming, No External
Programming Voltage Needed
• Three Channel Internal DMA
• Basic Timer With Real-Time Clock Feature
• Family Members are Summarized in Table 1
• For Complete Module Descriptions, See the
MSP430x5xx Family User's Guide (SLAU208)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
DESCRIPTION
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with extensive
low-power modes, is optimized to achieve extended battery life in portable measurement applications. The
device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to
maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to
active mode in less than 5 µs.
The MSP430F543xA and MSP430F541xA series are microcontroller configurations with three 16-bit timers, a
high performance 12-bit analog-to-digital (A/D) converter, up to four universal serial communication interfaces
(USCI), hardware multiplier, DMA, real-time clock module with alarm capabilities, and up to 87 I/O pins.
Typical applications for this device include analog and digital sensor systems, digital motor control, remote
controls, thermostats, digital timers, hand-held meters, etc.
Family members available are summarized in Table 1.
Table 1. Family Members
USCI
Flash SRAM ADC12_A Package
Channel A: Channel B:
Device Timer_A(1) Timer_B(2) I/O
(KB) (KB) (Ch) Type
UART/IrDA/ SPI/I2C
SPI
100 PZ,
MSP430F5438A 256 16 5, 3 7 4 4 14 ext / 2 int 87 113 ZQW
MSP430F5437A 256 16 5, 3 7 2 2 14 ext / 2 int 67 80 PN
100 PZ,
MSP430F5436A 192 16 5, 3 7 4 4 14 ext / 2 int 87 113 ZQW
MSP430F5435A 192 16 5, 3 7 2 2 14 ext / 2 int 67 80 PN
100 PZ,
MSP430F5419A 128 16 5, 3 7 4 4 14 ext / 2 int 87 113 ZQW
MSP430F5418A 128 16 5, 3 7 2 2 14 ext / 2 int 67 80 PN
(1) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(2) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
Table 2. Ordering Information(1)
PACKAGED DEVICES(2)
TAPLASTIC 100-PIN LQFP PLASTIC 80-PIN LQFP PLASTIC 113-BALL BGA
(PZ) (PN) (ZQW)
MSP430F5438AIPZ MSP430F5437AIPN MSP430F5438AIZQW
–40°C to 85°C MSP430F5436AIPZ MSP430F5435AIPN MSP430F5436AIZQW
MSP430F5419AIPZ MSP430F5418AIPN MSP430F5419AIZQW
(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
2Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
PZPACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7
P7.4/A12
P7.5/A13
P7.6/A14
P7.7/A15
P5.0/A8/VREF+/VeREF+
P5.1/A9/VREF−/VeREF−
AVCC
AVSS
P7.0/XIN
P7.1/XOUT
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/SMCLK
P1.7
P2.0/TA1CLK/MCLK
P9.7
P9.6
P9.5/UCA2RXDUCA2SOMI
P9.4/UCA2TXD/UCA2SIMO
P9.3/UCB2CLK/UCA2STE
P9.2/UCB2SOMI/UCB2SCL
P9.1/UCB2SIMO/UCB2SDA
P9.0/UCB2STE/UCA2CLK
P8.7
P8.6/TA1.1
P8.5/TA1.0
DVCC2
DVSS2
VCORE
P8.4/TA0.4
P8.3/TA0.3
P8.2/TA0.2
P8.1/TA0.1
P8.0/TA0.0
P7.3/TA1.2
P7.2/TB0OUTH/SVMOUT
P5.7/UCA1RXD/UCA1SOMI
P5.6/UCA1TXD/UCA1SIMO
P5.5/UCB1CLK/UCA1STE
P5.4/UCB1SOMI/UCB1SCL
MSP430F5438AIPZ
MSP430F5436AIPZ
MSP430F5419AIPZ
P6.3/A3
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
P5.3/XT2OUT
P5.2/XT2IN
DVSS4
DVCC4
P11.2/SMCLK
P11.1/MCLK
P11.0/ACLK
P10.7
P10.6
P10.5/UCA3RXDUCA3SOMI
P10.4/UCA3TXD/UCA3SIMO
P10.3/UCB3CLK/UCA3STE
P10.2/UCB3SOMI/UCB3SCL
P10.1/UCB3SIMO/UCB3SDA
P10.0/UCB3STE/UCA3CLK
P2.1/TA1.0
P2.2/TA1.1
P2.3/TA1.2
P2.4/RTCCLK
P2.5
P2.6/ACLK
P2.7/ADC12CLK/DMAE0
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
DVSS3
DVCC3
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/UCB1STE/UCA1CLK
P3.7/UCB1SIMO/UCB1SDA
P4.0/TB0.0
P4.1/TB0.1
P4.2/TB0.2
P4.3/TB0.3
P4.4/TB0.4
P4.5/TB0.5
P4.6/TB0.6
P4.7/TB0CLK/SMCLK
DVSS1
DVCC1
MSP430F543xA, MSP430F541xA
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SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Pin Designation, MSP430F5438AIPZ, MSP430F5436AIPZ, MSP430F5419AIPZ
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 3
P8.0/TA0.0
P7.3/TA1.2
P7.2/TB0OUTH/SVMOUT
P5.7/UCA1RXD/UCA1SOMI
P5.6/UCA1TXD/UCA1SIMO
P5.5/UCB1CLK/UCA1STE
P5.4/UCB1SOMI/UCB1SCL
P4.7/TB0CLK/SMCLK
P4.6/TB0.6
DVCC2
DVSS2
VCORE
P4.5/TB0.5
P4.4/TB0.4
P4.3/TB0.3
P4.2/TB0.2
P4.1/TB0.1
P4.0/TB0.0
P3.7/UCB1SIMO/UCB1SDA
P3.6/UCB1STE/UCA1CLK
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7
P7.4/A12
P7.5/A13
P7.6/A14
P7.7/A15
P5.0/A8/VREF+/VeREF+
P5.1/A9/VREF−/VeREF−
AVCC
AVSS
P7.0/XIN
P7.1/XOUT
DVSS1
DVCC1
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
PNPACKAGE
(TOP VIEW)
22 23
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
25 26 27 28
79 78 77 76 7580 74 72 71 7073
29 30 31 32 33
69 68
21
67 66 65 64
34 35 36 37 38 39 40
63 62 61
MSP430F5437AIPN
MSP430F5435AIPN
MSP430F5418AIPN
P6.3/A3
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCLK
P5.3/XT2OUT
P5.2/XT2IN
DVSS4
DVCC4
P8.6/TA1.1
P8.5/TA1.0
P8.4/TA0.4
P8.3/TA0.3
P8.2/TA0.2
P8.1/TA0.1
P1.4/TA0.3
P1.5/TA0.4
P1.6/SMCLK
P1.7
P2.0/TA1CLK/MCLK
P2.1/TA1.0
P2.2/TA1.1
P2.3/TA1.2
P2.4/RTCCLK
DVSS3
DVCC3
P2.5
P2.6/ACLK
P2.7/ADC12CLK/DMAE0
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Pin Designation, MSP430F5437AIPN, MSP430F5435AIPN, MSP430F5418AIPN
4Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12
C1 C2 C3 C11 C12
D1 D2 D4 D5 D6 D7 D8 D9 D11 D12
E1 E2 E4 E5 E6 E7 E8 E9 E11 E12
F1 F2 F4 F5 F8 F9 F11 F12
G1 G2 G4 G5 G8 G9 G11 G12
J1 J2 J4 J5 J6 J7 J8 J9 J11 J12
H1 H2 H4 H5 H6 H7 H8 H9 H11 H12
K1 K2 K11 K12
L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12
M1 M2 M3 M5 M6 M7 M8 M9 M10 M11 M12
M4
ZQWPACKAGE
(TOP VIEW)
MSP430F543xA, MSP430F541xA
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SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Pin Designation, MSP430F5438AIZQW, MSP430F5436AIZQW, MSP430F5419AIZQW
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Unified
Clock
System
256KB
192KB
128KB
Flash
16KB
RAM
MCLK
ACLK
SMCLK
I/OPorts
P1/P2
2×8I/Os
Interrupt
Capability
PA
1×16I/Os
CPUXV2
and
Working
Registers
EEM
(L:8+2)
XIN XOUT
JTAG/
Interface
SBW
PA PB PC PD
DMA
3Channel
XT2IN
XT OUT2
PE
Power
Management
LDO
SVM/
Brownout
SVS
SYS
Watchdog
PF
I/OPorts
P3/P4
2×8I/Os
PB
1×16I/Os
I/OPorts
P5/P6
2×8I/Os
PC
1×16I/Os
I/OPorts
P7/P8
2×8I/Os
PD
1×16I/Os
I/OPorts
P9/P10
2×8I/Os
PE
1×16I/Os
I/OPorts
P11
1×3I/Os
PF
1×3I/Os
MPY32
TA0
Timer_A
5CC
Registers
TA1
Timer_A
3CC
Registers
TB0
Timer_B
7CC
Registers
RTC_A CRC16
USCI0,1,2,3
USCI_Ax:
UART,
IrDA,SPI
UCSI_Bx:
SPI,I2C
ADC12_A
200KSPS
16Channels
(14ext/2int)
Autoscan
12Bit
DVCC DVSS AVCC AVSS
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x P10.x P11.x
RST/NMI
MAB
MDB
REF
Unified
Clock
System
256KB
192KB
128KB
Flash
16KB
RAM
MCLK
ACLK
SMCLK
I/OPorts
P1/P2
2×8I/Os
Interrupt
Capability
PA
1×16I/Os
CPUXV2
and
Working
Registers
EEM
(L:8+2)
XIN XOUT
JTAG/
Interface
SBW
PA PB PC PD
DMA
3Channel
XT2IN
XT OUT2
Power
Management
LDO
SVM/
Brownout
SVS
SYS
Watchdog
I/OPorts
P3/P4
2×8I/Os
PB
1×16I/Os
I/OPorts
P5/P6
2×8I/Os
PC
1×16I/Os
I/OPorts
P7/P8
2×8I/Os
PD
1×16I/Os
MPY32
TA0
Timer_A
5CC
Registers
TA1
Timer_A
3CC
Registers
TB0
Timer_B
7CC
Registers
RTC_A CRC16
USCI0,1
UCSI_Ax:
UART,
IrDA,SPI
USCI_Bx:
SPI,I2C
DVCC DVSS AVCC AVSS
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x
RST/NMI
ADC12_A
200KSPS
16Channels
(14ext/2int)
Autoscan
12Bit
MAB
MDB
REF
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Functional Block Diagram
MSP430F5438AIPZ, MSP430F5436AIPZ, MSP430F5419AIPZ,
MSP430F5438AIZQW, MSP430F5436AIZQW, MSP430F5419AIZQW
Functional Block Diagram
MSP430F5437AIPN, MSP430F5435AIPN, MSP430F5418AIPN
6Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
MSP430F543xA, MSP430F541xA
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SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Table 3. TERMINAL FUNCTIONS
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ PN ZQW
General-purpose digital I/O
P6.4/A4 1 1 A1 I/O Analog input A4 – ADC
General-purpose digital I/O
P6.5/A5 2 2 E4 I/O Analog input A5 – ADC
General-purpose digital I/O
P6.6/A6 3 3 B1 I/O Analog input A6 – ADC
General-purpose digital I/O
P6.7/A7 4 4 C2 I/O Analog input A7 – ADC
General-purpose digital I/O
P7.4/A12 5 5 F4 I/O Analog input A12 –ADC
General-purpose digital I/O
P7.5/A13 6 6 C1 I/O Analog input A13 – ADC
General-purpose digital I/O
P7.6/A14 7 7 D2 I/O Analog input A14 – ADC
General-purpose digital I/O
P7.7/A15 8 8 G4 I/O Analog input A15 – ADC
General-purpose digital I/O
Analog input A8 – ADC
P5.0/A8/VREF+/VeREF+ 9 9 D1 I/O Output of reference voltage to the ADC
Input for an external reference voltage to the ADC
General-purpose digital I/O
Analog input A9 – ADC
P5.1/A9/VREF-/VeREF- 10 10 E1 I/O Negative terminal for the ADC's reference voltage for both sources, the
internal reference voltage, or an external applied reference voltage
AVCC 11 11 E2 Analog power supply
AVSS 12 12 F2 Analog ground supply
General-purpose digital I/O
P7.0/XIN 13 13 F1 I/O Input terminal for crystal oscillator XT1
General-purpose digital I/O
P7.1/XOUT 14 14 G1 I/O Output terminal of crystal oscillator XT1
DVSS1 15 15 G2 Digital ground supply
DVCC1 16 16 H2 Digital power supply
General-purpose digital I/O with port interrupt
P1.0/TA0CLK/ACLK 17 17 H1 I/O TA0 clock signal TACLK input
ACLK output (divided by 1, 2, 4, or 8)
General-purpose digital I/O with port interrupt
P1.1/TA0.0 18 18 H4 I/O TA0 CCR0 capture: CCI0A input, compare: Out0 output
BSL transmit output
General-purpose digital I/O with port interrupt
P1.2/TA0.1 19 19 J4 I/O TA0 CCR1 capture: CCI1A input, compare: Out1 output
BSL receive input
General-purpose digital I/O with port interrupt
P1.3/TA0.2 20 20 J1 I/O TA0 CCR2 capture: CCI2A input, compare: Out2 output
General-purpose digital I/O with port interrupt
P1.4/TA0.3 21 21 J2 I/O TA0 CCR3 capture: CCI3A input compare: Out3 output
General-purpose digital I/O with port interrupt
P1.5/TA0.4 22 22 K1 I/O TA0 CCR4 capture: CCI4A input, compare: Out4 output
General-purpose digital I/O with port interrupt
P1.6/SMCLK 23 23 K2 I/O SMCLK output
P1.7 24 24 L1 I/O General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
P2.0/TA1CLK/MCLK 25 25 M1 I/O TA1 clock signal TA1CLK input
MCLK output
(1) I = input, O = output, N/A = not available on this package offering
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 7
MSP430F543xA, MSP430F541xA
SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
www.ti.com
Table 3. TERMINAL FUNCTIONS (continued)
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ PN ZQW
General-purpose digital I/O with port interrupt
P2.1/TA1.0 26 26 L2 I/O TA1 CCR0 capture: CCI0A input, compare: Out0 output
General-purpose digital I/O with port interrupt
P2.2/TA1.1 27 27 M2 I/O TA1 CCR1 capture: CCI1A input, compare: Out1 output
General-purpose digital I/O with port interrupt
P2.3/TA1.2 28 28 L3 I/O TA1 CCR2 capture: CCI2A input, compare: Out2 output
General-purpose digital I/O with port interrupt
P2.4/RTCCLK 29 29 M3 I/O RTCCLK output
P2.5 30 32 L4 I/O General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
P2.6/ACLK 31 33 M4 I/O ACLK output (divided by 1, 2, 4, 8, 16, or 32)
General-purpose digital I/O with port interrupt
P2.7/ADC12CLK/DMAE0 32 34 J5 I/O Conversion clock output ADC
DMA external trigger input
General-purpose digital I/O
Slave transmit enable – USCI_B0 SPI mode
P3.0/UCB0STE/UCA0CLK 33 35 L5 I/O Clock signal input – USCI_A0 SPI slave mode
Clock signal output – USCI_A0 SPI master mode
General-purpose digital I/O
P3.1/UCB0SIMO/UCB0SDA 34 36 M5 I/O Slave in, master out – USCI_B0 SPI mode
I2C data – USCI_B0 I2C mode
General-purpose digital I/O
P3.2/UCB0SOMI/UCB0SCL 35 37 J6 I/O Slave out, master in – USCI_B0 SPI mode
I2C clock – USCI_B0 I2C mode
General-purpose digital I/O
Clock signal input – USCI_B0 SPI slave mode
P3.3/UCB0CLK/UCA0STE 36 38 L6 I/O Clock signal output – USCI_B0 SPI master mode
Slave transmit enable – USCI_A0 SPI mode
DVSS3 37 30 M6 Digital ground supply
DVCC3 38 31 M7 Digital power supply
General-purpose digital I/O
P3.4/UCA0TXD/UCA0SIMO 39 39 L7 I/O Transmit data – USCI_A0 UART mode
Slave in, master out – USCI_A0 SPI mode
General-purpose digital I/O
P3.5/UCA0RXD/UCA0SOMI 40 40 J7 I/O Receive data – USCI_A0 UART mode
Slave out, master in – USCI_A0 SPI mode
General-purpose digital I/O
Slave transmit enable – USCI_B1 SPI mode
P3.6/UCB1STE/UCA1CLK 41 41 M8 I/O Clock signal input – USCI_A1 SPI slave mode
Clock signal output – USCI_A1 SPI master mode
General-purpose digital I/O
P3.7/UCB1SIMO/UCB1SDA 42 42 L8 I/O Slave in, master out – USCI_B1 SPI mode
I2C data – USCI_B1 I2C mode
General-purpose digital I/O
P4.0/TB0.0 43 43 J8 I/O TB0 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
General-purpose digital I/O
P4.1/TB0.1 44 44 M9 I/O TB0 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
General-purpose digital I/O
P4.2/TB0.2 45 45 L9 I/O TB0 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
General-purpose digital I/O
P4.3/TB0.3 46 46 L10 I/O TB0 capture CCR3: CCI3A/CCI3B input, compare: Out3 output
General-purpose digital I/O
P4.4/TB0.4 47 47 M10 I/O TB0 capture CCR4: CCI4A/CCI4B input, compare: Out4 output
General-purpose digital I/O
P4.5/TB0.5 48 48 L11 I/O TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output
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Table 3. TERMINAL FUNCTIONS (continued)
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ PN ZQW
General-purpose digital I/O
P4.6/TB0.6 49 52 M11 I/O TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output
General-purpose digital I/O
P4.7/TB0CLK/SMCLK 50 53 M12 I/O TB0 clock input
SMCLK output
General-purpose digital I/O
P5.4/UCB1SOMI/UCB1SCL 51 54 L12 I/O Slave out, master in – USCI_B1 SPI mode
I2C clock – USCI_B1 I2C mode
General-purpose digital I/O
Clock signal input – USCI_B1 SPI slave mode
P5.5/UCB1CLK/UCA1STE 52 55 J9 I/O Clock signal output – USCI_B1 SPI master mode
Slave transmit enable – USCI_A1 SPI mode
General-purpose digital I/O
P5.6/UCA1TXD/UCA1SIMO 53 56 K11 I/O Transmit data – USCI_A1 UART mode
Slave in, master out – USCI_A1 SPI mode
General-purpose digital I/O
P5.7/UCA1RXD/UCA1SOMI 54 57 K12 I/O Receive data – USCI_A1 UART mode
Slave out, master in – USCI_A1 SPI mode
General-purpose digital I/O
P7.2/TB0OUTH/SVMOUT 55 58 J11 I/O Switch all PWM outputs high impedance – Timer TB0
SVM output
General-purpose digital I/O
P7.3/TA1.2 56 59 J12 I/O TA1 CCR2 capture: CCI2B input, compare: Out2 output
General-purpose digital I/O
P8.0/TA0.0 57 60 H9 I/O TA0 CCR0 capture: CCI0B input, compare: Out0 output
General-purpose digital I/O
P8.1/TA0.1 58 61 H11 I/O TA0 CCR1 capture: CCI1B input, compare: Out1 output
General-purpose digital I/O
P8.2/TA0.2 59 62 H12 I/O TA0 CCR2 capture: CCI2B input, compare: Out2 output
General-purpose digital I/O
P8.3/TA0.3 60 63 G9 I/O TA0 CCR3 capture: CCI3B input, compare: Out3 output
General-purpose digital I/O
P8.4/TA0.4 61 64 G11 I/O TA0 CCR4 capture: CCI4B input, compare: Out4 output
Regulated core power supply output (internal usage only, no external current
VCORE(2) 62 49 G12 loading)
DVSS2 63 50 F12 Digital ground supply
DVCC2 64 51 E12 Digital power supply
General-purpose digital I/O
P8.5/TA1.0 65 65 F11 I/O TA1 CCR0 capture: CCI0B input, compare: Out0 output
General-purpose digital I/O
P8.6/TA1.1 66 66 E11 I/O TA1 CCR1 capture: CCI1B input, compare: Out1 output
P8.7 67 N/A D12 I/O General-purpose digital I/O
General-purpose digital I/O
Slave transmit enable – USCI_B2 SPI mode
P9.0/UCB2STE/UCA2CLK 68 N/A D11 I/O Clock signal input – USCI_A2 SPI slave mode
Clock signal output – USCI_A2 SPI master mode
General-purpose digital I/O
P9.1/UCB2SIMO/UCB2SDA 69 N/A F9 I/O Slave in, master out – USCI_B2 SPI mode
I2C data – USCI_B2 I2C mode
General-purpose digital I/O
P9.2/UCB2SOMI/UCB2SCL 70 N/A C12 I/O Slave out, master in – USCI_B2 SPI mode
I2C clock – USCI_B2 I2C mode
(2) VCORE is for internal usage only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE.
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Table 3. TERMINAL FUNCTIONS (continued)
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ PN ZQW
General-purpose digital I/O
Clock signal input – USCI_B2 SPI slave mode
P9.3/UCB2CLK/UCA2STE 71 N/A E9 I/O Clock signal output – USCI_B2 SPI master mode
Slave transmit enable – USCI_A2 SPI mode
General-purpose digital I/O
P9.4/UCA2TXD/UCA2SIMO 72 N/A C11 I/O Transmit data – USCI_A2 UART mode
Slave in, master out – USCI_A2 SPI mode
General-purpose digital I/O
P9.5/UCA2RXD/UCA2SOMI 73 N/A B12 I/O Receive data – USCI_A2 UART mode
Slave out, master in – USCI_A2 SPI mode
P9.6 74 N/A B11 I/O General-purpose digital I/O
P9.7 75 N/A A12 I/O General-purpose digital I/O
General-purpose digital I/O
Slave transmit enable – USCI_B3 SPI mode
P10.0/UCB3STE/UCA3CLK 76 N/A D9 I/O Clock signal input – USCI_A3 SPI slave mode
Clock signal output – USCI_A3 SPI master mode
General-purpose digital I/O
P10.1/UCB3SIMO/UCB3SDA 77 N/A A11 I/O Slave in, master out – USCI_B3 SPI mode
I2C data – USCI_B3 I2C mode
General-purpose digital I/O
P10.2/UCB3SOMI/UCB3SCL 78 N/A D8 I/O Slave out, master in – USCI_B3 SPI mode
I2C clock – USCI_B3 I2C mode
General-purpose digital I/O
Clock signal input – USCI_B3 SPI slave mode
P10.3/UCB3CLK/UCA3STE 79 N/A B10 I/O Clock signal output – USCI_B3 SPI master mode
Slave transmit enable – USCI_A3 SPI mode
General-purpose digital I/O
P10.4/UCA3TXD/UCA3SIMO 80 N/A A10 I/O Transmit data – USCI_A3 UART mode
Slave in, master out – USCI_A3 SPI mode
General-purpose digital I/O
P10.5/UCA3RXD/UCA3SOMI 81 N/A B9 I/O Receive data – USCI_A3 UART mode
Slave out, master in – USCI_A3 SPI mode
P10.6 82 N/A A9 I/O General-purpose digital I/O
P10.7 83 N/A B8 I/O General-purpose digital I/O
General-purpose digital I/O
P11.0/ACLK 84 N/A A8 I/O ACLK output (divided by 1, 2, 4, 8, 16, or 32)
General-purpose digital I/O
P11.1/MCLK 85 N/A D7 I/O MCLK output
General-purpose digital I/O
P11.2/SMCLK 86 N/A A7 I/O SMCLK output
DVCC4 87 67 B7 Digital power supply
DVSS4 88 68 B6 Digital ground supply
General-purpose digital I/O
P5.2/XT2IN 89 69 A6 I/O Input terminal for crystal oscillator XT2
General-purpose digital I/O
P5.3/XT2OUT 90 70 A5 I/O Output terminal of crystal oscillator XT2
Test mode pin – Selects four wire JTAG operation.
TEST/SBWTCK(3) 91 71 D6 I Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated
General-purpose digital I/O
PJ.0/TDO(4) 92 72 B5 I/O JTAG test data output port
General-purpose digital I/O
PJ.1/TDI/TCLK(4) 93 73 A4 I/O JTAG test data input or test clock input
(3) Please refer to Bootstrap Loader (BSL) and JTAG Operation for usage with BSL and JTAG functions
(4) Please refer to JTAG Operation for usage with JTAG function.
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Table 3. TERMINAL FUNCTIONS (continued)
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ PN ZQW
General-purpose digital I/O
PJ.2/TMS(4) 94 74 D5 I/O JTAG test mode select
General-purpose digital I/O
PJ.3/TCK(4) 95 75 B4 I/O JTAG test clock
Reset input active low
RST/NMI/SBWTDIO(3) 96 76 A3 I/O Non-maskable interrupt input
Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated.
General-purpose digital I/O
P6.0/A0 97 77 D4 I/O Analog input A0 – ADC
General-purpose digital I/O
P6.1/A1 98 78 B3 I/O Analog input A1 – ADC
General-purpose digital I/O
P6.2/A2 99 79 A2 I/O Analog input A2 – ADC
General-purpose digital I/O
P6.3/A3 100 80 B2 I/O Analog input A3 – ADC
Reserved N/A N/A (5)
(5) G5, E8, F8, G8, H8, E7, H7, E6, H6, E5, F5, H5, C3 are reserved and should be connected to ground.
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Program Counter PC/R0
Stack Pointer SP/R1
Status Register SR/CG1/R2
Constant Generator CG2/R3
General-Purpose Register R4
General-Purpose Register R5
General-Purpose Register R6
General-Purpose Register R7
General-Purpose Register R8
General-Purpose Register R9
General-Purpose Register R10
General-Purpose Register R11
General-Purpose Register R12
General-Purpose Register R13
General-Purpose Register R15
General-Purpose Register R14
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SHORT-FORM DESCRIPTION
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The
register-to-register operation execution time is one
cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator, respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data.
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Operating Modes
The MSP430 has one active mode and six software selectable low-power modes of operation. An interrupt event
can wake up the device from any of the low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
The following seven operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active
• Low-power mode 1 (LPM1)
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK and FLL loop control and DCOCLK are disabled
– DCO's dc-generator remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc generator is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc generator is disabled
– Crystal oscillator is stopped
– Complete data retention
• Low-power mode 4.5 (LPM4.5)
– Internal regulator disabled
– No data retention
– Wakeup from RST, digital I/O
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Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 4. Interrupt Sources, Flags, and Vectors
SYSTEM WORD
INTERRUPT SOURCE INTERRUPT FLAG PRIORITY
INTERRUPT ADDRESS
System Reset
Power-Up
External Reset
Watchdog Timeout, Password WDTIFG, KEYV (SYSRSTIV)(1) (2) Reset 0FFFEh 63, highest
Violation
Flash Memory Password Violation
PMM Password Violation
System NMI SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
PMM VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, (Non)maskable 0FFFCh 62
Vacant Memory Access JMBOUTIFG (SYSSNIV)(1)
JTAG Mailbox
User NMI
NMI NMIIFG, OFIFG, ACCVIFG (SYSUNIV)(1) (2) (Non)maskable 0FFFAh 61
Oscillator Fault
Flash Memory Access Violation
TB0 TBCCR0 CCIFG0 (3) Maskable 0FFF8h 60
TBCCR1 CCIFG1 ... TBCCR6 CCIFG6,
TB0 Maskable 0FFF6h 59
TBIFG (TBIV)(1) (3)
Watchdog Timer_A Interval Timer WDTIFG Maskable 0FFF4h 58
Mode
USCI_A0 Receive/Transmit UCA0RXIFG, UCA0TXIFG (UCA0IV)(1) (3) Maskable 0FFF2h 57
USCI_B0 Receive/Transmit UCB0RXIFG, UCB0TXIFG (UCAB0IV)(1) (3) Maskable 0FFF0h 56
ADC12_A ADC12IFG0 ... ADC12IFG15 (ADC12IV)(1) (3) Maskable 0FFEEh 55
TA0 TA0CCR0 CCIFG0(3) Maskable 0FFECh 54
TA0CCR1 CCIFG1 ... TA0CCR4 CCIFG4,
TA0 Maskable 0FFEAh 53
TA0IFG (TA0IV)(1) (3)
USCI_A2 Receive/Transmit UCA2RXIFG, UCA2TXIFG (UCA2IV)(1) (3) Maskable 0FFE8h 52
USCI_B2 Receive/Transmit UCB2RXIFG, UCB2TXIFG (UCB2IV)(1) (3) Maskable 0FFE6h 51
DMA DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)(1) (3) Maskable 0FFE4h 50
TA1 TA1CCR0 CCIFG0(3) Maskable 0FFE2h 49
TA1CCR1 CCIFG1 ... TA1CCR2 CCIFG2,
TA1 Maskable 0FFE0h 48
TA1IFG (TA1IV)(1) (3)
I/O Port P1 P1IFG.0 to P1IFG.7 (P1IV)(1) (3) Maskable 0FFDEh 47
USCI_A1 Receive/Transmit UCA1RXIFG, UCA1TXIFG (UCA1IV)(1) (3) Maskable 0FFDCh 46
USCI_B1 Receive/Transmit UCB1RXIFG, UCB1TXIFG (UCB1IV)(1) (3) Maskable 0FFDAh 45
USCI_A3 Receive/Transmit UCA3RXIFG, UCA3TXIFG (UCA3IV)(1) (3) Maskable 0FFD8h 44
USCI_B3 Receive/Transmit UCB3RXIFG, UCB3TXIFG (UCB3IV)(1) (3) Maskable 0FFD6h 43
I/O Port P2 P2IFG.0 to P2IFG.7 (P2IV)(1) (3) Maskable 0FFD4h 42
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RTC_A Maskable 0FFD2h 41
RT0PSIFG, RT1PSIFG (RTCIV)(1) (3)
0FFD0h 40
Reserved Reserved(4) ⋮ ⋮
0FF80h 0, lowest
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(3) Interrupt flags are located in the module.
(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, it is recommended to reserve these locations.
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Memory Organization
MSP430F5419A MSP430F5436A MSP430F5438A
MSP430F5418A MSP430F5435A MSP430F5437A
Memory (flash) Total Size 128 KB 192 KB 256 KB
Main: interrupt vector Flash 00FFFFh–00FF80h 00FFFFh–00FF80h 00FFFFh–00FF80h
Main: code memory Flash 025BFFh–005C00h 035BFFh–005C00h 045BFFh–005C00h
Bank 3 N/A 23 KB 64 KB
035BFFh–030000h 03FFFFh–030000h
Bank 2 23 KB 64 KB 64 KB
025BFFh–020000h 02FFFFh–020000h 02FFFFh–020000h
Main: code memory Bank 1 64 KB 64 KB 64 KB
01FFFFh–010000h 01FFFFh–010000h 01FFFFh–010000h
Bank 0 41 KB 41 KB 64 KB
00FFFFh–005C00h 00FFFFh–005C00h 045BFFh–040000h
00FFFFh–005C00h
Size 16 KB 16 KB 16 KB
Sector 3 4 KB 4 KB 4 KB
005BFFh–004C00h 005BFFh–004C00h 005BFFh–004C00h
Sector 2 4 KB 4 KB 4 KB
RAM 004BFFh–003C00h 004BFFh–003C00h 004BFFh–003C00h
Sector 1 4 KB 4 KB 4 KB
003BFFh–002C00h 003BFFh–002C00h 003BFFh–002C00h
Sector 0 4 KB 4 KB 4 KB
002BFFh–001C00h 002BFFh–001C00h 002BFFh–001C00h
Info A 128 B 128 B 128 B
0019FFh–001980h 0019FFh–001980h 0019FFh–001980h
Info B 128 B 128 B 128 B
00197Fh–001900h 00197Fh–001900h 00197Fh–001900h
Information memory
(flash) Info C 128 B 128 B 128 B
0018FFh–001880h 0018FFh–001880h 0018FFh–001880h
Info D 128 B 128 B 128 B
00187Fh–001800h 00187Fh–001800h 00187Fh–001800h
BSL 3 512 B 512 B 512 B
0017FFh–001600h 0017FFh–001600h 0017FFh–001600h
BSL 2 512 B 512 B 512 B
0015FFh–001400h 0015FFh–001400h 0015FFh–001400h
Bootstrap loader (BSL)
memory (Flash) BSL 1 512 B 512 B 512 B
0013FFh–001200h 0013FFh–001200h 0013FFh–001200h
BSL 0 512 B 512 B 512 B
0011FFh–001000h 0011FFh–001000h 0011FFh–001000h
Size 4KB 4KB 4KB
Peripherals 000FFFh–000000h 000FFFh–000000h 000FFFh–000000h
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Bootstrap Loader (BSL)
The BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the
device memory via the BSL is protected by an user-defined password. Usage of the BSL requires four pins as
shown in Table 5. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK
pins. For complete description of the features of the BSL and its implementation, see the MSP430 Memory
Programming User's Guide, literature number SLAU265.
Table 5. BSL Pin Requirements and Functions
DEVICE SIGNAL BSL FUNCTION
RST/NMI/SBWTDIO Entry sequence signal
TEST/SBWTCK Entry sequence signal
P1.1 Data transmit
P1.2 Data receive
VCC Power supply
VSS Ground supply
JTAG Operation
JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430
development tools and device programmers. The JTAG pin requirements are shown in Table 6. For further
details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's
Guide, literature number SLAU278.
Table 6. JTAG Pin Requirements and Functions
DEVICE SIGNAL DIRECTION FUNCTION
PJ.3/TCK IN JTAG clock input
PJ.2/TMS IN JTAG state control
PJ.1/TDI/TCLK IN JTAG data input/TCLK input
PJ.0/TDO OUT JTAG data output
TEST/SBWTCK IN Enable JTAG pins
RST/NMI/SBWTDIO IN External reset
VCC Power supply
VSS Ground supply
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface.
Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire
interface pin requirements are shown in Table 7. For further details on interfacing to development tools and
device programmers, see the MSP430 Hardware Tools User's Guide, literature number SLAU278.
Table 7. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL DIRECTION FUNCTION
TEST/SBWTCK IN Spy-Bi-Wire clock input
RST/NMI/SBWTDIO IN, OUT Spy-Bi-Wire data input/output
VCC Power supply
VSS Ground supply
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Flash Memory
The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the
flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually. Segments A to D are also called information memory.
• Segment A can be locked separately.
RAM Memory
The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage,
however all data is lost. Features of the RAM memory include:
• RAM memory has n sectors. The size of a sector can be found in Memory Organization.
• Each sector 0 to n can be complete disabled; however, data retention is lost.
• Each sector 0 to n automatically enters low-power retention mode when possible.
• For devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required.
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Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x5xx Family User's Guide, literature number
SLAU208.
Digital I/O
There are up to ten 8-bit I/O ports implemented: For 100-pin options, P1 through P10 are complete. P11 contains
three individual I/O ports. For 80-pin options, P1 through P7 are complete. P8 contains seven individual I/O ports.
P9 through P11 do not exist. Port PJ contains four individual I/O ports, common to all devices.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Pullup or pulldown on all ports is programmable.
• Drive strength on all ports is programmable.
• Edge-selectable interrupt and LPM4.5 wakeup input capability is available for all bits of ports P1 and P2.
• Read/write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise (P1 through P11) or word-wise in pairs (PA through PF).
Oscillator and System Clock
The clock system in the MSP430x5xx family of devices is supported by the Unified Clock System (UCS) module
that includes support for a 32-kHz watch crystal oscillator (XT1 LF mode), an internal very-low-power
low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an integrated internal
digitally controlled oscillator (DCO), and a high-frequency crystal oscillator (XT1 HF mode or XT2). The UCS
module is designed to meet the requirements of both low system cost and low power consumption. The UCS
module features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator,
stabilizes the DCO frequency to a programmable multiple of the selected FLL reference frequency. The internal
DCO provides a fast turn-on clock source and stabilizes in less than 5 µs. The UCS module provides the
following clock signals:
• Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal, a high-frequency crystal, the internal
low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitally controlled
oscillator DCO.
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by
same sources made available to ACLK.
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
Power Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains
programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor
(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is
implemented to provide the proper internal reset signal to the device during power-on and power-off. The
SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply
voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not
automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.
Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs operations with
32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations.
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MSP430F543xA, MSP430F541xA
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SLAS655B –JANUARY 2010–REVISED OCTOBER 2010
Real-Time Clock (RTC_A)
The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated
real-time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers
that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Calendar
mode integrates an internal calendar which compensates for months with less than 31 days and includes leap
year correction. The RTC_A also supports flexible alarm functions and offset-calibration hardware.
Watchdog Timer (WDT_A)
The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
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