11/8/04
Page 1 of 11
© 2003 Fairchild Semiconductor Corporation
AC/DC TO LOGIC INTERFACE
OPTOCOUPLER
HCPL-3700
DESCRIPTION
The HCPL-3700 voltage/current threshold detection optocoupler consists of an
AlGaAs LED connected to a threshold sensing input buffer IC which are optically
coupled to a high gain darlington output. The input buffer chip is capable of con-
trolling threshold levels over a wide range of input voltages with a single resistor.
The output is TTL and CMOS compatible.
FEATURES
• AC or DC input
• Programmable sense voltage
• Logic level compatibility
• Threshold guaranteed over temperature
(0°C to 70°C)
• Optoplanar™ construction for high
common mode immunity
• UL recognized (file # E90700)
APPLICATIONS
• Low voltage detection
• 5 V to 240 V AC/DC voltage sensing
• Relay contact monitor
• Current sensing
• Microprocessor Interface
• Industrial controls
ABSOLUTE MAXIMUM RATINGS
(No derating required up to 70°C)
Parameter Symbol Value Units
Storage Temperature T
STG
-55 to +125 °C
Operating Temperature T
OPR
-40 to +85 °C
Lead Solder Temperature T
SOL
260 for 10 sec °C
EMITTER
Average
I
IN
50 (MAX)
mAInput Current Surge 3 ms, 120 Hz Pulse Rate 140 (MAX)
Transient 10 µs, 120 Hz Pulse Rate 500 (MAX)
Input Voltage (Pins 2-3) V
IN
-0.5 (MIN) V
Input Power Dissipation (Note 1) P
IN
230 (MAX) mW
Total Package Power Dissipation (Note 2) P
T
305 (MAX) mW
DETECTOR
Output Current (Average) (Note 3) I
O
30 (MAX) mA
Supply Voltage (Pins 8-5) V
CC
-0.5 to 20 V
Output Voltage (Pins 6-5) V
O
-0.5 to 20 V
Output Power Dissipation (Note 4) P
O
210 (MAX) mW
8
8
1
8
1
1
TRUTH TABLE
(Positive Logic)
A 0.1 µF bypass capacitor
must be connected between
pins 8 and 5.
Input Output
HL
LH
1
2
3
45
8
6
7
AC
DC+
DC-
AC GND
V
NC
VO
CC
A
C/
D
C
P
O
WE
R
L
OG
I
C
R
X
H
C
PL-
3
7
00
G
ND
1
G
ND
2
AC/DC TO LOGIC INTERFACE
OPTOCOUPLER
HCPL-3700
11/8/04
Page 2 of 11
© 2003 Fairchild Semiconductor Corporation
ELECTRICAL CHARACTERISTICS
(T
A
= 0°C to 70°C Unless otherwise specified)
Parameter Test Conditions Symbol Min Typ Max Unit
Input Threshold Current (V
IN
= V
TH+
, V
CC
= 4.5 V) I
TH+
1.96 2.4 3.11 mA
(V
O
= 0.4 V, I
O
≥
4.2 mA) (Note 5) I
TH-
1.00 1.2 1.62 mA
Input
Threshold
Voltage
DC
(Pins 2,3)
(V
IN
= V
2
- V
3
, Pins 1 & 4 Open)
(V
CC
= 4.5 V, V
O
= 0.4 V)
(Note 5) (I
O
≥
4.2 mA)
V
TH+
3.35 3.8 4.05 V
(V
IN
= V
2
- V
3
, Pins 1 & 4 Open)
(V
CC
= 4.5 V, V
O
= 2.4 V)
(Note 5) (I
O
≥
100 µA)
V
TH-
2.01 2.5 2.86 V
AC
(Pins 1,4)
|V
IN
= V
1
- V
4
|
(Pins 2 & 3 Open)
(V
CC
= 4.5 V, V
O
= 0.4 V)
(Note 5) (I
O
≥
4.2 mA)
V
TH+
4.23 5.0 5.50 V
|V
IN
= |V
1
- V
4
|
(Pins 2 & 3 Open)
(V
CC
= 4.5 V, V
O
= 2.4 V)
(Note 5) (I
O
≤
100 µA)
V
TH-
2.87 3.7 4.20 V
Hysteresis (I
HYS
= I
TH+
- I
TH-
)I
HYS
1.2 mA
(V
HYS
= V
TH+
- V
TH-
)V
HYS
1.3 V
Input Clamp Voltage
(V
IHC1
= V
2
- V
3
, V
3
= GND)
(I
IN
= 10 mA, Pins 1 & 4
Connected to Pin 3)
V
IHC1
5.4 6.3 6.6 V
(V
IHC2
= |V
1
- V
4
|)
(|I
IN
| = 10 mA)
(Pins 2 & 3 Open)
V
IHC2
6.1 7.0 7.3 V
(V
IHC3
= V
2
- V
3
, V
3
= GND)
(I
IN
= 15 mA; Pins 1 & 4 Open) V
IHC3
12.5 13.4 V
(V
ILC
= V
2
- V
3
, V
3
= GND)
(I
IN
= -10 mA) V
ILC
-0.75 V
Input Current (V
IN
= V
2
- V
3
= 5.0 V)
(Pins 1 & 4 Open) I
IN
3.0 3.7 4.4 mA
Bridge Diode
Forward Voltage
(I
IN
= 3 mA) V
D1,2
0.65 V
(I
IN
= 3 mA) V
D3,4
0.65 V
Logic Low Output Voltage (V
CC
= 4.5 V; I
OL
= 4.2 mA)
(Note 5) V
OL
0.04 0.4 V
Logic High Output Current (Note 5) (V
OH
= V
CC
= 18 V) I
OH
100 µA
Logic Low Supply Current (V
2
- V
3
= 5.0 V; V
O
= Open)
(V
CC
= 5 V) I
CCL
1.0 4 mA
Logic High Supply Current (V
CC
= 18 V; V
O
= Open) I
CCH
0.01 4 µA
Input Capacitance (f = 1 MHz; V
IN
= 0V)
(Pins 2 & 3, Pins 1 & 4 Open) C
IN
50 pF
11/8/04
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© 2003 Fairchild Semiconductor Corporation
AC/DC TO LOGIC INTERFACE
OPTOCOUPLER
HCPL-3700
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Max Units
Supply Voltage VCC 218V
Operating Temperature TA070°C
Operating Frequency f 0 4 kHz
SWITCHING CHARACTERISTICS (TA = 25°C, VCC = 5 V Unless otherwise specified)
AC Characteristics Test Conditions Symbol Min Typ Max Unit
Propagation Delay Time
(to Output Low Level)
(RL = 4.7 kΩ, CL = 30 pF)
(Note 6) TPHL 6.0 15 µs
Propagation Delay Time
(to Output High Level)
(RL = 4.7 kΩ, CL = 30 pF)
(Note 6) TPLH 25.0 40 µs
Output Rise Time (10-90%) (RL = 4.7 kΩ, CL = 30 pF) tr45 µs
Output Fall Time (90-10%) (RL = 4.7 kΩ, CL = 30 pF) tf0.5 µs
Common Mode Transient Immunity
(at Output High Level)
(IIN = 0 mA, RL = 4.7 kΩ)
(VO min = 2.0 V, VCM = 1400 V)
(Notes 7,8)
|CMH| 4000 V/µs
Common Mode Transient Immunity
(at Output Low Level)
(IN = 3.11 mA,RL = 4.7 kΩ)
(VO max = 0.8 V, VCM = 140 V)
(Notes 7,8)
|CML| 600 V/µs
PACKAGE CHARACTERISTICS (TA = 0°C to 70°C Unless otherwise specified)
Characteristics Test Conditions Symbol Min Typ Max Unit
Withstand Insulation Voltage
(Relative humidity < 50%)
(TA = 25°C, t = 1 min)
(Notes 9,10)
VISO 2500 VRMS
Resistance (input to output) (Note 9) (VIO = 500 Vdc) RI-O 1012 Ω
Capacitance (input to output) (f = 1 MHz, VIO = 0 Vdc) CI-O 0.6 pF
AC/DC TO LOGIC INTERFACE
OPTOCOUPLER
HCPL-3700
11/8/04
Page 4 of 11
© 2003 Fairchild Semiconductor Corporation
1. Derate linearly above 70°C free-air temperature at a rate of 1.8 mW/°C.
2. Derate linearly above 70°C free-air temperature at a rate of 2.5 mW/°C.
3. Derate linearly above 70°C free-air temperature at a rate of 0.6 mA/°C.
4. Derate linearly above 70°C free-air temperature at a rate of 1.9 mW/°C.
5. Logic low output level at pin 6 occurs when VIN≥VTH+ and when VIN>VTH- once VIN exceeds VTH+. Logic high output level at pin
6 occurs when VIN≤VTH- and when VIN<VTH+ once VIN decreases below VTH-.
6. TPHL propagation delay is measured from the 2.5 V level of the leading edge of a 5.0 V input pulse (1 µs rise time) to the 1.5 V
level on the leading edge of the output pulse. TPLH propagation delay is measured on the trailing edges of the input and output
pulse. (Refer to Fig. 9)
7. Common mode transient immunity in logic high level is the maximum tolerable (positive) dVcm/dt on the leading edge of the
common mode pulse signal VCM, to assure that the output will remain in a logic high state (i.e., VO>2.0 V). Common mode
transient immunity in logic low level is the maximum tolerable (negative) dVcm/dt on the trailing edge of the common mode
pulse signal, VCM, to assure that the output will remain in a logic low state (i.e., VO<0.8 V). (Refer to Fig.10)
8. In applications where dVcm/dt may exceed 50,000 V/µs (Such as static discharge), a series resistor, RCC, should be included to
protect the detector chip from destructive surge currents. The recommended value for RCC is 240 V per volt of allowable drop
in VCC (between pin 8 and VCC) with a minimum value of 240 Ω.
9. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted together.
10. The 2500 VRMS/1 min. capability is validated by a 3.0 kVRMS/1 sec. dielectric voltage withstand test.
11. AC voltage is instantaneous voltage for VTH+ & VTH-.
12. All typicals at TA = 25°C, VCC = 5 V unless otherwise specified.
NOTES
11/8/04
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© 2003 Fairchild Semiconductor Corporation
AC/DC TO LOGIC INTERFACE
OPTOCOUPLER
HCPL-3700
TYPICAL PERFORMANCE CURVES
Fig. 1 Logic Low Supply Current vs. Operating Supply Voltage
VCC - OPERATING SUPPLY VOLTAGE (V)
4 6 8 10 12 14 16 18 20
ICCL - LOGIC LOW SUPPLY CURRENT (mA)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Fig. 2 Input Current vs. Input Voltage
VIN - INPUT VOLTAGE (V)
02468101214
IIN - INPUT CURRENT (mA)
-10
-5
0
5
10
15
20
25
30
35
40
45
50
DC (Pins 1,2 shorted together
pins 3,4 shorted together)
DC (Pins 1 & 4 Open)
AC (pins 2 & 3 Open)
Fig. 3 Input Current/Low Level Output Voltage
vs. Temperature
TA - TEMPERATURE (°C)
-40 -20 0 25 45 65 85
Input Current, IIN (mA)
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
4.2
VOL (mV)
0
10
20
30
40
50
60
70
80
90
100
110
120
Fig. 4 Current Threshold/Voltage Threshold
vs. Temperature
TA - TEMPERATURE (°C)
-40 -20 0 25 45 65 85
ITH(DC) - CURRENT THRESHOLD (mA)
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
VTH(DC) - VOLTAGE THRESHOLD (V)
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
4.2
VTH+
ITH+
VTH-
ITH-
IIN
VIN = 5.0 V
(PINS 2 and 3)
VCC = 5.0 V
VOL
V = 5.0 V
IOL = 4.2 mA
CC
Fig. 5 Propagation Delay vs. Temperature
TA - TEMPERATURE (°C)
-60 -40 -20 0 20 40 60 80 100
TP
- PROPAGATION DELAY (µs)
0
10
20
30
40
50
60
70
TPLH
TPHL
Fig. 6 Rise and Fall Time vs. Temperature
TA - TEMPERATURE (°C)
-40 -20 0 25 45 65 85
Tr - RISE TIME (µs)
Tf - FALL TIME (µs)
0
10
20
30
40
50
60
70
80
90
100
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Tf
Tr
AC/DC TO LOGIC INTERFACE
OPTOCOUPLER
HCPL-3700
11/8/04
Page 6 of 11
© 2003 Fairchild Semiconductor Corporation
Fig. 8 External Threshold Characteristics V+/V- vs. Rx
RX - EXTERNAL SERIES RESISTOR (KΩ)
0 40 80 120 160 200 240
V+/V- -EXTERNAL THRESHOLD VOLTAGE (V)
0
50
100
150
200
250
300
Fig. 7 Logic High Supply Current
vs. Temperature
TA - TEMPERATURE (°C)
-60 -40 -20 0 20 40 60 80 100
I
CCH
- LOGIC HIGH SUPPLY CURRENT (nA)
1
10
100
1000
V+ (AC) V- (AC)
V- (DC)
V+ (DC)
VO = OPEN
V
IIN
CC
= 0 mA
= 18 V
11/8/04
Page 7 of 11
© 2003 Fairchild Semiconductor Corporation
AC/DC TO LOGIC INTERFACE
OPTOCOUPLER
HCPL-3700
5
6
7
8
3
4
2
1
Z = 50
tr = 5ns
Generator
Pulse
OΩ
.1uf
bypass
O
(V )
+5V
RL
Output PHL
tPLH
t
5V
2.5V
IN
(V )
Input
(V )
Output
O
1.5 V
90%
AC
DC+
DC-
AC GND
V
V
O
CC
AC
DC-
DC+
AC
4
3
2
1
Output
O
GND
V
5
6(V )
R
bypass
.1uf
CCV
7
8
L
O
V
FF
IIN
A
B
+5V
C **
L
* SEE NOTE 8
R *
CC
+
Pulse Gen
CM
V
-
** C IS 30 pF, WHICH INCLUDES PROBE
AND STRAY WIRING CAPACITANCE
L
90%
10% 10%
r
tt
f
0V
V
O
OL
V
Switching Pos. (A)
I = 0 mA
VO
VCM
Switching Pos. (B)
I = 3.11 mA
V (Max)
V (Min)
O
O
IN
IN
CML
H
O
V VOL
CM
V
VCML
H
CM
5V
5V
V
Pulse Amplitude = 50 V
Pulse Width = 1 ms
f = 100 Hz
T = T = 1.0 µs (10 - 90%)
IN
rf
Fig. 9. Switching Test Circuit
Fig. 10. Test Circuit for Common Mode Transient Immunity and Typical Waveforms
AC/DC TO LOGIC INTERFACE
OPTOCOUPLER
HCPL-3700
11/8/04
Page 8 of 11
© 2003 Fairchild Semiconductor Corporation
NOTE
All dimensions are in inches (millimeters)
Package Dimensions (Through Hole)
Package Dimensions (0.4"Lead Spacing)
0.200 (5.08)
0.140 (3.55)
0.100 (2.54) TYP
0.022 (0.56)
0.016 (0.41)
0.020 (0.51) MIN
0.390 (9.91)
0.370 (9.40)
0.270 (6.86)
0.250 (6.35)
3
0.070 (1.78)
0.045 (1.14)
241
56 78
0.300 (7.62)
TYP
0.154 (3.90)
0.120 (3.05)
0.016 (0.40)
0.008 (0.20)
15° MAX
PIN 1
ID.
SEATING PLANE
0.200 (5.08)
0.140 (3.55)
0.100 (2.54) TYP
0.022 (0.56)
0.016 (0.41)
0.004 (0.10) MIN
0.390 (9.91)
0.370 (9.40)
0.270 (6.86)
0.250 (6.35)
3
0.070 (1.78)
0.045 (1.14)
241
56 78
0.400 (10.16)
TYP
0.154 (3.90)
0.120 (3.05)
0.016 (0.40)
0.008 (0.20)
0° to 15°
PIN 1
ID.
SEATING PLANE
Package Dimensions (Surface Mount)
Lead Coplanarity : 0.004 (0.10) MAX
0.270 (6.86)
0.250 (6.35)
0.390 (9.91)
0.370 (9.40)
0.022 (0.56)
0.016 (0.41)
0.100 (2.54)
TYP
0.020 (0.51)
MIN
0.070 (1.78)
0.045 (1.14)
0.300 (7.62)
TYP
0.405 (10.30)
MIN
0.315 (8.00)
MIN
0.045 [1.14]
32 14
5678
0.016 (0.41)
0.008 (0.20)
PIN 1
ID.
11/8/04
Page 9 of 11
© 2003 Fairchild Semiconductor Corporation
AC/DC TO LOGIC INTERFACE
OPTOCOUPLER
HCPL-3700
MARKING INFORMATION
ORDERING INFORMATION
Option
Order
Entry
Identifier
Description
S .S Surface Mount Lead Bend
SD .SD Surface Mount; Tape and reel
W .W 0.4” Lead Spacing
1
2
6
43 5
Definitions
1 Fairchild logo
2 Device number
3VDE mark (Note: Only appears on parts ordered with VDE
option – See order entry table)
4 Two digit year code, e.g., ‘03’
5 Two digit work week ranging from ‘01’ to ‘53’
6 Assembly package code
3700
T1YYXXV
AC/DC TO LOGIC INTERFACE
OPTOCOUPLER
HCPL-3700
11/8/04
Page 10 of 11
© 2003 Fairchild Semiconductor Corporation
QT Carrier Tape Specifications (“D” Taping Orientation)
Reflow Profile
0.30 ±0.05
4.0 ±0.1
4.0 ±0.1
Ø1.55 ±0.05
Ø1.6 ±0.1
1.75 ±0.10
12.0 ±0.1
10.30 ±0.20
13.2 ±0.2
0.1 MAX
User Direction of Feed
4.90 ±0.20
16.0 ±0.3
7.5 ±0.1
10.30 ±0.20
• Peak reflow temperature: 225 C (package surface temperature)
• Time of temperature higher than 183 C for 60–150 seconds
• One time soldering reflow is recommended
215 C, 10–30 s
225 C peak
Time (Minute)
0
300
250
200
150
100
50
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5
Temperature (°C)
Time above 183 C, 60–150 sec
Ramp up = 3 C/sec
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
11/8/04
Page 11 of 11
© 2003 Fairchild Semiconductor Corporation
AC/DC TO LOGIC INTERFACE
OPTOCOUPLER
HCPL-3700
