VN2222 VN2224 N-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information BVDSS / BVDGS RDS(ON) (max) ID(ON) (min) 220V 1.25 240V 1.25 Order Number / Package TO-92 20-Pin C-Dip 5.0A - VN2222NC 5.0A VN2224N3 - 7 Advanced DMOS Technology High Reliability Devices These enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertex's well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally-induced secondary breakdown. See pages 5-4 and 5-5 for MILITARY STANDARD Process Flows and Ordering Information. Features Free from secondary breakdown Low power drive requirement Ease of paralleling Supertex's vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Low CISS and fast switching speeds Excellent thermal stability Integral Source-Drain diode Package Options High input impedance and high gain Applications 19 3 18 4 17 D1 5 16 D2 6 15 D3 7 14 D4 8 13 NC S 9 12 S S 10 11 S S Amplifiers G1 Switches G2 Power supply circuits G3 Drivers (relays, hammers, solenoids, lamps, memories, displays, bipolar transistors, etc.) G4 S Absolute Maximum Ratings Drain-to-Source Voltage BVDSS Drain-to-Gate Voltage BVDGS Gate-to-Source Voltage 20V Soldering Temperature* 20 2 S Converters Operating and Storage Temperature 1 S Motor controls SGD TO-92 -55C to +150C top view 20-pin Ceramic DIP 300C Note: See Package Outline section for dimensions. * Distance of 1.6 mm from case for 10 seconds. 7-203 S S NC VN2222/VN2224 Thermal Characteristics Package ID (continuous)* ID (pulsed) Power Dissipation @ TC = 25C C/W C/W ja IDR* IDRM 0.9A 5.0A 1.0W 125 170 0.9A 5.0A TO-92 jc * ID (continuous) is limited by max rated Tj. Electrical Characteristics (@ 25C unless otherwise specified) Parameter BVDSS Min Drain-to-Source Breakdown Voltage VN2224 240 VN2222 220 VGS(th) Gate Threshold Voltage VGS(th) Change in VGS(th) with Temperature IGSS Gate Body Leakage IDSS Zero Gate Voltage Drain Current 1.0 ON-State Drain Current ID(ON) Typ Max VGS = 0V, ID = 5mA V VGS = VDS, ID = 5mA mV/C VGS = VDS, ID = 5mA -4 -5 1 100 nA VGS = 20V, VDS = 0V 50 A VGS = 0V, VDS = Max Rating 5 mA VGS = 0V, VDS = 0.8 Max Rating TA = 125C 2 A VGS = 5V, VDS = 25V VGS = 10V, VDS = 25V 10 Static Drain-to-Source ON-State Resistance 1.0 1.5 0.9 1.25 RDS(ON) Change in RDS(ON) with Temperature 1.0 1.4 GFS Forward Transconductance CISS Input Capacitance COSS 1.0 Conditions V 3.0 5 RDS(ON) Unit VGS = 10V, ID = 2A %/C VGS = 10V, ID = 2A VDS = 25V, ID = 2A 2.2 300 350 Common Source Output Capacitance 85 150 CRSS Reverse Transfer Capacitance 20 35 td(ON) Turn-ON Delay Time 6 15 tr Rise Time 16 25 td(OFF) Turn-OFF Delay Time 65 90 tf Fall Time 30 60 VSD Diode Forward Voltage Drop 0.8 1.0 trr Reverse Recovery Time 500 VGS = 5V, ID = 2A Symbol pF VGS = 0V, VDS = 25V f = 1 MHz ns VDD = 25V ID = 2A RGEN = 10 V VGS = 0V, ISD = 100mA ns VGS = 0V, ISD = 1A Notes: 1. All D.C. parameters 100% tested at 25C unless otherwise stated. (Pulse test: 300s pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. Switching Waveforms and Test Circuit VDD RL 10V 90% PULSE GENERATOR INPUT 0V 10% t(ON) td(ON) t(OFF) tr td(OFF) OUTPUT Rgen tF D.U.T. VDD 10% INPUT 10% OUTPUT 0V 90% 90% 7-204 VN2222/VN2224 Typical Performance Curves Output Characteristics Saturation Characteristics 10 10 VGS = 10V 8V 6V 8 8 ID (amperes) ID (amperes) VGS = 10V 6 4V 4 2 6 4V 4 2 3V 3V 0 8V 6V 0 0 10 20 30 40 0 50 2 4 6 8 10 VDS (volts) VDS (volts) Transconductance vs. Drain Current Power Dissipation vs. Case Temperature 5 10 VDS = 25V TA = -55C 3 PD (watts) GFS (siemens) 4 2 5 TA = 25C 1 TA = 125C TO-92 0 0 0 5 0 10 25 50 ID (amperes) 125 100 150 Thermal Response Characteristics Maximum Rated Safe Operating Area 10 Thermal Resistance (normalized) 1.0 1 ID (amperes) 75 TC (C) 0.1 TO-92 (DC) 0.01 0.8 0.6 0.4 TO-92 TC = 25C PD = 1W 0.2 TC = 25C 0.001 1 10 100 0 0.001 1000 VDS (volts) 0.01 0.1 tp (seconds) 7-205 1 10 7 VN2222/VN2224 Typical Performance Curves BVDSS Variation with Temperature On-Resistance vs. Drain Current 5 1.1 V GS = 5V RDS(ON) (ohms) BVDSS (normalized) 4 1.0 3 2 VGS = 10V 1 0.9 0 -50 0 50 100 0 150 2 4 6 8 10 ID (amperes) Tj (C) Transfer Characteristics V(th) and RDS Variation with Temperature 2.4 1.4 10 VDS = 25V VGS(th) (normalized) ID (amperes) 25C 125C 5 2.0 RDS @ 10V, 2A 1.0 1.6 0.8 1.2 0.6 0.8 0.4 0 0 2 4 6 8 10 0.4 -50 0 50 VGS (volts) 100 150 Tj (C) Capacitance vs. Drain-to-Source Voltage Gate Drive Dynamic Characteristics 400 10 f = 1MHz VGS (volts) C (picofarads) 200 100 VDS = 10V 8 CISS 300 COSS VDS = 40V 6 733 pF 4 2 300 pF CRSS 0 0 0 10 20 30 40 0 2 4 6 QG (nanocoulombs) VDS (volts) 7-206 8 10 RDS(ON) (normalized) Vth @ 5mA 1.2 TA = -55C Package Outline D 0.760 0.005 B1 0.065 0.003 S 0.080 0.005 14 0.250 0.008 8 E 1 0.165 0.005 A 0.035 0.005 7 Q 0.130 0.015 = 0 - 15 L 0.100 TYP. e1 B 0.018 0.002 14-Lead Ceramic Dual-In Line Package (C) Note: Circle (e.g. B ) indicates JEDEC Reference. C E1 0.310 0.010 0.011 0.002 CH06C Table Page 1 of 1 MainSupertex.gif Products.gif Selector_Side.gif ch06c.gif RDS(ON) Device Number BVDSS min (V) max () CISS typ (pf) VN0300 30 1.2 190 *3 VN0104 40 3.0 35 * VN3205 50 0.3 220 * VN0106 60 3.0 55 * VN2106 60 4.0 35 * 2N7000 60 5.0 60 *2 VN10K 60 5.0 60 * 2N7002 60 7.5 50 2N7008 60 7.5 50 *2 VN2222L 60 7.5 60 *3 VN13064 60 8.0 25 * VN2210 100 0.35 300 * VN2110 100 4.0 35 VN13104 100 8.0 25 VN2222 220 1.25 300 VN2224 240 1.25 300 * VN0550 500 60.0 45 * VN2450 500 13.0 150 * * VN2460 600 20.0 150 * * SOT-23 K1 TO-39 N2 TO-92 N3 Quad1 N6 SOT-89 N8 * * * * * * * Add package suffix for complete part number, e.g., VN0104N3 is VN0104 in a TO-92 package. Notes: 1. Package options are defined on individual data sheets. 2. No package suffix required. 3. Use package suffix "L" instead of "N3". 4. Not recommended for new designs. [Home] file://F:\export\projects\bitting2\imaging\BITTING\mail_pdf\recode\ch06c_table.htm 1/23/01