74HC/HCT173 MSI QUAD D-TYPE FLIP-FLOP; POSITIVE-EDGE TRIGGER; 3-STATE FEATURES : TYPICAL Gated input enable for hold (do SYMBOL | PARAMETER CONDITIONS UNIT nothing) mode HC HCT @ Gated output enable control ion del e tri . : propagation delay Edge-triggered D-type register teHL/ CP to On - 7 7 as @ Asynchronous master reset tPLH C.= 15 pF a MR to Q, 13 17 ns @ Output capability: bus driver Veco =5V Icc category: MSI tmax maximum clock frequency 88 88 MHz GENERAL DESCRIPTION Cy input capacitance 3.5 3.5 pF The 74HC/HCT173 are high-speed dissipati Si-gate CMOS devices and are pin Cep capacitance per flip-flop notes 1 and 2 20 i) pF compatible with low power Schottky TTL (LSTTL}. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT173 are 4-bit paralle! load registers with clock enable control, 3-state buffered outputs (Qg to Q3)} and master reset (MR}. When the two data enable inputs (E 1 and E3) are LOW, the data on the Dy inputs is loaded into the register synchronously with the LOW-to-HIGH clock (CP) transition, When one or both E, inputs are HIGH one set-up time prior to the LOW-to-HIGH clock transition, the register will retain the previous data. Data inputs and clock enable inputs are fully edge-triggered and must be stable only one set-up time prior to the LOW-to-HIGH clock transition. The master reset input (MR) is an active HIGH asynchronous input. When MR is GNO =0 V: Tamb =25 C; t, = t= Gns Notes 1. Cpp is used to determine the dynamic power dissipation (Pp in uW): Pp =Cpp x Vcc? x fj + (CL x Vcc? x fo) where: fj = input frequency in MHz CL output load capacitance in pF fo = output frequency in MHz Vcc supply voltage in V Z (CL x Vec? x fg) = sum of outputs 2. For HC the condition is Vj} = GND to Vcc For HCT the condition is V1 = GND to Vcc 1.5 V PACKAGE OUTLINES SEE PACKAGE INFORMATION SECTION PIN DESCRIPTION HIGH, all four flip-flops are reset (cleared) PIN NO. SYMBOL NAME AND FUNCTION independently of any other input condition. 1,2 OE, OE2 output enable input (active LOW) The 3-state output buffers are controlled 3.4.5.6 Qn to O 3-state flip-flop outputs by a 2-input NOR gate. When both output corn 0 3 : porop our 4 . d enable inputs (OE; and OE) are LOW, 7 ce clock input (LOW-to-HIGH, edge-triggered) the data in the register is presented to the 8 GND ground (0 V) Q, outputs. When one or both OE, inputs 9, 10 EE data enable inputs (active LOW) are HIGH, the outputs are forced to a high 1 F2 . p impedance OFF-state. The 3-state output 14,13, 12,11 | Dg to Dg data inputs buffers are completely independent of the 15 MR asynchronous master reset (active HIGH) register operation; the OE, transition does 1 V ositive supply volta not affect the clock and reset operations. 8 cc POSITIVE SUPPIY 9 oe, CI U [ve] Yeo ae, Ee Gl mA 14 13 12 i eB] [14] 80 4o Pa 91 % Oa Qa, 4 3] o; 10 Je) 173 7 cp Q2 ts] [2] O2 1 Pe) os Le] Da Ps ao ma % 4) 7 Oy ce[F| [10] E2 PPE td 7293637 3 4 5 6 GND Ce [9]}s 7293638 72936361 Fig. 1. Pin configuration. Fig. 2 Logic symbol. Fig. 3 IEC logic symbol. December 1990 36974HC/HCT173 Ms! FUNCTION TABLE INPUTS OUTPUTS REGISTER OPERATING MODES MR | CP {| Ey | Eo | Op | Op (register) reset (clear) H x xX x x L L t | ( L parallel load L t | [ h H L xX h x x Qn hold (no change) L xX x h Xx an 3-STATE BUFFER INPUTS OUTPUTS OPERATING MODES Qy (register) | GE, | GE2 | Aq | Ay] Q2/ a3 L L L Lik Jtete 7293838 read H L L H H H 4 Fig. 4 Functional diagram. : x H |X |/2 12/2 {2 disabled X x H z\z lz H = HIGH voltage jevel h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level | = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition q = lower case letters indicate the state of the referenced input (or output) one set-up time orior to the LOW-to-HIGH CP transition X = dont care Z = high impedance OF F-state t = LOW-to-HIGH CP transition Fig. 5 Logic diagram. pa} pb af oe Co) o at Lolcp fry Le FR2 Lolce rea cp Fra ar ah ah a Alo Ro Ro 8p wa >o e 3 Fo Qg Y Y 7293642 93 370 January 1986Quad D-type flip-flop; positive-edge trigger; 3-state 74HC/HCT173 MSI DC CHARACTERISTICS FOR 74HC For the OC characteristics see chapter HCMOS family characteristics, section Family specifications. Output capability: bus driver !oc category: MSi AC CHARACTERISTICS FOR 74HC GND =0V;t,= te = 6s; CL = 50 pF Tamb (C) TEST CONDITIONS 74HC ! SYMBOL | PARAMETER UNIT | Voc | WAVEFORMS +25 40 to +85 | 40 to +125 Vv min. | typ. | max. | min. | max. | min. | max. : 55 175 220 265 2.0 PHL | Propagation delay 20 | 35 44 53 |ns | 45 | Fig 6 | *PLH oon 16 | 30 a7 45 6.0 225 2.0 . 44 | 160 190 . tPHL propagation deiay 16 | 30 38 45 ns 4.5 Fig. 7 n 13. | 26 33 38 6.0 . 150 190 225 2.0 tp2H/ aatate ourput enabie time * 30 38 45 ns 45 Fig. 8 *PZL n t0.On 1s | 26 33 38 6.0 : : 52 150 1 225 2.0 tpH2/ State output disable time 19 | 30 oe 45 ns a5 | Fig.8 teLZ ;(OEn 10. On 15 | 26 33 38 6.0 t / 14 | 60 78 90 2.0 at output transition time 5 12 16 18 ns 4 Fig. 6 TLH 4 | 10 13 15 6.0 . 80 14 100 120 2.0 clack pulse width : tw 16 =| 5 20 24 ns 4.5 Fig. 6 HIGH or LOW 14 4 7 20 6.0 tw master reset pulse 18 [5 20 2 ns | 45 | Fig? width; HIGH 4 | 4 17 20 8.0 removal time 60 | -8 75 90 2.0 trem 12 | -3 15 18 ns 4.5 Fig. 7 MR to CP 10 | -2 13 15 6.0 set-up time 100 | 33 125 150 2.0 t 20 | 12 25 30 ns 45 { Fig 9 E, to CP 17 | 10 24 26 6.0 : 60 17 78 90 2.0 teu serup OP 2 (16 15 18 ns 45 Fig. 9 n fo 10 | 13 15 6.0 . Oo |-17 0 0 2.0 th ned time 0 |-8 0 0 ns 145 | Fig.9 n to CP o |-5 0 0 6.0 1 -11 1 1 2.0 hold time . th 1 -4 1 1 ns 4.5 Fig. 9 Dy to CP 1 |-3 1 1 6.0 . 6.0 | 26 4.8 4.0 2.0 fax maximum clock pulse 30 | 80 24 20 MHz 45 Fig. 6 requency 35 | 95 28 24 6.0 December 1990 371MSI 74HC/HCT173 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see chapter HCMOS family characteristics, section Family specifications. Output capability: bus driver {cc category: MSI Note to HCT types The value of additional quiescent supply current (Alcc) for a unit load of 1 is given in the family specifications. To determine Alcc per input, muitiply this value by the unit load coefficient shown in the table below. | | UNIT LOAD INPUT | COEFFICIENT GE}, OE2 | 0.50 MR 0.60 E1, Eo 0.40 Dn 0.25 cP 1.00 AC CHARACTERISTICS FOR 74HCT GND =OV;t,= ty =6ns; CL = 50 pF Tamb (C) TEST CONDITIONS 74HCT SYMBOL PARAMETER UNIT | Vcc | WAVEFORMS +25 ~40 to +85 | 40 to +125 Vv min.| typ. | max. | min.| max. | min. | max. putt "Pea, delay 20 | 40 50 60 | as 45 | Fig. 6 Propagation delay : tPHE MR to QO, 20 | 37 46 56 ns 45 Fig. 7 tezH/ 3-state output enable time : tPZL GE, to On 20 | 35 44 53 ns 45 Fig. 8 teHz/ 3-state output disable time . tPL2 ae, t0 On 19 | 30 38 45 ns 4.5 Fig. 8 TH output transition time 5 12 15 19 ns 4.5 Fig. 6 idth . w | Sane ule ie | 7 zo | | ns [45 | Fine master reset pulse . tw width; HIGH 15 | 6 19 22 ns 4.5 Fig. 7 trem mee 12 | -2 15 18 ns | 4.8 | Fig. 7 set-up time . tou E,, to CP 22 | 13 28 33 as 45 Fig. 9 set-up time i tgy Dy to CP 12 | 7 15 18 ns 45 | Fig. 9 hold time : . th E,, to CP 0 -6 0 0 ns 4.5 Fig. 9 hold time th Dn to CP o |-4 0 0 ns 45 Fig. 9 maximum clock pulse . fmax frequency 30 | 80 24 20 MHz | 4.5 | Fig.6 372 December 1990Quad D-type flip-flop; positive-edge trigger; 3-state AC WAVEFORMS 74HC/HCT173 MSI \ CP INPUT Q,, OUTPUT 7293040 Fig. 6 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the outout transition times and the maximum clock pulse frequency. MA INPUT Vay! wel tegen cP INPUT Vaal"? ae CL ae a, OUTPUT Val? 7293644 Fig. 7 Waveforms showing the master reset (MR) pulse width, the master reset to output (Q,,) propagation delays and the master reset to clock (CP) removal time. OUTFUT LOW-10- OFF OFF -to- LOW OuTPUT HIGH - to- OFF OFF -to-HIGH cutouts, i outpuls ___ outputs 7293830 snabied disabled enabled Fig. 8 Waveforms showing the 3-state enable and disable times. Uh, wl te | net Uy ie D, (NPUT cP INPUT 1EU376s Fig. 9 Waveforms showing the data set-up and hold times from input (E,, Dy) to clock (CP). Note to AC waveforms (1} HC > Vag = 50%; V, = GND to Vcc. HCT: Viy = 1.3V: V,_ = GND to 3V. Note to Fig. 9 The shaded areas indicate when the input is permitted to change for predictabie output performance. January 1986