Product Folder Sample & Buy Technical Documents Support & Community Tools & Software LM26LV, LM26LV-Q1 SNIS144G - JULY 2007 - REVISED SEPTEMBER 2016 LM26LV and LM26LV-Q1 1.6-V, WSON-6 Factory Preset Temperature Switch and Temperature Sensor 1 Features 3 Description * * * The LM26LV and LM26LV-Q1 are low-voltage, precision, dual-output, low-power temperature switches and temperature sensors. The temperature trip point (TTRIP) can be preset at the factory to any temperature in the range of 0C to 150C in 1C increments. Built-in temperature hysteresis (THYST) keeps the output stable in an environment of temperature instability. 1 * * * * * * * Low 1.6-V Operation Low Quiescent Current Latching Function: Device Can Latch the Over Temperature Condition Push-Pull and Open-Drain Temperature Switch Outputs Wide Trip Point Range of 0C to 150C Very Linear Analog VTEMP Temperature Sensor Output VTEMP Output Short-Circuit Protected Accurate Over -50C to 150C Temperature Range Excellent Power Supply Noise Rejection LM26LVQISD-130 and LM26LVQISD-135 are AEC-Q100 Qualified and are Manufactured on an Automotive Grade Flow: - Device Temperature Grade 0: -40C to 150C Ambient Operating Temperature Range - Device HBM ESD Classification Level 3 A - Device CDM ESD Classification Level C6 - Device MM ESD Classification Level M3 2 Applications * * * * * * Cell Phones and Wireless Transceivers Digital Cameras Battery Management Systems Automotive Applications Disk Drives Games and Appliances In normal operation the LM26LV or LM26LV-Q1 temperature switch outputs assert when the die temperature exceeds TTRIP. The temperature switch outputs will reset when the temperature falls below a temperature equal to (TTRIP - THYST). The OVERTEMP digital output, is active-high with a pushpull structure, while the OVERTEMP digital output, is active-low with an open-drain structure. The analog output, VTEMP, delivers an analog output voltage with Negative Temperature Coefficient (NTC). Driving the TRIP_TEST input high causes the digital outputs to be asserted for in-situ verification and causes the threshold voltage to appear at the VTEMP output pin, which could be used to verify the temperature trip point. The LM26LV's and LM26LV-Q1's low minimum supply voltage makes them ideal for 1.8-V system designs. The wide operating range, low supply current, and excellent accuracy provide a temperature switch solution for a wide range of commercial and industrial applications. Device Information(1) PART NUMBER LM26LV, LM26LV-Q1 PACKAGE WSON (6) BODY SIZE (NOM) 2.20 mm x 2.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Redundant Protection and Monitoring VDD Supply (+1.6V to +5.5V) Example: 2 to 3 Battery Cells VDD VTEMP LM26LV Analog Typical Transfer Characteristic ADC Input Microcontroller OVERTEMP OVERTEMP TRIP TEST GND Copyright (c) 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM26LV, LM26LV-Q1 SNIS144G - JULY 2007 - REVISED SEPTEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 4 4 4 4 5 5 6 7 9 Absolute Maximum Ratings ...................................... ESD Ratings: LM26LV .............................................. ESD Ratings: LM26LV-Q1 ........................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Accuracy Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 12 7.1 Overview ................................................................. 12 7.2 Functional Block Diagram ....................................... 12 7.3 Feature Description................................................. 13 7.4 Device Functional Modes........................................ 21 8 Application and Implementation ........................ 23 8.1 Application Information............................................ 23 8.2 Typical Application .................................................. 23 9 Power Supply Recommendations...................... 25 9.1 Power Supply Noise Immunity ................................ 25 10 Layout................................................................... 25 10.1 Layout Guidelines ................................................. 25 10.2 Layout Example .................................................... 26 11 Device and Documentation Support ................. 27 11.1 11.2 11.3 11.4 11.5 11.6 11.7 Documentation Support ........................................ Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 27 27 27 27 27 27 27 12 Mechanical, Packaging, and Orderable Information ........................................................... 27 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (February 2013) to Revision G Page * Added Device Information table, Pin Configuration and Functions section, Specifications section, ESD Ratings table, Thermal Information table, Switching Characteristics table, Detailed Description section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1 * Updated values in the Thermal Information table to align with JEDEC standards................................................................. 5 Changes from Revision E (February 2013) to Revision F * 2 Page Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 1 Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LM26LV LM26LV-Q1 LM26LV, LM26LV-Q1 www.ti.com SNIS144G - JULY 2007 - REVISED SEPTEMBER 2016 5 Pin Configuration and Functions NGF Package 6-Pin WSON Top View TRIP_TEST 1 GND 2 OVERTEMP 3 Thermal Pad 6 VTEMP 5 OVERTEMP 4 VDD Not to scale Pin Functions PIN NAME GND NO. 2 TYPE GND EQUIVALENT CIRCUIT DESCRIPTION Power supply ground -- VDD OVERTEMP 5 O Overtemperature switch output. Active high, push-pull. Asserted when the measured temperature exceeds the trip point temperature or if TRIP_TEST = 1. This pin may be left open if not used. GND OVERTEMP 3 O Overtemperature switch output. Active low, open-drain (See Determining the Pullup Resistor Value). Asserted when the measured temperature exceeds the trip point temperature or if TRIP_TEST = 1. This pin may be left open if not used. GND VDD TRIP_TEST 1 I TRIP_TEST pin. Active high input. If TRIP_TEST = 0 (Default) then: VTEMP = VTS, temperature sensor output voltage. If TRIP_TEST = 1 then: OVERTEMP and OVERTEMP outputs are asserted and VTEMP = VTRIP, temperature trip voltage. This pin may be left open if not used. 1 PA GND VDD 4 PWR Positive supply voltage -- VDD VSENSE VTEMP 6 O VTEMP analog voltage output. If TRIP_TEST = 0 then: VTEMP = VTS, temperature sensor output voltage. If TRIP_TEST = 1 then: VTEMP = VTRIP, temperature trip voltage. This pin may be left open if not used. GND Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LM26LV LM26LV-Q1 Submit Documentation Feedback 3 LM26LV, LM26LV-Q1 SNIS144G - JULY 2007 - REVISED SEPTEMBER 2016 www.ti.com Pin Functions (continued) PIN NAME NO. Thermal Pad -- TYPE -- EQUIVALENT CIRCUIT DESCRIPTION The best thermal conductivity between the device and the PCB is achieved by soldering the DAP of the package to the thermal pad on the PCB. The thermal pad can be a floating node. However, for improved noise immunity the thermal pad must be connected to the circuit GND node, preferably directly to pin 2 (GND) of the device. -- 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT Supply voltage -0.3 6 V Voltage at OVERTEMP pin -0.3 6 V Voltage at OVERTEMP and VTEMP pins -0.3 VDD + 0.5 V TRIP_TEST input voltage -0.3 VDD + 0.5 V -7 7 mA Output current, any output pin Input current at any pin (3) Maximum junction temperature, TJ(MAX) Storage temperature, Tstg (1) (2) (3) -65 5 mA 155 C 150 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. For soldering specifications, see Absolute Maximum Ratings for Soldering. When the input voltage (VI) at any pin exceeds power supplies (VI < GND or VI > VDD), the current at that pin must be limited to 5 mA. 6.2 ESD Ratings: LM26LV VALUE V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 4500 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) 1000 Machine model (MM) (1) (2) (3) (3) UNIT V 300 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. The machine model (MM) is a 200-pF capacitor charged to the specified voltage then discharged directly into each pin. 6.3 ESD Ratings: LM26LV-Q1 VALUE V(ESD) (1) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) 4500 Charged-device model (CDM), per AEC Q100-011 1000 Machine model (MM) 300 UNIT V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.4 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VDD Supply voltage 1.6 Supply current TA 4 MAX 5.5 8 Specified ambient temperature Submit Documentation Feedback NOM -50 UNIT V A 150 C Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LM26LV LM26LV-Q1 LM26LV, LM26LV-Q1 www.ti.com SNIS144G - JULY 2007 - REVISED SEPTEMBER 2016 6.5 Thermal Information THERMAL METRIC (1) LM26LV and LM26LV-Q1 UNIT NGF (WSON) 6 PINS RJA Junction-to-ambient thermal resistance 100.7 C/W RJC(top) Junction-to-case (top) thermal resistance 121.7 C/W RJB Junction-to-board thermal resistance 70 C/W JT Junction-to-top characterization parameter 7.1 C/W JB Junction-to-board characterization parameter 70.3 C/W RJC(bot) Junction-to-case (bottom) thermal resistance 15.9 C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.6 Electrical Characteristics Typical values apply for TA = TJ = 25C; minimum and maximum limits apply for TA = TJ = -50C to 150C, VDD = 1.6 V to 5.5 V (unless otherwise noted). (1) (2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT GENERAL SPECIFICATIONS IS Quiescent power supply current Hysteresis 4.5 8 16 A 5 5.5 C OVERTEMP DIGITAL OUTPUT--ACTIVE HIGH, PUSH-PULL VOH Logic High output voltage VDD 1.6 V, Source 340 A VDD - 0.2 VDD 2 V, Source 498 A VDD - 0.2 VDD 3.3 V, Source 780 A VDD - 0.2 VDD 1.6 V, Source 600 A VDD - 0.45 VDD 2 V, Source 980 A VDD - 0.45 VDD 3.3 V, Source 1.6 mA VDD - 0.45 V BOTH OVERTEMP AND OVERTEMP DIGITAL OUTPUTS VOL Logic Low output voltage VDD 1.6 V, Source 385 A 0.2 VDD 2 V, Source 500 A 0.2 VDD 3.3 V, Source 730 A 0.2 VDD 1.6 V, Source 690 A 0.45 VDD 2 V, Source 1.05 mA 0.45 VDD 3.3 V, Source 1.62 mA 0.45 V OVERTEMP DIGITAL OUTPUT--ACTIVE LOW, OPEN DRAIN IOH (1) (2) (3) Logic High output leakage current (3) TA = 30C 0.001 1 TA = 150C 0.025 1 A Limits are specified to TI's AOQL (Average Outgoing Quality Level). Typical values apply for TJ = TA = 25C and represent most likely parametric norm. The 1-A limit is based on a testing limitation and does not reflect the actual performance of the part. Expect to see a doubling of the current for every 15C increase in temperature. For example, the 1-nA typical current at 25C would increase to 16 nA at 85C. Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LM26LV LM26LV-Q1 Submit Documentation Feedback 5 LM26LV, LM26LV-Q1 SNIS144G - JULY 2007 - REVISED SEPTEMBER 2016 www.ti.com Electrical Characteristics (continued) Typical values apply for TA = TJ = 25C; minimum and maximum limits apply for TA = TJ = -50C to 150C, VDD = 1.6 V to 5.5 V (unless otherwise noted).(1)(2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VTEMP ANALOG TEMPERATURE SENSOR OUTPUT Gain 1 (trip point = 0C to 69C) VTEMP sensor gain -5.1 Gain 2 (trip point = 70C to 109C) -7.7 Gain 3 (trip point = 110C to 129C) -10.3 Gain 4 (trip point = 130C to 150C) -12.8 1.6 V VDD < 1.8 V Source 90 A, VDD - VTEMP 200 mV -1 Sink 100 A, VTEMP 260 mV VTEMP load regulation (4) VDD 1.8 V -0.1 0.1 Source 120 A, VDD - VTEMP 200 mV -1 Sink 200 A, VTEMP 260 mV mV/C 1 0.1 Source or sink = 100 A 1 1 0.29 Supply to VTEMP DC line regulation (5) CL VTEMP output load capacitance VDD = 1.6 V to 5.5 V Without series resistor. See Capacitive Loads. mV -0.1 mV 74 V/V -82 dB 1100 pF TRIP_TEST DIGITAL INPUT VIH Logic High threshold voltage VIL Logic Low threshold voltage IIH Logic High input current IIL Logic Low input current (3) (4) (5) VDD - 0.5 V 0.5 1.5 2.5 A 0.001 1 A Source currents are flowing out of the LM26LV or LM26LV-Q1. Sink currents are flowing into the LM26LV or LM26LV-Q1. Line regulation (DC) is calculated by subtracting the output voltage at the highest supply voltage from the output voltage at the lowest supply voltage. The typical DC line regulation specification does not include the output voltage shift discussed in Voltage Shift. 6.7 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS tEN Time from power ON to digital output enabled (1) tVTEMP Time from power ON to analog temperature valid (1) (1) 6 CL = 0 pF to 1100 pF MIN TYP MAX 1.1 2.3 UNIT ms 1 2.9 ms Figure 1 and Figure 2 show the definitions of tEN and tVTEMP. Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LM26LV LM26LV-Q1 LM26LV, LM26LV-Q1 www.ti.com SNIS144G - JULY 2007 - REVISED SEPTEMBER 2016 6.8 Accuracy Characteristics See (1) PARAMETER TEST CONDITIONS MIN MAX -2.2 2.2 -1.8 1.8 UNIT TRIP POINT ACCURACY Trip point accuracy (2) TA = 0C to 150C, VDD = 5 V C VTEMP ANALOG TEMPERATURE SENSOR OUTPUT ACCURACY (3) TA = 20C to 40C, VDD = 1.6 V to 5.5 V Gain 1 trip point = 0C to 69C Gain 2 trip point = 70C to 109C VTEMP temperature accuracy (2) Gain 3 trip point = 110C to 129C Gain 4 trip point = 130C to 150C (1) (2) (3) TA = 0C to 70C, VDD = 1.6 V to 5.5 V -2 2 TA = 0C to 90C, VDD = 1.6 V to 5.5 V -2.1 2.1 TA = 0C to 120C, VDD = 1.6 V to 5.5 V -2.2 2.2 TA = 0C to 150C, VDD = 1.6 V to 5.5 V -2.3 2.3 TA = -50C to 0C, VDD = 1.7 V to 5.5 V -1.7 1.7 TA = 20C to 40C, VDD = 1.8 V to 5.5 V -1.8 1.8 TA = 0C to 70C, VDD = 1.9 V to 5.5 V -2 2 TA = 0C to 90C, VDD = 1.9 V to 5.5 V -2.1 2.1 TA = 0C to 120C, VDD = 1.9 V to 5.5 V -2.2 2.2 TA = 0C to 150C, VDD = 1.9 V to 5.5 V -2.3 2.3 TA = -50C to 0C, VDD = 2.3 V to 5.5 V -1.7 1.7 TA = 20C to 40C, VDD = 2.3 V to 5.5 V -1.8 1.8 TA = 0C to 70C, VDD = 2.5 V to 5.5 V -2 2 TA = 0C to 90C, VDD = 2.5 V to 5.5 V -2.1 2.1 TA = 0C to 120C, VDD = 2.5 V to 5.5 V -2.2 2.2 TA = 0C to 150C, VDD = 2.5 V to 5.5 V -2.3 2.3 TA = -50C to 0C, VDD = 3 V to 5.5 V -1.7 1.7 TA = 20C to 40C, VDD = 2.7 V to 5.5 V -1.8 1.8 TA = 0C to 70C, VDD = 3 V to 5.5 V -2 2 TA = 0C to 90C, VDD = 3 V to 5.5 V -2.1 2.1 TA = 0C to 120C, VDD = 3 V to 5.5 V -2.2 2.2 TA = 0C to 150C, VDD = 3 V to 5.5 V -2.3 2.3 TA = -50C to 0C, VDD = 3.6 V to 5.5 V -1.7 1.7 C Limits are specified to TI's AOQL (Average Outgoing Quality Level). Accuracy is defined as the error between the measured and reference output voltages, tabulated in Table 1 at the specified conditions of supply gain setting, voltage, and temperature (C). Accuracy limits include line regulation within the specified conditions. Accuracy limits do not include load regulation; they assume no DC load. Changes in output due to self heating can be computed by multiplying the internal dissipation by the temperature thermal resistance. VDD 1.3V tEN OVERTEMP OVERTEMP Enabled Enabled Figure 1. Definition of tEN Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LM26LV LM26LV-Q1 Submit Documentation Feedback 7 LM26LV, LM26LV-Q1 SNIS144G - JULY 2007 - REVISED SEPTEMBER 2016 www.ti.com VDD tVTEMP Valid VTEMP Figure 2. Definition of tVTEMP 8 Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LM26LV LM26LV-Q1 LM26LV, LM26LV-Q1 www.ti.com SNIS144G - JULY 2007 - REVISED SEPTEMBER 2016 6.9 Typical Characteristics Figure 3. VTEMP Output Temperature Error vs Temperature Figure 4. Minimum Operating Temperature vs Supply Voltage Figure 5. Supply Current vs Temperature Figure 6. Supply Current vs Supply Voltage 100-mV overhead TA = 80C Sourcing current Figure 7. Load Regulation (1) 200-mV overhead (1) TA = 80C Figure 8. Load Regulation Sourcing Current (1) The curves shown represent typical performance under worst-case conditions. Performance improves with larger VTEMP, larger VDD, and lower temperatures. Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LM26LV LM26LV-Q1 Submit Documentation Feedback 9 LM26LV, LM26LV-Q1 SNIS144G - JULY 2007 - REVISED SEPTEMBER 2016 www.ti.com Typical Characteristics (continued) 400-mV overhead TA = 80C Sourcing current Figure 9. Load Regulation VDD = 1.6 V Sinking Current 10 VDD = 2.4 V Figure 10. Load Regulation (1) Sourcing current (1) Sinking Current Figure 12. Load Regulation(1) Sinking Current Figure 13. Load Regulation(1) (1) TA = 150C VDD = 1.8 V Figure 11. Load Regulation VDD = 2.4 V 1.72-V overhead (1) Figure 14. Change in VTEMP vs Overhead Voltage The curves shown represent typical performance under worst-case conditions. Performance improves with larger VTEMP, larger VDD, and lower temperatures. Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LM26LV LM26LV-Q1 LM26LV, LM26LV-Q1 www.ti.com SNIS144G - JULY 2007 - REVISED SEPTEMBER 2016 Typical Characteristics (continued) Gain 1 (Trip Points = 0C tp 69C) Figure 15. VTEMP Supply-Noise Rejection vs Frequency Gain 2 (Trip Points = 70C to 109C) Figure 16. Line Regulation VTEMP vs Supply Voltage Gain 3 (Trip Points = 110C to 129C) Figure 17. Line Regulation VTEMP vs Supply Voltage Figure 18. Line Regulation VTEMP vs Supply Voltage Gain 4 (Trip Points = 130C to 150C) Figure 19. Line Regulation VTEMP vs Supply Voltage Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LM26LV LM26LV-Q1 Submit Documentation Feedback 11 LM26LV, LM26LV-Q1 SNIS144G - JULY 2007 - REVISED SEPTEMBER 2016 www.ti.com 7 Detailed Description 7.1 Overview The LM26LV and LM26LV-Q1 are precision, dual-output, temperature switches with analog temperature sensor output. The trip temperature (TTRIP) is factory selected by the order number. The VTEMP class AB analog output provides a voltage that is proportional to temperature. The LM26LV and LM26LV-Q1 include an internal reference DAC (TEMP THRESHOLD), analog temperature sensor and analog comparator. The reference DAC is connected to one of the comparator inputs. The reference DAC output voltage (VTRIP) is preprogrammed by TI. The result of the reference DAC voltage and the temperature sensor output comparison is provided on two output pins OVERTEMP and OVERTEMP. The VTEMP output has a programmable gain. The output gain has 4 possible settings as described in Table 1. The gain setting is dependent on the temperature trip point selected. Built-in temperature hysteresis (THYST) prevents the digital outputs from oscillating. The OVERTEMP and OVERTEMP activates when the die temperature exceeds TTRIP and releases when the temperature falls below a temperature equal to TTRIP minus THYST. OVERTEMP is active-high with a push-pull structure. OVERTEMP, is active-low with an open-drain structure. The comparator hysteresis is fixed at 5C. Driving the TRIP-TEST high activates the digital outputs. A processor can check the logic level of the OVERTEMP or OVERTEMP, confirming that they changed to their active state. This allows for system production testing verification that the comparator and output circuitry are functional after system assembly. When the TRIP-TEST pin is high, the trip-level reference voltage appears at the VTEMP pin. Tying OVERTEMP to TRIP-TEST latches the output after it trips. It can be cleared by forcing TRIP-TEST low or powering off the LM26LV or LM26LV-Q1. 7.2 Functional Block Diagram VDD 4 TRIP TEST = 0 (Default) LM26LV 6 TRIP TEST = 1 VTS 3 VTEMP OVERTEMP VTRIP VDD TEMP SENSOR TEMP THRESHOLD 5 2 GND OVERTEMP 1 TRIP TEST Copyright (c) 2016, Texas Instruments Incorporated 12 Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LM26LV LM26LV-Q1 LM26LV, LM26LV-Q1 www.ti.com SNIS144G - JULY 2007 - REVISED SEPTEMBER 2016 7.3 Feature Description 7.3.1 LM26LV and LM26LV-Q1 VTEMP vs Die Temperature Conversion Table The LM26LV and LM26LV-Q1 have one out of four possible factory-set gains, Gain 1 through Gain 4, depending on the range of the Temperature Trip Point. The VTEMP temperature sensor voltage, in millivolts, at each discrete die temperature over the complete operating temperature range, and for each of the four Temperature Trip Point ranges, is shown in Table 1. This table is the reference from which the LM26LV and LM26LV-Q1 accuracy specifications (listed in Accuracy Characteristics) are determined. This table can be used, for example, in a host processor look-up table. See The Second-Order Equation (Parabolic) for the parabolic equation used in the Conversion Table. Table 1. VTEMP Temperature Sensor Output Voltage vs Die Temperature Conversion Table DIE TEMPERATURE (C) (1) ANALOG OUTPUT VOLTAGE, VTEMP (mV) (1) GAIN 1 GAIN 2 GAIN 3 GAIN 4 -50 1312 1967 2623 3278 -49 1307 1960 2613 3266 -48 1302 1952 2603 3253 -47 1297 1945 2593 3241 -46 1292 1937 2583 3229 -45 1287 1930 2573 3216 -44 1282 1922 2563 3204 -43 1277 1915 2553 3191 -42 1272 1908 2543 3179 -41 1267 1900 2533 3166 -40 1262 1893 2523 3154 -39 1257 1885 2513 3141 -38 1252 1878 2503 3129 -37 1247 1870 2493 3116 -36 1242 1863 2483 3104 -35 1237 1855 2473 3091 -34 1232 1848 2463 3079 -33 1227 1840 2453 3066 -32 1222 1833 2443 3054 -31 1217 1825 2433 3041 -30 1212 1818 2423 3029 -29 1207 1810 2413 3016 -28 1202 1803 2403 3004 -27 1197 1795 2393 2991 -26 1192 1788 2383 2979 -25 1187 1780 2373 2966 -24 1182 1773 2363 2954 -23 1177 1765 2353 2941 -22 1172 1757 2343 2929 -21 1167 1750 2333 2916 -20 1162 1742 2323 2903 -19 1157 1735 2313 2891 -18 1152 1727 2303 2878 -17 1147 1720 2293 2866 -16 1142 1712 2283 2853 -15 1137 1705 2272 2841 -14 1132 1697 2262 2828 -13 1127 1690 2252 2815 -12 1122 1682 2242 2803 VDD = 5 V. Values are bold for each gain's respective trip point range. Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LM26LV LM26LV-Q1 Submit Documentation Feedback 13 LM26LV, LM26LV-Q1 SNIS144G - JULY 2007 - REVISED SEPTEMBER 2016 www.ti.com Feature Description (continued) Table 1. VTEMP Temperature Sensor Output Voltage vs Die Temperature Conversion Table (continued) DIE TEMPERATURE (C) 14 ANALOG OUTPUT VOLTAGE, VTEMP (mV) (1) GAIN 1 GAIN 2 GAIN 3 GAIN 4 -11 1116 1674 2232 2790 -10 1111 1667 2222 2777 -9 1106 1659 2212 2765 -8 1101 1652 2202 2752 -7 1096 1644 2192 2740 -6 1091 1637 2182 2727 -5 1086 1629 2171 2714 -4 1081 1621 2161 2702 -3 1076 1614 2151 2689 -2 1071 1606 2141 2676 -1 1066 1599 2131 2664 0 1061 1591 2121 2651 1 1056 1583 2111 2638 2 1051 1576 2101 2626 3 1046 1568 2090 2613 4 1041 1561 2080 2600 5 1035 1553 2070 2587 6 1030 1545 2060 2575 7 1025 1538 2050 2562 8 1020 1530 2040 2549 9 1015 1522 2029 2537 10 1010 1515 2019 2524 11 1005 1507 2009 2511 12 1000 1499 1999 2498 13 995 1492 1989 2486 14 990 1484 1978 2473 15 985 1477 1968 2460 16 980 1469 1958 2447 17 974 1461 1948 2435 18 969 1454 1938 2422 19 964 1446 1927 2409 20 959 1438 1917 2396 21 954 1431 1907 2383 22 949 1423 1897 2371 23 944 1415 1886 2358 24 939 1407 1876 2345 25 934 1400 1866 2332 26 928 1392 1856 2319 27 923 1384 1845 2307 28 918 1377 1835 2294 29 913 1369 1825 2281 30 908 1361 1815 2268 31 903 1354 1804 2255 32 898 1346 1794 2242 33 892 1338 1784 2230 34 887 1331 1774 2217 35 882 1323 1763 2204 36 877 1315 1753 2191 37 872 1307 1743 2178 Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LM26LV LM26LV-Q1 LM26LV, LM26LV-Q1 www.ti.com SNIS144G - JULY 2007 - REVISED SEPTEMBER 2016 Feature Description (continued) Table 1. VTEMP Temperature Sensor Output Voltage vs Die Temperature Conversion Table (continued) DIE TEMPERATURE (C) ANALOG OUTPUT VOLTAGE, VTEMP (mV) (1) GAIN 1 GAIN 2 GAIN 3 GAIN 4 38 867 1300 1732 2165 39 862 1292 1722 2152 40 856 1284 1712 2139 41 851 1276 1701 2127 42 846 1269 1691 2114 43 841 1261 1681 2101 44 836 1253 1670 2088 45 831 1245 1660 2075 46 825 1238 1650 2062 47 820 1230 1639 2049 48 815 1222 1629 2036 49 810 1214 1619 2023 50 805 1207 1608 2010 51 800 1199 1598 1997 52 794 1191 1588 1984 53 789 1183 1577 1971 54 784 1176 1567 1958 55 779 1168 1557 1946 56 774 1160 1546 1933 57 769 1152 1536 1920 58 763 1144 1525 1907 59 758 1137 1515 1894 60 753 1129 1505 1881 61 748 1121 1494 1868 62 743 1113 1484 1855 63 737 1105 1473 1842 64 732 1098 1463 1829 65 727 1090 1453 1816 66 722 1082 1442 1803 67 717 1074 1432 1790 68 711 1066 1421 1776 69 706 1059 1411 1763 70 701 1051 1400 1750 71 696 1043 1390 1737 72 690 1035 1380 1724 73 685 1027 1369 1711 74 680 1019 1359 1698 75 675 1012 1348 1685 76 670 1004 1338 1672 77 664 996 1327 1659 78 659 988 1317 1646 79 654 980 1306 1633 80 649 972 1296 1620 81 643 964 1285 1607 82 638 957 1275 1593 83 633 949 1264 1580 84 628 941 1254 1567 85 622 933 1243 1554 86 617 925 1233 1541 Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LM26LV LM26LV-Q1 Submit Documentation Feedback 15 LM26LV, LM26LV-Q1 SNIS144G - JULY 2007 - REVISED SEPTEMBER 2016 www.ti.com Feature Description (continued) Table 1. VTEMP Temperature Sensor Output Voltage vs Die Temperature Conversion Table (continued) DIE TEMPERATURE (C) 16 ANALOG OUTPUT VOLTAGE, VTEMP (mV) (1) GAIN 1 GAIN 2 GAIN 3 GAIN 4 87 612 917 1222 1528 88 607 909 1212 1515 89 601 901 1201 1501 90 596 894 1191 1488 91 591 886 1180 1475 92 586 878 1170 1462 93 580 870 1159 1449 94 575 862 1149 1436 95 570 854 1138 1422 96 564 846 1128 1409 97 559 838 1117 1396 98 554 830 1106 1383 99 549 822 1096 1370 100 543 814 1085 1357 101 538 807 1075 1343 102 533 799 1064 1330 103 527 791 1054 1317 104 522 783 1043 1304 105 517 775 1032 1290 106 512 767 1022 1277 107 506 759 1011 1264 108 501 751 1001 1251 109 496 743 990 1237 110 490 735 979 1224 111 485 727 969 1211 112 480 719 958 1198 113 474 711 948 1184 114 469 703 937 1171 115 464 695 926 1158 116 459 687 916 1145 117 453 679 905 1131 118 448 671 894 1118 119 443 663 884 1105 120 437 655 873 1091 121 432 647 862 1078 122 427 639 852 1065 123 421 631 841 1051 124 416 623 831 1038 125 411 615 820 1025 126 405 607 809 1011 127 400 599 798 998 128 395 591 788 985 129 389 583 777 971 130 384 575 766 958 131 379 567 756 945 132 373 559 745 931 133 368 551 734 918 134 362 543 724 904 135 357 535 713 891 Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LM26LV LM26LV-Q1 LM26LV, LM26LV-Q1 www.ti.com SNIS144G - JULY 2007 - REVISED SEPTEMBER 2016 Feature Description (continued) Table 1. VTEMP Temperature Sensor Output Voltage vs Die Temperature Conversion Table (continued) DIE TEMPERATURE (C) ANALOG OUTPUT VOLTAGE, VTEMP (mV) (1) GAIN 1 GAIN 2 GAIN 3 GAIN 4 136 352 527 702 878 137 346 519 691 864 138 341 511 681 851 139 336 503 670 837 140 330 495 659 824 141 325 487 649 811 142 320 479 638 797 143 314 471 627 784 144 309 463 616 770 145 303 455 606 757 146 298 447 595 743 147 293 438 584 730 148 287 430 573 716 149 282 422 562 703 150 277 414 552 690 7.3.2 VTEMP vs Die Temperature Approximations The LM26LV's and LM26LV-Q1's VTEMP analog temperature output is very linear. Table 1 and the equation in The Second-Order Equation (Parabolic) represent the most accurate typical performance of the VTEMP voltage output versus temperature. 7.3.2.1 The Second-Order Equation (Parabolic) The data from Table 1, or Equation 1, when plotted, has an umbrella-shaped parabolic curve. VTEMP is in mV. GAIN1: VTEMP = 907.9 - 5.132 (TDIE - 30C) - 1.08 -3 (TDIE - 30C) GAIN2 : VTEMP = 1361.4 - 7.701 (TDIE - 30C) - 1.6 -3 (TDIE - 30C) GAIN3 : VTEMP = 1814.6 - 10.27 (TDIE - 30C) - 2.12 -3 (TDIE - 30C) GAIN4 : VTEMP = 2268.1 - 12.838 (TDIE - 30C) - 2.64 -3 (TDIE - 30C) (1) 7.3.2.2 The First-Order Approximation (Linear) For a quicker approximation, although less accurate than the second-order, over the full operating temperature range the linear formula below can be used. Using Equation 2, with the constant and slope in the following set of equations, the best-fit VTEMP versus die temperature performance can be calculated with an approximation error less than 18 mV. VTEMP is in mV. GAIN1: VTEMP = 1060 - 5.18 TDIE GAIN2 : VTEMP = 1590 - 7.77 TDIE GAIN3 : VTEMP = 2119 - 10.36 TDIE GAIN4 : VTEMP = 2649 - 12.94 TDIE Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LM26LV LM26LV-Q1 (2) Submit Documentation Feedback 17 LM26LV, LM26LV-Q1 SNIS144G - JULY 2007 - REVISED SEPTEMBER 2016 www.ti.com 7.3.2.3 First-Order Approximation (Linear) Over Small Temperature Range For a linear approximation, a line can easily be calculated over the desired temperature range from Table 1 using the two-point equation: ae V - V1 o V - V1 = c 2 / (T - T1 ) e T2 - T1 o where * * * * V is in mV T is in C T1 and V1 are the coordinates of the lowest temperature T2 and V2 are the coordinates of the highest temperature (3) For example, to determine the equation of a line with GAIN4, with a temperature from 20C to 50C, proceed using Equation 4, Equation 5, and Equation 6: ae 2010 mV - 2396 mV o V - 2396 mV = c / (T - 20C) 50C - 20C e o (4) V - 2396 mV = -12.8 mV/C x (T - 20C) V = -12.8 mV/C x (T - 20C) + 2396 mV (5) (6) Using this method of linear approximation, the transfer function can be approximated for one or more temperature ranges of interest. 7.3.3 OVERTEMP and OVERTEMP Digital Outputs The OVERTEMP active high, push-pull output and the OVERTEMP active low, open-drain output both assert at the same time whenever the die temperature reaches the factory preset temperature trip point. They also assert simultaneously whenever the TRIP_TEST pin is set high. Both outputs deassert when the die temperature goes below the temperature trip point hysteresis. These two types of digital outputs enable the user the flexibility to choose the type of output that is most suitable for his design. Either the OVERTEMP or the OVERTEMP digital output pins can be left open if not used. 7.3.3.1 OVERTEMP Open-Drain Digital Output The OVERTEMP active low, open-drain digital output, if used, requires a pullup resistor between this pin and VDD. The following section shows how to determine the pullup resistor value. 7.3.3.1.1 Determining the Pullup Resistor Value VDD iT RPull-Up VOUT OVERTEMP Digital Input iL isink 18 Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LM26LV LM26LV-Q1 LM26LV, LM26LV-Q1 www.ti.com SNIS144G - JULY 2007 - REVISED SEPTEMBER 2016 The pullup resistor value is calculated at the condition of maximum total current, IT, through the resistor. The total current is: IT = IL + ISINK where * * IT is the maximum total current through the pullup resistor at VOL. IL is the load current, which is very low for typical digital inputs. (7) The pullup resistor maximum value can be found by using Equation 8. VDD(MAX) - VOL R PULLUP = IT where * * VDD(MAX) is the maximum power supply voltage to be used in the customer's system. VOUT is the Voltage at the OVERTEMP pin. Use VOL for calculating the pullup resistor. (8) 7.3.3.1.1.1 Example Calculation Suppose, for this example, a VDD of 3.3 V 0.3 V, a CMOS digital input as a load, a VOL of 0.2 V. * * * * For VOL of 0.2 V the electrical specification for OVERTEMP shows a maximum ISINK of 385 A. Let IL = 1 A, then IT is about 386 A maximum. If 35 A is selected as the current limit then IT for the calculation becomes 35 A. VDD(MAX) is 3.3 V + 0.3 V = 3.6 V, then calculate the pullup resistor as RPULLUP = (3.6 - 0.2) / 35 A = 97 k. Based on this calculated value, select the closest resistor value in the tolerance family used. In this example, if 5% resistor values are used, then the next closest value is 100 k. 7.3.4 TRIP_TEST Digital Input The TRIP_TEST pin simply provides a means to test the OVERTEMP and OVERTEMP digital outputs electronically by causing them to assert, at any operating temperature, as a result of forcing the TRIP_TEST pin high. When the TRIP_TEST pin is pulled high the VTEMP pin is at the VTRIP voltage. If not used, the TRIP_TEST pin may either be left open or grounded. 7.3.5 VTEMP Analog Temperature Sensor Output The VTEMP push-pull output provides the ability to sink and source significant current. This is beneficial when, for example, driving dynamic loads like an input stage on an analog-to-digital converter (ADC). In these applications the source current is required to quickly charge the input capacitor of the ADC. See Application and Implementation for more discussion of this topic. The LM26LV and LM26LV-Q1 are ideal for applications which require strong source or sink current. 7.3.5.1 Noise Considerations The LM26LV's and LM26LV-Q1's supply-noise rejection (the ratio of the AC signal on VTEMP to the AC signal on VDD) was measured during bench tests. The device's typical attenuation is shown in Typical Characteristics. A load capacitor on the output can help to filter noise. For operation in very noisy environments, some bypass capacitance must be present on the supply within approximately 2 inches of the LM26LV or LM26LV-Q1. 7.3.5.2 Capacitive Loads The VTEMP Output handles capacitive loading well. In an extremely noisy environment, or when driving a switched sampling input on an ADC, it may be necessary to add some filtering to minimize noise coupling. Without any precautions, the VTEMP can drive a capacitive load less than or equal to 1100 pF as shown in Figure 20. For capacitive loads greater than 1100 pF, a series resistor is required on the output, as shown in Figure 21, to maintain stable conditions. Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LM26LV LM26LV-Q1 Submit Documentation Feedback 19 LM26LV, LM26LV-Q1 SNIS144G - JULY 2007 - REVISED SEPTEMBER 2016 www.ti.com VDD LM26LV OPTIONAL BYPASS CAPACITANCE VTEMP GND CLOAD d 1100 pF Figure 20. LM26LV or LM26LV-Q1 No Decoupling Required for Capacitive Loads Less Than 1100 pF. VDD LM26LV OPTIONAL BYPASS CAPACITANCE GND VTEMP RS CLOAD > 1100 pF Figure 21. LM26LV or LM26LV-Q1 With Series Resistor for Capacitive Loading Greater Than 1100 pF Table 2. Minimum Series Resistence for Capacitive Loads CLOAD MINIMUM RS 1.1 nF to 99 nF 3 k 100 nF to 999 nF 1.5 k 1 F 800 7.3.5.3 Voltage Shift The LM26LV and LM26LV-Q1 are very linear over temperature and supply voltage range. Due to the intrinsic behavior of an NMOS/PMOS rail-to-rail buffer, a slight shift in the output can occur when the supply voltage is ramped over the operating range of the device. The location of the shift is determined by the relative levels of VDD and VTEMP. The shift typically occurs when VDD - VTEMP = 1 V. This slight shift (a few millivolts) takes place over a wide change (approximately 200 mV) in VDD or VTEMP. Because the shift takes place over a wide temperature change of 5C to 20C, VTEMP is always monotonic. The accuracy specifications Accuracy Characteristics already includes this possible shift. 20 Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LM26LV LM26LV-Q1 LM26LV, LM26LV-Q1 www.ti.com SNIS144G - JULY 2007 - REVISED SEPTEMBER 2016 7.4 Device Functional Modes The LM26LV and LM26LV-Q1 have several modes of operation as detailed in the following drawings. VDD VDD 4 NC 1 4 5 OVERTEMP 1 NC LM26LV 6 3 100k Asserts when TDIE > TTRIP NC LM26LV See text. 3 OVERTEMP 6 Asserts when TDIE > TTRIP NC See text. 5 NC 2 NC 2 GND GND Copyright (c) 2016, Texas Instruments Incorporated Copyright (c) 2016, Texas Instruments Incorporated Figure 22. Temperature Switch Using Push-Pull Output Figure 23. Temperature Switch Using Open-Drain Output VDD 100k 4 TRIP TEST 3 1 LM26LV 6 5 OVERTEMP NC OVERTEMP 2 GND Copyright (c) 2016, Texas Instruments Incorporated Figure 24. TRIP_TEST Digital Output Test Circuit The TRIP_TEST pin, normally used to check the operation of the OVERTEMP and OVERTEMP pins, may be used to latch the outputs whenever the temperature exceeds the programmed limit and causes the digital outputs to assert. As shown in Figure 25, when OVERTEMP goes high the TRIP_TEST input is also pulled high and causes OVERTEMP output to latch high and the OVERTEMP output to latch low. The latch can be released by either momentarily pulling the TRIP_TEST pin low (GND), or by toggling the power supply to the device. The resistor limits the current out of the OVERTEMP output pin. Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LM26LV LM26LV-Q1 Submit Documentation Feedback 21 LM26LV, LM26LV-Q1 SNIS144G - JULY 2007 - REVISED SEPTEMBER 2016 www.ti.com Device Functional Modes (continued) VDD 100k 4 TRIP TEST 1 RESET Momentary 5 LM26LV 6 OVERTEMP NC 3 OVERTEMP 2 GND Copyright (c) 2016, Texas Instruments Incorporated Figure 25. Latch Circuit Using OVERTEMP Output Alternately, the circuit in Figure 25 the 100 k can be replaced with a short and the momentary reset switch may be removed. In this configuration, when OVERTEMP goes active high, it drives TRIP_TEST high. THRIP TEST high causes OVERTEMP to stay high. It is therefore latched. To release the latch, power down, then power up the LM26LV or LM26LV-Q1. The LM26LV and LM26LV-Q1 always come up in a released condition. 22 Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LM26LV LM26LV-Q1 LM26LV, LM26LV-Q1 www.ti.com SNIS144G - JULY 2007 - REVISED SEPTEMBER 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 ADC Input Considerations The LM26LV and LM26LV-Q1 have an analog temperature sensor output VTEMP that can be directly connected to an ADC (Analog-to-Digital Converter) input. Most CMOS ADCs found in microcontrollers and ASICs have a sampled data comparator input structure. When the ADC charges the sampling cap, it requires instantaneous charge from the output of the analog source such as the LM26LV or LM26LV-Q1 temperature sensor. This requirement is easily accommodated by the addition of a capacitor (CFILTER). The size of CFILTER depends on the size of the sampling capacitor and the sampling frequency. Because not all ADCs have identical input stages, the charge requirements vary. This general ADC application is shown as an example only. SAR Analog-to-Digital Converter Reset +1.6V to +5.5V LM26LV 6 4 VDD Input Pin RIN CBP 1 2 Sample VTEMP TRIP TEST OT GND OT 5 CFILTER CPIN CSAMPLE 3 Copyright (c) 2016, Texas Instruments Incorporated Figure 26. Suggested Connection to a Sampling Analog-to-Digital Converter Input Stage 8.2 Typical Application VDD Supply (+1.6V to +5.5V) Example: 2 to 3 Battery Cells VDD VTEMP LM26LV Analog ADC Input Microcontroller OVERTEMP OVERTEMP TRIP TEST GND Copyright (c) 2016, Texas Instruments Incorporated Figure 27. Typical Application Schematic Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LM26LV LM26LV-Q1 Submit Documentation Feedback 23 LM26LV, LM26LV-Q1 SNIS144G - JULY 2007 - REVISED SEPTEMBER 2016 www.ti.com Typical Application (continued) 8.2.1 Design Requirements For this design example, use the parameters listed in Table 3 as the input parameters. Table 3. Design Parameters PARAMETER EXAMPLE VALUE Temperature 0C to 150C (LM26LV), -40C to 85C for microcontroller Accuracy 2.3C (Gain1, TA = 0C to 150C) VDD 3.3 V IDD 8 A 8.2.2 Detailed Design Procedure The LM26LV and LM26LV-Q1 come with a factory preset trip point. See Mechanical, Packaging, and Orderable Information for available trip point options. Figure 27 shows the device's OVERTEMP output driving a microcontroller interrupt input to indicate an overtemperature event. In addition to the OVERTEMP output, a OVERTEMP output is available for use depending on the interrupt polarity of the microcontroller's interrupt pin. A VTEMP analog output is available to drive the microcontroller ADC input allowing the microcontroller to determine the sensing temperature of the LM26LV or LM26LV-Q1. The TRIP_TEST input is connected to a microcontroller output pin allowing the microcontroller to run on the fly electrical conductivity testing. For normal operation TRIP_TEST must be driven low by the microcontroller output. If no testing is required, the TRIP_TEST pin may be continuously grounded. 8.2.3 Application Curves VTEMP Output (Temp. of Leads) Trip Point Trip Point - Hysteresis OVERTEMP OVERTEMP Figure 28. VTEMP Analog Output Temperature Error 24 Submit Documentation Feedback Figure 29. Switch Output Function Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LM26LV LM26LV-Q1 LM26LV, LM26LV-Q1 www.ti.com SNIS144G - JULY 2007 - REVISED SEPTEMBER 2016 9 Power Supply Recommendations Bypass capacitors are optional, and maybe required if the supply line is extremely noisy at high frequencies. TI recommends that a local supply decoupling capacitor be used to reduce noise. For noisy environments, TI recommends a 100-nF supply decoupling capacitor placed closed across the VDD and GND pins of the LM26LV or LM26LV-Q1. 9.1 Power Supply Noise Immunity The LM26LV and LM26LV-Q1 are virtually immune from false triggers on the OVERTEMP and OVERTEMP digital outputs due to noise on the power supply. Test have been conducted showing that, with the die temperature within 0.5C of the temperature trip point, and the severe test of a 3 V***pp square wave "***noise" signal injected on the VDD line, with VDD from 2 V to 5 V, there were no false triggers. 10 Layout 10.1 Layout Guidelines 10.1.1 Mounting and Temperature Conductivity The LM26LV or LM26LV-Q1 can be applied easily in the same way as other integrated-circuit temperature sensors. The devices can be glued or cemented to a surface. The best thermal conductivity between the device and the PCB is achieved by soldering the DAP of the package to the thermal pad on the PCB. The temperatures of the lands and traces to the other leads of the LM26LV and LM26LV-Q1 also affect the temperature reading. Alternatively, the LM26LV or LM26LV-Q1 can be mounted inside a sealed-end metal tube, and can then be dipped into a bath or screwed into a threaded hole in a tank. As with any IC, the LM26LV or LM26LV-Q1 and accompanying wiring and circuits must be kept insulated and dry, to avoid leakage and corrosion. This is especially true if the circuit may operate at cold temperatures where condensation can occur. If moisture creates a short circuit from the VTEMP output to ground or VDD, the VTEMP output from the LM26LV or LM26LV-Q1 is not correct. Printed-circuit coatings are often used to ensure that moisture cannot corrode the leads or circuit traces. The thermal resistance junction-to-ambient (RJA) is the parameter used to calculate the rise of a device junction temperature due to its power dissipation. The equation used to calculate the rise in the LM26LV's and LM26LVQ1's die temperature is TJ = TA + R qJA ((VDD IQ ) + (VDD - VTEMP ) IL ) where * * * * TA is the ambient temperature IQ is the quiescent current IL is the load current on the output VO is the output voltage (9) For example, in an application where TA = 30C, VDD = 5 V, IDD = 9 A, Gain 4, VTEMP = 2231 mV, and IL = 2 A, the junction temperature would be 30.021C, showing a self-heating error of only 0.021C. Because the LM26LV's and LM26LV-Q1's junction temperature is the actual temperature being measured, minimize the load current that the VTEMP output is required to drive. If OVERTEMP is used with a 100k pullup resistor, and is asserted (low), then for this example the additional contribution is (152C/W) x (5 V)2 / 100 k = 0.038C for a total self-heating error of 0.059C. Thermal Information shows the thermal resistance of the LM26LV and LM26LV-Q1. Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LM26LV LM26LV-Q1 Submit Documentation Feedback 25 LM26LV, LM26LV-Q1 SNIS144G - JULY 2007 - REVISED SEPTEMBER 2016 www.ti.com 10.2 Layout Example VIA to power plane Optional thermal VIA to ground plane and back side of board for thermal conductivity path VIA to ground plane R is optional maybe directly connected to GND if TRIP TEST not used TRIP TEST VTEMP GND OVERTEMP VDD OVERTEMP 0.1 F Figure 30. Typical Layout Example VIA to power plane Optional thermal VIA to ground plane and back side of board for thermal conductivity path VIA to ground plane TRIP TEST GND OVERTEMP VTEMP OVERTEMP VDD 0.1 F Figure 31. Latching Layout Example 26 Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LM26LV LM26LV-Q1 LM26LV, LM26LV-Q1 www.ti.com SNIS144G - JULY 2007 - REVISED SEPTEMBER 2016 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation see the following: Absolute Maximum Ratings for Soldering (SNOA549) 11.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 4. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LM26LV Click here Click here Click here Click here Click here LM26LV-Q1 Click here Click here Click here Click here Click here 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.5 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.7 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LM26LV LM26LV-Q1 Submit Documentation Feedback 27 PACKAGE OPTION ADDENDUM www.ti.com 17-Jul-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LM26LVCISD-050/NOPB ACTIVE WSON NGF 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 050 LM26LVCISD-060/NOPB ACTIVE WSON NGF 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 060 LM26LVCISD-065/NOPB ACTIVE WSON NGF 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 065 LM26LVCISD-070/NOPB ACTIVE WSON NGF 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 070 LM26LVCISD-075/NOPB ACTIVE WSON NGF 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 075 LM26LVCISD-080/NOPB ACTIVE WSON NGF 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 080 LM26LVCISD-085/NOPB ACTIVE WSON NGF 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 085 LM26LVCISD-090/NOPB ACTIVE WSON NGF 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 090 LM26LVCISD-095/NOPB ACTIVE WSON NGF 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 095 LM26LVCISD-100/NOPB ACTIVE WSON NGF 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 100 LM26LVCISD-105/NOPB ACTIVE WSON NGF 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 105 LM26LVCISD-110/NOPB ACTIVE WSON NGF 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 110 LM26LVCISD-115/NOPB ACTIVE WSON NGF 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 115 LM26LVCISD-120/NOPB ACTIVE WSON NGF 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 120 LM26LVCISD-125/NOPB ACTIVE WSON NGF 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 125 LM26LVCISD-130/NOPB ACTIVE WSON NGF 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 130 LM26LVCISD-135/NOPB ACTIVE WSON NGF 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 135 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 17-Jul-2015 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LM26LVCISD-140/NOPB ACTIVE WSON NGF 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 140 LM26LVCISD-145/NOPB ACTIVE WSON NGF 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 145 LM26LVCISD-150/NOPB ACTIVE WSON NGF 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 150 LM26LVCISDX-050/NOPB ACTIVE WSON NGF 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 050 LM26LVCISDX-060/NOPB ACTIVE WSON NGF 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 060 LM26LVCISDX-065/NOPB ACTIVE WSON NGF 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 065 LM26LVCISDX-070/NOPB ACTIVE WSON NGF 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 070 LM26LVCISDX-075/NOPB ACTIVE WSON NGF 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 075 LM26LVCISDX-080/NOPB ACTIVE WSON NGF 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 080 LM26LVCISDX-085/NOPB ACTIVE WSON NGF 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 085 LM26LVCISDX-090/NOPB ACTIVE WSON NGF 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 090 LM26LVCISDX-095/NOPB ACTIVE WSON NGF 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 095 LM26LVCISDX-100/NOPB ACTIVE WSON NGF 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 100 LM26LVCISDX-105/NOPB ACTIVE WSON NGF 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 105 LM26LVCISDX-110/NOPB ACTIVE WSON NGF 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 110 LM26LVCISDX-115/NOPB ACTIVE WSON NGF 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 115 LM26LVCISDX-120/NOPB ACTIVE WSON NGF 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 120 LM26LVCISDX-125/NOPB ACTIVE WSON NGF 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 125 Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 17-Jul-2015 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LM26LVCISDX-130/NOPB ACTIVE WSON NGF 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 130 LM26LVCISDX-135/NOPB ACTIVE WSON NGF 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 135 LM26LVCISDX-140/NOPB ACTIVE WSON NGF 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 140 LM26LVCISDX-145/NOPB ACTIVE WSON NGF 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 145 LM26LVCISDX-150/NOPB ACTIVE WSON NGF 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 150 150 LM26LVQISD-130/NOPB ACTIVE WSON NGF 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 150 Q30 LM26LVQISD-135/NOPB ACTIVE WSON NGF 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 150 Q35 LM26LVQISDX-130/NOPB ACTIVE WSON NGF 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 150 Q30 LM26LVQISDX-135/NOPB ACTIVE WSON NGF 6 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 150 Q35 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 3 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 17-Jul-2015 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LM26LV, LM26LV-Q1 : * Catalog: LM26LV * Automotive: LM26LV-Q1 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 4 PACKAGE MATERIALS INFORMATION www.ti.com 10-Sep-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM26LVCISD-050/NOPB WSON NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISD-060/NOPB WSON NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISD-065/NOPB WSON NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISD-070/NOPB WSON NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISD-075/NOPB WSON NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISD-080/NOPB WSON NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISD-085/NOPB WSON NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISD-090/NOPB WSON NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISD-095/NOPB WSON NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISD-100/NOPB WSON NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISD-105/NOPB WSON NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISD-110/NOPB WSON NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISD-115/NOPB WSON NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISD-120/NOPB WSON NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISD-125/NOPB WSON NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISD-130/NOPB WSON NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISD-135/NOPB WSON NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISD-140/NOPB WSON NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 10-Sep-2015 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM26LVCISD-145/NOPB WSON NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISD-150/NOPB WSON NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISDX-050/NOPB WSON NGF 6 4500 330.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISDX-060/NOPB WSON NGF 6 4500 330.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISDX-065/NOPB WSON NGF 6 4500 330.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISDX-070/NOPB WSON NGF 6 4500 330.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISDX-075/NOPB WSON NGF 6 4500 330.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISDX-080/NOPB WSON NGF 6 4500 330.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISDX-085/NOPB WSON NGF 6 4500 330.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISDX-090/NOPB WSON NGF 6 4500 330.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISDX-095/NOPB WSON NGF 6 4500 330.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISDX-100/NOPB WSON NGF 6 4500 330.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISDX-105/NOPB WSON NGF 6 4500 330.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISDX-110/NOPB WSON NGF 6 4500 330.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISDX-115/NOPB WSON NGF 6 4500 330.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISDX-120/NOPB WSON NGF 6 4500 330.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISDX-125/NOPB WSON NGF 6 4500 330.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISDX-130/NOPB WSON NGF 6 4500 330.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISDX-135/NOPB WSON NGF 6 4500 330.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISDX-140/NOPB WSON NGF 6 4500 330.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISDX-145/NOPB WSON NGF 6 4500 330.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVCISDX-150/NOPB WSON NGF 6 4500 330.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVQISD-130/NOPB WSON NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVQISD-135/NOPB WSON NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVQISDX-130/NOP B WSON NGF 6 4500 330.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 LM26LVQISDX-135/NOP B WSON NGF 6 4500 330.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 10-Sep-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM26LVCISD-050/NOPB WSON NGF 6 1000 210.0 185.0 35.0 LM26LVCISD-060/NOPB WSON NGF 6 1000 210.0 185.0 35.0 LM26LVCISD-065/NOPB WSON NGF 6 1000 210.0 185.0 35.0 LM26LVCISD-070/NOPB WSON NGF 6 1000 210.0 185.0 35.0 LM26LVCISD-075/NOPB WSON NGF 6 1000 210.0 185.0 35.0 LM26LVCISD-080/NOPB WSON NGF 6 1000 210.0 185.0 35.0 LM26LVCISD-085/NOPB WSON NGF 6 1000 210.0 185.0 35.0 LM26LVCISD-090/NOPB WSON NGF 6 1000 210.0 185.0 35.0 LM26LVCISD-095/NOPB WSON NGF 6 1000 210.0 185.0 35.0 LM26LVCISD-100/NOPB WSON NGF 6 1000 210.0 185.0 35.0 LM26LVCISD-105/NOPB WSON NGF 6 1000 210.0 185.0 35.0 LM26LVCISD-110/NOPB WSON NGF 6 1000 210.0 185.0 35.0 LM26LVCISD-115/NOPB WSON NGF 6 1000 210.0 185.0 35.0 LM26LVCISD-120/NOPB WSON NGF 6 1000 210.0 185.0 35.0 LM26LVCISD-125/NOPB WSON NGF 6 1000 210.0 185.0 35.0 LM26LVCISD-130/NOPB WSON NGF 6 1000 210.0 185.0 35.0 LM26LVCISD-135/NOPB WSON NGF 6 1000 210.0 185.0 35.0 LM26LVCISD-140/NOPB WSON NGF 6 1000 210.0 185.0 35.0 LM26LVCISD-145/NOPB WSON NGF 6 1000 210.0 185.0 35.0 LM26LVCISD-150/NOPB WSON NGF 6 1000 210.0 185.0 35.0 Pack Materials-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 10-Sep-2015 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM26LVCISDX-050/NOPB WSON NGF 6 4500 367.0 367.0 35.0 LM26LVCISDX-060/NOPB WSON NGF 6 4500 367.0 367.0 35.0 LM26LVCISDX-065/NOPB WSON NGF 6 4500 367.0 367.0 35.0 LM26LVCISDX-070/NOPB WSON NGF 6 4500 367.0 367.0 35.0 LM26LVCISDX-075/NOPB WSON NGF 6 4500 367.0 367.0 35.0 LM26LVCISDX-080/NOPB WSON NGF 6 4500 367.0 367.0 35.0 LM26LVCISDX-085/NOPB WSON NGF 6 4500 367.0 367.0 35.0 LM26LVCISDX-090/NOPB WSON NGF 6 4500 367.0 367.0 35.0 LM26LVCISDX-095/NOPB WSON NGF 6 4500 367.0 367.0 35.0 LM26LVCISDX-100/NOPB WSON NGF 6 4500 367.0 367.0 35.0 LM26LVCISDX-105/NOPB WSON NGF 6 4500 367.0 367.0 35.0 LM26LVCISDX-110/NOPB WSON NGF 6 4500 367.0 367.0 35.0 LM26LVCISDX-115/NOPB WSON NGF 6 4500 367.0 367.0 35.0 LM26LVCISDX-120/NOPB WSON NGF 6 4500 367.0 367.0 35.0 LM26LVCISDX-125/NOPB WSON NGF 6 4500 367.0 367.0 35.0 LM26LVCISDX-130/NOPB WSON NGF 6 4500 367.0 367.0 35.0 LM26LVCISDX-135/NOPB WSON NGF 6 4500 367.0 367.0 35.0 LM26LVCISDX-140/NOPB WSON NGF 6 4500 367.0 367.0 35.0 LM26LVCISDX-145/NOPB WSON NGF 6 4500 367.0 367.0 35.0 LM26LVCISDX-150/NOPB WSON NGF 6 4500 367.0 367.0 35.0 LM26LVQISD-130/NOPB WSON NGF 6 1000 210.0 185.0 35.0 LM26LVQISD-135/NOPB WSON NGF 6 1000 210.0 185.0 35.0 LM26LVQISDX-130/NOPB WSON NGF 6 4500 367.0 367.0 35.0 LM26LVQISDX-135/NOPB WSON NGF 6 4500 367.0 367.0 35.0 Pack Materials-Page 4 MECHANICAL DATA NGF0006A www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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