GNDEN NR
IN OUT
TPS735-Q1
Optional bypass capacitor, C ,
NR
to reduce output noise
and increase PSRR.
Optional input capacitor, C ,
IN
to improve source
impedance, noise, and PSRR.
V
V
IN
EN
2.2 µF
Ceramic
VOUT
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TPS735-Q1
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TPS735-Q1 500-mA, Low Quiescent Current, Low-Noise, High PSRR,
Low-Dropout Linear Regulator
1 Features 2 Applications
1• Qualified for Automotive Applications • Automotive Infotainment
• AEC-Q100 Qualified With the Following Results: • Navigation Systems
• WiFi, WiMax Modules
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range • Telematics Systems
– Device HBM ESD Classification Level 2 • Microprocessor Power
– Device CDM ESD Classification Level C4B 3 Description
• Input Voltage: 2.7 V to 6.5 V The TPS735-Q1 family of low-dropout (LDO), low-
• 500-mA Low-Dropout Regulator with EN power linear regulators offers excellent ac
• Low IQ: 46 μAperformance with very low ground current. High
• Multiple Output Voltage Versions Available: power-supply rejection ratio (PSRR), low noise, fast
start-up, and excellent line and load transient
– Fixed Outputs of 1 V to 4.3 V responses are provided while consuming a very low
– Adjustable Outputs from 1.25 V to 6 V 46 μA (typical) ground current.
• High PSRR: 68 dB at 1 kHz The TPS735-Q1 family of devices is stable with
• Low Noise: 13.2 μVRMS ceramic capacitors and uses an advanced BiCMOS
• Fast Startup Time: 45 μsfabrication process to yield a typical dropout voltage
of 280 mV at 500-mA output. The TPS735-Q1 family
• Stable with a Low-ESR, 2-μF Output Capacitor of devices uses a precision voltage reference and
• Excellent Load and Line Transient Response feedback loop to achieve overall accuracy of 2%
• 2% Overall Accuracy (VOUT > 2.2 V) over all load, line, process, and
(Load, Line, Temperature, VOUT > 2.2 V) temperature variations. This family of devices is fully
specified from TA= –40°C to 125°C and is offered in
• Low Dropout: 280 mV at 500 mA a low-profile, 3-mm × 3-mm SON package.
• 3-mm × 3-mm SON-8 Packages
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TPS735-Q1 SON (8) 3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS735-Q1
SBVS252A –OCTOBER 2014–REVISED JANUARY 2015
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Table of Contents
8.1 Application Information............................................ 11
1 Features.................................................................. 18.2 Typical Application.................................................. 11
2 Applications ........................................................... 19 Power-Supply Recommendations...................... 14
3 Description............................................................. 110 Layout................................................................... 14
4 Revision History..................................................... 210.1 Layout Guidelines ................................................. 14
5 Pin Configuration and Functions......................... 310.2 Layout Example .................................................... 14
6 Specifications......................................................... 410.3 Thermal Protection................................................ 15
6.1 Absolute Maximum Ratings ...................................... 410.4 Package Mounting ................................................ 15
6.2 ESD Ratings.............................................................. 410.5 Power Dissipation ................................................. 15
6.3 Recommended Operating Conditions....................... 410.6 Estimating Junction Temperature ......................... 16
6.4 Thermal Information.................................................. 411 Device and Documentation Support................. 18
6.5 Electrical Characteristics........................................... 511.1 Device Support...................................................... 18
6.6 Typical Characteristics.............................................. 611.2 Documentation Support ........................................ 18
7 Detailed Description.............................................. 811.3 Trademarks........................................................... 18
7.1 Overview................................................................... 811.4 Electrostatic Discharge Caution............................ 18
7.2 Functional Block Diagram......................................... 811.5 Glossary................................................................ 18
7.3 Feature Description................................................... 912 Mechanical, Packaging, and Orderable
7.4 Device Functional Modes........................................ 10 Information ........................................................... 18
8 Application and Implementation ........................ 11
4 Revision History
Changes from Original (October 2014) to Revision A Page
• Made changes to product preview document......................................................................................................................... 1
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8
7
6
5
OUT
NC
NR/FB
GND
IN
NC
NC
EN
1
2
3
4
Exposed
Thermal Pad
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SBVS252A –OCTOBER 2014–REVISED JANUARY 2015
5 Pin Configuration and Functions
DRB Package
8-Pin SON With Exposed Thermal Pad
Top View
NC = No internal connection.
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown
EN 5 I mode. The EN pin can be connected to the IN pin if not used.
This pin is only available for the adjustable version. The FB pin is the input to the control-loop error amplifier,
FB 3 I and is used to set the output voltage of the device.
GND 4 — Ground
IN 8 I Input supply
NC 2, 6, 7 — Not internally connected
This pin is only available for the fixed voltage versions. Connecting an external capacitor to this pin
NR 3 — bypasses noise generated by the internal band gap and allows the output noise to be reduced to very low
levels. The maximum recommended capacitor is 0.01 µF.
This pin is the output of the regulator. A small 2-µF ceramic capacitor is required from this pin to ground to
OUT 1 O assure stability.
Exposed thermal — The pad must be tied to the GND pin.
pad
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6 Specifications
6.1 Absolute Maximum Ratings
At –40°C ≤TJand TA≤125°C (unless otherwise noted). All voltages are with respect to GND.(1)
MIN MAX UNIT
VIN –0.3 7 V
VEN –0.3 VIN + 0.3 V
Voltage VFB –0.3 1.6 V
VOUT –0.3 VIN + 0.3 V
Current IOUT Internally limited A
Continuous total power dissipation Continuous, PD(tot) See the Power Dissipation section
Operating junction temperature, TJ–40 150 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed as absolute maximum ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated as recommended operating conditions is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings VALUE UNIT
Human body model (HBM), per AEC Q100-002(1) ±2000
V(ESD) Electrostatic discharge Corner pins (1, 4, 5, and 8) ±750 V
Charged device model (CDM), per
AEC Q100-011 Other pins ±500
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VIN Input voltage 2.7 6.5 V
VOUT Output voltage VFB 6 V
IOUT Output current(1) 0 500 mA
TAOperating free-air temperature –40 125 °C
(1) When operating at TJnear 125°C, IOUT(min) is 500 µA.
6.4 Thermal Information TPS735-Q1
THERMAL METRIC(1) DRB (SON) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 54.1
RθJC(top) Junction-to-case (top) thermal resistance 71.0
RθJB Junction-to-board thermal resistance 28.4 °C/W
ψJT Junction-to-top characterization parameter 2.3
ψJB Junction-to-board characterization parameter 28.5
RθJC(bot) Junction-to-case (bottom) thermal resistance 9.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
Over operating temperature range (–40°C ≤TJ, TA≤125°C), VIN = VOUTnom + 0.5 V or 2.7 V (whichever is greater), IOUT =
1 mA, VEN = VIN, COUT = 2.2 μF, and CNR = 0.01 μF, unless otherwise noted.
For the adjustable version (TPS73501-Q1), VOUT = 3 V. Typical values are at TA= 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage(1) 2.7 6.5 V
VFB Internal reference (TPS73501-Q1) TJ= 25°C 1.196 1.208 1.220 V
Output voltage range
VOUT VFB 6 V
(TPS73501-Q1)
VOUT > 2.2 V –2% ±1% 2%
1 mA ≤IOUT ≤500 mA,
DC output accuracy(1) VOUT + 0.5 V ≤VIN < 6.5 V VOUT ≤2.2 V –3% ±1% 3%
ΔVOUT(ΔVIN) Line regulation(1) VOUTnom + 0.5 V ≤VIN ≤6.5 V 0.02 %/V
ΔVOUT(ΔIOUT) Load regulation 500 µA ≤IOUT ≤500 mA 0.005 %/mA
Dropout voltage(2)
VDO IOUT = 500 mA 280 500 mV
(VIN = VOUTnom – 0.1 V)
VOUT = 0.9 × VOUTnom, VIN = VOUTnom + 0.9 V,
ILIM Output current limit 800 1170 1900 mA
VIN ≥2.7 V
IGND Ground pin current 10 mA ≤IOUT ≤500 mA 45 65 μA
ISHDN Shutdown current VEN ≤0 V 0.15 1 μA
Feedback pin current
IFB VOUTnom = 1.2 V –0.5 0.5 μA
(TPS73501-Q1)
f = 100 Hz 60 dB
VIN = 3.85 V, VOUT = 2.85 V, f = 1k Hz 68 dB
PSRR Power-supply rejection ratio CNR = 0.01 µF, f = 10 kHz 41 dB
IOUT = 100 mA f = 100 kHz 21 dB
CNR = 0.01 μF 11 × VOUT μVRMS
BW = 10 Hz to
VnOutput noise voltage 100 kHz, VOUT = 2.8 V CNR = none 95 × VOUT μVRMS
CNR = none 45 μs
CNR = 0.001 μF 45 μs
tSTR Startup time CNR = 0.01 μF 50 μs
CNR = 0.047 μF 50 μs
VEN(HI) Enable high (enabled) 1.2 V
VEN(LO) Enable low (shutdown) 0.4 V
IEN(HI) Enable pin current, enabled VEN = VIN = 6.5 V 0.03 1 μA
Shutdown, temperature increasing 165 °C
Tsd Thermal shutdown temperature Reset, temperature decreasing 145 °C
UVLO Undervoltage lockout VIN rising 1.9 2.2 2.65 V
Vhys Hysteresis VIN falling 70 mV
(1) Minimum VIN = VOUT + VDO or 2.7 V, whichever is greater.
(2) VDO is not measured for this family of devices with VOUTnom < 2.8 V because the minimum VIN = 2.7 V.
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60
50
40
30
20
10
0
Current on the GND Pin ( A)m
0 50 100 150 200 250 300 350 400 450 500
Output Current (mA)
T = 25°C
J
T = 85°C
J
T = 125°C
J
T = 0°C
J
T = –40°C
J
500
450
400
350
300
250
200
150
100
50
0
Current on the GND Pin (nA)
-40 -25 -10 5 20 35 50 65 80 95 110 125
Junction Temperature ( )°C
VIN = 3.3 V
VIN = 5 V
V = 6.5 V
IN
2.55
2.54
2.53
2.52
2.51
2.5
2.49
2.48
2.47
2.46
2.45
Output Voltage (V)
0 50 100 150 200 250 300 350 400 450 500
Load (mA)
T = 25°C
J
T = 85°C
J
T = 125°C
J
T = 0°C
J
T = –40°C
J
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
-
-
-
-
-
Change in Output Voltage (%)
3 3.5 4 4.5 5 5.5 6 6.5
Input Voltage (V)
T = 25°C
J
T = 85°C
J
T = 125°C
J
T = 0°C
J
T = –40°C
J
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
-
-
-
-
-
Change in Output Voltage (%)
3 3.5 4 4.5 5 5.5 6 6.5
Input Voltage (V)
T = 25°C
J
T = 85°C
J
T = 125°C
J
T = 0°C
J
T = –40°C
J
TPS735-Q1
SBVS252A –OCTOBER 2014–REVISED JANUARY 2015
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6.6 Typical Characteristics
Over operating temperature range (–40°C ≤TJ, TA≤125°C), VIN = VOUTnom + 0.5 V or 2.7 V (whichever is greater), IOUT =
1 mA, VEN = VIN, COUT = 2.2 μF, and CNR = 0.01 μF, unless otherwise noted. TA= 25°C, unless otherwise noted.
IOUT = 100 mA
IOUT = 100 mA
Figure 2. TPS73525-Q1 Line Regulation
Figure 1. TPS73501-Q1 Line Regulation
The y-axis range is ±2% of 2.8 V The y-axis range is ±2% of 2.5 V
Figure 3. TPS73501-Q1 Load Regulation Figure 4. TPS73525-Q1 Load Regulation
VEN = 0.4 V
Figure 6. TPS73525-Q1 Ground Pin Current (Disable) vs
Figure 5. TPS73525-Q1 Ground Pin Current vs Temperature
Output Current
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140
120
100
80
60
40
20
0
Total Noise ( V )mRMS
0.01 0.1 110
Capacitance on the NR Pin (nF)
30
25
20
15
10
5
0
Total Noise ( V )mRMS
0510 15 20 25
Output Capacitance ( F)m
10 100 1k 10k 100k 1M 10M
Frequency (Hz)
90
80
70
60
50
40
30
20
10
0
PSRR (dB)
IOUT = 200 mA
IOUT = 100 mA
I = 1 mA
OUT
IOUT = 500 mA
IOUT = 250 mA
10 100 1k 10k 100k 1M 10M
Frequency (Hz)
90
80
70
60
50
40
30
20
10
0
PSRR (dB)
IOUT = 200 mA
IOUT = 100 mA
IOUT = 1 mA
IOUT = 500 mA
IOUT = 250 mA
400
350
300
250
200
150
100
50
0
Dropout Voltage (mV)
0 50 100 150 200 250 300 350 400 450 500
Output Current (mA)
T = 25°C
J
T = 85°C
J
T = 125°C
J
T = 0°C
J
T = –40°C
J
10 100 1k 10k 100k 1M 10M
Frequency (Hz)
90
80
70
60
50
40
30
20
10
0
PSRR (dB)
IOUT = 200 mA
IOUT = 100 mA
IOUT = 1 mA
IOUT = 500 mA
IOUT = 250 mA
TPS735-Q1
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SBVS252A –OCTOBER 2014–REVISED JANUARY 2015
Typical Characteristics (continued)
Over operating temperature range (–40°C ≤TJ, TA≤125°C), VIN = VOUTnom + 0.5 V or 2.7 V (whichever is greater), IOUT =
1 mA, VEN = VIN, COUT = 2.2 μF, and CNR = 0.01 μF, unless otherwise noted. TA= 25°C, unless otherwise noted.
Figure 7. TPS73501-Q1 Dropout Voltage vs Output Current Figure 8. Power-Supply Ripple Rejection vs Frequency
(VIN – VOUT = 1 V)
Figure 9. Power-Supply Ripple Rejection vs Frequency Figure 10. Power-Supply Ripple Rejection vs Frequency
(VIN – VOUT = 0.5 V) (VIN – VOUT = 0.3 V)
CNR = 0.01 µF, IOUT = 1 mA
Figure 12. TPS73525-Q1 RMS Noise vs COUT
Figure 11. TPS73525-Q1 RMS Noise vs CNR
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Thermal
Shutdown
UVLO
Current
Limit
3.3 M
Overshoot
Detect
500 k
1.208-V
Bandgap
IN
EN
FB
OUT
GND
400
Thermal
Shutdown
UVLO
Current
Limit
2 mA
Overshoot
Detect
500 k
Quickstart
1.208-V
Bandgap(1)
IN
EN
NR
OUT
GND
400
TPS735-Q1
SBVS252A –OCTOBER 2014–REVISED JANUARY 2015
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7 Detailed Description
7.1 Overview
The TPS735-Q1 family of low dropout (LDO) regulators combines the high performance required by many radio
frequency (RF) and precision analog applications with ultra-low current consumption. High PSRR is provided by
a high-gain, high-bandwidth error loop with good supply rejection and very low headroom (VIN – VOUT). Fixed
voltage versions provide a noise reduction pin to bypass noise generated by the band-gap reference and to
improve PSRR. A quick-start circuit fast-charges this capacitor at startup. The combination of high performance
and low ground current also make the TPS735-Q1 family of devices an excellent choice for portable applications.
All versions have thermal and overcurrent protection and are fully specified from –40°C ≤TJ, TA≤125°C.
7.2 Functional Block Diagram
NOTE: Fixed voltage versions between 1 V to 1.2 V have a 1-V band-gap circuit instead of a 1.208-V band-gap
circuit.
Figure 13. Fixed Voltage Versions
Figure 14. Adjustable Voltage Versions
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7.3 Feature Description
7.3.1 Internal Current-Limit
The TPS735-Q1 internal current-limit helps protect the regulator during fault conditions. During current-limit, the
output sources a fixed amount of current that is largely independent of the output voltage. For reliable operation,
do not operate the device in current-limit for extended periods of time.
The PMOS pass element in the TPS735-Q1 family of devices has a built-in body diode that conducts current
when the voltage at the OUT pin exceeds the voltage at the IN pin. This current is not limited, so if extended
reverse voltage operation is anticipated, external limiting can be appropriate.
7.3.2 Shutdown
The enable pin (EN) is active high and is compatible with standard and low-voltage TTL-CMOS levels. When
shutdown capability is not required, the EN pin can be connected to the IN pin.
7.3.3 Dropout Voltage
The TPS735-Q1 family of devices uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is
less than the dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-
output resistance (R(IN/OUT)) of the PMOS pass element. VDO scales with the output current because the PMOS
device behaves like a resistor in dropout.
As with any linear regulator, PSRR and transient response are degraded when (VIN – VOUT) approaches dropout.
This effect is shown in the Typical Characteristics section (see Figure 8 through Figure 10).
7.3.4 Startup and Noise Reduction Capacitor
Fixed voltage versions of the TPS735-Q1 family of devices use a quick-start circuit to fast-charge the noise
reduction capacitor, CNR, if present (see the Functional Block Diagram section). This architecture allows the
combination of very-low output noise and fast startup times. The NR pin is high impedance so a low-leakage CNR
capacitor must be used. Most ceramic capacitors are appropriate in this configuration. A high-quality, COG-type
(NPO) dielectric ceramic capacitor is recommended for CNR when used in environments where abrupt changes in
temperature can occur.
Note that for fastest start-up, apply VIN first, then drive the enable pin (EN) high. If the EN pin is tied to the IN pin,
start-up is somewhat slower. Refer to the Typical Application section (see Figure 17 and Figure 18). The quick-
start switch is closed for approximately 135 μs. To ensure that CNR is charged during the quick-start time, use a
capacitor with a value of no more than 0.01 μF.
7.3.5 Transient Response
As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude
but increases the transient response duration. In the adjustable version, adding CFB between the OUT and FB
pins improves stability and transient response performance. The transient response of the TPS735-Q1 family of
devices is enhanced by an active pulldown that engages when the output overshoots by approximately 5% or
more when the device is enabled. When enabled, the pull-down device behaves like a 400-Ωresistor to ground.
7.3.6 Undervoltage Lockout (UVLO)
The TPS735-Q1 family of devices uses an undervoltage lockout circuit to keep the output shut off until the
internal circuitry is operating properly. The UVLO circuit has a deglitch feature so that the UVLO typically ignores
undershoot transients on the input if the transients are less than 50 μs in duration.
7.3.7 Minimum Load
The TPS735-Q1 family of devices is stable and well-behaved with no output load. To meet the specified
accuracy, a minimum load of 500 μA is required. Below 500 μA and at junction temperatures near 125°C, the
output can drift up enough to cause the output pulldown to turn on. The output pulldown limits voltage drift to 5%
(typically) but ground current can increase by approximately 50 μA. In most applications, the junction does not
reach high temperatures at light loads because very little power is dissipated. Therefore, the specified ground
current is valid at no load in most applications.
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7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
• The input voltage has previously exceeded the UVLO voltage and has not decreased below the UVLO
threshold minus Vhys.
• The input voltage is greater than the nominal output voltage added to the dropout voltage.
• The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased
below the enable falling threshold.
• The output current is less than the current limit.
• The device junction temperature is less than the thermal shutdown temperature.
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this condition, the output
voltage is equal to the input voltage minus the dropout voltage. The transient performance of the device is
significantly degraded because the pass device is in a triode state and the LDO behaves like a resistor. Line or
load transients in dropout can result in large output voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
• The input voltage is less than the UVLO threshold minus Vhys, or has not yet exceeded the UVLO threshold.
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
• The device junction temperature is greater than the thermal shutdown temperature.
Table 1 shows the conditions that lead to the different modes of operation.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE VIN VEN IOUT TJ
Normal mode VIN > VOUTnom + VDO and VIN > UVLO VEN > VEN(HI) IOUT < ILIM TJ< 165°C
Dropout mode UVLO < VIN < VOUTnom + VDO VEN > VEN(HI) — TJ< 165°C
Disabled mode
(any true condition VIN < UVLO – Vhys VEN < VEN(LO) — TJ> 165°C
disables the device)
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GNDEN FB
IN OUT
Optional input capacitor, CIN,
to improve source
impedance, noise, and PSRR.
TPS73501-Q1 2.2 µF
Ceramic
VIN
VEN
R1
R2
CFB
VOUT
(R1 + R2)
R2
VOUT(nom) = × 1.208 V
GNDEN NR
IN OUT
TPS735-Q1
Optional bypass capacitor, C ,
NR
to reduce output noise
and increase PSRR.
Optional input capacitor, C ,
IN
to improve source
impedance, noise, and PSRR.
V
V
IN
EN
2.2 µF
Ceramic
VOUT
TPS735-Q1
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS735-Q1 family of automotive-qualified LDO regulators provides a design with an ultra-low noise, high
PSRR, low-dropout linear regulation with a very small ground current (46 µA, typical).
The devices are stable with ceramic capacitors, and have a dropout voltage of 280 mV at the full output rating of
500 mA. The features of the TPS735-Q1 family of devices enables the LDO regulators to be suitable for a wide
variety of applications, with minimal design complexity.
8.2 Typical Application
Figure 15 shows the basic circuit connections for fixed-voltage models. Figure 16 gives the connections for the
adjustable output version (TPS73501-Q1). Use the equation in Figure 16 to calculate the value of R1 and R2 for
any output voltage.
Figure 15. Typical Application Circuit for Fixed Voltage Versions
Figure 16. Typical Application Circuit for Adjustable Voltage Versions
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Typical Application (continued)
8.2.1 Design Requirements
8.2.1.1 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, connecting a 0.1-μF to 1-μF low-equivalent series-
resistance (ESR) capacitor across the input supply near the regulator is good analog design practice. This
capacitor counteracts reactive input sources and improves transient response and ripple rejection. A higher-value
capacitor can be necessary if large, fast, rise-time load transients are anticipated or if the device is located
several inches from the power source. If source impedance is not sufficiently low, a 0.1-μF input capacitor can be
necessary to ensure stability.
The TPS735-Q1 family of devices is designed to be stable with standard ceramic output capacitors of values
2μF or larger. X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR
over temperature. Maximum ESR of the output capacitor is < 1 Ωand, therefore, the output capacitor type must
either be ceramic or conductive polymer electrolytic.
8.2.1.2 Feedback Capacitor Requirements (TPS73501-Q1 only)
The feedback capacitor (CFB), shown in Figure 16, is required for stability. For a parallel combination of R1 and
R2 equal to 250 kΩ, any value between 3 pF to 1 nF can be used. Fixed voltage versions have an internal 30-pF
feedback capacitor that is quick-charged at start-up. Larger value capacitors also improve noise slightly. The
TPS73501-Q1 device is stable in unity-gain configurations (the OUT pin is tied to the FB pin) without CFB.
8.2.2 Detailed Design Procedure
8.2.2.1 Output Noise
In most LDO regulators, the band gap is the dominant noise source. If a noise-reduction capacitor (CNR) is used
with the TPS735-Q1 family of devices, the band gap does not contribute significantly to noise. Instead, noise is
dominated by the output-resistor divider and the error-amplifier input. To minimize noise in a given application,
use a 0.01-μF noise reduction capacitor. For the adjustable version, smaller value resistors in the output resistor
divider reduce noise. A parallel combination that gives 2 μA of divider current has the same noise performance
as a fixed voltage version with a CNR. To further optimize noise, ESR of the output capacitor can be set to
approximately 0.2 Ω. This configuration maximizes phase margin in the control loop, reducing the total output
noise up to 10%. The maximum recommended capacitor is 0.01 µF.
Equation 1 calculates the approximate integrated output noise from 10 Hz to 100 kHz with a CNR value of
0.01 µF.
Vn(µVRMS) = 11 (µVRMS / V) × VOUT (V) (1)
The TPS73501-Q1 adjustable version does not have the noise-reduction pin available, so ultra-low noise
operation is not possible. Noise can be minimized according to the previously listed recommendations.
12 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated
Product Folder Links: TPS735-Q1
10 ms/div
50 mV/div
50 mV/div
50 mV/div
0.5 V/div
VOUT
C = 470 F OSCON
OUT m
C = 10 F
OUT m
C = 2.2 F
OUT m
4 V
3 V
VIN
VOUT
10 ms/div
7
6
5
4
3
2
1
0
1-
Voltage (V)
VIN EN
= V
VOUT
10 ms/div
200 mV/div
200 mV/div
200 mV/div
500 mA/div
C = 470 F OSCON
OUT m
C = 10 F
OUT m
C = 2.2 F
OUT m
500 mA
1 mA
IOUT
VOUT
10 ms/div
3.5
3
2.5
2
1.5
1
0.5
0
0.5-
Voltage (V)
VEN
VOUT,C = 2.2 F
OUT m
VOUT,C = 10 F
OUT m
10 ms/div
3.5
3
2.5
2
1.5
1
0.5
0
0.5-
Voltage (V)
VEN
VOUT OUT
C = 2.2 F,m
VOUT OUT
C = 10 F,m
TPS735-Q1
www.ti.com
SBVS252A –OCTOBER 2014–REVISED JANUARY 2015
Typical Application (continued)
8.2.3 Application Curves
At VIN = VOUTnom + 0.5 V or 2.7 V (whichever is greater), IOUT = 1 mA, VEN = VIN, COUT = 2.2 μF, CNR = 0.01 μF,
and TA= 25°C, unless otherwise noted.
Figure 17. TPS73525-Q1 Turn-On Response (VIN = VEN) Figure 18. TPS73525-Q1 Turn-On Response Using EN
VIN = 3 V
RL= 5 Ω
Figure 20. TPS73525-Q1 Load Transient Response
Figure 19. TPS73525-Q1 Power-Up and Power-Down
(VIN = VEN)
Figure 21. TPS73525-Q1 Line Transient Response
Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: TPS735-Q1
Thermal
Pad
1
2
3
4
8
7
6
5
OUT
NC
NR/FB
GND
IN
NC
NC
EN
CNR(1)
COUT(1)
CIN(1)
Input GND
Plane
Output GND
Plane
VOUT
VIN
TPS735-Q1
SBVS252A –OCTOBER 2014–REVISED JANUARY 2015
www.ti.com
9 Power-Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.7 V and 6.5 V. The input
voltage range must provide adequate headroom in order for the device to have a regulated output. This input
supply must be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help
improve output noise.
10 Layout
10.1 Layout Guidelines
For best overall performance, place all circuit components on the same side of the circuit board and as near as
practical to the respective LDO pin connections. Place ground return connections to the input and output
capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side,
copper surface. The use of vias and long traces to create LDO component connections is strongly discouraged
and negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics,
and thereby reduces load-current transients, minimizes noise, and increases circuit stability. A ground reference
plane is also recommended and is either embedded in the printed circuit board (PCB) itself or located on the
bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output
voltage, shields the LDO from noise, and behaves similar to a thermal plane to spread (or sink) heat from the
LDO device when connected to the PowerPAD™. In most applications, this ground plane is necessary to meet
thermal requirements.
10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
To improve ac performance (such as PSRR, output noise, and transient response), designing the board with
separate ground planes for VIN and VOUT is recommended, with each ground plane connected only at the GND
pin of the device. In addition, the ground connection for the bypass capacitor must connect directly to the GND
pin of the device.
10.2 Layout Example
(1) CIN and COUT are 0603 capacitors and CNR is a 0402 capacitor. The footprint is shown to scale with package size.
Figure 22. TPS735-Q1 Fixed Version Layout Reference Diagram
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Product Folder Links: TPS735-Q1
A
JA D
125 C T
RP
T
q
TPS735-Q1
www.ti.com
SBVS252A –OCTOBER 2014–REVISED JANUARY 2015
10.3 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 165°C, allowing the
device to cool. When the junction temperature cools to approximately 145°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit can cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a
result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, limit junction temperature to 125°C maximum. To estimate the thermal margin in
a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good reliability, trigger thermal protection at least 40°C above
the maximum expected ambient condition of a particular application. This configuration produces a worst-case
junction temperature of 125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS735-Q1 family of devices is designed to protect against overload
conditions. This protection circuitry is not intended to replace proper heatsinking. Continuously running the
TPS735-Q1 family of devices into thermal shutdown degrades device reliability.
10.4 Package Mounting
Solder pad footprint recommendations for the TPS735-Q1 family of devices are available from the Texas
Instruments web site at www.ti.com.
10.5 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the PCB layout. The PCB area around the device that is free of other components moves the heat from the
device to the ambient air. Performance data for JEDEC low- and high-K boards are given in the Thermal
Information table. Using heavier copper increases the effectiveness in removing heat from the device. The
addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation is equal to the product of the
output current and the voltage drop across the output pass element, as shown in Equation 2.
PD= (VIN – VOUT)×IOUT (2)
NOTE
When the device is used in a condition of high input and low output voltages, PDcan
exceed the junction temperature rating even when the ambient temperature is at room
temperature.
Equation 3 is an example calculation for the power dissipation (PD) of the DRB package.
PD= (6.5 V – 1.2 V) × 500 mA = 2.65 W (3)
Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input
voltage necessary to achieve the required output performance.
On the DRB package, the primary conduction path for heat is through the exposed thermal pad to the PCB. The
pad can be connected to ground or left floating; however, the pad must be attached to an appropriate amount of
copper PCB area to ensure the device does not overheat. The maximum allowable junction-to-ambient thermal
resistance depends on the maximum ambient temperature, maximum device junction temperature, and power
dissipation of the device. Use Equation 4 to calculate the maximum junction-to-ambient thermal resistance.
(4)
Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: TPS735-Q1
1 mm
T on top
of IC
T
T on PCB
surface
B
JT J T JT D
JB J B JB D
: T T P
: T T P
< < u
< < u
160
140
120
100
80
60
40
20
00 1 2 3 4 5 678 9 10
Board Copper Area (in2)
Junction-to-Ambient Thermal
Resistance (°C/W)
TPS735-Q1
SBVS252A –OCTOBER 2014–REVISED JANUARY 2015
www.ti.com
Power Dissipation (continued)
Knowing the maximum RθJA, the minimum amount of PCB copper area needed for appropriate heatsinking can
be estimated using Figure 23.
NOTE: The RθJA value at a board size of 9 in2(that is, 3 in × 3 in) is a JEDEC standard.
Figure 23. RθJA vs Board Size
Figure 23 shows the variation of RθJA as a function of copper area in the board that is connected to the thermal
pad. Figure 23 is intended only as a guideline to demonstrate the effects of heat spreading in the ground plane
and is not to be used to calculate actual thermal performance.
NOTE
When the device is mounted on an application PCB, TI strongly recommends using ΨJT
and ΨJB, as explained in the Estimating Junction Temperature section.
10.6 Estimating Junction Temperature
Using the thermal metrics ΨJT and ΨJB, as shown in the Thermal Information table, the junction temperature can
be estimated with the corresponding formulas (given in Equation 5).
where:
• PDis the power dissipation calculated with Equation 2,
• TTis the temperature at the center-top of the device package, and
• TBis the PCB temperature measured 1 mm away from the device package on the PCB surface (as shown in
Figure 24). (5)
Figure 24. Measuring Points for TTand TB
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Product Folder Links: TPS735-Q1
35
30
25
20
15
10
5
0
JT JB
and ( C/W)°
0 2 46 8 10
Board Copper Area (in2)
51 3 7 9
JT
JB
TPS735-Q1
www.ti.com
SBVS252A –OCTOBER 2014–REVISED JANUARY 2015
Estimating Junction Temperature (continued)
NOTE
Both TTand TBcan be measured on actual application boards using an infrared
thermometer.
For more information about measuring TTand TB, see the application note, Using New Thermal Metrics,
SBVA025.
According to Figure 25, the thermal metrics (ΨJT and ΨJB) have very little dependency on copper area. Using ΨJT
or ΨJB with Equation 5 is a good way to estimate TJby simply measuring TTor TBon an application board.
Figure 25. ΨJT and ΨJB vs Board Size
Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: TPS735-Q1
TPS735-Q1
SBVS252A –OCTOBER 2014–REVISED JANUARY 2015
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Table 2. Device Nomenclature(1)
PRODUCT VOUT
TPS735xx(x)yyyz XX(X) is the nominal output voltage. For output voltages with a resolution of 100 mV, two
digits are used in the ordering number; otherwise, three digits are used (for example, 33 =
3.3 V; 125 = 1.25 V).
YYY is the package designator.
Zis the tape and reel quantity (R = 3000, T = 250).
01 is the adjustable version.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
•IC Package Thermal Metrics,SPRA953
• TPS735EVM-276 User Guide, SLVU256
•Using New Thermal Metrics,SBVA025
11.3 Trademarks
PowerPAD is a trademark of Texas Instruments, Inc.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated family of devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated
Product Folder Links: TPS735-Q1
PACKAGE OPTION ADDENDUM
www.ti.com 7-Apr-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS73501QDRBRQ1 ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 501DRB
TPS73512QDRBRQ1 ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 512DRB
TPS73515QDRBRQ1 ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 515DRB
TPS73518QDRBRQ1 ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 518DRB
TPS73525QDRBRQ1 ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 525DRB
TPS73527QDRBRQ1 ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 527DRB
TPS73530QDRBRQ1 ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 530DRB
TPS73533QDRBRQ1 ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 533DRB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 7-Apr-2017
Addendum-Page 2
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS735-Q1 :
•Catalog: TPS735
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS73501QDRBRQ1 SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73512QDRBRQ1 SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73515QDRBRQ1 SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73518QDRBRQ1 SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73525QDRBRQ1 SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73527QDRBRQ1 SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73530QDRBRQ1 SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73533QDRBRQ1 SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2017
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS73501QDRBRQ1 SON DRB 8 3000 367.0 367.0 35.0
TPS73512QDRBRQ1 SON DRB 8 3000 367.0 367.0 35.0
TPS73515QDRBRQ1 SON DRB 8 3000 367.0 367.0 35.0
TPS73518QDRBRQ1 SON DRB 8 3000 367.0 367.0 35.0
TPS73525QDRBRQ1 SON DRB 8 3000 367.0 367.0 35.0
TPS73527QDRBRQ1 SON DRB 8 3000 367.0 367.0 35.0
TPS73530QDRBRQ1 SON DRB 8 3000 367.0 367.0 35.0
TPS73533QDRBRQ1 SON DRB 8 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2017
Pack Materials-Page 2
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