Description
Designed for pulse width modulated (PWM) control of DC
motors, the A4950 is capable of peak output currents to ±3.5 A
and operating voltages to 40 V.
Input terminals are provided for use in controlling the speed and
direction of a DC motor with externally applied PWM control
signals. Internal synchronous rectification control circuitry is
provided to lower power dissipation during PWM operation.
Internal circuit protection includes overcurrent protection,
motor lead short to ground or supply, thermal shutdown with
hysteresis, undervoltage monitoring of VBB, and crossover-
current protection.
For high ambient operating temperature applications, an
automotive grade device is offered (A4950K). The K grade
device is tested across extended temperature and voltage
ranges to ensure compliance in automotive or industrial
applications.
The A4950 is provided in a low-profile 8-pin SOICN package
with exposed thermal pad (suffix LJ) that is lead (Pb) free, with
100% matte tin leadframe plating.
A4950-DS, Rev. 4
Features and Benefits
• Low RDS(on) outputs
• Overcurrent protection (OCP)
Motor short protection
Motor lead short to ground protection
Motor lead short to battery protection
• Low Power Standby mode
• Adjustable PWM current limit
• Synchronous rectification
• Internal undervoltage lockout (UVLO)
• Crossover-current protection
• A4950K is AEC-Q100 Grade 1 qualified
• Commercial temperature grade (A4950E: –40°C to 85°C )
• Automotive temperature grade (A4950K: –40°C to 125°C)
Full-Bridge DMOS PWM Motor Driver
Package: 8-pin SOICN with exposed
thermal pad (suffix LJ)
Functional Block Diagram
Not to scale
A4950
Control
Logic
LSS
OUT1
OUT2
VBB
IN1
IN2
Charge
Pump
OSC
Disable
Load
Supply
UVLO
VREF
7V
GND
÷
(Optional)
TSD
10
Full-Bridge DMOS PWM Motor Driver
A4950
2
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Terminal List Table
Number Name Function
1 GND Ground
2 IN2 Logic input 2
3 IN1 Logic input 1
4 VREF Analog input
5 VBB Load supply voltage
6 OUT1 DMOS full bridge output 1
7 LSS Power return – sense resistor connection
8 OUT2 DMOS full bridge output 2
– PAD Exposed pad for enhanced thermal dissipation
Pin-out Diagram
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Unit
Load Supply Voltage VBB 40 V
Logic Input Voltage Range VIN –0.3 to 6 V
VREF Input Voltage Range VREF –0.3 to 6 V
Sense Voltage (LSS pin) VS–0.5 to 0.5 V
Motor Outputs Voltage VOUT –2 to 42 V
Output Current IOUT Duty cycle = 100% 3.5 A
Transient Output Current iOUT TW < 500 ns 6 A
Operating Temperature Range TA
Temperature Range E –40 to 85 °C
Temperature Range K –40 to 125 °C
Maximum Junction Temperature TJ(max) 150 °C
Storage Temperature Range Tstg –55 to 150 °C
Selection Guide
Part Number Packing Ambient Operating Temperature, TA
A4950ELJTR-T 3000 pieces per 13-in. reel –40°C to 85°C
A4950KLJTR-T 3000 pieces per 13-in. reel –40°C to 125°C
Thermal Characteristics may require derating at maximum conditions, see application information
Characteristic Symbol Test Conditions* Value Unit
Package Thermal Resistance RJA
On 2-layer PCB with 0.8 in2
. exposed 2-oz. copper each side 62 ºC/W
On 4-layer PCB based on JEDEC standard 35 ºC/W
*Additional thermal information available on the Allegro website.
8
7
6
5
1
2
3
4
OUT2
LSS
OUT1
VBB
GND
IN2
IN1
VREF
PAD
Full-Bridge DMOS PWM Motor Driver
A4950
3
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS Valid for Temperature Range E version at TJ = 25°C and for Temperature Range K
version at TJ = –40°C to 150°C, VBB = 8 to 40 V, unless otherwise specified
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
General
Load Supply Voltage Range VBB 8 – 40 V
RDS(on) Sink + Source Total RDS(on)
IOUT = |2.5 A|, TJ = 25°C – 0.6 0.8
IOUT = |2.5 A|, TJ = 150°C – 1.1 1.5
Load Supply Current IBB
fPWM < 30 kHz – 10 20 mA
Low Power Standby mode – – 10 A
Body Diode Forward Voltage Vf
Source diode, If = –2.5 A – – 1.5 V
Sink diode, If = 2.5 A – – 1.5 V
Logic Inputs
Logic Input Voltage Range
VIN(1) 2.0 – – V
VIN(0) – – 0.8 V
VIN(STANDBY) Low Power Standby mode – – 0.4 V
Logic Input Current IIN(1) VIN = 2.0 V – 40 100 A
IIN(0)V
IN = 0.8 V – 16 40 A
Logic Input Pull-Down Resistance RRRLOGIC(PD) VIN = 0 V = IN1 = IN2 – 50 – k
Input Hysteresis VHYS – 250 550 mV
Timing
Crossover Delay tCOD 50 – 500 ns
VREF Input Voltage Range VREF 0–5V
Current Gain A
V
VREF / ISS
, VREF = 5 V 9.5 – 10.5 V/V
VREF / ISS
, VREF = 2.5 V 9.0 – 10.0 V/V
VREF / ISS
, VREF = 1 V 8.0 – 10.0 V/V
Blank Time tBLANK 234s
Constant Off-time toff 16 25 34 s
Standby Timer tst IN1 = IN2 < VIN(STANDBY) – 1 1.5 ms
Power-Up Delay tpu ––30s
Protection Circuits
UVLO Enable Threshold VBBUVLO VBB increasing 7 7.5 7.95 V
UVLO Hysteresis VBBUVLOhys – 500 – mV
Thermal Shutdown Temperature TJTSD Temperature increasing – 160 – °C
Thermal Shutdown Hysteresis TTSDhys Recovery = TJTSD – TTSDhys –15–°C
Full-Bridge DMOS PWM Motor Driver
A4950
4
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Characteristic Performance
PWM Control Timing Diagram
PWM Control Truth Table
IN1 IN2 10×VS > VREF OUT1 OUT2 Function
0 1 False L H Reverse
1 0 False H L Forward
0 1 True H/L L Chop (mixed decay), reverse
1 0 True L H/L Chop (mixed decay), forward
1 1 False L L Brake (slow decay)
0 0 False Z Z Coast, enters Low Power Standby mode after 1 ms
Note: Z indicates high impedance.
Reverse/
Fast Decay
Reverse/
Slow Decay
Forward/
Fast Decay
Forward/
Slow Decay
GND
GND
+IREG
0 A
-IREG
IN1
IN2
IOUT(x)
VIN(1)
VIN(1)
Full-Bridge DMOS PWM Motor Driver
A4950
5
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Description
Device Operation
The A4950 is designed to operate DC motors. The output drivers
are all low-RDS(on) , N-channel DMOS drivers that feature inter-
nal synchronous rectification to reduce power dissipation. The
current in the output full bridge is regulated with fixed off-time
pulse width modulated (PWM) control circuitry. The IN1 and IN2
inputs allow two-wire control for the bridge.
Protection circuitry includes internal thermal shutdown, and pro-
tection against shorted loads, or against output shorts to ground
or supply. Undervoltage lockout prevents damage by keeping the
outputs off until the driver has enough voltage to operate nor-
mally.
Standby Mode
Low Power Standby mode is activated when both input (INx)
pins are low for longer than 1 ms. Low Power Standby mode
disables most of the internal circuitry, including the charge pump
and the regulator. When the A4950 is coming out of standby
mode, the charge pump should be allowed to reach its regulated
voltage (a maximum delay of 200 s) before any PWM com-
mands are issued to the device.
Internal PWM Current Control
Initially, a diagonal pair of source and sink FET outputs are
enabled and current flows through the motor winding and the
optional external current sense resistor, RS
. When the voltage
across RS equals the comparator trip value, then the current sense
comparator resets the PWM latch. The latch then turns off the
sink and source FETs (Mixed Decay mode).
VREF
The maximum value of current limiting is set by the selection of
RSx and the voltage at the VREF pin. The transconductance func-
tion is approximated by the maximum value of current limiting,
ITripMAX (A), which is set by:
ITripMAX =10 RS
VREF
where VREF is the input voltage on the VREF pin (V) and RS is
the resistance of the sense resistor () on the LSS terminal.
Overcurrent Protection
A current monitor will protect the IC from damage due to output
shorts. If a short is detected, the IC will latch the fault and disable
the outputs. The fault latch can only be cleared by coming out of
Low Power Standby mode or by cycling the power to VBB. Dur-
ing OCP events, Absolute Maximum Ratings may be exceeded
for a short period of time before the device latches.
Shutdown
If the die temperature increases to approximately 160°C, the full
bridge outputs will be disabled until the internal temperature falls
below a hysteresis, TTSDhys , of 15°C. Internal UVLO is present
on VBB to prevent the output drivers from turning-on below the
UVLO threshold.
Braking
The braking function is implemented by driving the device in
Slow Decay mode, which is done by applying a logic high to both
inputs, after a bridge-enable Chop command (see PWM Control
Truth Table). Because it is possible to drive current in both direc-
tions through the DMOS switches, this configuration effectively
shorts-out the motor-generated BEMF, as long as the Chop com-
mand is asserted. The maximum current can be approximated by
VBEMF / RL . Care should be taken to ensure that the maximum
ratings of the device are not exceeded in worse case braking situ-
ations: high speed and high-inertia loads.
Full-Bridge DMOS PWM Motor Driver
A4950
6
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Synchronous Rectification
When a PWM off-cycle is triggered by an internal fixed off-time
cycle, load current will recirculate. The A4950 synchronous rec-
tification feature turns-on the appropriate DMOSFETs during the
current decay, and effectively shorts out the body diodes with the
low RDS(on) driver. This significantly lowers power dissipation.
When a zero current level is detected, synchronous rectification is
turned off to prevent reversal of the load current.
Mixed Decay Operation
The bridges operate in Mixed Decay mode. Referring to the
lower panel of the figure below, as the trip point is reached, the
device goes into fast decay mode for 50% of the fixed off-time
period. After this fast decay portion the device switches to slow
decay mode for the remainder of the off-time. During transitions
from fast decay to slow decay, the drivers are forced off for the
Crossover Delay, tCOD . This feature is added to prevent shoot-
through in the bridge. During this “dead time” portion, synchro-
nous rectification is not active, and the device operates in fast
decay and slow decay only.
Mixed Decay Mode Operation
VPHASE
IOUT
IOUT
+
–
0
See Enlargement A
Enlargement A
tCOD
tCOD
tCOD
Fixed Off-Time, toff = 25 s
Fast Decay Slow Decay
ITrip
0.50 × toff 0.50 × toff
Full-Bridge DMOS PWM Motor Driver
A4950
7
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Application Information
Sense Pin (LSS)
In order to use PWM current control, a low-value resistor is
placed between the LSS pin and ground for current sensing pur-
poses. To minimize ground-trace IR drops in sensing the output
current level, the current sensing resistor should have an indepen-
dent ground return to the star ground point. This trace should be
as short as possible. For low-value sense resistors, the IR drops in
the PCB can be significant, and should be taken into account.
When selecting a value for the sense resistor be sure not to
exceed the maximum voltage on the LSS pin of ±500 mV at
maximum load. During overcurrent events, this rating may be
exceeded for short durations.
Ground
A star ground should be located as close to the A4950 as possible.
The copper ground plane directly under the exposed thermal pad
of the device makes a good location for the star ground point. The
exposed pad can be connected to ground for this purpose.
Layout
The PCB should have a thick ground plane. For optimum
electrical and thermal performance, the A4950 must be soldered
directly onto the board. On the underside of the A4950 package is
an exposed pad, which provides a path for enhanced thermal dis-
sipation. The thermal pad must be soldered directly to an exposed
surface on the PCB in order to achieve optimal thermal conduc-
tion. Thermal vias are used to transfer heat to other layers of the
PCB.
The load supply pin, VBB, should be decoupled with an electro-
lytic capacitor (typically 100 F) in parallel with a lower valued
ceramic capacitor placed as close as practicable to the device.
GND
RS
GND
GND GND
C1
BULK
CAPACITANCE
VBB
OUT2
OUT1
C2
V
BB
1
PAD
A4950
C1 C2
OUT2
LSS
OUT1
VBB
IN2
IN1
VREF
GND
R
S
PCB
Thermal Vias
Trace (2 oz.)
Signal (1 oz.)
Ground (1 oz.)
Thermal (2 oz.)
Solder
A4950
Bill of Materials
Item Reference Value Units Description
1RS 0.25
(for VREF = 5 V, IOUT = 2 A) 2512, 1 W, 1% or better,
carbon film chip resistor
2 C1 0.22 F X5R minimum, 50 V or greater
3 C2 100 F Electrolytic, 50 V or greater
Full-Bridge DMOS PWM Motor Driver
A4950
8
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package LJ, 8-Pin SOICN
with exposed thermal pad
3.30
2
1
8
Reference land pattern layout (reference IPC7351
SOIC127P600X175-9AM); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a multilayer
PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
PCB Layout Reference View
C
1.27
5.602.41
1.75
0.65
2.41 NOM
3.30 NOM
C
SEATING
PLANE
1.27 BSC
GAUGE PLANE
SEATING PLANE
ATerminal #1 mark area
B
C
B
21
8
C
SEATING
PLANE
C0.10
8X
0.25 BSC
1.04 REF
1.70 MAX
For Reference Only; not for tooling use (reference MS-012BA)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
4.90 ±0.10
3.90 ±0.10 6.00 ±0.20
0.51
0.31 0.15
0.00
0.25
0.17
1.27
0.40
8°
0°
Exposed thermal pad (bottom surface); dimensions may vary with device
A
Branded Face
Full-Bridge DMOS PWM Motor Driver
A4950
9
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Copyright ©2011-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to
permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, LLC assumes no re spon si bil i ty for its
use; nor for any in fringe ment of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Revision History
Revision Revision Date Description of Revision
Rev. 4 August 6, 2012 Add AEC qualification; update PWM table
