© 2007 Microchip Technology Inc. DS41211D
PIC12F683
Data Sheet
8-Pin Flash-Based, 8-Bit
CMOS Microcontrollers with
nanoWatt Technology
DS41211D-page ii © 2007 Microchip Technology Inc.
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The Microchip name and logo, the Microchip logo, Accur on,
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© 2007, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrit y of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
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Company’s quality system processes and procedures are for its PIC®
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EEPROMs, microperipherals, nonvolatile memory and analog
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manufacture of development systems is ISO 9001:2000 certified.
© 2007 Microchip Technology Inc. DS41211D-page 1
PIC12F683
8-Pin Flash-Based, 8-Bit CMOS Microcontrollers with
nanoWatt Technology
High-Performance RISC CPU:
Only 35 instructions to learn:
- All single-cycle instructions except branches
Operati ng spe ed:
- DC – 20 MHz oscillator/clock input
- DC – 200 ns instruction cycle
Interrupt capability
8-level deep hardware stack
Direct, Indirect and Relative Addressing modes
Special Microcontroller Features:
Precision Internal Oscillator:
- Factory calibrated to ±1%, typical
- Software selectable frequency range of
8 MHz to 125 kHz
- Software tunable
- Two-Speed Start-up mode
- Crystal fail detect for critical applications
- Clock mode switching during operation for
power saving s
Power-Saving Sleep mode
Wide operating voltage range (2.0V-5.5V)
Industri al and Extend ed tem pera t ure range
Power-on Reset (POR)
Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
Brown-out Reset (BOR) with software contro l
option
Enhanced Low-Current Watchdog Timer (WDT)
with on-chip oscillator (software selectable nomi-
nal 268 seconds with full prescaler) with software
enable
Multiplexed Master Clear with pull-up/input pin
Programmable code protection
High Endurance Flash/EEPROM cell:
- 100,000 writ e Flash endurance
- 1,000,000 write EEPROM endurance
- Flash/Data EEPROM Retention: > 40 years
Low-Power Features:
Standby Current:
- 50 nA @ 2.0V, typical
Operating Current:
-11μA @ 32 kHz, 2.0V, typical
-220μA @ 4 MHz, 2.0V, typical
Watchdog Timer Current:
-1μA @ 2.0V, typical
Peripheral Feat ures:
6 I/O pins with individual direction control:
- High current source/sink for direct LED drive
- Interrupt-on-pin change
- Individually programmable weak pull-ups
- Ultra Low-Power Wake-up on GP0
Analog Compar ator module with:
- One analog comparator
- Programmable on-chip voltage reference
(CVREF) module (% of VDD)
- Comparator inputs and output externally
accessible
A/D Converter:
- 10-bit resolution and 4 channels
Timer0: 8-bit timer/counter with 8-bit
progra mmab le pres caler
Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Timer1 Gate (count enable)
- Option to use OSC1 and OSC2 in LP mode as
T imer1 oscillator if INTOSC mode selected
Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
Capture , Comp a r e, PWM mo dul e:
- 16-bit Capture, max resolution 12.5 ns
- Compare, max resolution 200 ns
- 10-bit PWM, max frequency 20 kHz
In-Circuit Serial Programming™ (ICSP™) via
two pins
Device Program Memory Data Memory I/O 10-bit A/D (ch) Comparators Timers
8/16-bit
Flash (words ) SRAM (bytes ) EEPROM (byt es)
PIC12F683 2048 128 256 6 4 1 2/1
PIC12F683
DS41211D-page 2 © 2007 Microchip Technology Inc.
8-Pin Diagram (PDIP, SOIC)
8-Pin Diagram (DFN)
8-Pin Diagram (DFN-S)
TABLE 1: 8-PIN SUMMARY
I/O Pin Analog Comparators Timer CCP Interrupts Pull-ups Basic
GP0 7AN0 CIN+ IOC YICSPDAT/ULPWU
GP1 6 AN1/VREF CIN- IOC Y ICSPCLK
GP2 5AN2 COUT T0CKI CCP1 INT/IOC Y
GP3(1) 4— IOCY
(2) MCLR/VPP
GP4 3AN3 T1G IOC YOSC2/CLKOUT
GP5 2 T1CKI IOC Y OSC1/CLKIN
1 VDD
—8 VSS
Note 1: Input only.
2: Only when pin is configured for external MCLR.
VDD
GP5/T1CKI/OSC1/CLKIN
GP4/AN3/T1G/OSC2/CLKOUT
GP3/MCLR/VPP
VSS
GP0/AN0/CIN+/ICSPDAT/ULPWU
GP1/AN1/CIN-/VREF/ICSPCLK
GP2/AN2/T0CKI/INT/COUT/CCP1
PIC12F683
1
2
3
4
8
7
6
5
1
2
3
45
6
7
8
PIC12F683
VSS
GP0/AN0/CIN+/ICSPDAT/ULPWU
GP1/AN1/CIN-/VREF/ICSPCLK
GP2/AN2/T0CKI/INT/COUT/CCP1
VDD
GP5/TICKI/OSC1/CLKIN
GP4/AN3/TIG/OSC2/CLKOUT
GP3/MCLR/VPP
1
2
3
45
6
7
8
PIC12F683
VSS
GP0/AN0/CIN+/ICSPDAT/ULPWU
GP1/AN1/CIN-/VREF/ICSPCLK
GP2/AN2/T0CKI/INT/COUT/CCP1
VDD
GP5/TICKI/OSC1/CLKIN
GP4/AN3/TIG/OSC2/CLKOUT
GP3/MCLR/VPP
© 2007 Microchip Technology Inc. DS41211D-page 3
PIC12F683
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 Memory O rganization................................................................................................................................................................... 7
3.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 19
4.0 GPIO Port................................................................................................................................................................................... 31
5.0 Timer0 Module ........................................................................................................................................................................... 41
6.0 Timer1 Module with Gate Control............................................................................................................................................... 44
7.0 Timer2 Module ........................................................................................................................................................................... 49
8.0 Comparator Module............................................. .. .... .... .. ......... .... .. .... ....... .... .... .. .... ......... .......................................................... 51
9.0 Analog-to-Digital Converter (AD C) Module ................................................................................................................................ 61
10.0 Data EEPROM Mem o ry................................ ..................... ........................... ............................................................................. 71
11.0 Capture/Compare/PWM (CCP) Module. .... ............... ...... ............... ...... ............. ...... ............... ...... .............................................. 75
12.0 Specia l Features of the CPU.................... ............................ ..................... ..................... ............................................................ 83
13.0 Instruction Set Summary.......................................................................................................................................................... 101
14.0 Development Support............................................................................................................................................................... 111
15.0 Electrical Specifications............................................................................................................................................................ 115
16.0 DC and AC Characteristics Graphs and Tables.......................................... .... .... .. .... ......... .... .... .. ............................................ 137
17.0 Packagin g In fo rmation.............................. ..................... ............................ ............................................................................... 159
Appendix A: Data Sheet Revision History................................................ .... ......... .... .... .... ......... .... .. .................................................. 165
Appendix B: Migrating From Other PIC® Devices................ .. ......... .... .... .. .... ......... .... .... .. ......... .... .... .. .............................................. 165
The Micro chip Web Site.................. ............................ ........................... ........................... ................................................................. 171
Customer Change Notification Service........ ...... ............. ...... ............... ...... ............... ...... .... ............................................................... 171
Customer Support................. ...... ............. ...... .... ............. ...... .... ............. ...... ............. ...... ................................................................... 171
Reader Response.............................................................................................................................................................................. 172
Product Identification System ............................................................................................................................................................ 173
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PIC12F683
DS41211D-page 4 © 2007 Microchip Technology Inc.
NOTES:
© 2007 Microchip Technology Inc. DS41211D-page 5
PIC12F683
2.0 DEVICE OVERVIEW
The PIC12F683 is covered by this data sheet. It is
available in 8-pin PDIP, SOIC and DFN-S packages.
Figure 2-1 shows a block diagram of the PIC12F683
device. Table 2-1 shows the pinout description.
FIGURE 2-1: PIC12F683 BLOCK DIAGRAM
Flash
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction Reg
Program Counter
RAM
File
Registers
Direct Addr 7
RAM Addr 9
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
8
8
8
3
8-Level Stack 128 bytes
2k x 14
(13-bit)
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
MCLR VSS
Brown-out
Reset
1 Analog Com para tor
Timer0 Timer1
Data
EEPROM
256 bytes
EEDATA
EEADDR
GP0
GP1
GP2
GP3
GP4
GP5
AN0 AN1 AN2 AN3 CIN- CIN+ COUT
T0CKI
INT
T1CKI
Configuration
Internal
Oscillator
VREF
T1G VDD
8
Timer2 CCP
Block CCP1
CVREF
Analog- t o-D ig ital Conv erter
PIC12F683
DS41211D-page 6 © 2007 Microchip Technology Inc.
TABLE 2-1: PIC12F683 PINOUT DESCRIPTION
Name Function Input
Type Output
Type Description
VDD VDD Power Positive supply
GP5/T1CKI/OSC1/CLKIN GP5 TTL CMOS GPIO I/O with prog. pull-up and interrupt-on-change
T1CKI ST Timer1 clock
OSC1 XTAL Crystal/Resonator
CLKIN ST Extern al clock input/RC oscillator connection
GP4/AN3/T1G/OSC2/CLKOUT GP4 TTL CMOS GPIO I/O with prog. pull-up and interrupt-on-change
AN3 AN A/D Channel 3 input
T1G ST T imer1 gate
OSC2 XTAL Crystal/Resonator
CLKOUT CMOS FOSC/4 output
GP3/MCLR/VPP GP3 TTL GPIO input with interrupt-on-change
MCLR ST Master Clear with internal pull-up
VPP HV Programming voltage
GP2/AN2/T0CKI/INT/COUT/CCP1 GP2 ST CMOS GPIO I/O with prog. pull-up and interrupt-on-change
AN2 AN A/D Channel 2 input
T0CKI ST Timer0 clock input
INT S T External Interrupt
COUT CMOS Comparator 1 output
CCP1 ST CMOS Capture input/Compare output/PWM output
GP1/AN1/CIN-/VREF/ICSPCLK GP1 TTL CMOS GPIO I/O with prog. pull-up and interrupt-on-change
AN1 AN A/D Channel 1 input
CIN- AN Comparator 1 input
VREF AN External Voltage Reference for A/D
ICSPCLK ST Ser ial Programm ing Clock
GP0/AN0/CIN+/ICSPD AT/ULPWU GP0 TTL CMOS GPIO I/O with prog. pull-up and interrupt-on-change
AN0 AN A/D Channel 0 input
CIN+ AN Comparator 1 input
ICSPDAT ST CMOS Serial Programming Data I/O
ULPWU AN Ultra Low-Power Wake-up input
VSS VSS Power Ground reference
Legend: AN = Analog input or output CMOS = CMOS compatible input or output
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels
HV = High Voltage XTA L = Crystal
© 2007 Microchip Technology Inc. DS41211D-page 7
PIC12F683
3.0 MEMORY ORGANIZATION
3.1 Program Memory Organization
The PIC12F683 has a 13-bit program counter capable
of addr essing an 8k x 14 program m emory spac e. Only
the first 2k x 14 (0000h-07FFh) for the PIC12F683 is
physically implemented. Accessing a location above
these boundaries will cause a wraparound within the
first 2K x 14 space. The Reset vector is at 0000h and
the interrupt vector is at 0004h (see Figure 3-1).
FIGURE 3-1: PROGRAM MEMORY M AP
AND STACK FOR THE
PIC12F683
3.2 Data Memory Organization
The dat a memory (see Figure 3-2) is p artitioned into two
banks, which contain the General Purpose Registers
(GPR) and the Special Function Registers (SFR). The
Special Function Registers are located in the first 32
locations of each bank. Register locations 20h-7Fh in
Bank 0 and A0h-BFh in Bank 1 are General Purpose
Registers, implemented as static RAM. Register
locations F0h-FFh in Bank 1 point to addresses 70h-7Fh
in Bank 0. All other RAM is unimplemented and returns
0’ when read. RP0 of the STATUS register is the bank
select bit.
RP0
0Bank 0 is selected
1Bank 1 is selected
PC<12:0>
13
0000h
0004h
0005h
07FFh
0800h
1FFFh
Stack Level 1
Stack Level 8
Reset V ector
Interrupt Vector
On-chip Program
Memory
CALL, RETURN
RETFIE, RETLW
Stack Level 2
Wraps to 0000h-07FF h
Note: The IRP and RP1 bits of the STATUS
register are reserved and should always
be maintained as ‘0’s.
PIC12F683
DS41211D-page 8 © 2007 Microchip Technology Inc.
3.2. 1 GENERAL PURPOSE REGISTE R
FILE
The register file is organized as 128 x 8 in the
PIC12F683. Each register is accessed, either directly
or indirectly, through the File Select Register FSR (see
Section 3.4 “Indirect Addressing, INDF and FSR
Registers”).
3.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table 3-1). These
registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
assoc iated with th e “core” are described in this sec tion.
Those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
FIGURE 3-2: DATA MEMORY MAP OF
THE PIC12F 68 3
Indirect addr.(1)
TMR0
PCL
STATUS
FSR
GPIO
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
7Fh
BANK 0
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
CMCON0 VRCON
General
Purpose
Registers
96 Bytes
EEDAT
EEADR
EECON2(1)
File
Address File
Address
WPU
IOC
Indirect addr.(1)
OPTION_REG
PCL
STATUS
FSR
TRISIO
PCLATH
INTCON
PIE1
PCON
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
FFh
BANK 1
ADRESH
ADCON0
EECON1
ADRESL
ANSEL
BFh
General
Purpose
Registers
32 Bytes
Accesses 70h-7Fh F0h
TMR2
T2CON
CCPR1L
CCPR1H
CCP1CON
WDTCON
CMCON1
OSCCON
OSCTUNE
PR2
C0h
EFh
© 2007 Microchip Technology Inc. DS41211D-page 9
PIC12F683
TABLE 3-1: P IC12F683 SPECIAL REGISTERS SUMMARY BANK 0
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Page
Bank 0
00h INDF Addressing this location use s content s of FSR to address data memory (no t a physical regi ster) xxxx xxxx 17, 90
01h T MR0 Timer0 Module Register xxxx xxxx 41, 90
02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 17, 90
03h STATUS IRP(1) RP1(1) RP0 TO PD ZDCC0001 1xxx 11, 90
04h FSR Indirect Data Memory Address Pointer xxxx xxxx 17, 90
05h GPIO GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx 31, 90
06h Unimplemented
07h Unimplemented
08h Unimplemented
09h Unimplemented
0Ah PCLATH Write Buffer for upper 5 bits of Program Counter ---0 0000 17, 90
0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 13, 90
0Ch PIR1 EEIF ADIF CCP1IF CMIF OSFIF TMR2IF TMR1IF 000- 0000 15, 90
0Dh Unimplemented
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx 44, 90
0Fh T MR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx 44, 90
10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 47, 90
11h
TMR2 Timer2 Module Regist er 0000 0000 49, 90
12h
T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 50, 90
13h CCP R1L Capture/Com pare/PWM Register 1 Low Byte xxxx xxxx 76, 90
14h CCP R1H Cap ture/Com pare/PWM Register 1 High Byte xxxx xxxx 76, 90
15h CCP1CON DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 75, 90
16h Unimplemented
17h Unimplemented
18h WDTCON WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 97, 90
19h CMCON0 —COUT CINV CIS CM2 CM1 CM0 -0-0 0000 56, 90
1Ah CMCON1 T1GSS CMSYNC ---- --10 57, 90
1Bh Unimplemented
1Ch Unimplemented
1Dh Unimplemented
1Eh ADRESH Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx 61,90
1Fh ADCON0 ADFM VCFG CHS1 CHS0 GO/DONE ADON 00-- 0000 65,90
Legend: – = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.
PIC12F683
DS41211D-page 10 © 2007 Microchip Technology Inc.
TABLE 3-2: PIC12F683 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 B it 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Page
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 17, 90
81h
OPTION_REG
GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 12, 90
82h P CL Program Counter’s (PC) Least Significant Byte 0000 0000 17, 90
83h STATUS IRP(1) RP1(1) RP0 TO PD ZDCC0001 1xxx 11, 90
84h FSR Indirect Data Memory Address Pointer xxxx xxxx 17, 90
85h TRISIO TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 32, 90
86h Unimplemented
87h Unimplemented
88h Unimplemented
89h Unimplemented
8Ah PCLATH Write Buffer for upper 5 bits of Program Count er ---0 0000 17, 90
8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 13, 90
8Ch PIE1 EEIE ADIE CCP1IE CMIE OSFIE TMR2IE TMR1IE 000- 0000 14, 90
8Dh Unimplemented
8Eh PCON ULPWUE SBOREN —PORBOR --01 --qq 16, 90
8Fh OSCCON IRCF2 IRCF1 IRCF0 OSTS(2) HTS LTS SCS -110 x000 20, 90
90h OSCTUNE TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 24, 90
91h Unimplemented
92h PR2 Timer2 Module Period Register 1111 1111 49, 90
93h Unimplemented
94h Unimplemented
95h WPU(3) —WPU5WPU4 WPU2 WPU1 WPU0 --11 -111 34, 90
96h IOC IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 34, 90
97h Unimplemented
98h Unimplemented
99h VRCON VREN —VRR VR3 VR2 VR1 VR0 0-0- 0000 58, 90
9Ah EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 71, 90
9Bh EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 71, 90
9Ch EECON1 WRERR WREN WR RD ---- x000 72, 91
9Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 72, 91
9Eh ADRE SL Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result xxxx xxxx 66, 91
9Fh ANSEL ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 33, 91
Legend: – = unimplemented locations read as ‘0’, u = unc hanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.
2: OSTS bit of the OSCCON register reset to 0with Dual Speed Start-up and LP, HS or XT selected as the oscillator.
3: GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register.
© 2007 Microchip Technology Inc. DS41211D-page 11
PIC12F683
3.2.2.1 STATUS Register
The S TATUS registe r, shown i n Register 3-1, cont a ins :
Arithmetic status of the ALU
Reset status
Ban k sele ct bits for data memory (S RAM)
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabl ed. These bit s are set or clea red according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For exam pl e, CLRF STATUS, will c lea r the up per three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not affect-
ing any S tat us bits, see the “In struction Set Summary”.
Note 1: Bits IRP a nd RP1 of th e STATUS register
are not used by the PIC12F683 and
should be maintained as clear. Use of
these b its is n ot reco mmen ded, s ince this
may affect upward compatibility with
future products.
2: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction.
REGISTER 3-1: STATUS: STATUS REGISTER
Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD ZDCC
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IRP: This bit is reserved and should be maintained as ‘0
bit 6 RP1: This bit is reserved and should be maintained as ‘0
bit 5 RP0: Register Bank Select bit (used for direct addressing)
1 = Bank 1 (80h FFh)
0 = Bank 0 (00h 7Fh)
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by th e CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions), For Borrow, the polarity is
reversed.
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rot ate (RRF, RLF) instructi ons, this bit is loaded with either the high-orde r or low-o rder
bit of the source register.
PIC12F683
DS41211D-page 12 © 2007 Microchip Technology Inc.
3.2.2.2 OPTION Register
The OPTION register is a readable and writable
register, which contains various control bits to
configure:
TMR0/WDT prescaler
External GP2 /INT inte rrup t
•TMR0
Weak pull-ups on GPIO
Note: To achieve a 1:1 prescaler assignment for
Timer0, assign the prescaler to the WDT
by setting PSA bit of the OPTION register
to ‘1’ See Section 5.1.3 “Software Pro-
grammable Prescaler”.
REGISTER 3-2: OPTION_REG: OPTION REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GPPU: GPIO Pull-up Enable bit
1 = GPIO pull-ups are disabled
0 = GPIO pull-ups are enabled by individual PORT latch values in WPU register
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5 T0CS: Timer0 Clock Sou rce Sel ect bit
1 = Transit ion on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assig nment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Note 1: A dedicated 1 6-bit WDT postscale r is available. See Section 12.6 “Watchdog Timer (WDT)” for more
information.
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
BIT VALUE TIMER0 RATE WD T RATE
© 2007 Microchip Technology Inc. DS41211D-page 13
PIC12F683
3.2.2.3 INTCON Register
The INTCON register is a readable and writable
register, which cont ains the v arious enabl e and flag bits
for TMR0 re gis ter overflow, GPIO chan ge and externa l
GP2/INT pin interrupts.
Note: Interru pt flag bit s are set w hen an interr upt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User software should ensure the appropri-
ate interrupt flag bits are clear prior to
enabling an interrupt.
REGISTER 3-3: INTCON: INTERRUPT CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GIE PEIE T0IE INTE GPIE T0IF INTF GPIF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: Timer0 Ov erfl ow Interru pt Enab le bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4 INTE: GP2/INT External Interrupt Enable bit
1 = Enables the GP2/INT external interrupt
0 = Disables the GP2/INT external interrupt
bit 3 GPIE: GPIO Change Interrupt Enable bit(1)
1 = Enables the GPIO change interrupt
0 = Disables the GPIO change interrupt
bit 2 T0IF: Timer0 Overflow Interrupt Flag bit(2)
1 = Timer0 register has overflowed (must be cleared in software)
0 = Timer0 register did not overflow
bit 1 INTF: GP2/INT External Interrupt Flag bit
1 = The GP2/INT external interrupt occurred (must be cleared in software)
0 = The GP2/INT external interrupt did not occur
bit 0 GPIF: GPIO Change Interrupt Flag bit
1 = When at least one of the GPIO <5:0> pins changed state (must be cleared in software)
0 = None of the GPIO <5:0> pins have changed state
Note 1: IOC register must also be enabled.
2: T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before
clearing T0IF bit.
PIC12F683
DS41211D-page 14 © 2007 Microchip Technology Inc.
3.2.2.4 PIE1 Regist er
The PIE1 regis te r con t ai ns th e in terrupt enable bi t s, a s
shown in Register 3-4.
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 3-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
EEIE ADIE CCP1IE CMIE OSFIE TMR2IE TMR1IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 EEIE: EE Write Complete Interrupt Enable bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 4 Unimplemented: Read as ‘0
bit 3 CMIE: Comparator Interr upt Enable bit
1 = Enables the Comparator 1 interrupt
0 = Disables the Comparator 1 interrupt
bit 2 OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enables the oscillator fail interrupt
0 = Disables the oscillator fail inter rupt
bit 1 TMR2IE: Timer2 to PR2 Match Interrupt Enable bit
1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt
bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt
© 2007 Microchip Technology Inc. DS41211D-page 15
PIC12F683
3.2.2.5 PIR1 Register
The PIR1 register contains the interrupt flag bits, as
shown in Register 3-5.
Note: Interru pt flag bi ts are set when an interrupt
conditi on occ urs, regar dless o f the s tate of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User so ftware sh ould ensu re the approp ri-
ate interrupt flag bits are clear prior to
enabling an interrupt.
REGISTER 3-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
EEIF ADIF CCP1IF CMIF OSFIF TMR2IF TMR1IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation has not completed or has not been started
bit 6 ADIF: A/D Interrupt Flag bit
1 = A/D conversion complete
0 = A/D conversion has not completed or has not been started
bit 5 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register captu re occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 4 Unimplemented: Read as ‘0
bit 3 CMIF: Comparator Interrupt Flag bit
1 = Comparator 1 output has changed (must be cleared in software)
0 = Comparator 1 output has not changed
bit 2 OSFIF: Oscillator Fail Interrupt Flag bit
1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = System clock operating
bit 1 TMR2IF: Timer2 to PR2 Match Interrupt Flag bit
1 = Timer2 to PR2 match occurred (must be cleared in software)
0 = Timer2 to PR2 match has not occurred
bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = Timer1 register overflowed (must be cleared in software)
0 = Timer1 has not overflowed
PIC12F683
DS41211D-page 16 © 2007 Microchip Technology Inc.
3.2.2.6 PCON Regist er
The Power Control (PCON) register contains flag bits
(see Table 12-2) to differentiate between a:
Power-on Reset (POR)
Brown-out Reset (BOR)
Watchdog Timer Reset (WDT)
External MCLR Reset
The PCON register also controls the Ultra Low-Power
Wake-up and software enable of the BOR.
The PCON register bits are shown in Register 3-6.
REGISTER 3-6: PCON: POWER CONTROL REGISTER
U-0 U-0 R/W-0 R/W-1 U-0 U-0 R/W-0 R/W-x
ULPWUE SBOREN —PORBOR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0
bit 5 ULPWUE: Ultra Low-Power Wake-Up Enable bit
1 = Ultra Low-Power Wake-up enabled
0 = Ultra Low-Power Wake-up disabled
bit 4 SBOREN: Software BOR Enable bit(1)
1 = BOR enabled
0 = BOR disabled
bit 3-2 Unimplemented: Read as ‘0
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown- out R eset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-ou t Res et o ccurre d (m us t be se t in sof tw are afte r a Power-on Reset o r Brow n- out Re set
occurs)
Note 1: Set BOREN<1:0> = 01 in the Configuration Word register for this bit to control the BOR.
© 2007 Microchip Technology Inc. DS41211D-page 17
PIC12F683
3.3 PCL and PCLATH
The Program Counter (PC) is 13 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not
directly readable or writable and comes from PCLATH.
On any Reset, the PC is cleared. Figure 3-3 shows the
two situations for the loading of the PC. The upper
example in Figure 3-3 shows how the PC is loaded on a
write to PCL (PCLATH<4:0> PCH). The lower exam-
ple in Figure 3-3 shows how the PC is loaded during a
CALL or GOTO instruction (PCLATH<4:3> PCH).
FIGURE 3-3: LOADING OF PC IN
DIFFERENT SITUATIONS
3.3.1 COMPUTED GOTO
A comput ed GOTO is a ccom pli shed by addi ng a n offset
to the program counter (ADDWF PCL). When perform-
ing a table read using a computed GOTO method, care
should be ex ercise d if th e t able loca tion c rosse s a PCL
memory boundary (each 256-byte block). Refer to the
Application Note AN556, “Implementing a Table Read”
(DS00556).
3.3.2 STACK
The PIC12F683 family has an 8-level x 13-bit wide
hardware stack (see Figure 3-1). The stack space is
not part of either program or data space and the Stack
Pointer is not readable or writable. The PC is PUSHed
onto the stac k whe n a CALL instruction is executed or
an interrupt causes a branch. The stack is POPed in
the event of a RETURN, RETLW or a RETFIE instruction
execution. PCLATH is not affected by a PUSH or POP
operation.
The st ack operates as a circular buf fer . This means that
after the stack has been PUSHed eight times, the ninth
push ove rwrite s the va lue tha t was s tored fro m the firs t
push. The tenth pus h ov erw ri tes the second pus h (an d
so on).
3.4 Indirect Addressing, INDF and
FSR Registers
The INDF register is no t a physical reg ister . Addr essing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses data pointed to by the File Select
Register (FSR). Reading INDF itself indirectly will
produce 00h. Writing to the INDF register indirectly
results in a no operation (although Status bits may be
affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR register and the IRP bit of
the STATUS register, as shown in Figure 3-4.
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 3-1.
EXAMPLE 3-1: INDIRECT ADDRESSING
PC
12 8 7 0
5PCLATH<4:0>
PCLATH
Instruction with
ALU Result
GOTO, CALL
OPCODE<10:0>
8
PC
12 11 10 0
11
PCLATH<4:3>
PCH PCL
87
2
PCLATH
PCH PCL
PCL as
Destination
Note 1: There are no Status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
interr upt add ress.
MOVLW 0x20 ;initialize pointer
MOVWF FSR ;to RAM
NEXT CLRF INDF ;clear INDF register
INCF FSR ;inc pointer
BTFSS FSR,4 ;all done?
GOTO NEXT ;no clear next
CONTINUE ;yes continue
PIC12F683
DS41211D-page 18 © 2007 Microchip Technology Inc.
FIGURE 3-4: DIRECT/INDIRECT ADDRESSING PIC12F683
For memory map detail, see Figure 3-2.
Note 1: The RP1 and IRP bits are reserv ed; always maintain these bits clear.
Data
Memory
Indirect AddressingDirect Addressing
Bank Select Location Select
RP1(1) RP0 6 0
From Opcode IRP(1) File Select Register
70
Bank Select Location Select
00 01 10 11 180h
1FFh
00h
7Fh
Bank 0 Bank 1 B ank 2 Bank 3
Not Used
© 2007 Microchip Technology Inc. DS41211D-page 19
PIC12F683
3.0 OSCILLATOR MODULE (WITH
FAIL-SAFE CLOCK MONITOR)
3.1 Overview
The Oscillator module has a wide variety of clock
sources and selection features that allow it to be used
in a wide range of applications while maximizing perf or-
mance and minimizing power consumption. Figure 3-1
illustrates a block diagram of the Oscillator module.
Clock sources can be configured from external
oscilla tors, quartz crystal resonators , ceramic resonators
and Resistor-Capacitor (RC) circuits. In addition, the
system clock source can be configured from one of two
internal oscillators, with a choice of speeds selectable via
software. Addi tio nal clo ck feat ures inc lud e:
Selectable system clock source between external
or internal via sof tware.
Two-Speed Start-up mode, which minimizes
latency between external oscillator start-up and
code execution.
Fail-Safe Clock Monitor (FSCM) designed to
detect a failure of the external clock source (LP,
XT, HS, EC or RC modes) and switch
automatically to the internal oscillator.
The Os cillator mod ule can be c onfigured in one of eig ht
clock modes.
1. EC – External clock with I/O on O SC2/CLKOUT.
2. LP – 32 kHz Low-Power Crystal mode.
3. XT – Medium Gain Crystal or Ceramic
Resonator Oscillator mode.
4. HS – High Gain Crystal or Ceramic Resonator
mode.
5. RC – External Resistor-Capacitor (RC) with
FOSC/4 output on OSC2/CLKOUT.
6. RCIO – External Resistor-Capacitor (RC) with
I/O on OSC2/CLKOUT.
7. INTOSC – Internal oscillator with FOSC/4 output
on OSC2 and I/O on OSC1/CLKIN.
8. INTOSCIO – Internal oscillator with I/O on
OSC1/CLKIN and OSC2/CLKOUT.
Clock Source modes are configured by the FOSC<2:0>
bits in the Configuration Word register (CONFIG). The
internal clock can be generated from two internal
oscillators. The HFINTOSC is a calibrated
high-frequency oscillator. The LFINTOSC is an
uncalibrated low-frequency oscillator.
FIGURE 3-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
(CP U and Peripherals)
OSC1
OSC2
Sleep
External Oscillator
LP, XT, HS, RC, RCIO, EC
System Clock
Postscaler
MUX
MUX
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
250 kHz
IRCF<2:0>
111
110
101
100
011
010
001
000
31 kHz
Power-up Timer (PWRT)
FOSC<2:0>
(Configuration Word Register)
SCS<0>
(OSCCON Register)
Internal Oscillator
(OSCCON Register)
Watchdog Timer (WDT)
Fail-Safe Clock Monitor (FSCM)
HFINTOSC
8 MHz
LFINTOSC
31 kHz
INTOSC
PIC12F683
DS41211D-page 20 © 2007 Microchip Technology Inc.
3.2 Oscillator Control
The Oscillator Control (OSCCON) register (Figure 3-1)
controls the system clock and frequency selection
options. The OSCCON register contains the following
bits:
Frequency selection bits (IRCF)
Frequency Status bits (HTS, LTS)
System clock control bits (OSTS, SCS)
REGISTER 3-1: OSCCON: OSCILLATOR CONTROL REGISTER
U-0 R/W-1 R/W-1 R/W-0 R-1 R-0 R-0 R/W-0
IRCF2 IRCF1 IRCF0 OSTS(1) HTS LTS SCS
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as0
bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits
111 =8MHz
110 = 4 MHz (default)
101 =2MHz
100 =1MHz
011 =500kHz
010 =250kHz
001 =125kHz
000 = 31 kHz (LFINTOSC)
bit 3 OSTS: Oscillator Start-up Time-out Status bit(1)
1 = Device is running from the external clock defined by FOSC<2:0> of the Configuration Word register
0 = Device is running from the internal oscillator (HFINTOSC or LF INTOSC)
bit 2 HTS: HFINTOSC Status bit (High Frequency – 8 MHz to 125 kHz)
1 = HFINTOSC is stable
0 = HFINTOSC is not stable
bit 1 LTS: LFINTOSC Stable bit (Low Frequency – 31 kHz)
1 = LFINT OSC is stable
0 = LFINTOSC is not st abl e
bit 0 SCS: System Clock Select bit
1 = Internal oscillator is used for system clock
0 = Clock source defined by FOSC<2:0> of the Configuration Word register
Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe
mode is enable d.
© 2007 Microchip Technology Inc. DS41211D-page 21
PIC12F683
3.3 Clock Source Modes
Clock Source modes can be classified as external or
internal.
External Clock mod es rely on e xternal circui try fo r
the clock source. Examples are: Oscillator mod-
ules (EC mode), quartz crystal resonators or
ceramic resonators (LP, XT and HS modes) and
Resistor-Capacito r (RC ) mode circuits.
Internal clock sources are contained internally
within the Oscillator module. The Oscillator
module has two internal oscillators: the 8 MHz
High-Frequency Internal Oscillator (HFINTOSC)
and the 31 kHz Low -Frequency Internal Os cillator
(LFINTOSC).
The syste m cl oc k ca n be selected betw ee n ex tern al or
internal clock sources via the System Clock Select
(SCS) bit of the OSCCON register. See Section 3.6
“Clock Switching” for additional information.
3.4 External Clock Modes
3.4.1 OSCILLATOR START-UP TIMER (OST)
If the Oscillator module is configured for LP, XT or HS
modes, the Oscillator Start-up Timer (OST) counts
1024 oscillations from OSC1. This occurs following a
Power-on Reset (POR) and when the Power-up Timer
(PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
increment and program execution is suspended. The
OST ensures that the oscillator circuit, using a quartz
cryst al res onator o r ce ramic res onator, has st arte d and
is providing a stable system clock to the Oscillator
module. When switching between clock sources, a
delay is required to allow the new clock to stabilize.
These oscillator delays are shown in Table 3-1.
In order to mi nimize laten cy between externa l oscillator
start-up and code execution, the Two-Speed Clock
Start-up mode can be selected (see Section 3.7
“Two-Speed Clock Start-up Mode”).
TABLE 3-1: OSCILLATOR DELAY EXAMPLES
3.4.2 EC MODE
The External Clock (EC) mode allows an externally
generated logic level as the system clock source. When
operating in this mode, an external clock source is
connected to the OSC1 input and the OSC2 is available
for general purpose I/O. Figure 3-2 shows the pin
connections for EC mode.
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC® MCU design is fully
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.
FIGURE 3-2: EXTERNAL CLOCK (EC)
MODE OPERATION
Switch From Switch To Frequency Oscillator Delay
Sleep/POR LFINTOSC
HFINTOSC 31 kHz
125 kHz to 8 MHz Oscillator Warm-Up Delay (TWARM)
Sleep/POR EC, RC DC – 20 MHz 2 instruction cycles
LFINTOSC (31 kHz) EC, RC DC – 20 MHz 1 cycle of each
Sleep/POR LP, XT, HS 32 kHz to 20 MHz 1024 Cloc k Cyc les (OST)
LFINTOSC (31 kHz) HFINTOSC 125 kHz to 8 MHz 1 μs (approx.)
OSC1/CLKIN
OSC2/CLKOUT(1)
I/O
Clock from
Ext. System PIC® MCU
Note 1: Alternat e pin functions are listed in the
Device Overview.
PIC12F683
DS41211D-page 22 © 2007 Microchip Technology Inc.
3.4.3 LP, XT, HS MODES
The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 a nd OSC2 (Figur e 3-3). The mod e selects a low ,
medium or high gain setting of the internal
inverter-amplifier to support various resonator types
and speed.
LP Oscillator mode select s the lowest gain setting of the
internal inverter-amplifier . LP mode current consumption
is the least of the three mo des. This mode is designed to
drive only 32.768 kHz tuning-fork type crystals (watch
crystals).
XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current c onsumption is the medium of the three mo des.
This mode is best suited to drive resonators with a
medium drive level specification.
HS Oscillator mode selects the highest gain setting of the
internal inverter-amplifier . HS mode current c onsumption
is the highest of the three modes. This mode is best
suited fo r reso nato rs that require a h igh driv e s ettin g.
Figure 3-3 and Figure 3-4 show typical circuits for
quartz crystal and ceramic resonators, respectively.
FIGURE 3-3: QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
FIGURE 3-4: CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
Note 1: A series resistor (RS) may be required for
quartz crystals with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 MΩ to 10 MΩ).
C1
C2
Quartz
RS(1)
OSC1/CLKIN
RF(2) Sleep
To Internal
Logic
PIC® MCU
Crystal
OSC2/CLKOUT
Note 1: Quartz crystal characteristics vary according
to type, package and manufacturer. The
user should consult the manufacturer data
sheet s fo r spec ifica tions and re comm ende d
application.
2: Always veri fy os ci lla tor performance ov er
the VDD and temperature range that is
expected for the application.
3: For oscillator de sign assistance, re ference
the following Microchip Applications Notes:
• AN826, “Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices” (DS00826)
• AN849, “Basic PIC® Oscillator Design
(DS00849)
• AN943, “Practical PIC® Oscillator
Analysis and Design” (DS00943)
• AN949, “Making Your Oscillator Work
(DS00949)
Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 MΩ to 10 M Ω).
3: An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation.
C1
C2 Ceramic RS(1)
OSC1/CLKIN
RF(2) Sleep
To Internal
Logic
PIC® MCU
RP(3)
Resonator OSC2/CLKOUT
© 2007 Microchip Technology Inc. DS41211D-page 23
PIC12F683
3.4.4 EXTERNAL RC MODES
The external Resistor-Capacitor (RC) modes support
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required. There are two modes: RC and RCIO.
In RC mode, the RC circuit connects to OSC1.
OSC2/CLKOUT outputs the RC oscillator frequency
divide d by 4. This signal ma y b e u se d to pro vide a clock
for external circuitry, synchronization, calibration, test
or other application requirements. Figure 3-5 shows
the external RC mode connections.
FIGURE 3-5: EXTERNAL RC MODES
In RCIO mode, the RC circuit is connected to OSC1.
OSC2 becomes an additional general purpose I/O pin.
The RC oscillator frequency is a function of the supply
voltage, the resis tor (REXT) and capacitor (CEXT) values
and the operating temperature. Other factors affecting
the oscillator frequency are:
threshold voltage variation
component tolerances
pack aging var iations in capacitanc e
The user also needs to take into account variation due
to tolerance of external RC components used.
3.5 Internal Clock Modes
The Oscillator module has two independent, internal
oscillators that can be configured or selected as the
system clock source.
1. The HFINTOSC (High-Frequency Internal
Oscillator) is factory calibrated and operates at
8 MHz. The f requenc y o f the HFINT O SC can be
use r-ad just ed via software using the OSCTUNE
register (Register 3-2).
2. The LFINTOSC (Low-Frequency Internal
Oscillator) is uncalibrated and operates at 31 kHz.
The sys tem cloc k speed can b e select ed via soft ware
using the Internal Oscillator Frequency Select bits
IRCF<2:0> of the OSCCON register.
The syste m cl oc k can be selected between ext erna l or
inte rnal cloc k sources via the S ystem Clo ck Select ion
(SCS) bit of the OSCCON register. See Section 3.6
“Clock Switching” for more information.
3.5.1 INTOSC AND INTOSCIO MODES
The INTOSC and INTOSCIO modes configure the
internal oscillators as the system clock source when
the devi ce is pr ogrammed using the o scillato r selectio n
or the FOSC<2:0> bits in the Configuration Word
register (CONFIG). See Section 12.0 “Special
Features of the CPU” for more information.
In INTOSC mode, OSC 1/CLKIN is av ailable for general
purpose I/O. OSC2/CLKOUT outputs the selected
internal oscillator fre quency divide d by 4. The CLKO UT
signal may be used to provide a clock for external
circuitry, synchronization, calibration, test or other
application requirements.
In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT
are available for general purpose I/O.
3.5.2 HFINTOSC
The High-Fre quency Int ernal Oscil lator (HFINT OSC) is
a factory calibrated 8 MHz internal clock source. The
frequency of the HFINTOSC can be altered via
software using the OSCTUNE register (Register 3-2).
The output of the HFINTOSC connects to a postscaler
and multiplexer (see Figure 3-1). One of seven
frequencies can be selected via software using the
IRCF<2:0> bits of the OSCCON register. See
Section 3.5.4 “Frequency Select Bits (IRCF)” for
more information.
The HFINTOSC is enabled by selecting any frequency
betwee n 8 MHz and 125 kHz b y set ting th e I RCF<2:0 >
bits of the OSCCON register 000. Then, set the
System Clock Source (SCS) bit of the OSCCON
register to 1 or enable Two-Speed St art-up by settin g
the IESO bit in the Configuration Word register
(CONFIG) to ‘1’.
The HF Internal Oscillator (HTS) bit of the OSCCON
register indicates whether the HFINTOSC is stable or not.
OSC2/CLKOUT(1)
CEXT
REXT
PIC® MCU
OSC1/CLKIN
FOSC/4 o r
Internal
Clock
VDD
VSS
Recommended values: 10 kΩ REXT 100 kΩ, <3 V
3 kΩ REXT 100 kΩ, 3-5V
CEXT > 20 pF, 2-5V
Note 1: Alternate pin functions are listed in the Device
Overview.
2: Output depen ds upon R C or R CIO clo ck mo de
.
I/O(2)
PIC12F683
DS41211D-page 24 © 2007 Microchip Technology Inc.
3.5.2.1 OSCTUNE Register
The HFINTOSC is factory calibrated but can be
adjusted in software by writing to the OSCTUNE
register (Register 3-2).
The default value of the OSCTUNE register is ‘0’. The
value is a 5-bit two’s complement number.
When the OSCTUNE register is modified, the
HFINTOSC frequency will begin shifting to the new
frequency. Code execution continues during this shift.
There is no indication that the shift has occurred.
OSCTUNE does not affect the LFINTOSC frequency.
Operation of features that depend on the LFINTOSC
clock source frequency, such as the Power-up Timer
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock
Monitor (FSCM) and p eripherals, are not affected by the
change in frequency.
REGISTER 3-2: OSCTUNE: OSCILLATOR TUNING REGISTER
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TUN4 TUN3 TUN2 TUN1 TUN0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0
bit 4-0 TUN<4:0>: Frequency Tuning bits
01111 = Maximu m frequency
01110 =
00001 =
00000 = Oscillator module is running at the calibrated frequency.
11111 =
10000 = Minimum fre quenc y
© 2007 Microchip Technology Inc. DS41211D-page 25
PIC12F683
3.5.3 LFINTOSC
The Low-Frequency Internal Oscillator (LFINTOSC) is
an uncalibrated 31 kHz internal clock source.
The output of the LFINTOSC connects to a postscaler
and multiplexer (see Figure 3-1). Select 31 kHz, via
software, using the IRCF<2:0> bits of the OSCCON
register. See Section 3.5.4 “Frequency Select Bits
(IRCF)” for more information . The LFINTOSC is also the
frequency for the Power-up Timer (PWRT), Watchdog
Timer (WDT) and Fail-Safe Clock Mo nitor (FSCM).
The LFINTOSC is enabled by selecting 31 kHz
(IRCF<2:0> bit s of the OSCCON regis ter = 000) as th e
system clock source (SCS bit of the OSCCON
register = 1), or when any of the follo wing are enable d:
Two-Speed Start-up IESO bi t of the C o nfi gura tio n
Word register = 1 and IRCF<2:0> bit s of the
OSCCON regis ter = 000
Power-up Timer (PWRT)
Watchdog Timer (WDT)
Fail-Safe Clock Monitor (FSCM)
The LF Internal Oscillator (LTS) bit of the OSCCON
register indicates whether the LFINTOSC is stable or
not.
3.5.4 FREQUENCY SELECT BITS (IRCF)
The output of the 8 MHz HFINTOSC and 31 kHz
LFINTOSC connects to a postscaler and multiplexer
(see Figure 3-1). The Internal Oscillator Frequency
Select bits IRCF<2:0> of the OSCCON register select
the frequency output of the internal oscillators. One of
eight frequencies can be selected via software:
•8 MHz
4 MHz (Default after Reset)
•2 MHz
•1 MHz
500 kHz
250 kHz
125 kHz
31 kHz (LFINTOSC)
3.5.5 HF AND LF INTOSC CLOCK
SWITCH TIMING
When switching between the LFINTOSC and the
HFINTOSC, the new oscillator may already be shut
down to save power (see Figure 3-6). If th is is the cas e,
there is a delay after the IRCF<2:0> bits of the
OSCCON register are modified before the frequency
selection takes place. The LTS and HTS bits of the
OSCCON register will reflect the current active status
of the LFINTOSC and HFINTOSC oscillators. The
timing of a frequency selection is as follows:
1. IRCF<2:0> bits of the OSCCON register are
modified.
2. If the new clock is shut down, a clock start-up
delay is started.
3. Clock switch circuitry waits for a falling edge of
the current clock.
4. CLKOUT is held low and the clock switch
circuit ry w ai t s for a rising edg e in the new clock.
5. CLKOUT is now connected with the new clock.
LT S and HTS b its of th e OSCCON r egiste r are
updated as require d.
6. Clock swit ch is complete.
See Figure 3-1 for more details.
If the internal oscillator speed selected is between
8 MHz and 125 kHz, there is no start-up delay before
the new frequency is selected. This is because the old
and new frequencies are derived from the HFINTOSC
via the post s ca ler and multiplexe r.
Start-up delay specifications are located in the
Electrical Spe cifications Chapter of this d ata sheet,
under AC Specifications (Oscillator Module).
Note: Following any Reset, the IRC F<2:0> bits of
the OSCCON register are set to110’ and
the frequency selection is set to 4 MHz.
The user can modify the IRCF bits to
select a different frequency.
PIC12F683
DS41211D-page 26 © 2007 Microchip Technology Inc.
FIGURE 3-6: INTERNAL OSCILLATOR SWITCH TIMING
HFINTOSC
LFINTOSC
IRCF <2:0>
System Clock
HFINTOSC
LFINTOSC
IRCF <2:0>
System Clock
HF LF(1)
0= 0
0= 0
Start-up Time 2-cycle Sync Running
2-cycle Sync Running
HFINTOSC LFINTOSC (FSCM and WDT disabled)
Note 1: When going from LF to HF.
HFINTOSC LFINTOSC (Either FSCM or WDT enabled)
LFINTOSC
HFINTOSC
IRCF <2:0>
System Clock
= 0 0
Start-up Time 2-cycle Sync Running
LFINTOSC HFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled
© 2007 Microchip Technology Inc. DS41211D-page 27
PIC12F683
3.6 Clock Switching
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS) bit of the OSCCON
register.
3.6.1 SYSTEM CLOCK SELECT (SCS) BIT
The System Clock Select (SCS) bit of the OSCCON
register selects the system clock source that is used for
the CPU and peripherals.
When the SCS bit of the OSCCON register = 0,
the system clock source is determined by
configuration of the FOSC<2:0> bits in the
Conf iguration Word register (CON FIG).
When the SCS bit of the OSCCON register = 1,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<2:0>
bits of the OSCCON register. Afte r a Reset, the
SCS bit of the OSCCON register is always
cleared.
3.6.2 OSCILLA T OR START-UP TIME-OU T
STATUS (OSTS) B IT
The Oscillator Start-up Time-out Status (OSTS) bit of
the OSCCON register indicates whether the system
clock is running from the external clock source, as
defined by the FOSC<2:0> bits in the Configuration
Word register (CONFIG), or from the internal clock
source. In particular , OSTS indicates that the Oscillator
Start-up Timer (OST) has timed out for LP, XT or HS
modes.
3.7 Two-Speed Clock Start-up Mode
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up
time from the time spent awake and can reduce the
overall power consumption of the device.
This mode allows the application to wake-up from
Sleep, perform a few instructions using the INTOSC
as the clock source and go back to Sleep without
waiting for the primary oscillator to become stable.
When the Oscillator module is configured for LP, XT or
HS modes, the Oscillator Start-up Timer (OST) is
enabled (see Section 3.4.1 “Oscillator Start-up Timer
(OST)). The OST will suspend program execution until
1024 oscillations are counted. Two-Speed Start-up
mode minimizes the delay in code execution by
operating from the internal oscillator as the OST is
counting. When the OST count reaches 1024 and the
OSTS bit of the OSCCON register is set, program
execution switches to the ext ernal oscillator.
3.7.1 TWO-SPEED START-UP MODE
CONFIGURATION
Two-Speed Start-up mode is configured by the
following settings:
IESO (of the Configuration Word register) = 1;
Internal/External Switchover bit (Two-Speed
St art -up mode enabled).
SCS (of the OSCCON register) = 0.
FOSC<2:0> bits in the Configuration Word
register (CONFIG) configured for LP, XT or HS
mode.
Two-Speed Start-up mode is entered after:
Power-on Reset (POR) and, if enabled, after
Power-up Timer (PWRT) has expired, or
Wake-up from Sleep.
If the external clock oscillator is configured to be
anything other than LP, XT or HS mode, then
Two-Speed Start-up is disabled. This is because the
external clock oscillator does not require any
stabilization time after POR or an exit from Sleep.
3.7. 2 TWO-SPEED START-UP
SEQUENCE
1. Wake-up from Power-on Reset or Sleep.
2. Instructions begin execution by the internal
oscillator at the frequency set in the IRCF<2:0>
bits of th e O SCCON re giste r.
3. OST enabled to count 1024 clock cycles.
4. OST timed out, wait for falling edge of the
internal oscillator.
5. OSTS is set.
6. System cloc k held lo w until the next fallin g edge
of new clock (LP, XT or HS mode).
7. System clock is switched to external clock
source.
Note: Any automatic clock switch, which may
occur from T wo-Speed S tart-up or Fail-Safe
Clock Monito r , does not update the SCS bit
of the OSCCON register. The user can
monitor the OSTS bit of the OSCCON
register to determine the current system
clock sour ce.
Note: Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit of the OSCCON register to
remain clear.
PIC12F683
DS41211D-page 28 © 2007 Microchip Technology Inc.
3.7.3 CHECKING TWO-SPEED CLOCK
STATUS
Checking the state of the OSTS bit of the OSCCON
register will confirm if the microcontroller is running
from the external clock source, as defined by the
FOSC<2:0> bits in the Configuration Word register
(CONFIG), or the internal oscillator.
FIGURE 3-7: TWO-SPEED START-UP
0 1 1022 1023
PC + 1
TOSTT
HFINTOSC
OSC1
OSC2
Program Counter
System Clock
PC - N PC
© 2007 Microchip Technology Inc. DS41211D-page 29
PIC12F683
3.8 Fail-Safe Clock Monitor
The Fail-Saf e Cl oc k Mo nit or (FSC M) al lows the dev ic e
to conti nue operating should th e e xte rna l os ci ll ator fail.
The FSCM can detect oscillator failure any time after
the Oscillator Start-up Timer (OST) has expired. The
FSCM is enabled by setting the FCMEN bit in the
Configuration Word register (CONFIG). The FSCM is
applicable to all external oscillator modes (LP, XT, HS,
EC, RC and RCIO).
FIGURE 3-8: FSCM BLOCK DIAGRAM
3.8.1 FAIL-SAFE DETECTIO N
The FSCM module detects a failed oscillator by
compari ng the extern al osci llat or to the FSCM sa mple
clock. The sample clock is generated by dividing the
LFINTOSC by 64. See Figure 3-8. Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock cle ars the latch on each rising edge of th e
sample clock. A failure is detected when an entire
half-cycle of the sample clock elapses before the
primary clock goes low.
3.8.2 FAIL-SAFE OPERATION
When the external clock fails, the FSCM switches the
devi ce clock to an interna l clock s ource and s ets the b it
flag OSFIF of the PIR1 register. Setting this flag will
generate an interrupt if the OSFIE bit of the PIE1
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation.
The internal clock source chosen by the FSCM is
determined by the IRCF<2:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.
3.8.3 FAIL-SAFE CONDITION CLEARING
The Fail-Safe condition is cleared after a Reset,
executing a SLEEP instruction or toggling the SCS bit
of the OSCCON register. When the SCS bit is toggled,
the OST is restarted. While the OST is running, the
device co ntinue s to op erate fro m the I NT OSC selecte d
in OSCCON. When the OST times out, the Fail-Safe
condition is cleared and the device will be operating
from the ex ternal cl ock sourc e. The Fai l-Safe co nditio n
must be c le ared bef ore th e O SFIF flag can be cle are d.
3.8.4 RESET OR WAKE-UP FROM SLEEP
The FSCM is designed to detect an oscillator failure
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
any type of Reset. The OST is not used with the EC or
RC Clock modes so that the FSCM will be active as
soon as the Reset or wake-up has completed. When
the FSCM is enabled, the Two-Speed Start-up is also
enabled . Therefore, the device will alway s be ex ecuting
code while the OST is operating.
External
LFINTOSC ÷ 64
S
R
Q
31 kHz
(~32 μs) 488 Hz
(~2 ms)
Clock Monitor
Latch
Clock
Failure
Detected
Oscillator
Clock
Q
Sample Clock Note: Due to the wide range of oscillator start-up
times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
OSTS bit of the OSCCON register to verify
the oscillator start-up and that the system
clock switchover has successfully
completed.
PIC12F683
DS41211D-page 30 © 2007 Microchip Technology Inc.
FIGURE 3-9: FSCM TIMING DIAGRAM
TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Val ue on
POR, BOR
Value on
all other
Resets(1)
CONFIG(2) CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0
INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x
OSCCON IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 x000 -110 x000
OSCTUNE TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu
PIE1 EEIE ADIE CCP1IE CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000
PIR1 EEIF ADIF CCP1IF CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000
Legend: x = unknown, u = unchanged, = unimplemented locations read as0’. Shaded cells are not used by oscillators.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: See Configuration Word register (Register 12-1) for operation of all register bits.
OSCFIF
System
Clock
Output
Sample Clock
Failure
Detected
Oscillator
Failure
Note: The system c lock is normally at a much higher frequency than the sam ple clock. The relative frequencies in
this example have been chosen for clarity.
(Q)
Test Test Test
Clock Monitor Output
© 2007 Microchip Technology Inc. DS41211D-page 31
PIC12F683
4.0 GPIO PORT
There are as many as six general purpose I/O pins
available. Depending on which peripherals are
enabled , some or all of the pins may not be a vailable as
general purpose I/O. In general, when a peripheral is
enabled, the associated pin may not be used as a
general purpose I/O pin.
4.1 GPIO and the TRISI O Registers
GPIO is a 6-bit wide, bidirectional port. The
corresponding data direction register is TRISIO.
Setting a TRISIO bit (= 1) will make the corresponding
GPIO pin an input (i.e., put the corresponding output
driver in a High-Impedance mode). Clearing a TRISIO
bit (= 0) will make the corresponding GPIO pin an
output (i.e., put the contents of the output latch on the
selected pin). An exception is GP3, which is input only
and its TRISIO bit will always read as ‘1’. Example 4-1
shows how to initialize GPIO.
Readi ng the GPIO regis ter reads the st atus of the pins,
whereas writing to it will write to the PORT latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pin s are
read, this value is modified and then written to the
PORT data latch. GP3 reads ‘0’ when MCLR E = 1.
The TRISIO register controls the direction of the GPIO
pins, ev en w he n th ey a re being used as ana log inputs .
The user must ensure the bits in the TRISIO register
are maintained set when using them as analog inputs.
I/O pins configured as analog input always read 0’.
EXAMPLE 4- 1: INITIALIZI NG GPIO
Note: The ANSEL and CMCON0 registers must
be initialized to configure an analog
channel as a digital input. Pins configured
as analog inputs will read ‘0’.
BANKSEL GPIO ;
CLRF GPIO ;Init GPIO
MOVLW 07h ;Set GP<2:0> to
MOVWF CMCON0 ;digital I/O
BANKSEL ANSEL ;
CLRF ANSEL ;digital I/O
MOVLW 0Ch ;Set GP<3:2> as inputs
MOVWF TRISIO ;and set GP<5:4,1:0>
;as outputs
REGISTER 4-1: GPIO: GENERAL PURPOSE I/O REGISTER
U-0 U-0 R/W-x R/W-0 R-x R/W-0 R/W-0 R/W-0
GP5 GP4 GP3 GP2 GP1 GP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0
bit 5-0 GP<5:0>: GPIO I/O Pin bit
1 = Port pin is > VIH
0 = Port pin is < VIL
PIC12F683
DS41211D-page 32 © 2007 Microchip Technology Inc.
4.2 Additional Pin Functions
Every GPIO pin on the PIC12F683 has an
interrupt-on-change option and a weak pull-up option.
GP0 has an Ultra Low-Power Wake-up option. The
nex t three sections describe these functions.
4.2.1 ANSEL REGISTER
The ANSEL register is used to configure the Input
mode of an I/O pin to analog. Setting the appropriate
ANSEL bit hi gh wil l ca us e all digi t al read s on the pi n to
be rea d as 0’ and allow analog functions on the pin to
operate correctly.
The state of the ANSEL bits has no affect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affec ted port.
4.2.2 WEAK PULL-UPS
Each of the GPIO pins, ex cept GP3, has an indivi dually
configurable internal weak pull-up. Control bits WPUx
enable or disable each pull-up. Refer to Register 4-4.
Each weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset by the GPPU bit of the
OPTION register). A weak pull-up is automatically
enabled for GP3 when configured as MCLR and
disabled when GP3 is an I/O. There is no software
control of the MCLR pull-up.
4.2.3 INTERRUPT-ON-CHANGE
Each of the GPIO pins is individually configurable as an
interrupt-on-change pin. Control bits IOCx enable or
disable the interrupt function for each pin. Refer to
Register 4-5. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
comp ared with the old val ue latch ed on the la st read of
GPIO. Th e ‘mismatch’ o utputs of t he last read are OR’d
together to set the GPIO Change Interrupt Flag bit
(GPIF) in the INTCON register (Register 3-3).
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, clears the
interrupt by :
a) Any read or write of GPIO. This will end the
mismatch condition, then,
b) Clear the flag bit GPIF.
A mismatch condition will continue to set flag bit GPIF.
Reading GPIO will end the mismatch condition and
allow flag bit GPIF to be cleared. The latch holding the
last read value is not affected by a MCLR nor
Brown-out Reset. After these resets, the GPIF flag will
continue to be set if a mismatch is present.
REGISTER 4-2: TRISIO GPIO TRI-STATE REGISTER
U-0 U-0 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1
—TRISIO5
(2,3) TRISIO4(2) TRISIO3(1) TRISIO2 TRISIO1 TRISIO0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0
bit 5:4 TRISIO<5:4>: GPIO Tri-State Control bit
1 = GPIO pin configured as an input (tri-stated)
0 = GPIO pin configured as an output
bit 3 TRISIO<3>: GPIO Tr i-State Control bit
Input only
bit 2:0 TRISIO<2:0>: GPIO Tri-State Control bit
1 = GPIO pin configured as an input (tri-stated)
0 = GPIO pin configured as an output
Note 1: TRISIO<3> always reads ‘1’.
2: TRISIO<5:4> always reads ‘1’ in XT, HS and LP OSC modes.
3: TRISIO<5> always reads ‘1’ in RC and RCIO and EC modes.
Note: If a change on the I/O pin should occur
when any GPIO operation is being
executed, then the GPIF interrupt flag may
not get set.
© 2007 Microchip Technology Inc. DS41211D-page 33
PIC12F683
REGISTER 4-3: ANSEL: ANALOG SELECT REGISTER
U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1
ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0
bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
bit 3-0 ANS<3:0>: Analog Select bits
Analog select between analog or digital function on pins AN<3:0>, respectively.
1 = Analog input. Pin is assigned as analog input(1).
0 = Digital I/O. Pin is assigned to port or special function.
Note 1: Setting a pin to an analog input automatically disables the digit al input circuitry, weak pull-ups and interrupt-on-change,
if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on
the pin.
PIC12F683
DS41211D-page 34 © 2007 Microchip Technology Inc.
REGISTER 4-4: WPU: WEAK PULL-UP REGISTER
U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1
WPU5 WPU4 WPU2 WPU1 WPU0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as0
bit 5-4 WPU<5:4>: Weak Pull-up Control bits
1 = Pull-up enabled
0 = Pull-up disabled
bit 3 Unimplemented: Read as0
bit 2-0 WPU<2:0>: Weak Pull-up Control bits
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global GPPU must be enabled for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISIO = 0).
3: The GP3 pull-up is enabled when configured as MCLR and disabled as an I/O in the Configuration Word.
4: WPU<5:4> always reads1’ in XT, HS and LP OSC modes.
REGISTER 4-5: IOC: INTERRUPT-ON-CHANGE GPIO REGISTER
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IOC5 IOC4 IOC3 IOC2 IOC1 IOC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as0
bit 5-0 IOC<5:0>: Interrupt-on-change GPIO Control bits
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.
2: IOC<5:4> always reads ‘0’ in XT, HS and LP OSC modes.
© 2007 Microchip Technology Inc. DS41211D-page 35
PIC12F683
4.2.4 ULTRA LOW-POWER WAKE-UP
The Ultra Low-Power Wake-up (ULPWU) on GP0
allows a slow falling voltage to generate an inter-
rupt-on-change on GP0 without excess current con-
sumption. The mode is selected by setting the
ULPWUE bit of the PCON register. This enables a
small current sink which can be used to discharge a
cap aci tor on GP0 .
To use this feature, the GP0 pin is configured to output
1’ to charge the capacitor, interrupt-on-change for GP0
is enabled and G P0 is configured as an input. The UL P-
WUE bit is set to begin the discharge and a SLEEP
instruction is performed. When the voltage on GP0
drops bel ow VIL, an interrupt will be ge nerated which will
cause the device to wake-up. Depending on the state of
the GIE bit of the INTCON register, the device will either
jump to the interrupt vector (0004h) or execute the next
instruction when the interrupt event occurs. See
Section 4.2.3 “Interrupt-on-Change” and
Section 12.4.3 “GPIO Interrupt” for more information.
This feature provides a low-power technique for period-
ically wak ing up th e de vi ce from Sleep. Th e tim e-o ut i s
dependent on the discharge time of the RC circuit
on GP0. See Example 4-2 for initializing the Ultra
Low-Power Wake-up module.
The series resistor provides overcurrent protection for
the GP0 pin and can allow for software calibration of the
time-out ( see F igu re 4- 1). A time r can be us ed to mea-
sure the cha rge ti me and disch ar ge time o f t he capaci-
tor . The charge time can then be adjusted to provide the
desired interrupt delay. This technique will compensate
for the affects of temperature, voltage and component
accuracy. The Ultra Low-Power Wake-up peripheral
can also be configured as a simple Programmable
Low-Voltage Detect or temperature sensor .
EXAMPLE 4-2: ULTRA LOW-POWER
WAKE-UP INITIALIZATION
Note: For mo re i nforma tion , ref er to the Appl ic a-
tion Note AN879, Using the Microchip
Ultra Low-Power Wake-up Module”
(DS00879).
BANKSEL CMCON0 ;
MOVLW H’7’ ;Turn off
MOVWF CMCON0 ;comparators
BANKSEL ANSEL ;
BCF ANSEL,0 ;RA0 to digital I/O
BCF TRISA,0 ;Output high to
BANKSEL PORTA ;
BSF PORTA,0 ;charge capacitor
CALL CapDelay ;
BANKSEL PCON ;
BSF PCON,ULPWUE ;Enable ULP Wake-up
BSF IOCA,0 ;Select RA0 IOC
BSF TRISA,0 ;RA0 to input
MOVLW B’10001000’ ;Enable interrupt
MOVWF INTCON ; and clear flag
SLEEP ;Wait for IOC
NOP ;
PIC12F683
DS41211D-page 36 © 2007 Microchip Technology Inc.
4.2.5 PIN DESCRIPTIONS AND
DIAGRAMS
Each GPIO pin is multiplexed with other functions. The
pins and their com bi ned f unc tio ns a r e bri efl y de sc ribed
here. For specific inf ormation about indi vidual function s
such as the comparator or the ADC, refer to the
appropriate section in this data sheet.
4.2.5.1 GP0/AN0/CIN+/ICSPDAT/ULPWU
Figur e 4-1 show s th e diag ram for th is pin . T he GP0 pin
is configurable to function as one of the following:
a general purpo se I/O
an analog input for the ADC
an analog input to the comparator
In-Ci rcuit Serial Programming™ data
an analog input to the Ultra Low-Power Wake-up
FIGURE 4-1: BLOCK DIAGRAM OF GP0
I/O pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
RD GPIO
RD
WR
WR
RD
WR
IOC
RD
IOC
Interrupt-on-
To Comparator
Analog
Input Mode(1)
GPPU
Analog
Input Mode(1)
Change
Q3
WR
RD
01
IULP
WPU
Data Bus
WPU
GPIO
TRISIO
TRISIO
GPIO
Note 1: Comparator mode and ANSEL determines Analog Input mode.
VT
ULPWUE
-
+
VSS
To A/D Converter
© 2007 Microchip Technology Inc. DS41211D-page 37
PIC12F683
4.2.5.2 GP1/AN1/CIN-/VREF/ICSPCLK
Figure 4-2 shows the d iagram fo r this pin. T he GP1 pin
is configurable to function as one of the following:
a general pu rpose I/ O
an analog input for the ADC
a analog input to the comparator
a voltage reference input for the ADC
In-Circuit Serial Programming clock
FIGURE 4-2: BLOCK DIAGRAM OF GP1
4.2.5.3 GP2/AN2/T0CKI/INT/COUT/CCP1
Figur e 4-3 show s th e diag ram for th is pin . T he GP2 pin
is configurable to function as one of the following:
a general purpo se I/O
an analog input for the ADC
the clock input for Timer0
an external edge triggered interrupt
a digita l outp ut from the Com p ara tor
a digital input/output for the CCP (refer to
Section 11.0 “Capture/Compare/PWM (CCP)
Module”).
FIGURE 4-3: BLOCK DIAGRAM OF GP2
I/O pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Data
WR
WPU
RD
WPU
RD GPIO
RD
GPIO
WR
GPIO
WR
TRISIO
RD
TRISIO
WR
IOC
RD
IOC
Interrupt-on-
To Comparator
Analog
Input Mode(1)
GPPU
Analog
Input Mode(1)
change
Bus
Note 1: Comparator mode and ANSEL determines Analog
Input mode.
Q3
To A/D Converter
I/O pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Analog
Input Mode
Data
WR
WPU
RD
WPU
RD
GPIO
WR
GPIO
WR
TRISIO
RD
TRISIO
WR
IOC
RD
IOC
To A/D Converter
0
1
COUT
COUT
Enable
To INT
To Timer0
Analog
Input Mode
GPPU
RD GPIO
Analog
Input
Mode
Interrupt-on-
change
Bus
Q
3
Note 1: Comparator mode and ANSEL determines Analog
Input mode.
PIC12F683
DS41211D-page 38 © 2007 Microchip Technology Inc.
4.2.5.4 GP3/MCLR/VPP
Figure 4-4 shows the d iagram fo r this pin. T he GP3 pin
is configurable to function as one of the following:
a general pu rpose input
as Master Clear Reset with weak pull-up
FIGURE 4-4: BLOCK DIAGRAM OF GP3
4.2.5.5 GP4/AN3/T1G/OSC2/CLKOUT
Figur e 4-5 show s th e diag ram for th is pin . T he GP4 pin
is configurable to function as one of the following:
a general purpo se I/O
an analog input for the ADC
a Timer1 gate input
a cryst al/ reso nator connectio n
a cloc k outpu t
FIGURE 4-5: BLOCK DIAGRAM OF GP4
Input
VSS
D
Q
CK
Q
D
EN
Q
Data
RD GPIO
RD
WR
IOC
RD
Reset MCLRE
RD VSS
D
EN
Q
MCLRE
VDD
Weak
MCLRE
Interrupt-on-
change
pin
GPIO
IOC
Bus
TRISIO
Q3
I/O pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Analog
Input Mode
Data
WR
WPU
RD
WPU
RD
GPIO
WR
GPIO
WR
TRISIO
RD
TRISIO
WR
IOC
RD
IOC
FOSC/4
To A/D Converter
Oscillator
Circuit
OSC1
CLKOUT
0
1
CLKOUT
Enable
Enable
Analog
Input Mode
GPPU
RD GPIO
To T1G
INTOSC/
RC/EC(2)
CLK(1)
Modes
CLKOUT
Enable
Note 1: CLK modes are XT, HS, LP, optiona l LP oscillator and
CLKOUT Enable.
2: With CLKOUT option.
Interrupt-on-
change
Bus
Q3
© 2007 Microchip Technology Inc. DS41211D-page 39
PIC12F683
4.2.5.6 GP5/T1CKI/OSC1/CLKIN
Figure 4-6 shows the d iagram fo r this pin. T he GP5 pin
is configurable to function as one of the following:
a general pu rpose I/ O
a Timer1 clock input
a crystal/resonator connection
a clock input
FIGURE 4-6: BLOCK DIAGRAM OF GP5
TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH GPIO
I/O pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Data
WR
WPU
RD
WPU
RD
GPIO
WR
GPIO
WR
TRISIO
RD
TRISIO
WR
IOC
RD
IOC
To Ti mer1 or CLKGEN
INTOSC
Mode
RD GPIO
INTOSC
Mode
GPPU
OSC2
(1)
Note 1: Timer1 LP oscillator enabled.
2: When using Timer1 with LP oscillator, the
Schmitt Tri gger is bypassed.
TMR1LPEN(1)
Interrupt-on-
change
Oscillator
Circuit
Bus
Q3
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on
POR, BOR
Va lue on
all other
Resets
ANSEL ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 -000 1111
CCP1CON DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CMCON0 COUT CINV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000
PCON —ULPWUESBOREN POR BOR --01 --qq --0u --uu
INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x
IOC IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 --00 0000
OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
GPIO GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --x0 x000
T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 0000 0000
TRISIO TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
WPU WPU5 WPU4 WPU2 WPU1 WPU0 --11 -111 --11 -111
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by GPIO.
PIC12F683
DS41211D-page 40 © 2007 Microchip Technology Inc.
NOTES:
© 2007 Microchip Technology Inc. DS41211D-page 41
PIC12F683
5.0 TIMER0 MODULE
The Timer0 module is an 8-bit timer/counter with the
following features:
8-bit timer/counter register (TMR0)
8-bit prescaler (shared with Watchdog Timer)
Programmable internal or external clock source
Programmable external clock edge selection
Inter rupt on ov erflow
Figure 5-1 is a block diagram of the Timer0 module.
5.1 Timer0 Operation
When use d as a tim er, the T imer0 modul e can be used
as either an 8-bit timer or an 8-bit counter.
5.1.1 8-BIT TIMER MODE
When used as a timer, the Timer0 module will
increment every instruction cycle (without prescaler).
Timer mode is selected by clearing the T0CS bit of the
OPTION register to ‘0’.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
5.1.2 8-BIT COUNTER MODE
When used as a counter, the Timer0 module will
increment on every rising or falling edge of the T0CKI
pin. The incrementing edge is determined by the T0SE
bit of the OPTION register . Counter mode is selected by
setting the T0CS bit of the OPTION register to 1’.
FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Note: The value writ ten to the T MR0 register can
be adju sted, in order to ac count for th e two
instruction cycle delay when TMR0 is
written.
T0CKI
T0SE
pin
TMR0
Watchdog
Timer
WDT
Time-out
PS<2:0>
WDTE
Data Bus
Set Flag bi t T0 IF
on Overflow
T0CS
Note 1: T0SE, T0CS, PSA, PS<2:0> ar e bits in the OPTION register.
2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register.
3: WDTE bit is in the Configuration Word register.
0
1
0
1
0
1
8
8
8-bit
Prescaler
0
1
FOSC/4
PSA
PSA
PSA
16-bit
Prescaler 16
WDTPS<3:0>
31 kHz
INTOSC
SWDTEN
Sync
2 Tcy
PIC12F683
DS41211D-page 42 © 2007 Microchip Technology Inc.
5.1.3 SOFTWARE PROGR AMMABLE
PRESCALER
A single software programmable prescaler is available
for use with either Timer0 or the Watchdog Timer
(WDT), but not both simultaneously. The prescaler
assignme nt is control led by the PSA bit o f the OPTI ON
register. To assign t he p res caler to T im er 0, th e PSA b it
must be cleared to a0’.
There are 8 prescaler options for the Timer0 module
ranging from 1:2 to 1:256. The prescale values are
select able via the PS<2:0> bit s of the OPTIO N register .
In order to have a 1:1 prescaler value for the Timer0
module, the prescaler must be assigned to the WDT
module.
The prescaler is not readable or writable. When
assigned to the T im er0 module, all instructions writing to
the TMR0 register will clear the prescaler.
When the prescaler is assigned to WDT, a CLRWDT
instruction will clear the prescaler along with the WDT.
5.1.3.1 Switching Prescaler Between
Timer0 and WDT Modules
As a result of having the prescaler assigned to either
Timer0 or the WDT, it is possible to generate an
unintended device Reset when switching prescaler
values . When chan gin g th e presca le r ass ig nme nt from
Timer0 to the WDT module, the instruction sequence
shown in Example 5-1, must be executed.
EXAMPLE 5-1: CHANGING PRESCALER
(TIMER0 WDT)
When changing the prescaler assignment from the
WDT to the Timer0 module, the following instruction
sequence must be executed (see Example 5-2).
EXAMPLE 5-2: CHANGING PRESCALER
(WDT TIMER0)
5.1.4 TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The T0IF interrupt
flag bit of the INTCON register is set every time the
TMR0 register overflows, regardless of whether or not
the Timer0 interrupt is enabled. The T0IF bit must be
cleared in software. The Timer0 interrupt enable is the
T0IE bit of the INTCON register.
5.1.5 USING TIMER0 WITH AN
EXTERNAL CLOCK
When Timer 0 is in Coun ter mode, t he synchronizatio n
of the T0CKI input and the Timer0 register is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, the
high and low peri od s of the ex tern al cl oc k so urc e mus t
meet the timing requirements as shown in the
Section 15.0 “Electrical Specifications”.
BANKSEL TMR0 ;
CLRWDT ;Clear WDT
CLRF TMR0 ;Clear TMR0 and
;prescaler
BANKSEL OPTION_REG ;
BSF OPTION_REG,PSA ;Select WDT
CLRWDT ;
;
MOVLW b’11111000’ ;Mask prescaler
ANDWF OPTION_REG,W ;bits
IORLW b’00000101’ ;Set WDT prescaler
MOVWF OPTION_REG ;to 1:32
Note: The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
CLRWDT ;Clear WDT and
;prescaler
BANKSEL OPTION_REG ;
MOVLW b’11110000’ ;Mask TMR0 select and
ANDWF OPTION_REG,W ;prescaler bits
IORLW b’00000011’ ;Set prescale to 1:16
MOVWF OPTION_REG ;
© 2007 Microchip Technology Inc. DS41211D-page 43
PIC12F683
TABLE 5-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
REGISTER 5-1: OPTION_REG: OPTION REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GPPU: GPIO Pull-up Enable bit
1 = GPIO pull-ups are disabled
0 = GPIO pull-ups are enabled by individual PORT latch values in WPU register
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5 T0CS: Timer0 Clock Source S elect bit
1 = Transit ion on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assig nme nt bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Note 1: A dedicated 16-bit WDT postscaler is available. See Section 12.6 “Watchdog Timer (WDT)” for more
information.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x
OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
TRISIO TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the T imer0
module.
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
BIT VALUE TIMER0 RATE WD T RATE
PIC12F683
DS41211D-page 44 © 2007 Microchip Technology Inc.
6.0 TIMER1 MODULE WITH GATE
CONTROL
The Timer1 module is a 16-bit timer/counter with the
following features:
16-bit tim er/coun ter register p air (TMR 1H:TMR 1L)
Programmable internal or external clock source
3-bit prescaler
Op tional LP oscillator
Synchronous or asynchronous operation
Timer1 gate (count enable) via comparator or
T1G pin
Inter rupt on ov erflow
Wake-up on overflow (external cloc k,
Asynchronous mode only)
Specia l Event Trigger (with CCP)
Comparator output synchronization to Timer1
clock
Figure 6-1 is a block diagram of the Timer1 module.
6.1 Timer1 Operation
The Timer1 module is a 16-bit incrementing counter
which is acces sed through the TMR 1H:TMR1L reg ister
pair. Writes to TMR1H or TMR1L directly update the
counter.
When us ed with an interna l clock so urce, the module i s
a time r. When us ed wit h an ext erna l clock source, the
module can be used as either a timer or counter.
6.2 Clock Source Selection
The TMR1CS bit of the T1CON register is used to select
the clock source. When TMR1CS = 0, the clock source
is FOSC/4. When TMR1CS = 1, the clock source is
supplied exte rnally.
FIGURE 6-1: TIMER1 BLOCK DIAGRAM
Clock Source TMR1CS
FOSC/4 0
T1CKI pin 1
TMR1H TMR1L
Oscillator T1SYNC
T1CKPS<1:0>
Prescaler
1, 2, 4, 8 Synchronize(3)
det
1
0
0
1
Synchronized
clock input
2
Set flag bit
TMR1IF on
Overflow TMR1(2)
TMR1GE
TMR1ON
T1OSCEN
1
0
COUT
T1GSS
T1GINV
To Comparator Module
Timer1 Clock
TMR1CS
OSC2/T1G
OSC1/T1CKI
Note 1: ST Buffer is low power type when using LP oscillator, or high speed type when using T1CKI.
2: Timer1 register increm ents on rising edge.
3: Synchronize does not operate while in Sleep.
(1)
EN
INTOSC
Without CLKOUT
FOSC/4
Internal
Clock
© 2007 Microchip Technology Inc. DS41211D-page 45
PIC12F683
6.2.1 INTERNAL CLOCK SOURCE
When the internal clock source is selected the
TMR1H:TMR1L register pair will increment on multiples
of TCY as determined by the T ime r1 p rescaler.
6.2.2 EXTERNAL CLOCK SOURCE
When the external clock source is selected, the Timer1
module may wo rk as a timer or a cou nter.
When counting, Timer1 is incremented on the rising
edge of the external clock input T1CKI. In addition, the
Counter mode clock can be synchronized to the
microcontroller system clock or run async hronously.
If an external clock oscillator is needed (and the
microc ontroller is using the INTOS C withou t CLKOUT),
Timer1 can use the LP oscillator as a clock source.
6.3 Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPS bits of the
T1CON register control the prescale counter. The
prescale counter is not directly readable or writable;
however , the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
6.4 Timer1 Oscillator
A low-power 32.768 kHz crystal oscillator is built-in
between pins OSC1 (input) and OSC2 (amplifier
output). The oscillator is enabled by setting the
T1OSCEN control bit of the T1CON register. The
oscillator will continue to run during Sleep.
The Timer1 oscillator is shared with the system LP
oscillator. Thus, Timer1 can use this mode only when
the primary system clock is derived from the internal
oscill ator or when in LP osci llator mod e. The user m ust
provide a software time delay to ensure proper oscilla-
tor start-up.
TRISI O < 5 : 4> bits ar e set wh en th e Timer1 os ci l la tor is
enabled. GP5 and GP4 bits read as ‘0’ and TRISIO5
and TRISIO4 bits read as1’.
6.5 Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYNC of the T1CON register is set, the
external clock input is not synchronized. The timer
continues to increment asynchronous to the internal
phase clocks. The timer will continue to run during
Sleep and can generate an interrupt on overflow,
which will wake-up the processor. However, special
precautions in software are needed to read/write the
timer (see Section 6.5.1 “Reading and Writing
Timer1 in Asynchronous Counter Mode”).
6.5.1 READING AND WRITING T IMER1 IN
ASYNCHRONOUS COUNTER
MODE
Reading TMR1H or TMR1L while the timer is running
from an e xternal asyn chronous cl ock will ens ure a valid
read (taken care of in hardware). However, the user
should keep i n mind that rea ding t he 16-bi t time r in tw o
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes , it is re commend ed that th e user s imply sto p
the timer and write the desired values. A write
conte ntion may occ ur by w ritin g to th e timer regist ers,
while the register is incrementing. This may pro duce an
unpredictable value in the TMR1H:TTMR1L register
pair.
6.6 Timer1 Gate
Timer1 gate source is software configurable to be the
T1G pin or the output of the Com parator. This allows the
device to directly time external events using T1G or
analog events using Comparator 2. See the CMCON1
register (Register 8-2) for selecting the Timer1 gate
source. This feature can simplify the software for a
Delta-Sigma A/D converter and many other applications.
For more information on Delta-Sigma A/D converters,
see the Microchip w eb site (www.microchip.com).
Timer1 gate can be inverted using the T1GINV bit of
the T1CON register, whether it orig inates from the T1G
pin or Comparator 2 output. This configures Timer1 to
measure either the active-high or active-low time
between events.
Note: In Counter mode, a falling edge must be
registered by the counter prior to the first
incr em enti ng ris ing edge.
Note: The oscillator requires a start-up and
stabilization time before use. Thus,
T1OSCEN should be set and a suitable
delay observed prior to enabling Timer1.
Note: When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce a single spurious
increment.
Note: TMR1GE bit of the T1CON register must
be set to use either T1G or COUT as the
Timer1 gate source. See Register 8-2 fo r
more information on selecting the Timer1
gate sou rce .
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DS41211D-page 46 © 2007 Microchip Technology Inc.
6.7 Timer1 Interrupt
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Ti mer1 in terrupt fl ag bit of th e PIR1 regis ter is
set. To enable the interrupt on rollover, you must set
these bits:
Timer1 interrupt enable bit of the PIE1 register
PEIE bit of the INTCON register
GIE bit of the INTCON register
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
6.8 Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in
Asynch ronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
TMR1ON bit of the T1CON register must be set
TMR1IE bit of the PIE1 register must be set
PEIE bit of the INTCON register must be set
The device will wake-up on an overflow and execute
the next instruction. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine (0004h).
6.9 CCP Special Event Trigger
If a CCP is configured to trigger a special event, the
trigger will clear the TMR1H:TMR1L register pair. This
special event does not cause a Timer1 interrupt. The
CCP mo dule may still be configured to ge nerate a CCP
interrupt.
In this mode of o peration, the CCPR1H:CCPR1L regis-
ter pair effectively becomes the period register for
Timer1.
Timer1 should be synchronized to the FOSC to utilize
the Special Event Trigger. Asynchronous operation of
Timer1 can cause a Special Event Trigger to be
missed.
In the eve nt that a wri te to TMR1H or TM R1L coinci des
with a Special Even t Tr igger from t he CCP, the write will
take precedence.
For more information, see Section on CCP.
6.10 Comparator Synchronization
The same clock us ed to increment Timer1 can also be
used to synchronize the comparator output. This
feature is enabled in the Comparator module.
When using the comparator for Timer1 gate, the
comparator output should be synchronized to Timer1.
This ensures Timer1 does not miss an increment if the
comp ara tor changes.
For more information, see Section 8.0 “Comparator
Module”.
FIGURE 6-2: TIMER1 INCREMENTING EDGE
Note: The T MR1H:TTMR1L register p air and the
TMR1IF bit should be cleared before
enabling interrupts.
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Ar rows indicate counter increm ents.
2: In Counter mode, a falling edge must be re gistered by the counter prior to t he first incrementing rising edge of
the clock.
© 2007 Microchip Technology Inc. DS41211D-page 47
PIC12F683
6.11 Timer1 Control Register
The Timer1 Control register (T1CON), shown in
Register 6-1, is used to control Timer1 and select the
various features of the Timer1 module.
REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
T1GINV(1) TMR1GE(2) T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 T1GINV: Timer1 Gate Invert bit(1)
1 = Timer1 gate is active-high (Timer1 counts when gate is high)
0 = Timer1 gate is active-low (Timer1 counts when gate is low)
bit 6 TMR1GE: Timer1 Gate Enable bit(2)
If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1 = Timer1 is on if Timer1 gate is not active
0 = Timer1 is on
bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale Value
10 = 1:4 Prescale Value
01 = 1:2 Prescale Value
00 = 1:1 Prescale Value
bit 3 T1OSCEN: LP Osci lla tor Enab le C ontro l bit
If INTOSC without CLKOUT oscillator is active:
1 = LP oscillator is enabled for Timer1 clock
0 = LP oscillator is off
Else:
This bit is ignored. LP oscillator is disabled.
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1 CS = 1:
1 = Do not synchroniz e exte rnal cloc k inp ut
0 = Synchronize external clock input
TMR1 CS = 0:
This bit is ignored. Timer1 uses the internal clock
bit 1 TMR1CS: Timer1 Clock Sourc e Sele ct bit
1 = External clock from T1CKI pin (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source.
2: TMR1GE bit must be set to use either T1G pin or COUT, as selected by the T1GSS bit of the CMCON1
register, as a Timer1 gate source.
PIC12F683
DS41211D-page 48 © 2007 Microchip Technology Inc.
TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all othe r
Resets
CONFIG(1) CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0
CMCON1 —T1GSSCMSYNC ---- --10 ---- --10
INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x
PIE1 EEIE ADIE CCP1IE CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000
PIR1 EEIF ADIF CCP1IF CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
Legend: x = unknown, u = unchanged, = unimplemented, read as0’. Shaded cells are not used by the Timer1 module.
Note 1: See Configuration Word register (Register 12-1) for operation of all register bits.
© 2007 Microchip Technology Inc. DS41211D-page 49
PIC12F683
7.0 TIMER2 MODULE
The Timer2 module is an 8-bit timer with the following
features:
8-bit timer register (TMR2)
8-bit period register (PR2)
Interrupt on TMR2 match with PR2
Software programmable prescaler (1:1, 1:4, 1:16)
Software programmable postscaler (1:1 to 1:16)
See Figure 7-1 for a block diagram of Timer2.
7.1 Timer2 Operation
The clock input to the Timer2 module is the system
instruction clock (FOSC/4). The clock is fed into the
Timer2 prescaler, which has prescale options of 1:1,
1:4 or 1:16. The output of the prescal er is the n use d to
increm ent the TM R2 regis ter.
The val ues of T MR2 and PR2 are co nstan tly com pared
to determine when they match. TMR2 will increment
from 00h until it matches the value in PR2. When a
match occurs, two things happen:
TMR2 is reset to 00h on the next increment cycle.
The Timer2 postscaler is incremented
The match output of the Timer2/PR2 comparator is
then fed into th e T i mer2 post sca ler. The post sca ler has
post scal e options of 1 :1 to 1: 16 inclus ive. The output of
the Timer2 postscaler is used to set the TMR2IF
interrupt flag bit in the PIR1 register.
The TMR2 and PR2 registers are both fully readable
and w rita ble. O n any Rese t, the TMR2 regis ter is set to
00h and the PR2 register is set to FFh.
Timer2 is turned on by setting the TMR2ON bit in the
T2CON register to a ‘1’. Tim er2 is turned off by clearin g
the TMR2ON bit to a ‘0’.
The Timer2 presc ale r is contro lle d by the T2CKPS bits
in the T2CON register. The Timer2 postscaler is
controlled by the TOUTPS bits in the T2CON register.
The prescaler and postscaler counters are cleared
when:
A write to TMR2 occurs.
A write to T2CON occurs.
Any device Reset occurs (Power-on Rese t, MCLR
Reset, Wa tchdog Timer Reset, or Brown-out
Reset).
FIGURE 7-1: TIMER2 BLOCK DIAGRAM
Note: TMR2 is not cleared when T2CON is
written.
Comparator
TMR2 Sets Flag
TMR2
Output
Reset
Postscaler
Prescaler
PR2
2
FOSC/4
1:1 to 1:16
1:1, 1:4, 1:16
EQ
4
bit TMR2IF
TOUTPS<3:0>
T2CKPS<1:0>
PIC12F683
DS41211D-page 50 © 2007 Microchip Technology Inc.
TABLE 7-1: SUMMARY OF ASSOCIATED TIMER2 REGISTERS
REGISTER 7-1: T2CON: TIMER 2 CONTROL REGISTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as0
bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits
0000 = 1:1 Postscaler
0001 = 1:2 Postscaler
0010 = 1:3 Postscaler
0011 = 1:4 Postscaler
0100 = 1:5 Postscaler
0101 = 1:6 Postscaler
0110 = 1:7 Postscaler
0111 = 1:8 Postscaler
1000 = 1:9 Postscaler
1001 = 1:10 Postscaler
1010 = 1:11 Po stscaler
1011 = 1:12 Postscaler
1100 = 1:13 Postscaler
1101 = 1:14 Postscaler
1110 = 1:15 Postscaler
1111 = 1:16 Postscaler
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00 =Prescaler is 1
01 =Prescaler is 4
1x = Prescaler is 16
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x
PIE1 EEIE ADIE CCP1IE CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000
PIR1 EEIF ADIF CCP1IF CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000
PR2 Timer2 Module Period Register 1111 1111 1111 1111
TMR2 Holding Register for the 8-bit TMR2 Register 0000 0000 0000 0000
T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as 0’. Shaded cells are not used for Timer2 module.
© 2007 Microchip Technology Inc. DS41211D-page 51
PIC12F683
8.0 COMPARATOR MODULE
Comparators are used to interface analog circuits to a
digital circuit by comparing two analog voltages and
providing a digital indication of their relative magnitudes.
The comparators are very useful mixed signal building
blocks because they provide analog functionality
independent of the program execution. The analog
comparator module includes the following features:
Multiple comparator configurations
Comparator ou tput is avail able internall y/externally
Programmable output polarity
Interrupt-on-change
Wake-up from Sleep
Timer1 gate (co unt ena ble)
Output synchronization to Timer1 clock input
Programmable volt age reference
8.1 Comparator Overview
The comparator is shown in Figure 8-1 along with the
relationship between the analog input levels and the
digital output. When the analog voltage at VIN+ is less
than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
VIN-, the outp ut of the comp arator is a digita l high le vel.
FIGURE 8-1: SINGLE COMPARATOR
FIGURE 8-2: COMPARATOR OUTPUT BLOCK DIAGRAM
+
VIN+
VIN-Output
Output
VIN+
VIN-
Note: The black areas of the output of the
comparator represents the uncertainty
due to input offsets and response time.
CMSYNC
DQ
EN
To COUT pin
RD CMCON0
Set CMIF bit
MULTIPLEX
Port Pins
Q3*RD CMCON0
Reset
To Data B u s
CINV
Timer1
clock sourc e(1)
0
1
To Timer1 Gate
Note 1: Com parator output is latched on falling edge of Timer1 clock source.
2: Q1 and Q3 are phases of the four-phase sys tem clock (FOSC).
3: Q1 is held high during Sleep mode.
DQ
DQ
EN
CL
Q1
PIC12F683
DS41211D-page 52 © 2007 Microchip Technology Inc.
8.2 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 8-3. Sinc e the analo g input pins share thei r con-
nection with a digital input, they have reverse biased
ESD protection diodes to VDD and VSS. The analog
input, therefore, must be between VSS and VDD. If the
input voltage deviates from this range by more than
0.6V in either direction, one of the diodes is forward
biased and a latch-up may occur.
A maximum source impedance of 10 kΩ is recommended
for the analog sources. Also, any external component
connected to an anal og inpu t pin, such as a capacitor or
a Zener diode, should h ave very little leakage curr ent to
minimize inaccuracies introduced.
FIGURE 8-3: ANALOG INPUT MODEL
Note 1: When reading a PORT register, all pins
configu red a s anal og inp uts will read as a
0’. Pins configured as digital inputs will
convert as an analog input, according to
the input specification.
2: Analog levels on any pin defined as a
digit al input, may ca use the input buff er to
consume more current than is specified.
VA
Rs < 10K
CPIN
5 pF
VDD
VT 0.6V
VT 0.6V
RIC
ILEAKAGE
±5 00 nA
Vss
AIN
Legend: CPIN = Input Capaci tance
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconne ct Resista nce
RS= Source I mpedance
VA= Analog Voltage
VT= Threshold Voltage
To ADC Input
© 2007 Microchip Technology Inc. DS41211D-page 53
PIC12F683
8.3 Comparator Configuration
There are eigh t mod es of operat ion fo r the comp arato r.
The CM<2:0 > bit s of the C MCON0 reg ister are used to
select these modes as shown in Figure 8-4.
Analog function (A): digital input buffer is disabled
Digital function (D): comparator digital output,
overrides port function
Normal port function (I/O): independent of com-
parator
The port pins denoted as “A” will read as a ‘0
regardless of the state of the I/O pin or the I/O control
TRIS bit. Pins used as analog inputs should also have
the corresponding TRIS bit set to ‘1’ to disable the
digital output driver. Pins denoted as “D” should have
the corresponding TRIS bit set to0’ to enable the
digital output driver.
FIGURE 8-4: COMPARATOR I/O OPERATING MODES
Note: Compara tor in terr upts sh ould be dis abled
during a Comparator mode change to
preve nt uni nten de d interru pt s .
Comparator Reset (POR Default Value – low power) Comparator w/o Output and with Internal Reference
CM<2:0> = 000 CM<2:0> = 100
Comparator with Output Multiplexed Input with Internal Reference and Output
CM<2:0> = 001 CM<2:0> = 101
Comparator without Output Multiplexed Input with Internal Reference
CM<2:0> = 010 CM<2:0> = 110
Comparator with Output and Internal Reference Comparator Off (Lowest power)
CM<2:0> = 011 CM<2:0> = 111
Legend: A = Analog Input, ports always reads 0 CIS = Comparator Input Switch (CMCON0<3>)
I/O = Normal port I/O D = Comparator Digital Output
Note 1: Reads as ‘0’, unless CINV = 1.
CIN-
CIN+ Off(1)
A
A
COUT (pin) I/O
CIN-
CIN+ COUT
A
I/O
COUT (pin) I/O From CV REF Module
CIN-
CIN+ COUT
A
A
COUT (pin) D
CIN-
CIN+ COUT
A
A
COUT (pin) D
From CVREF Module
CIS = 0
CIS = 1
CIN-
CIN+ COUT
A
A
COUT (pin) I/O
CIN-
CIN+ COUT
A
A
COUT (pin) I/O
From CVREF Module
CIS = 0
CIS = 1
CIN-
CIN+ COUT
A
I/O
COUT (pin) D
From CVREF Module
CIN-
CIN+ Off(1)
I/O
I/O
COUT (pin) I/O
PIC12F683
DS41211D-page 54 © 2007 Microchip Technology Inc.
8.4 Comparator Control
The CMCON0 register (Register 8-1) provides access
to the following comparator features:
Mode selection
Output state
Output pol arit y
Input switch
8.4.1 COMPARATOR OUTPUT STATE
The Com parator st ate can a lways be read int ernally via
the COU T bit o f the CMC ON0 regi ster . T he comp arat or
state may also be directed to the COUT pin in the
following modes:
CM<2:0> = 001
CM<2:0> = 011
CM<2:0> = 101
When one of the above modes is selected, the associ-
ated TRIS bit of the COUT pin must be cleared.
8.4.2 COMPARATOR OUTPUT POLARITY
Inverting the output of the comparator is functionally
equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
setting the CINV bit of the CMCON0 register. Clearing
CINV result s in a non-inv erted outp ut. A comple te tabl e
showing the output state versus input conditions and
the polarity bit is shown in Table 8-1.
TABLE 8-1: OUTPUT STATE VS. INPUT
CONDITIONS
8.4.3 COMPARATOR INPUT SWITCH
The inverti ng input of the comp arator may be swit ched
between two analog pins in the following modes:
CM<2:0> = 101
CM<2:0> = 110
In the above modes, both pins remain in analog mode
regardless of which pin is selected as the input. The
CIS bit of the CMCON0 register controls the comparator
input swi tch.
8.5 Comparator Response Time
The comparator output is indeterminate for a period of
time afte r the change of an i nput source or the selection
of a new refe rence volta ge. This period is refer red to as
the response time. The response time of the
comparator differs from the settling time of the voltage
reference. Therefore, both of these times must be
considered when determining the total response time
to a comparator input change. See the Comparator and
Voltage Reference Specifications in Section 15.0
“Electrical Specifications” for more details.
Input Conditions CINV COUT
VIN- > VIN+00
VIN- < VIN+01
VIN- > VIN+11
VIN- < VIN+10
Note: COUT refers to both the register bit and
output pin.
© 2007 Microchip Technology Inc. DS41211D-page 55
PIC12F683
8.6 Comparator Interrupt Operation
The comparator interrupt flag is set whenever there is
a change in the output value of the comparator.
Changes are recognized by means of a mismatch cir-
cuit which consists of two latches and an exclusive-or
gate (see Figure 8.2). One latch is updated with the
comparator output level when the CMCON0 register is
read. This latch retains the value until the next read of
the CMCON0 register or the occurrence of a Reset.
The other latch of the mismatch circuit is updated on
every Q1 system clock. A mismatch condition will occur
when a comparator output change is clocked through
the second latch on the Q1 clock cycle. The mismatch
condition will persist, holding the CMIF bit of the PIR1
register true, until either the CMCON0 register is read
or the comparator output returns to the previous state.
Software will need to maintain information about the
stat us of the comp arator outp ut to determine the actual
change that has occurred.
The CMIF bit of the PIR1 register, is the comparator
interrupt flag. This bit must be reset in software by
clearing it to0’. Since i t is a lso po ssib le t o writ e a ‘1’ to
this register, a simulated interrupt may be initiated.
The CMIE bit of the PIE1 register and the PEIE and GIE
bits of the INTCON register must all be set to enable
comparator interrupts. If any of these bits are cleared,
the interrupt is not enabled, although the CMIF bit of
the PIR1 regist er will s till b e set i f an inte rrupt co nditio n
occurs.
The use r , in the Interru pt Service Rout ine, can clear th e
inter rupt in the fol lowi ng man ne r :
a) Any read or write of CMCON0. This will end the
mismatch condition.
b) Clear the CMIF int errup t flag.
A persistent mismatch condition will preclude clearing
the CMIF in terrupt flag. Read ing C MCO N0 wil l e nd th e
mismatch condition and allow the CMIF bit to be
cleared.
FIGURE 8-5: COMPARATOR
INTERRUPT TIMING W/O
CMCON0 READ
FIGURE 8-6: COMPARATOR
INTERRUPT TIMING WITH
CMCON0 READ
Note: A write op erati on to the CMCON0 regist er
will also clear the mismatch condition
because all writes include a read
operation at the beginning of the write
cycle.
Note: If a change in the CMCON0 register
(COUT) should occur when a read
operation is being executed (start of the
Q2 cycle), then the CMIF interrupt flag
may not get set.
Note 1: If a change in the CMCON0 register
(COUT) s hould occur when a re ad opera-
tion is being executed (start of the Q2
cycle ), then the CMIF of the PIR1 regist er
interrupt flag may not get set.
2: When either comparator is first enabled,
bias circuitry in the Comparator module
may cause an invalid output from the
comparator until the bias circuitry is
stable. Allow about 1 μs for bias settling
then clear the mismatch condition and
interrupt flags before enabling comparator
interrupts.
Q1
Q3
CIN+
COUT
Set CMIF (level)
CMIF
TRT
reset by software
Q1
Q3
CIN+
COUT
Set CMIF (level)
CMIF
TRT
reset by software
cleared by CMCON0 read
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DS41211D-page 56 © 2007 Microchip Technology Inc.
8.7 Operation During Sleep
The compa rator , if enabled b efore entering Sleep mode,
remains active during Sleep. The additional current
consumed by the comparator is shown separately in
Section 15.0 “Electrical Specifications”. If the
comparator is not used to wake the device, power
consumption can be minimized while in Sleep mode by
turning off the c omparator. The comparator is turned off
by se lec ting m ode CM< 2:0 > = 000 or CM<2:0> = 111
of the CMCON0 register.
A change to the comparator output can wake-up the
device from Sleep. To enable the comparator to wake
the dev ice from Sleep, th e CMIE bit of the PIE1 register
and the PEIE bit of the INTCON register must be set.
The instruction following the Sleep instruction always
executes following a wake from Sleep. If the GIE bit of
the INTCON register is also set, the device will then
execute the Interrupt Service Routine.
8.8 Effects of a Reset
A device Reset forces the CMCON0 and CMCON1
registers to th eir Res et st ates . This forc es th e Comp ar-
ator module to be in the Comparator Reset mode
(CM<2:0> = 000). Thus, all comparator inputs are
analog inp uts with the comp arator disabled to consume
the smallest current possible.
REGISTER 8-1: CMCON0: COMPARATOR CONFIGURATION REGISTER
U-0 R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—COUT CINV CIS CM2 CM1 CM0
bit 7 bit 0
Legend:
R = Readable bi t W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0
bit 6 COUT: Comparator Output bit
When CINV = 0:
1 = VIN+ > VIN-
0 = VIN+ < VIN-
When CINV = 1:
1 = VIN+ < VIN-
0 = VIN+ > VIN-
bit 5 Unimplemented: Read as ‘0
bit 4 CINV: Comparator Output Inversion bit
1 = Output inverted
0 = Output not inverted
bit 3 CIS: Comparator I nput Switch bit
When CM <2:0> = 110 or 101:
1 = CIN+ connects to VIN-
0 = CIN- connects to VIN-
When CM <2:0> = 0xx or 100 or 111:
CIS has no effect.
bit 2-0 CM<2:0>: Comparator Mode bits (See Figure 8-5)
000 = CIN pins are configured as analog, COUT pin configured as I/O, Comparator output turned off
001 = CIN pins are configured as analog, COUT pin configured as Comparator output
010 = CIN pins are configured as analog, COUT pin configured as I/O, Comparator output available internally
011 = CIN- pin is configured as analog, CIN+ pin is configured as I/O, COUT pin configured as
Comparator output, CVREF is non-inverting input
100 = CIN- pin is conf igured as analog , CIN+ pin is configured as I/O, COUT pin is configured as I/O, Comparator output
available internally, CVREF is non-inverting input
101 = CIN pins are configured as analog and multiplexed, COUT pin is configured as
Comparator output, CVREF is non-inverting input
110 = CIN pins are configured as analog and multiplexed, COUT pin is configured as I/O,
Comparator output available internally, CVREF is non-invert ing input
111 = CIN pins are configured as I/O, COUT pin is configured as I/O, Comparator output disabled, Comparator off.
© 2007 Microchip Technology Inc. DS41211D-page 57
PIC12F683
8.9 Comparator Gating Timer1
This feat ure can be used to time the d uration or interva l
of analog events. Clearing the T1GSS bit of the
CMCON1 register will enable Timer1 to increment
based on the output of the comparator. This requires
that Timer1 is on and gating is enabled. See
Section 6.0 “Timer1 Module with Gate Control” for
details.
It is recommended to synchronize the comparator with
Timer1 by setting the CMSYNC bit when the
comparator is used as the Timer1 gate source. This
ensures Timer1 does not miss an increment if the
comparator changes during an increment.
8.10 Synchronizing Comparator Output
to Timer1
The comparator output can be synchronized with
Timer1 by setting the CMSYNC bit of the CMCON1
register. When enabled, the comparator output is
latched on the falling edge of t he Timer1 clock source.
If a prescaler is used with Timer1, the comparator
output is latched after the prescaling function. To
prevent a race condition, the comparator output is
latched on the falling edge of the Timer1 clock source
and Timer1 increments on the rising edge of its clock
source. Se e the Comparator Block D iagram (Figure 8-
2) and the Timer1 Bloc k Diagr am (F igure 6- 1) for more
information.
REGISTER 8-2: CMCON1: COMPARATOR CONFIGURATION REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0
T1GSS CMSYNC
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-2 Unimplemented: Read as ‘0
bit 1 T1GSS: Timer1 Gate Source Select bit(1)
1 = Timer 1 Gate Source is T1G pin (pin should be configured as digital input)
0 = Timer 1 Gate Source is comparator output
bit 0 CMSYNC: Comparator Output Synchronization bit(2)
1 = Output is synchronized with falling edge of Timer1 clock
0 = Output is asynchronous
Note 1: Refer to Section 6.6 “Timer1 Gate.
2: Refer to Figure 8-2.
PIC12F683
DS41211D-page 58 © 2007 Microchip Technology Inc.
8.11 Comparator Voltage Reference
The Comparator Voltage Reference module provides
an internally generated voltage reference for the
comparators. The following features are available:
Independent from Comparator operation
Two 16-level voltage ranges
Output clamped to VSS
Ratiometric with VDD
The VRCON register (Register 8-3) controls the
Voltage Reference module shown in Figure 8-7.
8.11.1 INDEPENDENT OPERATION
The comparator voltage reference is independent of
the comparator configuration. Setting the VREN bit of
the VRCON register will enable the voltage reference.
8.11.2 OUTPUT VOLTAGE SELECTION
The CVREF voltage reference has 2 ranges with 16
voltage levels in each range. Range selection is
controlled by the VRR bit of the VRCON register. The
16 levels are set with the VR<3:0> bits of the VRCON
register.
The CVREF output voltage is determined by the following
equations:
EQUATION 8-1: CV REF OUTPUT VOLTAGE
The full range of VSS to VDD cannot be realized due to
the construction of the module. See Figure 8-1.
8.11.3 OUTPUT CLAMPED TO VSS
The CVREF output voltage can be set to Vss with no
power consumptio n by config uring VRCON as f ollows:
•VREN=0
•VRR=1
•VR<3:0>=0000
This allows the comparator to detect a zero-crossing
while not consuming additional CVREF module curren t.
8.11.4 OUTPUT RATIOMETRIC TO VDD
The comparator voltage reference is VDD derived and
therefore, the CVREF output changes with fluctuations in
VDD. The tested absolute accuracy of the Comparator
Voltage Reference can be found in Section 15.0
“Electrical Specifications”.
VRR 1 (low range):=
VRR 0 (high range):=
CVREF (VDD/4) + =
CVREF (VR<3:0>/24) VDD×=
(VR<3:0> VDD/32)×
REGISTER 8-3: VRCON: VOLTAGE REFERENCE CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
VREN —VRR VR3 VR2 VR1 VR0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 VREN: CVREF Enable bit
1 = CVREF circuit powered on
0 = CVREF circuit powered down, no IDD drain and CVREF = VSS.
bit 6 Unimplemented: Read as ‘0
bit 5 VRR: CVREF Range Selection bit
1 = Low range
0 = High range
bit 4 Unimplemented: Read as ‘0
bit 3-0 VR<3:0>: CVREF Value Selection 0 VR<3:0> 15
When VRR = 1: CVREF = (VR<3 :0>/24) * VDD
When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD
© 2007 Microchip Technology Inc. DS41211D-page 59
PIC12F683
FIGURE 8-7: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
T ABLE 8-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE
REFERENCE MODULES
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Valu e on
all othe r
Resets
ANSEL ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 -000 1111
CMCON0 —COUT CINV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000
CMCON1 T1GSS CMSYNC ---- --10 ---- --10
INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x
PIE1 EEIE ADIE CCP1IE —CMIEOSFIE TMR2IE TMR1IE 000- 0000 0000 0000
PIR1 EEIF ADIF CCP1IF —CMIFOSFIF TMR2IF TMR1IF 000- 0000 000- 0000
GPIO GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu
TRISIO TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
VRCON VREN —VRR VR3 VR2 VR1 VR0 0-0- 0000 -0-0 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for comparator.
VRR
8R
VR<3:0>(1)
16-1 Analog
8RRR RR
CVREF to
16 Stages
Comparator
Input
VREN
VDD
MUX
VR<3:0> = 0000
VREN
VRR
0
1
2
14
15
Note 1: Care should be taken to ensure VREF
remains within the comparator Common
mode input range. See Section 15.0
“Electrical Specifications” for more detail.
PIC12F683
DS41211D-page 60 © 2007 Microchip Technology Inc.
NOTES:
© 2007 Microchip Technology Inc. DS41211D-page 61
PIC12F683
9.0 ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESL and ADRESH).
The ADC voltage reference is software selectable to
either VDD or a v olt age applied to the ex ternal re ference
pins.
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be us ed to wak e-up the
device from Sleep.
Figure 9-1 shows the block diagram of the ADC.
FIGURE 9-1: ADC BLOCK DIAGRAM
9.1 ADC Configuration
When configuring and using the ADC the following
functio ns must be considere d:
GPIO configuration
Channel selection
ADC voltage reference selection
ADC co nversion clock source
Interrupt control
Results formatting
9.1.1 GPIO CONFIGURATION
The ADC can be used to convert both analog and digital
signals. When converting analog signals, the I/O pin
should be configured for analog by setting the associated
TRIS and ANSEL bits. See the corresponding GPIO
section for more information.
9.1.2 CHANNEL SELECTION
The CHS bi ts of the ADCON0 regi ster deter mine whic h
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 9.2
“ADC Op eratio n” for more information.
GP0/AN0
A/D
GP1/AN1/VREF
GP2/AN2
VDD
VREF
ADON
GO/DONE
VCFG = 1
VCFG = 0
CHS
ADRESH ADRESL
10
10
ADFM
GP4/AN3
0 = Left Justify
1 = Right Justify
Note: Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
PIC12F683
DS41211D-page 62 © 2007 Microchip Technology Inc.
9.1.3 ADC VOLTA GE REFERENCE
The VCFG bit of the ADCON0 register provides contro l
of the positive voltage reference. The positive voltage
reference can be either VDD or an external voltage
source. The negative voltage reference is always
connec ted to the ground refe renc e.
9.1.4 CONVERSION CLOCK
The source of the conversion clock is software select-
able via the ADCS bits of the ANSEL register. There
are seven possible clock options:
•F
OSC/2
•F
OSC/4
•FOSC/8
•FOSC/16
•F
OSC/32
•FOSC/64
•FRC (dedicated internal oscillator)
The time to complete one bit conversion is defined as
TAD. One ful l 1 0-b it c on ve rsi on requires 11 TAD periods
as shown in Figure 9-2.
For correct conversion, the appropriate TAD specificatio n
must be met. See A/D conversion requirements in
Section 15.0 “Electrical Specifications” for more
information. Table 9-1 gives examples of appropriate
ADC clock selections.
TABLE 9-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V)
FIGURE 9-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
Note: Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
ADC Clock Period (TAD) Device Freque ncy (FOSC)
ADC Clock Source ADCS<2:0> 20 MHz 8 MHz 4 MHz 1 MHz
FOSC/2 000 100 ns(2) 250 ns(2) 500 ns(2) 2.0 μs
FOSC/4 100 200 ns(2) 500 ns(2) 1.0 μs(2) 4.0 μs
FOSC/8 001 400 ns(2) 1.0 μs(2) 2.0 μs8.0 μs(3)
FOSC/16 101 800 ns(2) 2.0 μs4.0 μs16.0 μs(3)
FOSC/32 010 1.6 μs4.0 μs8.0 μs(3) 32.0 μs(3)
FOSC/64 110 3.2 μs8.0 μs(3) 16.0 μs(3) 64.0 μs(3)
FRC x11 2-6 μs(1,4) 2-6 μs(1,4) 2-6 μs(1,4) 2-6 μs(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 4 μs for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the
conversion will be perform ed during Sleep.
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9
Set GO/DONE bit
Holding Capacitor is Disconnected from Analog Input (typically 100 ns)
b9 b8 b7 b6 b5 b4 b3 b2
TAD10 TAD11
b1 b0
TCY to TAD
Conversion S tarts
ADRESH and ADRESL registers are loaded,
GO bit is cleared,
ADIF bit is set,
Holding capacitor is connected to analog input
© 2007 Microchip Technology Inc. DS41211D-page 63
PIC12F683
9.1.5 INTERRUPTS
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC interrupt flag is the ADIF bit in the
PIR1 reg ister. The ADC inte rrupt en able i s the ADIE bit
in the PIE1 register. The ADIF bit must be cleared in
software.
This interrupt can be generated while the device is
operatin g or while in Sle ep. If the device is in Sle ep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruc tio n is always executed. If the user is attem ptin g
to wake-up from Sleep and resume in-line code
execution, the global interrupt must be disabled. If the
global interrupt is enabled, execution will switch to the
inter rupt se rvi ce rout ine .
Please see Section 12.4 “Interrupts” for more
information.
9.1.6 RESULT FORMATTING
The 10- bit A/D conversion resu lt can be suppli ed in two
formats, left justified or right justified. The ADFM bit of
the ADCON0 register controls the output format.
Figure 9-3 shows the two output formats.
FIGURE 9-3: 10-BIT A/D CONVERSION RESULT FORMAT
9.2 ADC Operation
9.2.1 STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the
GO/DONE bit of the ADCON0 register to a ‘1’ will st art
the Analog-to-Digital conversion.
9.2.2 COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will:
Clear the GO/DONE bit
Set the ADIF flag bit
Update the ADRESH:A DRESL regis ters with new
conversion result
9.2.3 TERMINATING A CONVERSION
If a conversion must be terminated before completion,
the GO/DONE bit can be cleared in software. The
ADRESH:ADRESL registers will not be updated with
the partially complete Analog-to-Digital conversion
sample. Instead, the ADRESH:ADRESL register pair
will retain the value of the previous conversion. Addi-
tionall y, a 2 TAD delay is req uired befo re another acqu i-
sition can be initiated. Following this delay, an input
acquisition is automatically started on the selected
channel.
Note: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
ADRESH ADRESL
(ADFM = 0)MSB LSB
bit 7 bit 0 bit 7 bit 0
10-bit A/D Result Unimplemented: Read as ‘0
(ADFM = 1)MSB LSB
bit 7 bit 0 bit 7 bit 0
Unimplemented: Read as ‘0 10-bit A/D Result
Note: The GO/DONE bit shou ld not be set in th e
same instruction that turns on the ADC.
Refer to Section 9.2.6 “A/D Conversion
Procedure”.Note: A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
PIC12F683
DS41211D-page 64 © 2007 Microchip Technology Inc.
9.2.4 ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC clock source is selected, the
ADC wa its on e additio nal instru ction bef ore sta rting th e
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present conver-
sion to be aborted and the ADC module is turned off,
although the ADON bit remains set.
9.2.5 SPECIAL EVENT TRIGGER
The CCP Special Event Trigger allows periodic ADC
measurements without software intervention. When
this trigger occurs, the GO/DONE bit is set by h ardware
and the Timer1 counter resets to zero.
Using the Special Event T rigger does not assure proper
ADC timi ng. It is the us er’s respons ibili ty to en sure th at
the ADC ti ming requirements are met.
See Section 11.0 “Capture/Compare/PWM (CCP)
Module” for more information.
9.2.6 A/D CONVERSION PROCEDURE
This is an example procedure for using the ADC to
perform an Analog-to-Digit al conve rsion:
1. Configure GPIO Port:
Disable pin output driver (See TRIS register)
Configure pin as analog
2. Configur e the ADC modul e:
Select ADC conve rsion cloc k
Configure voltage reference
Select ADC input channel
Select result format
Turn on ADC module
3. Configure ADC interrupt (optional):
Clear ADC interrupt flag
Enable ADC interrupt
Enable peripheral interrupt
Enable global interrupt(1)
4. Wait the required acquisition time(2).
5. Start conversion by setting the GO/DONE bit.
6. Wait for ADC conv ers ion to com ple te b y o ne o f
the following:
Polling the GO/DONE bit
Waiting for the ADC interrupt (interrupts
enabled)
7. Read ADC Result
8. Clear the ADC interrup t flag (requi red if interrupt
is enabled).
EXAMPLE 9-1: A/D CONVERSION
9.2.7 ADC REGISTER DEFINITIONS
The following registers are used to control the
operation of the ADC.
Note 1: The global inte rrupt c an be d isabled i f the
user is attem pti ng to wak e-up from Sleep
and resume in-line code execution.
2: See Section 9.3 “A/D Acquisition
Requirements.
;This code block configures the ADC
;for polling, Vdd reference, Frc clock
;and GP0 input.
;
;Conversion start & polling for completion
; are included.
;
BANKSEL TRISIO ;
BSF TRISIO,0 ;Set GP0 to input
BANKSEL ANSEL ;
MOVLW B’01110001’ ;ADC Frc clock,
IORWF ANSEL ; and GP0 as analog
BANKSEL ADCON0 ;
MOVLW B’10000001’ ;Right justify,
MOVWF ADCON0 ;Vdd Vref, AN0, On
CALL SampleTime ;Acquisiton delay
BSF ADCON0,GO ;Start conversion
BTFSC ADCON0,GO ;Is conversion done?
GOTO $-1 ;No, test again
BANKSEL ADRESH ;
MOVF ADRESH,W ;Read upper 2 bits
MOVWF RESULTHI ;Store in GPR space
BANKSEL ADRESL ;
MOVF ADRESL,W ;Read lower 8 bits
MOVWF RESULTLO ;Store in GPR space
© 2007 Microchip Technology Inc. DS41211D-page 65
PIC12F683
REGISTER 9-1: ADCON0: A/D CONTROL REGISTER 0
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM VCFG CHS1 CHS0 GO/DONE ADON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ADFM: A/D Conversion Result Format Select bit
1 = Right justif ied
0 = Left justifie d
bit 6 VCFG: V oltage Referen ce bit
1 = V REF pin
0 = VDD
bit 5-4 Unimplemented: Read as ‘0
bit 3-2 CHS<1:0>: Analog Channel Select bits
00 = AN0
01 = AN1
10 = AN2
11 = AN3
bit 1 GO/DONE: A/D Conversion Status bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 0 ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
PIC12F683
DS41211D-page 66 © 2007 Microchip Technology Inc.
REGISTER 9-2: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 ADRES<9:2>: ADC Result Register bits
Upper 8 bits of 10-bit conversion result
REGISTER 9-3: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES1 ADRES0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 ADRES<1:0>: ADC Result Register bits
Lower 2 bits of 10-bit conversion result
bit 5-0 Reserved: Do not use.
REGISTER 9-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES9 ADRES8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-2 Reserved: Do not use.
bit 1-0 ADRES<9:8>: ADC Result Register bits
Upper 2 bits of 10-bit conversion result
REGISTER 9-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 ADRES<7:0>: ADC Result Register bits
Lower 8 bits of 10-bit conversion result
© 2007 Microchip Technology Inc. DS41211D-page 67
PIC12F683
9.3 A/D Acquisition Requirements
For the A DC t o meet i ts specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 9-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge the
capacitor CHOLD. The sampling switch (RSS) impedance
varies over the device voltage (VDD), see Figure 9-4.
The maximum recommended impedance for analog
sources is 10 kΩ. As the source impedance is
decreased, the acquisition time may be decreased.
After the analog input channel is selected (or changed),
an A/D acquisition must be done before the conversion
can be started. To calculate the minimum acquisition
time, Equation 9-1 may be used. This equation
assumes that 1/2 LSb error is used (1024 steps for the
ADC). The 1/2 LSb erro r is the maximum er ror allow ed
for the ADC to meet its specified resolution.
EQUATION 9-1: ACQUISITION TIME EXAMPLE
TACQ Amplifier Settling Time Hold Capacitor Charging Time Temperature Coefficient++=
TAMP TCTCOFF++=
s TCTemperature - 25°C()0.05µs/°C()[]++=
TCCHOLD RIC RSS RS++() ln(1/2047)=
10pF 1k
Ω
7k
Ω
10k
Ω
++() ln(0.0004885)=
1.37
=µs
TACQ S1.37µS50°C- 25°C()0.05µSC()[]++=
4.67µS=
VAPPLIED 1e
Tc
RC
---------
⎝⎠
⎜⎟
⎛⎞
VAPPLIED 11
2047
------------
⎝⎠
⎛⎞
=
VAPPLIED 11
2047
------------
⎝⎠
⎛⎞
VCHOLD=
VAPPLIED 1e
TC
RC
----------
⎝⎠
⎜⎟
⎛⎞
VCHOLD=
;[1] VCHOLD charged to within 1/2 lsb
;[2] VCHOLD charge response to VAPPLIED
;combining [1] and [2]
The value for TC can be approximated with th e follow ing eq uations:
Solving for TC:
Therefore:
Temperature 50°C and external impedance of 10k
Ω
5.0 V VDD=
Assumptions:
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin
leakage specification.
PIC12F683
DS41211D-page 68 © 2007 Microchip Technology Inc.
FIGURE 9-4: ANALOG INPUT MODEL
FIGURE 9-5: ADC TRANSFER FUNCTION
CPIN
VA
Rs ANx
5 pF
VDD
VT = 0.6V
VT = 0.6V I LEAKAGE
RIC 1k
Sampling
Switch
SS Rss
CHOLD = 10 pF
VSS/VREF-
6V
Sampling Switch
5V
4V
3V
2V
567891011
(kΩ)
VDD
± 500 nA
Legend: CPIN
VT
I LEAKAGE
RIC
SS
CHOLD
= Input Capacitance
= Threshold Voltage
= Leakage current at the pin due to
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance
various junctions
RSS
3FFh
3FEh
ADC Output Code
3FDh
3FCh
004h
003h
002h
001h
000h
Full-Scale
3FBh
1 LSB ideal
VSS/VREF-Zero-Scale
Transition VDD/VREF+
Transition
1 LSB ideal
Full-Scale Range
Analog Input Voltage
© 2007 Microchip Technology Inc. DS41211D-page 69
PIC12F683
TABLE 9-2: SUMMARY OF ASSOCIATED ADC REGISTERS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value o n
POR, BOR
Value on
all other
Resets
ADCON0 ADFM VCFG CHS1 CHS0 GO/DONE ADON 00-- 0000 0000 0000
ANSEL ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 -000 1111
ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu
ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu
INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x
PIE1 EEIE ADIE CCP1IE CMIE OSFIE TMR2IE TMR1IE 000- 0000 0000 0000
PIR1 EEIF ADIF CCP1IF CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000
GPIO GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu
TRISIO TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
Legend: x = unknown, u = unchanged, = unimplemented read as ‘0’. Shaded cells are not used for ADC module.
PIC12F683
DS41211D-page 70 © 2007 Microchip Technology Inc.
NOTES:
© 2007 Microchip Technology Inc. DS41211D-page 71
PIC12F683
10.0 DATA EEPROM MEMORY
The EEPROM data memory is readable and writable
during norma l operati on (full VDD range). This memory
is not directly mapped in the register file space.
Instead, it is indirectly addressed through the Special
Function Registers. There are four SFRs used to read
and write this memory:
EECON1
EECON2 (not a physically implemented register)
EEDAT
EEADR
EEDAT holds the 8-bit da t a fo r read/ write , and EEADR
holds the address of the EEPROM location being
accessed . PIC12F683 has 256 bytes of dat a EEPROM
with an address range from 0h to FFh.
The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
writes the n ew data (erase be fore write). The EEPROM
data memory is rated for high erase/write cycles. The
write time is controlled by an on-chip timer. The write
time will vary with voltage and temperature as well as
from chip-to-chip. Please refer to AC Specifications in
Section 15.0 “Electrical Specifications” for exact
limits.
When the data memory is code-protected, the CPU
may continue to read and write the data EEPROM
memory. The device programmer ca n no longer access
the data EEPROM data and will read zeroes.
REGISTER 10-1: EEDAT: EEPROM DATA REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 EEDATn: Byte Value to Write To or Read From Data EEPROM bits
REGISTER 10-2: EEADR: EEPROM ADDRESS REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 EEADR: Specifies One of 256 Locations for EEPROM Read/Write Op erat ion bit s
PIC12F683
DS41211D-page 72 © 2007 Microchip Technology Inc.
10.1 EECON1 and EECON2 Registers
EECON1 is the control register with four low-order bits
physically implemented. The upper four bits are non-
impleme nted and read as0’s.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set in
software. They are cleared in hardware at completion
of th e r ead or wr i t e ope r a tio n. T he ina bi l it y t o clea r t he
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write operation.
On powe r-up, the WR EN bit is clear. The WRERR bi t is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset during normal
operatio n. In these s ituations , following Reset, the us er
can check the WRERR bit, clear it and rewrite the
location. The data and address will be cleared.
Therefore, the EEDAT and EEADR registers will need
to be re-initialized.
Interrupt fl ag, EEIF bit of the PIR1 reg is ter, is set when
write is complete. This bit must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the data EEPROM write sequence.
Note: The EECON1, EEDAT and EEADR
registers should not be modified during a
data EEPROM write (WR bit = 1).
REGISTER 10-3: EECON1: EEPROM CONTROL REGISTER
U-0 U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0
WRERR WREN WR RD
bit 7 bit 0
Legend:
S = Bit can only be set
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 Unimplemented: Read as ‘0
bit 3 WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during
normal operation or BOR Reset)
0 = The write operation completed
bit 2 WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
bit 1 WR: Write Control bit
1 = Initiates a wri te cycle (T he bit is cle ared by hardwa re onc e wri te is comp let e. The WR bit ca n only
be set, not cleared, in software.)
0 = Write cycle to the data EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM re ad (Read takes on e cycle. RD is cleared in ha rdware. The RD bit can o nly
be set, not cleared, in software.)
0 = Does not initiate an EEPROM read
© 2007 Microchip Technology Inc. DS41211D-page 73
PIC12F683
10.2 Reading the EEPROM Data
Memory
To read a data memory location, the user must write the
address to the EEADR register and then set control bit
RD of the EECON1 register , as show n in Example 10-1.
The data is available, at the very next cycle, in the
EEDAT register. Therefore, it can be read in the next
instruction. EEDA T holds thi s value until another read, or
until it is written to by the user (during a wr ite operation).
EXAMPLE 10-1: DATA EEPROM READ
10.3 Writing to the EEPROM Data
Memory
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDAT register. Then the user must follow a
specific sequence to initiate the write for each byte, as
shown in Example 10-2.
EXAMPLE 10-2: DATA EEPROM WRITE
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment. A cycle count is executed during the
required s equence . Any number th at is not equa l to the
required cycles to execute the required sequence will
prevent the data from being written into the EEPROM.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
After a write sequence has been initiated, clearing the
WREN bit wil l not af fect this writ e cycle. T he WR bit will
be inhibi ted from bei ng s et u nless the WREN b it is se t.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. The EEIF bit of the
PIR1 register must be cleared by software.
10.4 Write Veri fy
Depending on the application, good programming
practice may dictate that the value written to the data
EEPROM should b e verifie d (see Example 10-3) to th e
desired value to be written.
EXAMPL E 10- 3: W R ITE VE RIF Y
10.4.1 USING THE DATA EEPROM
The data EEPROM is a high-endurance, byte
addressable array that has been optimized for the
storage of frequently changing information (e.g.,
program variables or other data that are updated often).
When variables in one section change frequently, while
variables in another section do not change, it is possible
to exceed the total number of write cycles to the
EEPROM (specification D124) without exceeding the
total number of write cycles to a single byte
(specifications D120 and D120A). If this is the case,
then a re fr esh of the arra y must be per formed . F or th is
reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
Flash program memory.
BANKSEL EEADR ;
MOVLW CONFIG_ADDR ;
MOVWF EEADR ;Address to read
BSF EECON1,RD ;EE Read
MOVF EEDAT,W ;Move data to W
BANKSEL EECON1 ;
BSF EECON1,WREN ;Enable write
BCF INTCON,GIE ;Disable INTs
BTFSC INTCON,GIE ;See AN576
GOTO $-2 ;
MOVLW 55h ;Unlock write
MOVWF EECON2 ;
MOVLW AAh ;
MOVWF EECON2 ;
BSF EECON1,WR ;Start the write
BSF INTCON,GIE ;Enable INTS
Required
Sequence
BANKSELEEDAT ;
MOVF EEDAT,W ;EEDAT not changed
;from previous write
BSF EECON1,RD ;YES, Read the
;value written
XORWF EEDAT,W
BTFSS STATUS,Z ;Is data the same
GOTO WRITE_ERR ;No, handle error
: ;Yes, continue
PIC12F683
DS41211D-page 74 © 2007 Microchip Technology Inc.
10.5 Protection Against Spurious Write
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been buil t in. On power-up, WR EN is cleare d. Also, the
Power-up Timer (64 ms duration) prevents
EEPROM write.
The wri te in iti ate sequence an d the WREN bi t tog eth er
help prevent an accidental write during:
Brown-out
•Power Glitch
Software Malfunction
10.6 Dat a EEPROM Operation During
Code-Protect
Data memo ry can be code-pro tected b y program ming
the CPD bit in the Configuration Word register
(Register 12-1) to 0’.
When the data memory is code-protected, the CPU is
able to read and write data to the data EEPROM. It is
recommended to code-protect the program memory
when code-protecting data memory. This prevents
anyone from programming zeroes over the existing
code (which will execute as NOPs) to reach an added
routine, programmed in unused program memory,
which outputs the contents of data memory.
Programming unused locations in program memory to
0’ will also help prevent data memory code protection
from becom ing breac hed .
TABLE 10-1: SUMMARY OF ASSOCIATED DATA EEPROM REGISTERS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all othe r
Resets
INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000
PIR1 EEIF ADIF CCP1IF CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000
PIE1 EEIE ADIE CCP1IE CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000
EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000
EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000
EECON1 ——— WRERR WREN WR RD ---- x000 ---- q000
EECON2(1) EEPROM Control Register 2 ---- ---- ---- ----
Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not
used by the Data EEPROM module.
Note 1: EE CON2 is not a physical register.
© 2007 Microchip Technology Inc. DS41211D-page 75
PIC12F683
11.0 CAPTURE/COMPARE/PWM
(CCP) MODULE
The Capture/Compare/PWM module is a peripheral
which allows the user to time and control different
events. In Capture mode, the peripheral allows the
timing of the duration of an event.The Compare mode
allows the user to trigger an external event when a
predetermined amount of time has expired. The PWM
mode can generate a Pulse-Width Modulated signal of
varying frequency and duty cycle.
The timer resources used by the module are shown in
Table 11-1
Additional information on CCP modules is available in
the Applic ation Not e AN594 , “Using the CCP Modules”
(DS00594).
TABLE 11-1: CCP MODE – TIMER
RESOURCES REQUIRED
CCP Mode Timer Resource
Capture Timer1
Compare Timer1
PWM Timer2
REGISTER 11-1: CCP1CON: CCP1 CONTROL REGISTER
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0
bit 5-4 DC1B<1:0>: PWM Duty Cycle Least Significant bits
Capture mode:
Unused.
Compare mode:
Unused.
PWM mo de:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.
bit 3-0 CCP1M<3:0>: CCP Mode Select bits
0000 = Capture/Compare/PWM off (resets CCP module)
0001 = Unused (reserved)
0010 = Unused (reserved)
0011 = Unused (reserved)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCP1IF bit is set)
1001 = Comp are mo de, clear output on match (CC P1IF bit is set)
1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin
is unaffected)
1011 = Compare mode, trigger special event (CCP1IF bit is set, TMR1 is reset and A/D
conversion is started if the ADC module is enabled. CCP1 pin is unaffected.)
110x = PWM mode active-high
111x = PWM mode active-low
PIC12F683
DS41211D-page 76 © 2007 Microchip Technology Inc.
11.1 Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit val ue of the TMR1 register when an event occurs
on pin CCP1. An event is defined as one of the
following and is configured by the CCP1M<3:0> bits of
the CCP1CON register:
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
When a cap ture i s m ade, the I nterrupt Re quest Flag bit
CCP1IF of the PIR1 register is set. The interrupt flag
must be cleared in software. If another capture occurs
before the value in the CCPR1H, CCPR1L register pair
is read, the old captured value is overwritten by the new
captured value (see Figure 11-1).
11.1.1 CCP1 PIN CONFIGURATION
In Capture mode, the CCP1 pin should be configured
as an input by setting the associated TRIS control bit.
FIGURE 11-1: CAPTURE MODE
OPERATION BLOCK
DIAGRAM
11.1.2 TIMER1 MODE SELECTION
T imer1 must be running in T imer mode or Synchroni zed
Counter mode for the CCP module to use the capture
feature. In Asynchronous Counter mode, the capture
operation may not work.
11.1.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCP1IE i nterrupt en able bit of the PIE1 regis ter clear to
avoid false interrupts. Additionally, the user should
clear the CCP1IF interrupt flag bit of the PIR1 register
following any change in operating mode.
11.1.4 CCP PRESCALER
There are four prescaler settings specified by the
CCP1M<3:0> bits of the CCP1CON register.
Whenever the CCP module is turned off, or the CCP
module is not in Capture mode, the prescaler counter
is cleared. Any Reset will clear the prescal er counter.
Switching from one capture prescaler to another does not
clear the prescaler and may generate a false interrupt. To
avoid this unexpected operation, turn the module off by
clearing the CCP1CON register before changing the
prescaler (see Example 11-1).
EXAMPLE 11 -1: CHANGING BETWEEN
CAPTURE PRESCALERS
Note: If the C CP1 pin is con figured as an output ,
a write to the GPIO port can cause a
capture co ndition.
CCPR1H CCPR1L
TMR1H TMR1L
Set Flag bit CCP1IF
(PIR1 reg ister )
Capture
Enable
CCP1CON<3:0>
Prescaler
÷ 1, 4, 16
and
Edge Detect
pin
CCP1
System Clock (FOSC)
BANKSEL CCP1CON ;Set Bank bits to point
;to CCP1CON
CLRF CCP1CON ;Turn CCP module off
MOVLW NEW_CAPT_PS ;Load the W reg with
; the new prescaler
; move value and CCP ON
MOVWF CCP1CON ;Load CCP1CON with this
; value
© 2007 Microchip Technology Inc. DS41211D-page 77
PIC12F683
11.2 Compare Mode
In C ompare mo de, t he 16- bit CC PR1 re gist er va lue is
constantly compared against the TMR1 register pair
value. When a match occurs, the CCP1 module may:
Toggle th e CCP1 out put.
Set the CCP1 output.
Clear the CCP1 output.
Generate a Special Event Trigger.
Generate a Software Interrupt.
The action on the pin is based on the value of the
CCP1M<3:0> control bits of the CCP1CON register.
All Compare modes can generate an interrupt.
FIGURE 11-2: COMPARE MODE
OPERATION BLOCK
DIAGRAM
11.2.1 CCP1 PIN CONFIGURATION
The user m us t co nfi gure the C CP 1 pin a s an out put b y
clearing the associated TRIS bit.
11.2.2 TIMER1 MODE SELECTION
In Compare mode, Timer1 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
11.2.3 SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen
(CCP1M<3:0> = 1010), the CCP1 module does not
assert control of the CCP1 pin (see the CCP1CON
register).
11.2.4 SPECIAL EVENT TRIGGER
When Special Event Trigger mode is chosen
(CCP1M<3:0> = 1011), the CCP1 module does the
following:
Resets Timer1
Starts an ADC conversion if ADC is enabled
The CCP 1 module do es not assert co ntrol of the CC P1
pin in this mode (see the CCP1CON register).
The Special Event Trigger output of the CCP occurs
immediately upon a match between the TMR1H,
TMR1L register pair and the CCPR1H, CCPR1L
register pair. The TMR1H, TMR1L register pair is not
reset until th e next r ising ed ge of the T imer1 clock. This
allows the CCPR1H, CCPR1L register pair to
effectively provide a 16-bit programmable period
register for Timer1.
Note: Clearing the CCP1CON register will force
the CCP1 compare output latch to the
default low level. This is not the GPIO I/O
data l atc h.
CCPR1H CCPR1L
TMR1H TMR1L
Comparator
QS
ROutput
Logic
Specia l Event Trigge r
Set CCP1IF Interrupt Flag
(PIR1)
Match
TRIS
CCP1CON<3:0>
Mode Select
Output Enable
Pin
Special Event Trigger will:
Clear TMR1H and TMR1L registers.
NOT set interrupt flag bit TMR1IF of the PIR1 register.
Set the GO/DONE bit to start the ADC conversion.
CCP1 4
Note 1: The Special Event Trigger from the CCP
module does not set interrupt flag bit
TMRxIF of the PIR1 register.
2: Removing the match condition by
changing the contents of the CCPR1H
and CCPR1L register pair, between the
clock edge that generates the Special
Event Trigger and the clock edge that
generates the T imer1 Reset, wi ll preclude
the Reset from occurring.
PIC12F683
DS41211D-page 78 © 2007 Microchip Technology Inc.
11.3 PWM Mode
The PWM mode generates a Pulse-Width Modulated
signal on the CCP1 pin. The duty cycle, period and
resolution are determined by the following registers:
•PR2
•T2CON
CCPR1L
CCP1CON
In Pulse-Width Modulation (PWM) mode, the CCP
module produce s up to a 10 -bit resoluti on PWM outp ut
on the CCP1 pin. Since the CCP1 pin is multiplexed
with the POR T dat a latch, the TRIS for that pi n must be
cleared to enable the CCP1 pin output driver.
Figure 11-1 shows a simplified block diagram of PWM
operation.
Figure 11-4 shows a typical waveform of the PWM
signal.
For a ste p-by-step proc edure on how t o set up the CC P
module for PWM operation, see Section 11.3.7
“Setup for PWM Operation”.
FIGURE 11-3: SIMPLIFIED PWM BLOCK
DIAGRAM
The PWM output (Figure 11-4) has a time base
(period) and a time that the output stays high (duty
cycle).
FIGURE 11-4: CCP PWM OUTPUT
Note: Clearing the CCP1CON register will
relinquish CCP1 control of the CCP1 pin.
CCPR1L
CCPR1H(2) (Slave)
Comparator
TMR2
PR2
(1)
RQ
S
Duty Cycle Registers CCP1CON<5:4>
Clear Timer2 ,
toggle CCP1 pin and
latch duty cycle
Note 1: The 8-bit timer TMR2 register is concatenated
with the 2-bit internal system clock (FOSC), or
2 bits of the prescaler , to create the 10-bit time
base.
2: In PWM mode, CCPR1H is a read-only register
.
TRIS
CCP1
Pin
Comparator
Period
Pulse Width
TMR2 = 0
TMR2 = CCPR1L:CCP1CON<5:4>
TMR2 = PR2
© 2007 Microchip Technology Inc. DS41211D-page 79
PIC12F683
11.3.1 PWM PE RIO D
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the
formula of Equation 11-1.
EQUATION 11-1: PWM PERIOD
When TM R2 is equa l to PR2, t he followi ng three ev ents
occur on t he next inc rement cy cle:
TMR2 is cl eare d
The CCP1 pi n is se t. (Ex cep tio n: If the PWM duty
cycle = 0%, the pin will not be set.)
The PWM dut y cycl e is latched from CCPR1L i nto
CCPR1H.
11.3.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing a 10-bit
value to multiple registers: CCPR1L register and
DC1B<1:0> bits of the CCP1CON register. The
CCPR1L contains the eight MSbs and the CCP1<1:0>
bits of the CCP1CON register contain the two LSbs.
CCPR1L and DC1B<1:0> bits of the CCP1CON
register can be written to at any time. The duty cycle
value is not latched into CCPR1H until after the period
completes (i.e., a match between PR2 and TMR2
registers occurs). While using the PWM, the CCPR1H
register is read-only.
Equation 11-2 is used to calculate the PWM pulse
width.
Equat ion 11-3 is used to calcula te the PWM duty cy cl e
ratio.
EQUATION 11-2: PULSE WIDTH
EQUATION 11-3: DUTY CYCLE RATIO
The CCPR1H register and a 2-bit internal latch are
used to dou ble buf fer th e PWM duty cycle. Thi s doubl e
buffering is es sential for glitchless PWM operation.
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (FOSC), or 2 bits of
the prescaler , to create the 10-bit time ba se. The system
clock is used if the Timer2 prescaler is set to 1:1.
When the 1 0-bit time base matches the CCPR1H and 2-
bit latch, then the CCP1 pin is cl eared (see Figure 11-1).
11.3.3 PWM RES OLUTIO N
The res olution de termines the number of avai lable dut y
cycles for a given period. For example, a 10-bit resolution
will result in 1024 discrete duty cycles, whereas an 8-bit
resolu ti on will re su lt in 2 56 discrete du ty c ycl es .
The maximum PWM resolution is 10 bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 11-4.
EQUATION 11-4: PWM RESOLUTION
TABLE 11-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
TABLE 11-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
Note: The Timer2 postscaler (see Section 7.0
“Timer2 Module”) is not used in the
determination of the PWM frequency.
PWM Period PR2()1+[]4TOSC =
(TM R2 Presc ale Value)
Note: If the pulse width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
Pulse Width CCPR1L:CCP1CON<5:4>() =
TOSC (TMR2 Prescale Value)
Duty Cycle Ratio CCPR1L:CCP1CON<5:4>()
4PR2 1+()
-----------------------------------------------------------------------=
Resolution 4PR2 1+()[]log 2()log
------------------------------------------ bits=
PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescale (1, 4, 16) 16 4 1 1 1 1
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 6.6
PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz
Timer Prescale (1, 4, 16) 16 4 1 1 1 1
PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09
Maximum Resolution (bits) 8 8 8 6 5 5
PIC12F683
DS41211D-page 80 © 2007 Microchip Technology Inc.
11.3.4 OPERATION IN SLEEP MODE
In Sleep mode, the TMR2 register will not increment
and the st ate of the module will not change. If the CCP1
pin is dri ving a value , it wi ll cont inue to d rive th at valu e.
When the device wakes up, TMR2 wil l continue from it s
previous state.
11.3.5 CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 3.0 “Oscillator Module (With Fail-Safe
Clock Monitor)” for additional details.
11.3.6 EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
11.3.7 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Disable the PWM pin (CCP1) output drivers by
setting the associated TRIS bit.
2. Set the PWM period by loading the PR2 register .
3. Configure the CCP module for the PWM mode
by loading the CCP1CON register with the
appropriate values.
4. Set the PWM duty cycle by loading the CCPR1L
register and DC1B bits of the CCP1CON register .
5. Configure and start Timer2:
Clear the TMR2IF interrupt flag bit of the
PIR1 register.
Set the T im er2 pres cale value by loa din g the
T2CKPS bits of the T2CON register.
Enabl e Timer2 by se ttin g th e TM R 2ON bit of
the T2CON register.
6. Enable PWM outpu t afte r a ne w PW M cy cle has
started:
Wait until Timer2 overflows (TMR2IF bit of
the PIR1 register is set).
Enable the CCP1 pin output driver by
clearing the associated TRIS bit.
© 2007 Microchip Technology Inc. DS41211D-page 81
PIC12F683
TABLE 11-4: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
TABLE 11-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
CCP1CON DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB) xxxx xxxx xxxx xxxx
CCPR1H Capture/C ompare/PWM Regis ter 1 High Byte (MSB) xxxx xxxx xxxx xxxx
CMCON1 —————T1GSSCMSYNC ---- --10 ---- --10
INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x
PIE1 EEIE ADIE CCP1IE CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000
PIR1 EEIF ADIF CCP1IF CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000
T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 0000 0000
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx xxxx xxxx
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx xxxx xxxx
TRISIO TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
Legend: – = Unimpl emented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture and Compare.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
CCP1CON DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB) xxxx xxxx xxxx xxxx
CCPR1H Capture/C ompare/PWM Regis ter 1 High Byte (MSB) xxxx xxxx xxxx xxxx
INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x
PIE1 EEIE ADIE CCP1IE CMIE OSFIE TMR2IE TMR1IE 000- 0000 -000 0000
PIR1 EEIF ADIF CCP1IF CMIF OSFIF TMR2IF TMR1IF 000- 0000 -000 0000
PR2 Timer2 Perio d Regi ste r 1111 1111 1111 1111
T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
TMR 2 Timer2 Module Regi ster 0000 0000 0000 0000
TRISIO TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
Legend: – = Unimpl emented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the PWM.
PIC12F683
DS41211D-page 82 © 2007 Microchip Technology Inc.
NOTES:
© 2007 Microchip Technology Inc. DS41211D-page 83
PIC12F683
12.0 SPECIAL FEATURES OF THE
CPU
The PIC12F683 has a host of features intended to
maximize system reliability, minimize cost through
elimination of external components, provide power
saving features and offer code protection.
These features are:
Reset
- Power-on Reset (P OR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
Interrupts
Watchdog Timer (WDT)
Oscillator Selection
Sleep
Code Protection
ID Locations
In-Circuit Serial Programming™
The PIC12F683 has two timers that offer necessary
delays on pow er-up. One is the Oscillator Start-up T imer
(OST), intended to keep th e chip i n Reset until the crys-
tal oscillator is stable. The other is t he Power-up Timer
(PWRT), which provides a fixed delay of 64 ms (nomi-
nal) on power-up only, designed to keep the part in
Reset while the power supply stabilizes. There is also
circuitry to reset the device if a brown-out occurs, which
can use the Power-up T ime r to provide at least a 64 ms
Reset. With these three functions on-chip, most
applications need no external R ese t circuitry.
The Sleep mode is des igned to of fer a very l ow-c urrent
Power-down mode. The user can wake-up from Sleep
through:
•External Reset
Watchdog Timer Wake-up
An interrupt
Several oscillator options are also made available to
allow the p art to f it th e a ppl ic ati on. The INTOSC op tio n
saves system cost while the LP crystal option saves
power. A set of Configuration bits are used to select
various o ptions (see Register 12-1).
12.1 Configuration Bits
The Configuration bits can be programmed (read as
0’), or left unprogrammed (read as ‘1’) to select various
device configurations as shown in Register 12-1.
These bits are mapped in program memory location
2007h.
Note: Address 2007h is beyond the user
program memory space. It belongs to the
special configuration memory space
(2000h-3FFFh), which can be accessed
only during programming. See
PIC12F6XX/16F6XX Memory Program-
ming Specification” (DS41204) for more
information.
PIC12F683
DS41211D-page 84 © 2007 Microchip Technology Inc.
REGISTER 12-1: CONFIG: CONFIGURATION WORD REGISTER
FCMEN IESO BOREN1 BOREN0
bit 15 bit 8
CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit P = Programmable’ U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 Unimplemented: Read as ‘1
bit 11 FCMEN: Fail-Safe Clock Monitor Enabled bit
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
bit 10 IESO: Internal External Switchover bit
1 = Internal External Switchover mode is enabled
0 = Internal External Switchover mode is disabled
bit 9-8 BOREN<1:0>: Brown-out Reset Selection bits(1)
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit of the PCON register
00 = BOR disabled
bit 7 CPD: Data Code Protection bit(2)
1 = Data memory code protection is disabled
0 = Data memory code protect ion is enabled
bit 6 CP: Code Protection bit(3)
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
bit 5 MCLRE: GP3/MCLR pin function select bit(4)
1 = GP3/MCLR pin function is MCLR
0 = GP3/MCLR pin function is digital input, MCLR internally tied to VDD
bit 4 PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 3 WDTE: Watchdog Ti mer Enable bit
1 = WDT enabled
0 = WDT disabled and can be enabled by SWDTEN bit of the WDTCON register
bit 2-0 FOSC<2:0>: Oscillator Selection bits
111 = RC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN
110 = RCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN
101 = INTOSC osci llat or : CLKOUT fu nctio n on GP4/OSC2/CLKOUT pin, I/O funct ion on GP5/OSC1/CLKIN
100 = INTOSCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN
011 = EC: I/O function on GP4/OSC2/CLKOUT pin, CLKIN on GP5/OSC1/CLKIN
010 = HS oscillator: High-speed crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN
001 = X T oscillator: Crystal/resonator on GP4/OSC2/CLKO UT and GP5/OSC1/C LKI N
000 = LP oscillator: Low-power crystal on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The entire data EEPROM will be erased when the code protection is turned off.
3: The entire program memory will be erased when the code protection is turned off.
4: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
© 2007 Microchip Technology Inc. DS41211D-page 85
PIC12F683
12.2 Calibrati on Bits
Brown-out Reset (BOR), Power-on Reset (POR) and
8 MHz internal oscillator (HFINTOSC) are factory cali-
brated. These calibration values are stored in fuses
located in the Calibration Word (2009h). The Calibra-
tion Word is not erased when using the specified bulk
erase sequence in the “PIC12F6XX/16F6XX Memory
Programm ing Specific ation” (DS412 44) and thus, does
not require reprogramming.
12.3 Reset
The PIC1 2F683 diffe rentiates betw een various ki nds of
Reset:
a) P ower-on R eset (POR)
b) WDT Reset during normal operation
c) WDT Reset during Sleep
d) MCLR Reset during normal operation
e) MCLR Reset during Sleep
f) Brown-out Reset (BOR)
Some regi sters a re not af fected in a ny Rese t conditio n;
their status is un kn ow n on POR a nd un ch ang ed i n any
other Reset. Most other registers are reset to a “Reset
state” on:
Power- on Reset
•MCLR
Reset
•MCLR
Reset during Sleep
WDT Reset
Brown-out Reset (BOR)
WDT wake-up does not cause register resets in the
same manner as a WDT Reset since wake-up is
viewed as the resumptio n of no rm al op era t ion . T O an d
PD bits are set or cleared differently in different Reset
situati ons, as indicat ed in Table 12-2. Software c an use
these bits to determine the nature of the Reset. See
Table 12-4 for a full description of Reset states of all
registers.
A simplif ied block diagra m of the On-Chip Rese t Circu it
is sh own i n Figure 12-1.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Section 15.0 “Electrical
Specifications” for pulse-width specifications.
FIGURE 12-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Note 1: Refer to the Configuration Word register (Register 12-1).
S
RQ
External
Reset
MCLR/VPP pin
VDD
OSC1/
WDT
Module
VDD Rise
Detect
OST/PWRT
LFINTOSC
WDT
Time-out
Power-on Reset
OST
10-bit Ripple Counter
PWRT
Chip_Reset
11-bit Ripple Counter
Reset
Enable OST
Enable PWRT
SLEEP
Brown-out(1)
Reset SBOREN
BOREN
CLKI pin
PIC12F683
DS41211D-page 86 © 2007 Microchip Technology Inc.
12.3.1 POWER-ON RESET
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper
operation. To take advantage of the POR, simply
connect the MCLR pin through a resistor to VDD. This
will eliminate external RC components usually needed
to create Power-on Reset. A maximum rise time for
VDD is required. See Section 15.0 “Electrical
Specifications” for details. If the BOR is enabled, the
maximum rise time specification does not apply. The
BOR circuitry will keep the device in Reset until VDD
reaches VBOD (see Section 12.3.4 “Brown-Out Reset
(BOR)”).
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
For addi tional inform ation, refer to the Ap plicatio n No te
AN607, “Power-up Trouble Shooting” (DS00607).
12.3.2 MCLR
PIC12F683 has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pul ses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
Voltages applied to the MCLR pin that exceed its
specification can result in both MCLR Resets and
excessive current beyond the device specification
during the ESD event. For this reason, Microchip
recommends that the MCLR pin no longer be tied
directly to VDD. The use of an RC network , as shown in
Figure 12-2, is suggeste d.
An internal MCLR option is enabled by clearing the
MCLRE bit in the Configuration Word register. When
MCLRE = 0, the Reset signal to the chip is generated
internally. When the MCLRE = 1, the GP3/MCLR pin
becomes an external Reset input. In this mode, the
GP3/MCLR pin has a weak pull-up to VDD.
FIGURE 12-2: RECOMMENDED MCLR
CIRCUIT
12.3.3 POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 64 ms (nominal)
time-out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates from the 31 kHz
LFINTOSC oscillator. For more information, see
Section 3.5 “Internal Clock Mo des”. Th e ch ip is ke pt
in Reset as long as PWRT is active. The PWRT delay
allows the VDD to rise to an acceptable level. A
Configuration bit, PWRTE, can disable (if set) or enable
(if cleared or programmed) the Power-up Timer. The
Power-up Timer should be enabled when Brown-out
Reset is enabled, although it is not required.
The Power-up Timer delay will vary from chip-to-chip
due to:
•V
DD variation
Temperature variation
Process variation
See DC parameters for details (Section 15.0
“Electrical Specifications”).
Note: The POR circuit does not produce an
internal Reset when VDD declines. To
re-enable the POR, VDD must reach Vss
for a minimum of 100 μs.
Note: Voltage spikes below VSS at the MCLR
pin, induc ing cu rrent s gre ater than 80 mA,
may ca use la tch-up . Thus , a ser ies res is-
tor of 50-100 Ω should be used when
applying a “low” level to the MCLR pin,
rather than pulling this pin directly to VSS.
VDD
PIC®
MCLR
R1
1kΩ (or greater)
C1
0.1 μF
(optional, not critical)
R2
100 Ω
(needed with capacitor)
SW1
(optional)
MCU
© 2007 Microchip Technology Inc. DS41211D-page 87
PIC12F683
12.3.4 BROWN-OUT RESET (BOR)
The BOREN0 and BOREN1 bits in the Configuration
Word register select one of four BOR modes. Two
modes have been added to a llow softw are or hardwa re
control of the BOR enable. When BOREN<1:0> = 01,
the SBOREN bit of the PCON register enables/disables
the BOR, allowing it to be controlled in software. By
selecting BOREN<1:0> = 10, the BOR is automatically
disabled in Sleep to conserve power and enabled on
wake-up. In this mode, the SBOREN bit is disabled.
See Register 12-1 for the Configuration Word
definition.
A brown-out occurs when VDD falls below VBOR for
greater than parameter TBOR (see Section 15.0
“Electrical Specifications”). The brown-out condition
will reset the device. This will occur regardless of VDD
slew rate. A Brown-out Reset may not occur if VDD falls
below VBOR for less than parameter TBOR.
On any Reset (Power-on, Brown-out Reset, Watchdog
T imer , et c.), the ch ip will remai n in Reset until VDD rises
above VBOR (see Figure 12-3). If enabled, the
Power-up Timer w i ll b e in vo ke d by th e R es et a nd k ee p
the chip in Reset an additional 64 ms.
If VDD drops below VBOR while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-u p Timer will be re-initialized. Onc e VDD
rises above VBOR, the Power-up Timer will execute a
64 ms Reset.
12.3.5 BOR CALIBRAT ION
The PIC12F683 stores the BOR calibration values in
fuses located in the Calibration Word register (2008h).
The Cali bration Word reg ister is not erased when using
the specified bulk erase sequence in the
PIC12F6XX/16F6XX Memory Programming Specifi-
cation” (DS41204) and thus, does not require
reprogramming.
FIGURE 12-3: BROWN-OUT SITUATIONS
Note: The Power-up Timer is enabled by the
PWRTE bit in the Configuration Word
register.
Note: Address 2008h is beyond the user pro-
gram memory space. It belongs to the
special configuration memory space
(2000h-3FFFh), which can be accessed
only during programming. See
PIC12F6XX/16F6XX Memory Program-
ming Specification” (DS41204) for more
information.
64 ms(1)
VBOR
VDD
Internal
Reset
VBOR
VDD
Internal
Reset 64 ms(1)
< 64 ms
64 ms(1)
VBOR
VDD
Internal
Reset
Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.
PIC12F683
DS41211D-page 88 © 2007 Microchip Technology Inc.
12.3.6 TIME-OUT SEQUENCE
On power-up, the time-out seque nce is a s follows:
PWRT time-out is invoked after POR has expired.
OST is activated after the PWRT time-out has
expired.
The total time-out will vary based on oscillator
configuration and PWR TE bit status. For example, in EC
mode with PWRTE bit erased (PWRT disabled), there
will be no time-out at all. Figure 12-4, Figure 12-5 and
Figure 12-6 depict time-out sequences. The device can
execute code from the INTOSC while OST is active by
enabling Two-Speed Start-up or Fail-Safe Monitor (see
Section 3.7.2 “Two-Speed Start-up Sequence” and
Section 3.8 “Fail-Safe Clock Monitor”).
Since the time-outs oc cur from the POR pulse, if MCLR
is kept low lon g enough, the time-out s will expire. Then,
bringing MCLR high will begin execution immediately
(see Figure 12-5). This is useful for testing purposes or
to synchronize more than one PIC12F683 device
operating in parallel.
Table 12-5 shows the Reset conditions for some
special registers, while Table 12-4 shows the Reset
conditions for all the registers.
12.3.7 POWER CONTROL (PCON)
REGISTER
The Power Control register PCON (address 8Eh) has
two Status bits to indicate what type of Reset occurred
last.
Bit 0 is BOR (Brown-out). BOR is unknown on
Power-on Reset. It must then be set by the user and
checked on subsequent Resets to see if BOR = 0,
indicating that a Brown-out has occurred. The BOR
Status bit is a “don’t care” and is not necessarily
predictable if the brown-out circuit is disabled
(BOREN<1:0> = 00 in the Configuration Word
register).
Bit 1 is POR (Power-on Reset). It is a 0’ on Power-on
Reset and unaf fec ted oth erwise. T he user m ust write a
1’ to this bit following a Power-on Reset. On a subse-
quent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset has occurred (i.e., VDD may have
gone too low).
For more information, see Section 4.2.4 “Ultra
Low-Power Wake-up” and Section 12.3.4
“Brown-Out Reset (BOR)”.
TABLE 12-1: TIME-OUT IN VARIOUS SITUATIONS
TABLE 12-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE
TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET
Oscillator Configuration Power-up Brown-out Reset Wake-up from
Sleep
PWRTE = 0PWRTE = 1PWRTE = 0PWRTE = 1
XT, HS, LP TPWRT + 1024 •
TOSC 1024 • TOSC TPWRT + 1024 •
TOSC 1024 • TOSC 1024 • TOSC
RC, EC, INTOSC TPWRT —TPWRT ——
POR BOR TO PD Condition
0x11Power-on Reset
u011Brown-out Reset
uu0uWDT Reset
uu00WDT Wake -up
uuuuMCLR Reset during normal operation
uu10MCLR Reset during Sleep
Legend: u = unchanged, x = unknown
Name Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets(1)
CONFIG(2) BOREN1 BOREN0 CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0
PCON ULPWUE SBOREN —PORBOR --01 --qq --0u --uu
STATUS IRP RP1 RP0 TO PD ZDC C0001 1xxx 000q quuu
Legend: u = unchanged , x = unknown, – = unimplemented bit, reads as0’, q = value depends on condition. Shaded cells are not used by BOR.
Note 1: Other (non Power-up) Resets include MCLR Rese t and Watchdog Timer R e set dur ing nor ma l opera tion .
2: See Configuration Word register (Register 12-1) for operation of all register bits.
© 2007 Microchip Technology Inc. DS41211D-page 89
PIC12F683
FIGURE 12-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR)
FIGURE 12-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR)
FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD)
TPWRT
TOST
VDD
MCLR
Internal POR
PWRT T ime-out
OST Time-out
Internal Reset
VDD
MCLR
Internal POR
PWRT Time-out
OST Time-out
Internal Reset
TPWRT
TOST
TPWRT
TOST
VDD
MCLR
Internal POR
PWRT Time-out
OST Time-out
Internal Reset
PIC12F683
DS41211D-page 90 © 2007 Microchip Technology Inc.
TABLE 12-4: INITIALIZATION CONDITION FOR REGISTERS
Register Address Power-on Reset MCLR Reset
WDT Rese t
Brown-out Reset(1)
Wake-up from Sleep
through Interrupt
Wake-up from Sleep through
WDT Time-out
W—xxxx xxxx uuuu uuuu uuuu uuuu
INDF 00h/80h xxxx xxxx xxxx xxxx uuuu uuuu
TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu
PCL 02h/82h 0000 0000 0000 0000 PC + 1(3)
STATUS 03h/83h 0001 1xxx 000q quuu(4) uuuq quuu(4)
FSR 04h/84h xxxx xxxx uuuu uuuu uuuu uuuu
GPIO 05h --x0 x000 --x0 x000 --uu uuuu
PCLATH 0Ah/8Ah ---0 0000 ---0 0000 ---u uuuu
INTCON 0Bh/8Bh 0000 0000 0000 0000 uuuu uuuu(2)
PIR1 0Ch 0000 0000 0000 0000 uuuu uuuu(2)
TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu
TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 10h 0000 0000 uuuu uuuu -uuu uuuu
TMR2 11h 0000 0000 0000 0000 uuuu uuuu
T2CON 12h -000 0000 -000 0000 -uuu uuuu
CCPR1L 13h xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1H 14h xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 15h --00 0000 --00 0000 --uu uuuu
WDTCON 18h ---0 1000 ---0 1000 ---u uuuu
CMCON0 19h 0000 0000 0000 0000 uuuu uuuu
CMCON1 20h ---- --10 ---- --10 ---- --uu
ADRESH 1Eh xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 1Fh 00-- 0000 00-- 0000 uu-- uuuu
OPTION_REG 81h 1111 1111 1111 1111 uuuu uuuu
TRISIO 85h --11 1111 --11 1111 --uu uuuu
PIE1 8Ch 0000 0000 0000 0000 uuuu uuuu
PCON 8Eh --01 --0x --0u --uu(1,5) --uu --uu
OSCCON 8Fh -110 q000 -110 q000 -uuu uuuu
OSCTUNE 90h ---0 0000 ---u uuuu ---u uuuu
PR2 92h 1111 1111 1111 1111 1111 1111
WPU 95h --11 -111 --11 -111 uuuu uuuu
IOC 96h --00 0000 --00 0000 --uu uuuu
VRCON 99h 0-0- 0000 0-0- 0000 u-u- uuuu
EEDAT 9Ah 0000 0000 0000 0000 uuuu uuuu
EEADR 9Bh 0000 0000 0000 0000 uuuu uuuu
Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt
vector (0004h).
4: See Table 12-5 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bi t 0 = u.
© 2007 Microchip Technology Inc. DS41211D-page 91
PIC12F683
TABLE 12-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS
EECON1 9Ch ---- x000 ---- q000 ---- uuuu
EECON2 9Dh ---- ---- ---- ---- ---- ----
ADRESL 9Eh xxxx xxxx uuuu uuuu uuuu uuuu
ANSEL 9Fh -000 1111 -000 1111 -uuu uuuu
TABLE 12-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)
Register Address Power-on Reset MCLR Reset
WDT Rese t
Brown-out Reset(1)
Wake-up from Sleep
through Interrupt
Wake-up from Sleep through
WDT Time-out
Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt
vector (0004h).
4: See Table 12-5 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bi t 0 = u.
Condition Program
Counter Status
Register PCON
Register
Power-on Reset 000h 0001 1xxx --01 --0x
MCLR Reset during Normal Operation 000h 000u uuuu --0u --uu
MCLR Reset during Sleep 000h 0001 0uuu --0u --uu
WDT Reset 000h 0000 uuuu --0u --uu
WDT Wake-up PC + 1 uuu0 0uuu --uu --uu
Brown-out Reset 000h 0001 1uuu --01 --10
Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu --uu --uu
Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’.
Note 1: When the w ake-up is du e to an inter rupt and G lobal In terrupt Ena ble bit, GIE, is set, the PC is loade d with
the inter rupt vector (0004h) afte r execution of PC + 1.
PIC12F683
DS41211D-page 92 © 2007 Microchip Technology Inc.
12.4 Interrupts
The PIC12F683 has multiple interrupt sources:
External Inte rrup t GP2/INT
Timer0 Overflow Interrupt
GPIO Change Interrupts
Comparator Interrupt
A/D Interrupt
Timer1 Overflow Interrupt
Timer2 Match Interrupt
EEPROM Data Write Interrupt
Fail-Safe Clock Monitor Interrupt
CCP Interrupt
The Interrup t Control register (INTCON) and Peripheral
Interrupt Request Register 1 (PIR1) record individual
interrupt requests in flag bits. The INTCON register
also has individual and global interrupt enable bits.
The Global Interrupt Enable bit, GIE of the INTCON
register, enables (if set) all unmasked interrupts, or
disables (if cleared) all interrupts. Individual interrupts
can be disabled through their corresponding enable
bits in the INTCON register and PIE1 register. GIE is
cleared on Reset.
When an interrupt is serviced, the following actions
occu r aut omatically:
The GIE i s clea red to disable an y fu rthe r interrupt.
The return address is pushed onto the stack.
The PC is loaded with 0004h.
The Return from Interrupt instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enabl es unm as ke d inte rrupts.
The following interrupt flags are contained in the
INTCON register:
INT Pin Interrupt
GPIO Change Interrupt
Timer0 Overflow Interrupt
The perip heral interru pt flags ar e cont ained in the PIR1
register. The corresponding interrupt enable bit is
contained in the PIE1 register.
The following interrupt flags are contained in the PIR1
register:
EEPROM Data Write Interrupt
A/D Interrupt
Comparator Interrupt
Timer1 Overflow Interrupt
Timer2 Match Interrupt
Fail-Safe Clock Monitor Interrupt
CCP Interrupt
For external interrupt events, such as the INT pin or
GPIO change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends upon when the interrupt event occurs (see
Figure 12-8). The latency is the same for one or
two-cycle instructions. Once in the Interrupt Service
Routine, the source(s) of the interrupt can be
determined by polling the interrupt flag bits. The
interrupt flag bit(s) must be cleared in software before
re-enabling interrupts to avoid multiple interrupt
requests.
For additional information on Timer1, Timer2,
comparators, ADC, data EEPROM or Enhanced CCP
modules, refer to the respective peripheral section.
12.4.1 GP2/INT INTERRUPT
The external interrupt on the GP2/INT pin is
edge-trig gered; either on t he rising e dge i f the INTEDG
bit of the OPTION register is set, or the falling edge, if
the INTE DG bit i s clear. When a v alid e dge ap pears o n
the GP2/ INT pin, the INTF bit o f the INTCON register i s
set. This interrupt can be di sabled by clearing the IN TE
control bit of the INTCON register. The INTF bit must
be cleared by softwa re i n the Interrupt Serv ic e Rou t in e
before re -enabling this int errupt. The GP2/INT in terrupt
can wake-up the processor from Sleep, if the INTE bit
was set prior to going into Sleep. See Section 12.7
“Power-Down M ode (Sleep)” f or deta ils on Sleep and
Figure 12-10 for timing of wake-up from Sleep through
GP2/INT interrupt.
Note 1: Individual interrupt flag bits are set,
regardless of the status of their
corresponding mask bit or the GIE bit.
2: When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The interrupts, which were
ignored, are still pending to be serviced
when the GIE bit is set again.
Note: The ANSEL and CMCON0 registers must
be initialized to configure an analog
channel as a digital input. Pins configured
as analog inputs will read ‘0 and cannot
generate an interrupt.
© 2007 Microchip Technology Inc. DS41211D-page 93
PIC12F683
12.4.2 TIMER0 INTERRUPT
An overflow (FFh 00h) in the TMR0 register will set
the T0IF (INTCON<2>) bit. The interrupt can be
enabled / di sa ble d by s etti ng/ cle ari ng the T0IE bit of the
INTCON register. See Section 5.0 “Timer0 Module”
for operation of the Timer0 module.
12.4.3 GPIO INTERRUPT
An input change on GPIO change sets the GPIF bit of
the INTCON register. The interrupt can be
enabled/disabled by setting/clearing the GPIE bit of the
INTCON register. Plus, individual pins can be
configured through the IOC register.
FIGURE 12-7: INTERRUP T LOGIC
Note: If a change on the I/O pin should occur
when any GPIO operation is being
executed, then the GPIF interrupt flag may
not get set.
TMR1IF
TMR1IE
CMIF
CMIE
T0IF
T0IE
INTF
INTE
GPIF
GPIE
GIE
PEIE
Wake-up (If in Sleep mode)
Inte rrup t to C PU
EEIE
EEIF
ADIF
ADIE
IOC-GP0
IOC0
IOC-GP1
IOC1
IOC-GP2
IOC2
IOC-GP3
IOC3
IOC-GP4
IOC4
IOC-GP5
IOC5
TMR2IF
TMR2IE
CCP1IF
CCP1IE
OSFIF
OSFIE
PIC12F683
DS41211D-page 94 © 2007 Microchip Technology Inc.
FIGURE 12-8: INT PIN INTERRUPT TIMING
TABLE 12-6: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT S
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000
IOC IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 --00 0000
PIR1 EEIF ADIF CCP1IF CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000
PIE1 EEIE ADIE CCP1IE CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000
Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by the interrupt module.
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
OSC1
CLKOUT
INT pin
INTF flag
(INTCON reg.)
GIE bi t
(INTCON reg.)
INST RUCTION FL OW
PC
Instruction
Fetched
Instruction
Executed
Interrupt Latency
PC PC + 1 PC + 1 0004h 0005h
Inst (0004h) Inst (0005h)
Dummy Cycle
Inst (PC) Inst (PC + 1)
Inst (PC – 1) Inst (0004h)
Dummy Cycle
Inst ( PC)
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 15.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
(1) (2)
(3) (4)
(5)
(1)
© 2007 Microchip Technology Inc. DS41211D-page 95
PIC12F683
12.5 Context Saving During Interr upts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (e.g., W and STATUS
registers). This must be implemented in software.
Since the lower 16 bytes of al l banks are common in the
PIC12F683 (see Figure 3-2), temporary holding regis-
ters, W_TEMP and STATUS_TEMP, should be placed
in here. These 16 l oc ati ons do not requ ire ba nk ing an d
therefore, makes it easier to context save and restore.
The same code shown in Example 12-1 can be used
to:
Store the W register.
Store the STATUS register.
Execute the ISR code.
Restore the Status (and Bank Select Bit register).
Restore the W register.
EXAMPLE 12-1: SAVING STATUS AND W REGISTERS IN RAM
Note: The PIC1 2F683 n ormall y does n ot requi re
saving the PCLATH. However, if com-
puted GOTO’s are used in the ISR and the
main code, the PCLATH must be saved
and restored in the ISR.
MOVWF W_TEMP ;Copy W to TEMP register
SWAPF STATUS,W ;Swap status to be saved into W
;Swaps are used because they do not affect the status bits
MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register
:
:(ISR) ;Insert user code here
:
SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W
;(sets bank to original state)
MOVWF STATUS ;Move W into STATUS register
SWAPF W_TEMP,F ;Swap W_TEMP
SWAPF W_TEMP,W ;Swap W_TEMP into W
PIC12F683
DS41211D-page 96 © 2007 Microchip Technology Inc.
12.6 Watchdog Timer (WDT)
The WDT has the following features:
Operates from the LFINTOSC (31 kHz)
Contain s a 16-bit prescaler
Shares an 8-bit prescaler with Timer0
Time-out period is from 1 ms to 268 seconds
Configuration bit and software controlled
WDT is cleared under certain conditions described in
Table 12-7.
12.6.1 WDT OSCILLAT OR
The WDT derives its time base from the 31 kHz
LFINTOSC. The LTS bit of the OSCCON regi ste r does
not reflect that the LFINTOSC is enabled.
The value of WDTCON is ‘---0 1000’ on all R ese ts.
This gives a nominal time base of 17 ms.
12.6.2 WDT CONTROL
The WDTE bit is located in the Configuration Word
register. When set, the WDT runs continuously.
When the WDTE bit i n the Configurati on Word register
is set, the SWDTEN bit of the WDTCON register has no
effect. If WDTE is clear, then the SWDTEN bit can be
used to e nable and d isable the WDT. Setting the b it will
enable it and clearing the bit will disable it.
The PSA and PS<2:0> bits of the OPTION register
have the same function as in previous versions of the
PIC12F683 Family of microcontrollers. See
Section 5.0 “Timer0 Module” for more information.
FIGURE 12-9: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 12-7: WDT STATUS
Note: When the Oscillator Start-up Timer (OST)
is invoked, the WDT is held in Reset,
bec ause the WD T Ri pple C ounte r i s us ed
by the OST to perform the oscillator delay
count. When the OST count has expired,
the WDT will begin counting (if enabled).
Conditions WDT
WDTE = 0
Cleared
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST
31 kHz
PSA
16-bit WDT Prescaler
From Timer0 Clock Source
Prescaler(1)
8
PS<2:0>
PSA
WDT Time -out
To Timer0
WDTPS<3:0>
WDTE from Configuration Word register
1
1
0
0
SWDTEN from WDTCON
LFINTOSC Clock
Note 1: This is the shared Timer0/WDT prescaler. See Sectio n 5.0 “Timer0 Module” for more information.
© 2007 Microchip Technology Inc. DS41211D-page 97
PIC12F683
TABLE 12-8: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG T IMER
REGISTER 12-2: WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0 U-0 U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0
WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0
bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits
Bit Value = Prescale Rate
0000 = 1:32
0001 = 1:64
0010 = 1:128
0011 = 1:256
0100 = 1:512 (Reset value)
0101 = 1:1024
0110 = 1:2048
0111 = 1:4096
1000 = 1:8192
1001 = 1:16384
1010 = 1:32768
1011 = 1:65536
1100 = Reserv ed
1101 = Reserv ed
1110 = Reserv ed
1111 = Reserv ed
bit 0 SWDTEN: Software Enable or Disable t he Watchdog Timer(1)
1 = WDT is turned on
0 = WDT is turned off (Reset value)
Note 1: If WDTE Configuration bit = 1, then WDT is always enabled, irrespective of this control bit. If WDTE
Configu ration b it = 0, then it is possible to turn WDT on/off with this control bit.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 V a lue on
POR, BOR
Value on
all other
Resets
WDTCON WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000
OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
CONFIG CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0
Legend: Shaded cells are not used by the Watchdog T imer.
Note 1: See Register 12-1 for operation of all Configuration Word register bits.
PIC12F683
DS41211D-page 98 © 2007 Microchip Technology Inc.
12.7 Power-Down Mode (Sleep)
The Power-down mode is entered by executing a
SLEEP instruction.
If the Watchdog Timer is enabled:
WDT will be cleared but keeps running.
•PD
bit in the STATUS register is cleared.
•TO
bit is set.
Oscillator driver is turned off.
I/O ports maintain the status they had before SLEEP
was executed (driving high, low or high-impedance).
For lowest current consumption in this mode, all I/O pins
should be either at V DD or VSS, with no external circuitry
drawing current from the I/O pin and the comparators
and CVREF should be disabled. I/O pins that are
high-impedance inputs should be pulled high or low
externally to avoid switching current s caused by floating
input s. The T0CKI input should also be at VDD or VSS for
lowest current consumption. The contribution from
on-chip pull-ups on GPIO s hould be c onsidered.
The MCLR pin must be at a logic high level.
12.7.1 WAKE-UP FROM SLEEP
The devi ce can wake -up from Sleep through one of th e
following events:
1. External Reset input on MCLR pin.
2. Watchdog Timer wake-up (if WDT was
enabled).
3. Interrupt from GP2/INT pin, GPIO change or a
peripheral interrupt.
The firs t event wi ll cause a devic e Reset. The two latter
events are considered a continuation of program
execution. The TO and PD bits in the STATUS register
can be us ed to determine the cause o f a device R ese t.
The PD bit , whi ch i s set on pow er-u p, is clea red w hen
Sleep is invoked. TO bit is cleared if WDT wake-up
occurred.
The follo wing periph eral interrupt s can wake the device
from Sleep:
1. Timer1 interrupt. Timer1 must be operating as
an asynchronous counter.
2. ECCP Capture mode interrupt.
3. A/D conve rsion (when A/D clock source is FRC).
4. EEPROM write operation completion.
5. Comparator output changes state.
6. Interrupt-on-change.
7. External Interrupt from INT pin.
Other peripherals cannot generate interrupts since
during Sleep, no on-chip clocks are present.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up thro ugh an interrupt event, the co rres pon din g
interrupt enable bit must be set (enabled). Wake-up
occurs regardless of the state of the GIE bit. If the GIE
bit is clear (disabled), the device continues execution at
the ins truction a fter the SLEEP i nstructio n. If the GI E bit
is set (enabled), the device executes the instruction
after the SLEEP instruction, then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOP after the SLEEP instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
12.7.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and inte rrupt fla g bit s et, one of the fo llow ing wil l occur:
If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will
comple te as a NOP. Therefore, th e WDT and WDT
prescaler and postscaler (if enabled) will not be
cleared, the TO bit will not be set and the PD bit
will not be cleared.
If the interrupt occurs during or after the
execution of a SLEEP instruc tion, the device will
Immediately wake-up from Sleep. The SLEEP
instruction is executed. Therefore, the WDT and
WDT prescal er and pos t s ca ler (if ena bled) will be
cleared, the TO bit will be set and the PD bit will
be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruct ion completes . To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT ins truction
should be executed before a SLEEP instruction. See
Figure 12-10 for more details.
Note: It should be noted that a Reset generated
by a WDT time-out does not drive MCLR
pin low.
Note: If the g lobal interrup ts a re disa bled (G IE is
cleared ) and a ny inte rrupt so urce has both
it s interrupt enabl e bit and the corres pond-
ing interrupt flag bits set, the device will
immediately wake-up from Sleep.
© 2007 Microchip Technology Inc. DS41211D-page 99
PIC12F683
FIGURE 12-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT
12.8 Code Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out using ICSP for ver ification purposes.
12.9 ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are
readable and writable during Program/Verify mode.
Only the Least Significant 7 bits of the ID locations are
used.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
PC PC + 1 PC + 2
Inst(PC) = Sleep
Inst(PC – 1)
Inst(PC + 1)
Sleep
Processor in
Sleep
Interrupt Latency(3)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h) Inst(0005h)
Inst(0004h)
Dummy Cycle
PC + 2 0004h 0005h
Dummy Cycle
TOST(2)
PC + 2
Note 1: XT, HS or LP Oscilla tor mode assumed.
2: TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RCIO Oscillator modes.
3: GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution w ill cont inue in-l ine.
4: CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.
Note: The entire data EEPROM and Flash pro-
gram memory will be erased when the
code protection is turned off. See the
PIC12F6XX/16 F6XX Memor y
Programming Specification” (DS41204)
for more information.
PIC12F683
DS41211D-page 100 © 2007 Microchip Technology Inc.
12.10 In-Circuit Serial Programming™
The PIC12F683 microcontrollers can be serially
progra mmed w hile in t he en d app licati on c ircuit. This i s
simply done with five connections for:
•clock
•data
power
ground
programming voltage
This allows customers to manufacture boards with
unprogrammed devices and then program the micro-
controller just before shipping the product. This also
allows the most recent firmware or a custom firmware
to be programmed.
The device is placed into a Program/Verify mode by
holding the GP0 and GP1 pins low, while raising the
MCLR (VPP) pin from VIL to VIHH. See the
PIC12F6XX/16F6XX Memory Programming
Specification” (DS41204) for more information. GP0
become s the programm ing dat a and G P1 becom es the
programming clock. Both GP0 and GP1 are Schmitt
Trigger inputs in Program/Verify mode.
A typical In-Circuit Serial Programming connection is
shown in Figure 12-11.
FIGURE 12-11: TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
12.11 In-Circuit Debugger
Since in-circuit debugging requires access to three
pins, M PLAB® ICD 2 deve lo pment w ith a 1 4-pin devic e
is not practical. A special 14-pin PIC12F683 ICD device
is used with MPLAB ICD 2 to provide separate clock,
data and MCLR pins and frees all normally available
pins to the user.
A special debugging adapter allows the ICD device to
be used in place of a PIC12F683 device. The
debuggi ng adapter is the only source of th e ICD device.
When th e ICD pin on the PIC12F 683 ICD de vice is held
low, the In-Circuit Debugger functionality is enabled.
This function allows simple debugging functions when
used with MPL AB ICD 2. When the microc ontroller ha s
this feature enabled, some of the resources are not
available for general use. Table 12-9 shows which
features are consumed by the background debugger.
TABLE 12-9: DEBUGGER RESOURCES
For more information, see “MPLAB® ICD 2 In-Circuit
Debugger User’s Guide” (DS51331), available on
Micro c hip’s we b site (www.microchip .com) .
FIGURE 12-12: 14-PIN ICD PINOUT
External
Connector
Signals
To Normal
Connections
To Normal
Connections
PIC12F683
VDD
VSS
MCLR/VPP/GP3
GP1
GP0
+5V
0V
VPP
CLK
Data I/O
* * *
*
* Isolation devices (as required)
Resource Description
Stack 1 level
Program Memory Address 0h must be NOP
700h-7FFh
14-Pin PDIP
PIC12F683-ICD
In-Circuit Debug Device
NC
ICDMCLR
VDD
GP5
GP4
GP3
ICD
ICDCLK
ICDDATA
GND
GP0
GP1
GP2
NC
1
2
3
4
5
6
7
14
13
12
9
11
10
8
© 2007 Microchip Technology Inc. DS41211D-page 101
PIC12F683
13.0 INSTRUCTION SET SUMMARY
The PIC 12F683 i nstructio n set i s highly orthogon al and
is comprised of three basic categories:
Byte-oriented operations
Bit-oriented operations
Literal and cont rol operations
Each PIC16 instruction is a 14-bit word divided into an
opcode, which specifies the instruction type and one or
more operands, which further specify the operation of
the instruction. The formats for each of the categories
is presented in Figure 13-1, while the various opcode
fields are sum m ariz ed in Table 13-1.
Table 13-2 lists the instructions recognized by the
MPASMTM assembler.
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The desti nation designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W regis ter . If ‘d’ is one, the res ult is place d
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator, which selects the bit affected by the
operation, while ‘f’ represents the address of the file in
which the bit is located.
For literal and control operations, ‘k’ represents an
8-bit or 11-bit constant, or literal value.
One instr uction cycle co nsists of four os cillator periods ;
for an oscillator frequency of 4 MHz, this gives a
nominal instruction execution time of 1 μs. All
instructions are executed within a single instruction
cycle, unless a conditional test is true, or the program
counter is changed as a result of an instruction. When
this occurs, the execution takes two instruction cycles,
with the second cycle executed as a NOP.
All instruction examples use the format0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
13.1 Read-Modify-Write Operations
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
tion, or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
For example, a CLRF PORTA instruction will read
PORTA, clear all the data bits , then write the result back
to PORTA. This example would have the unintended
consequence of clearing the condition that s et the RAIF
flag.
TABLE 13-1: OPCODE FIELD
DESCRIPTIONS
FIGURE 13-1: GENERAL FORMAT FOR
INSTRUCTIONS
Field Description
fRegister file address (0x00 to 0x7F)
WWorking register (accumulator)
bBit address within an 8-bit file register
kLiteral field, constant data or label
xDon’t care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
dDestination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
PC Program Counter
TO Time-out bit
CCarry bit
DC Digit carry bit
ZZero bit
PD Power-down bit
Byte-oriented file r e gister operations
13 8 7 6 0
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operati ons
13 10 9 7 6 0
OPCODE b (BIT # ) f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
13 8 7 0
OPCODE k (li te r a l )
k = 8-bit immediate value
13 11 10 0
OPCODE k (liter a l )
k = 11-bit immediate value
General
CALL and GOTO instructions only
PIC12F683
DS41211D-page 102 © 2007 Microchip Technology Inc.
TABLE 13-2: PIC12F683 INSTRUCTION SET
Mnemonic,
Operands Description Cycles 14-Bit Opcode Status
Affected Notes
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C, DC, Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
Z
1, 2
1, 2
2
1, 2
1, 2
1, 2, 3
1, 2
1, 2, 3
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1, 2
1, 2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Call Subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move litera l to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C, DC, Z
Z
TO, PD
Z
TO, PD
C, DC, Z
Z
Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used wil l be that value present
on the pins t hemselves. For example, if the data latch is 1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1) , the prescaler will be cleared if
assigned to the Timer0 module.
3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
© 2007 Microchip Technology Inc. DS41211D-page 103
PIC12F683
13.2 Instruction Descriptions
ADDLW Add literal and W
Syntax: [ label ] ADDLW k
Operands: 0 k 255
Operation: (W) + k (W)
Status Affected: C, DC, Z
Description: The contents of the W register
are added to the eight-bit literal ‘k’
and the result is placed in the
W register.
ADDWF Add W and f
Syntax: [ label ] ADDWF f,d
Operands: 0 f 127
d ∈ [0,1]
Operation: (W) + (f) (destination)
Status Affected: C, DC, Z
Desc ription: Ad d the content s of the W register
with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W registe r . I f
‘d’ is ‘1’, the result is stored back
in register ‘f’.
ANDLW AND literal with W
Syntax: [ label ] ANDLW k
Operands: 0 k 255
Operation: (W) .AND. (k) (W)
Status Affected: Z
Description: The contents of W register are
AND’ed with the eight-bit literal
‘k’. The result is placed in the W
register.
ANDWF AND W with f
Syntax: [ label ] ANDWF f,d
Operands: 0 f 127
d ∈ [0,1]
Operation: (W) .AND. (f) (destination)
Status Affected: Z
Description: AND the W register with register
‘f’. If ‘d’ is ‘0’, the resu lt is stored in
the W register. If ‘d’ is 1’, the
result is sto r ed bac k in regi ste r ‘f’.
BCF Bit Clear f
Syntax: [ label ] BCF f,b
Operands: 0 f 127
0 b 7
Operation: 0 (f<b>)
St at us Af fe cte d: None
Description: Bit ‘b’ in register ‘f’ is cleared.
BSF Bit Set f
Syntax: [ label ] BSF f,b
Operands: 0 f 127
0 b 7
Operation: 1 (f<b>)
St at us Af fe cte d: None
Description: Bit ‘b’ in register ‘f’ is set.
BTFSC Bit Test f, Skip if Clear
Syntax: [ label ] BTFSC f,b
Operands: 0 f 127
0 b 7
Operation: skip if (f<b>) = 0
St at us Af fe cte d: None
Descr iption: If bit ‘b’ in regis ter ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the
next instru ction is discarde d, and
a NOP is executed instead, making
this a 2-cycle instruction.
PIC12F683
DS41211D-page 104 © 2007 Microchip Technology Inc.
BTFSS Bit Test f, Skip if Set
Syntax: [ label ] BTFSS f,b
Operands: 0 f 127
0 b < 7
Operation: skip if (f<b>) = 1
Status Affected: None
Desc ription: If bit ‘b’ in register ‘f’ i s ‘0’, the next
instructi on is exec uted .
If bit ‘b’ is ‘1’, then the next
instructi on is dis ca rded an d a NOP
is exec ute d i nst ead, making thi s a
2-cycle instruction.
CALL Call Subroutine
Syntax: [ label ] CALL k
Operands: 0 k 2047
Operation: (PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
Status Affected: None
Description: Call Subroutine. First, return
address (PC + 1) is pushed onto
the stack. The eleven-bit
immediate address is loaded into
PC bits <10:0>. The upper bits of
the PC are loa ded from PC LATH.
CALL is a two-cycle instruction.
CLRF Clear f
Syntax: [ label ] CLRF f
Operands: 0 f 127
Operation: 00h (f)
1 Z
Status Affected: Z
Desc ript ion : The content s of regi ste r ‘f’ are
cleared and the Z bit is set.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h (W)
1 Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z)
is set.
CLRWDT Clear Watchdog Timer
Syntax: [ label ] CLRWDT
Operands: None
Operation: 00h WDT
0 WDT prescaler,
1 TO
1 PD
St at us Af fe cte d: TO, PD
Description: CLRWDT instruction resets the
W atchdog T imer . It also resets the
prescaler of the WDT.
Status bits TO and PD are set.
COMF Complement f
Syntax: [ label ] COMF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) (destination)
St at us Af fe cte d: Z
Description: The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’,
the result is stored back in
register ‘f’.
DECF Decrement f
Syntax: [ label ] DECF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - 1 (destination)
St at us Af fe cte d: Z
Description: Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is 1’, the result is
stored back in register ‘f’.
© 2007 Microchip Technology Inc. DS41211D-page 105
PIC12F683
DECFSZ Decrement f, Skip if 0
Syntax: [ label ] DECFSZ f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - 1 (destination);
skip if result = 0
Status Affected: None
Description: The contents of register ‘f’ are
decrem ented. If ‘d’ is ‘0’, th e result
is placed in the W register. If ‘d’ is
1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next
instruction is executed. If the
resu lt is ‘0’, then a NOP is
executed instead, making it a
2-cycle instruction.
GOTO Unconditional Branch
Syntax: [ label ] GOTO k
Operands: 0 k 2047
Operation: k PC<10:0>
PCLATH<4:3> PC<12:11>
Status Affected: None
Description: GOTO is an unconditional branch.
The e le ven -bi t im me dia t e v al ue i s
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a
two-cycle instruction.
INCF Increment f
Syntax: [ label ] INCF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) + 1 (destination)
Status Affected: Z
Description: The contents of register ‘f’ are
incremen ted. If ‘ d’ is 0’, the result
is placed in the W register. If ‘d’ is
1’, the result is placed back in
register ‘f’.
INCFSZ Increment f, Skip if 0
Syntax: [ label ] INCFSZ f,d
Operands: 0 f 127
d [0,1]
Operation: (f) + 1 (destination),
skip if result = 0
St at us Af fe cte d: None
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next
instruction is executed. If the
result is0’, a NOP is executed
instead, making it a 2-cycle
instruction.
IORLW Inclusive OR literal with W
Syntax: [ label ] IORLW k
Operands: 0 k 255
Operation: (W) .OR. k (W)
St at us Af fe cte d: Z
Descr iption: The con tents of t he W register a re
OR’ed with the eight-bit literal ‘k’.
The result is placed in the
W registe r.
IORWF Inclusive OR W with f
Syntax: [ label ] IORWF f,d
Operands: 0 f 127
d [0,1]
Operation: (W) .OR. (f) (destin ation)
St at us Af fe cte d: Z
Description: Inclusive OR the W register with
register ‘f’. If ‘d’ is 0’, the result is
placed in the W register. If ‘d’ is
1’, the result is pla ce d back in
register ‘f’.
PIC12F683
DS41211D-page 106 © 2007 Microchip Technology Inc.
MOVF Move f
Syntax: [ label ] MOVF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) (dest)
Status Affected: Z
Description: The contents of register f is
moved to a destination dependent
upon the status of d. If d = 0,
destination is W register. If d = 1,
the destination is file register f
itsel f. d = 1 is useful to test a file
register since status flag Z is
affected.
Words: 1
Cycles: 1
Example: MOVF FSR, 0
After Instruction
W= value in FSR
register
Z= 1
MOVLW Move literal to W
Syntax: [ label ] MOVLW k
Operands: 0 k 255
Operation: k (W)
Status Affected: None
Desc ription: The eight-bit l iteral ‘k’ i s loaded i nto
W register. The “don’t cares” will
assemble a s ‘0’s.
Words: 1
Cycles: 1
Example: MOVLW 0x5A
After Instruction
W= 0x5A
MOVWF Move W to f
Syntax: [ label ] MOVWF f
Operands: 0 f 127
Operation: (W) (f)
St at us Af fe cte d: None
Description: Move data from W register to
register ‘f’.
Words: 1
Cycles: 1
Example: MOVW
F
OPTION
Before Instruction
OPTION= 0xFF
W = 0x4F
After Instruction
OPTION= 0x4F
W = 0x4F
NOP No Operation
Syntax: [ label ] NOP
Operands: None
Operation: No operation
St at us Af fe cte d: None
Description: No operation.
Words: 1
Cycles: 1
Example: NOP
© 2007 Microchip Technology Inc. DS41211D-page 107
PIC12F683
RETFIE Return from Interrupt
Syntax: [ label ] RETFIE
Operands: None
Operation: TOS PC,
1 GIE
Status Affected: None
Description: Return from Interrupt. Stack is
POPed an d Top-of-S tack (T OS) is
loaded in the PC. Interrupts are
enabled by setting Global
Interrupt Enable bit, GIE
(INTCON<7>). This is a two-cycle
instruction.
Words: 1
Cycles: 2
Example: RETFIE
After Interrupt
PC = TOS
GIE = 1
RETLW Return with literal in W
Syntax: [ label ] RETLW k
Operands: 0 k 255
Operation: k (W);
TOS PC
St at us Af fe cte d: None
Description: The W register is loaded with the
eight bit literal ‘k’. The program
counter is loaded from the top of
the stack (the return address).
This is a two-cycle instruction.
Words: 1
Cycles: 2
Example:
TABLE
CALL TABLE;W contains
table
;offset value
;W now has table value
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
RETLW kn ; End of table
Before Instruction
W = 0x07
After Instruction
W = value of k8
RETURN Return from Subroutine
Syntax: [ label ] RETURN
Operands: None
Operation: TOS PC
St at us Af fe cte d: None
Description: Return from subroutine. The stack
is POPed an d the top of th e s tack
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.
PIC12F683
DS41211D-page 108 © 2007 Microchip Technology Inc.
RLF Rotate Left f through Carry
Syntax: [ label ] RLF f,d
Operands: 0 f 127
d [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ‘f’ are
rotated one bit to the left through
the Carry flag. If ‘d’ is ‘0’, the
result is placed in the W register.
If ‘d’ is1’, the result is stored
back in register ‘f’.
Words: 1
Cycles: 1
Example: RLF REG1,0
Before Instruction
REG1 = 1110 0110
C=0
After Instruction
REG1 = 1110 0110
W = 1100 1100
C=1
RRF Rotate Right f through Carry
Syntax: [ label ] RRF f,d
Operands: 0 f 127
d [0,1]
Operation: See description below
Status Affected: C
Desc ript ion : The content s of regis te r ‘f’ are
rotat ed one bit to the r ight throug h
the Carry flag. If ‘d’ is ‘0’, the
result is placed in the W register.
If ‘d’ is ‘1’, the result is place d
back in reg ister ‘f’.
Register fC
Register fC
SLEEP Enter Sleep mode
Syntax: [ label ] SLEEP
Operands: None
Operation: 00h WDT,
0 WDT prescaler,
1 TO,
0 PD
St at us Af fe cte d: TO , PD
Descripti on: The power-down S tatus bit, PD is
cleared. Time-out Status bit, TO
is set. Watchdog Timer and its
prescaler are cleared.
The processor is put into Sleep
mode with th e oscillator sto pped.
SUBLW Subtract W from literal
Syntax: [ label ] SUBLW k
Operands: 0 k 255
Operation: k - (W) → (W)
Status Affected: C, DC, Z
Description: The W register is subtracted (2’s
complement method) from the
eight-bit literal ‘k’. The result is
placed in the W register.
C = 0W > k
C = 1W k
DC = 0W<3:0> > k<3:0>
DC = 1W<3:0> k<3:0>
© 2007 Microchip Technology Inc. DS41211D-page 109
PIC12F683
SUBWF Subtract W from f
Syntax: [ label ] SUBWF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - (W) → (destination)
Status Affected: C, DC, Z
Description: Subtract (2’s complement method)
W register from register ‘f’. If ‘d’ is
0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f.
SWAPF Swap Nibbles in f
Syntax: [ label ] SWAPF f,d
Operands: 0 f 127
d [0,1]
Operation: (f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Status Affected: None
Description: The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
0’, the result is placed in the W
register. If ‘d’ is ‘1’, the result is
placed in register ‘f’.
C = 0W > f
C = 1W f
DC = 0W<3:0> > f<3:0>
DC = 1W<3:0> f<3:0>
XORLW Exclusive OR literal with W
Syntax: [ label ] XORLW k
Operands: 0 k 255
Operation: (W) .XOR. k → (W)
St at us Af fe cte d: Z
Description: The contents of the W register
are XOR’ed with the eig ht-b it
literal ‘k’. The result is placed in
the W register.
XORWF Exclusive OR W with f
Syntax: [ label ] XORWF f,d
Operands: 0 f 127
d [0,1]
Operation: (W) .XOR. (f) → (destination)
St at us Af fe cte d: Z
Description: Exclusive OR the contents of the
W register with register ‘f’. If ‘d’ is
0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
PIC12F683
DS41211D-page 110 © 2007 Microchip Technology Inc.
NOTES:
© 2007 Microchip Technology Inc. DS41211D-page 111
PIC12F683
14.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
Integrated Development Environment
- MPLAB® IDE Software
Assemblers/Compilers/Linkers
- MPASMTM Assembler
- MPLAB C18 and MPLAB C30 C Compilers
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
- MPLAB ASM30 Assembler/Linker/Library
Simulators
- MPLAB SIM Software Simulator
•Emulators
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB REAL ICE™ In-Circuit Emulator
In-Circuit Debugger
- MPLAB ICD 2
Device Progra mmers
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
- PICkit™ 2 Development Programmer
Low-Cost Demonstration and Development
Boards and Evaluation Kits
14.1 MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- Emulator (sold separatel y)
- In-Circuit Deb ugger (sold separately)
A full-featured editor with color-coded context
A multiple project manager
Customizable data windows with direct edit of
contents
High-level source code debugging
Visual device initializer for easy register
initialization
Mouse over variable inspection
Drag and drop variables from source to watch
windows
Exten si ve on-l in e help
Integration of select third party tools, such as
HI-TECH Software C Compilers and IAR
C Compilers
The MPLAB IDE allows you to:
Edit your source files (eithe r asse mbly or C)
One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools
(automatically updates all project information)
Debug us ing :
- Source files (assemb ly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
PIC12F683
DS41211D-page 112 © 2007 Microchip Technology Inc.
14.2 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assemb ler for all PIC MCUs.
The MPASM Assembler generates relocatable object
files fo r the MPLINK Ob ject Linker , Int el® standa rd HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
Integration into MPLAB IDE projects
User-defined macros to streamline
assembly code
Conditional assembly for multi-purpose
sour ce fil es
Directives that allow complete control over the
assembly process
14.3 MPLAB C18 and MPLAB C30
C Compilers
The MPLAB C18 and MPLAB C30 Code Development
Systems are complete ANSI C compilers for
Microchip’s PIC18 and PIC24 families of microcontrol-
lers an d th e d sPIC 3 0 a nd ds PIC33 family of d igi t al si g-
nal controllers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol info rmation tha t is optimized to the MPLAB IDE
debugger.
14.4 MPLINK Object Linker/
MPLIB Object Librari an
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB O bject Li brarian manag es the cre ation an d
modification of library files of precompiled code. When
a routine from a library is called from a source file , only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
Efficient linking of single libraries instead of many
smaller files
Enhanced code maintainability by grouping
related modules together
Flexible creation of libraries with easy module
listing, replacement, de letion and extraction
14.5 MPLAB ASM30 Assembler, Linker
and Librarian
MPLAB ASM30 Assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 C Compiler uses the
assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linke d with other relocatable ob ject files and
arch ives to c rea te an e xecu tabl e fil e. N otabl e fe atu res
of the assembler include:
Support for the entire dsPIC30F instruction set
Support for fixed-point and floating-point data
Command line interface
Rich dire cti ve set
Flexible macro language
MPLAB IDE compatibility
14.6 MPLAB SIM Software Simulator
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most periph erals and inte rnal regi sters.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
offers the flexibility to develop and debug code outside
of the hardware laboratory environment, making it an
excellent, economical software development tool.
© 2007 Microchip Technology Inc. DS41211D-page 113
PIC12F683
14.7 MPLAB ICE 2000
High-Performance
In-Circui t Emu lator
The MPLAB ICE 2000 In-Circuit Emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PIC
microcontrollers. Software control of the MPLAB ICE
2000 In-Circuit Emulator is advanced by the MPLAB
Integrated Development Environment, which allows
editing, building, downloading and source debugging
from a single environment.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitor-
ing feat ures. Interc hangeabl e proces sor modul es allow
the system to be easily reconfigured for emulation of
different processors. The architecture of the MPLAB
ICE 2000 In-Circuit Emulator allows expansion to
support new PIC microcontrollers.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows® 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
14.8 MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash D SC® and MCU devic es. It debugs and
programs PIC® and dsPIC® Flash microcontrollers with
the easy-to-use, powerful graphical user interface of the
MPLAB Integrated Development Environment (IDE),
included with each kit.
The MPLAB REAL ICE pro be is connected to the design
engineer’s PC using a high-speed USB 2.0 interface and
is connected to the target with either a connector
compatible with the popular MPLAB ICD 2 system
(RJ11) or with the new high speed, noise tolerant, low-
voltage differential signal (LVDS) interconnection
(CAT5).
MPLAB REAL ICE is field upgradeable through future
firmware downloads in MPLAB IDE. In upcoming
releases of MPLAB ID E, new devic es w ill be supported,
and new features will be add ed, such as software break-
points and assembly code trace. MPLAB REAL ICE
offers significant advantages over competitive emulators
including low-cost, full-speed emulation, real-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables .
14.9 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash PIC
MCUs and can be used to develop for these and other
PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes
the in-circuit debugging capability built into the Flash
devices. This feature, along with Microchip’s In-Circuit
Serial ProgrammingTM (ICSPTM) protocol, offers cost-
effective, in-circuit Flash debugging from the graphical
user interface of the MPLAB Integrated Development
Environment. This enables a designer to develop and
debug sou rce code by s etting bre akpoi nts , singl e step-
ping and watching variables, and CPU status and
peripheral registers. Running at full speed enables
testing hardware and applications in real time. MPLAB
ICD 2 also serves as a development programmer for
selected PIC devices.
14.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64 ) for men us an d error m essages and a m odu-
lar, detachable socket assembly to support various
pack age types. The ICSP™ cable assembly is incl uded
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Devic e Programmer ca n read, verif y and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 h as high-spe ed co mmunicat ions and
optimized algorithms for quick programming of large
memory devices and in corporates an SD/MMC card for
file storage and secure data applications.
PIC12F683
DS41211D-page 114 © 2007 Microchip Technology Inc.
14.11 PICSTART Plus Development
Programmer
The PICSTART Plus Development Programmer is an
easy-to-use, low-cost, prototype programmer. It
connects to the PC via a COM (RS-232) port. MPLAB
Inte grated Dev elopmen t En vironme nt so ftware makes
using the programmer simple and efficient. The
PICSTART Plus Development Programmer supports
most PIC devices in DIP packages up to 40 pins.
Larger pin count devices, such as the PIC16C92X and
PIC17C76 X, may be sup ported with an a dapter socket.
The PICSTART Plus Development Programmer is CE
compliant.
14.12 PICkit 2 Development Programmer
The PICkit™ 2 Development Programmer is a low-cost
programmer and selected Flash device debugger with
an easy-to-use interface for programming many of
Microchip’s baseline, mid-range and PIC18F families of
Flash m emory microcontrol lers. The PICkit 2 S tarter Kit
includes a prototyping development board, twelve
sequential lessons, software and HI-TECH’s PICC™
Lite C compiler , and is desig ned to hel p get up to s peed
quickly using PIC® microcontrollers. The kit provides
everything needed to program, evaluate and develop
applications using Microchip’s powerful, mid-range
Flash memory family of microcontrollers.
14.13 Demonstration, Development and
Evaluation Boards
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards includ e prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The board s suppo rt a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory .
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart® battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Check the Microchip web page (www.microchip.com)
and the latest “Product Selector Guide” (DS00148) for
the complete list of demonstration, development and
evaluation kits.
© 2007 Microchip Technology Inc. DS41211D-page 115
PIC12F683
15.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings(†)
Ambient temperature under bias..........................................................................................................-40° to +125°C
Storage temperature........................................................................................................................ -65°C to +150°C
Vo lt a ge on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V
Vo lt a ge on MCLR with respect to Vss ............................................................................................... -0.3V to +13.5V
Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)
Total power dissipation(1) ...............................................................................................................................800 mW
Maximum curr ent o ut of VSS pin ...................................................................................................................... 95 mA
Maximum curr ent i nto VDD pin......................................................................................................................... 95 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...............................................................................................................± 20 mA
Output clamp current, IOK (Vo < 0 or Vo >VDD).........................................................................................................± 20 mA
Maximum output current sunk by any I/O pin....................................................................................................25 mA
Maximum output current sourced by any I/O pin..............................................................................................25 mA
Maximum current sunk by GPIO...................................................................................................................... 90 mA
Maximum current sourced GPIO...................................................................................................................... 90 mA
Note 1: Power d issip ati on is calc ulated as fo llows: PDIS = VDD x {IDD IOH} + {(VDD – VOH) x IOH} + (VOl x IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
PIC12F683
DS41211D-page 116 © 2007 Microchip Technology Inc.
FIGURE 15-1: PIC12F683 VOLTAGE-FREQUENCY GRAPH,
-40°C
TA
+125°C
FIGURE 15-2: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE
5.5
2.0
3.5
2.5
0
3.0
4.0
4.5
5.0
Frequency (MHz)
VDD (V)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
82010
125
25
2.0
0
60
85
VDD (V)
4.0 5.04.5
Temperature (°C)
2.5 3.0 3.5 5.5
± 1%
± 2%
± 5%
© 2007 Microchip Technology Inc. DS41211D-page 117
PIC12F683
15.1 DC Characteristi cs: PIC12F683-I (Industrial)
PIC12F683-E (Extended)
DC CHARACTERISTICS Standard Opera ting Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Sym Characteristic Min Typ† Max Units Conditions
D001
D001C
D001D
VDD Supply Voltage 2.0
2.0
3.0
4.5
5.5
5.5
5.5
5.5
V
V
V
V
FOSC < = 8 MHz: HFINTOSC, EC
FOSC < = 4 MHz
FOSC < = 10 MHz
FOSC < = 20 MHz
D002* VDR RAM Data Retention
Voltage(1) 1.5 V Device in Sleep mode
D003 VPOR VDD Start Voltage to
ensure internal Power-on
Reset signal
—VSS —VSee Section 12.3.1 “Pow er-o n Reset”
for details.
D004* SVDD VDD Rise Rate to ensure
internal Power-on Reset
signal
0.05 V/ms See Section 12.3.1 “Power-on Reset”
for details.
* These parameters are characterized but not tested.
Data i n “Typ” colum n i s at 5.0V, 25°C unless othe rw ise s tated. Thes e parameters are for design gu ida nce
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
PIC12F683
DS41211D-page 118 © 2007 Microchip Technology Inc.
15.2 DC Characteristi cs: PIC12F683-I (Industrial)
PIC12F683-E (Extended)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Device Char ac teri st ics Min Typ† Max Units Conditions
VDD Note
D010 Supply Current (IDD)(1, 2) —1116μA2.0FOSC = 32 kHz
LP Oscillator mode
—1828μA3.0
—3554μA5.0
D011* 140 240 μA2.0F
OSC = 1 MHz
XT Oscillator mode
220 380 μA3.0
380 550 μA5.0
D012 260 360 μA2.0F
OSC = 4 MHz
XT Oscillator mode
420 650 μA3.0
—0.81.1mA5.0
D013* 130 220 μA2.0F
OSC = 1 MHz
EC Osci llator mode
215 360 μA3.0
360 520 μA5.0
D014 220 340 μA2.0F
OSC = 4 MHz
EC Osci llator mode
375 550 μA3.0
0.65 1.0 mA 5.0
D015 8 20 μA2.0F
OSC = 31 kHz
LFINTOSC mode
—1640μA3.0
—3165μA5.0
D016* 340 450 μA2.0F
OSC = 4 MHz
HFINTOSC mode
500 700 μA3.0
—0.81.2mA5.0
D017 410 650 μA2.0F
OSC = 8 MHz
HFINTOSC mode
700 950 μA3.0
1.30 1.65 mA 5.0
D018 230 400 μA2.0F
OSC = 4 MHz
EXTRC mode(3)
400 680 μA3.0
0.63 1.1 mA 5.0
D019 2.6 3.25 mA 4.5 FOSC = 20 MHz
HS Osci llator mode
2.8 3.35 mA 5.0
* These parameters are characterized but not tested.
Data in “Typ” c olu mn is at 5. 0V, 25°C unless ot he rwise stated. Th ese param eters are for des ign gui dance
only and are not tested.
Note 1: The test con ditions for al l IDD me asurem ent s in acti ve op eration mod e are: OSC1 = e xternal s quare wav e,
from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loadin g and swi tchin g rate, oscilla tor type, int erna l code exe cutio n patte rn and temp erature, al so have
an impact on the current consumption.
3: For RC oscillat or config urations, cu rrent th rough REXT i s not in cluded. The curren t through the resi stor can
be extended by the formula IR = VDD/2REXT (mA) with REXT in kΩ.
© 2007 Microchip Technology Inc. DS41211D-page 119
PIC12F683
15.3 DC Characteristi cs: PIC12F683-I (Industrial)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
Param
No. Device Characteristics Min Typ† Max Units Conditions
VDD Note
D020 Power-down Base
Current(IPD)(2) 0.05 1.2 μA 2.0 WDT, BOR, Comparators, VREF and
T1OSC dis ab led
0.15 1.5 μA3.0
0.35 1.8 μA5.0
150 500 nA 3.0 -40°C TA +25°C
D021 1.0 2.2 μA 2.0 WDT Current(1)
—2.04.0μA3.0
—3.07.0μA5.0
D022 42 60 μA 3.0 BOR Current(1)
85 122 μA5.0
D023 32 45 μA 2 .0 Comparator Current(1), both
comparators enabled
—6078μA3.0
120 160 μA5.0
D024 30 36 μA2.0CV
REF Current(1) (high range)
—4555μA3.0
—7595μA5.0
D025* 39 47 μA2.0CV
REF Current(1) (low range)
—5972μA3.0
98 124 μA5.0
D026 4.5 7.0 μA 2.0 T1OSC Current(1), 32.768 kHz
—5.08.0μA3.0
—6.012μA5.0
D027 0.30 1.6 μA 3.0 A/D Current(1), no conversion in
progress
0.36 1.9 μA5.0
* These parameters are characterized but not tested.
Data in “Typ” c olu mn is at 5. 0V, 25°C unless ot he rwise stated. Th ese param eters are for des ign gui dance
only and are not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD
current from this limit. Max values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
PIC12F683
DS41211D-page 120 © 2007 Microchip Technology Inc.
15.4 DC Characteristics: PIC12F683-E (Extended)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C for extended
Param
No. Device Characteristics Min Typ† Max Units Conditions
VDD Note
D020E Power-down Base
Current (IPD)(2) —0.05 9 μA 2.0 WDT, BOR, Comparators, VREF an d
T1OSC disabled
—0.1511 μA3.0
—0.3515 μA5.0
D021E 1 17.5 μA 2.0 WDT Current(1)
—219μA3.0
—322μA5.0
D022E 42 65 μA 3.0 BOR Current(1)
—85127μA5.0
D023E 32 45 μA 2.0 Compara tor Curren t(1), both
comparators enabled
—6078μA3.0
—120160μA5.0
D024E 30 70 μA2.0CV
REF Current(1) (high range)
—4590μA3.0
—75120μA5.0
D025E* 39 91 μA2.0CV
REF Current(1) (low range)
—59117μA3.0
—98156μA5.0
D026E 4.5 25 μA 2.0 T1OSC Current(1), 32.768 kHz
—530μA3.0
—640μA5.0
D027E 0.30 12 μA 3.0 A/D Current(1), no conversion in
progress
—0.3616 μA5.0
* These parameters are characterized but not tested.
Data in “Typ” colum n is at 5 .0V, 25°C u nle ss otherwise st ated. These parame ters are for d esi gn gui dan ce
only and are not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD
current from this limit. Max values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
© 2007 Microchip Technology Inc. DS41211D-page 121
PIC12F683
15.5 DC Characteristi cs: PIC12F683-I (Industrial)
PIC12F683-E (Extended)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Sym Characteristic Min Typ† Max Units Conditions
VIL Input Low Voltage
I/O Port:
D030 with TTL buffer Vss 0.8 V 4.5V VDD 5.5V
D030A Vss 0. 15 VDD V2.0V VDD 4.5V
D031 with Schmitt Trigger buf fer Vss 0.2 VDD V2.0V VDD 5.5V
D032 MCLR, OSC1 (RC mode)(1) VSS —0.2 VDD V
D033 OSC1 (XT and LP modes) V SS —0.3V
D033A OSC1 (HS mode) VSS —0.3 VDD V
VIH Input High Voltage
I/O ports:
D040 with TTL buffer 2.0 VDD V4.5V VDD 5.5V
D040A 0.25 VDD + 0.8 VDD V2.0V VDD 4.5V
D041 with Schmitt Tr igger buffer 0.8 VDD —VDD V2.0V VDD 5.5V
D042 MCLR 0.8 VDD —VDD V
D043 OSC1 (XT and LP modes) 1.6 VDD V
D043A OSC1 (HS mode) 0.7 VDD —VDD V
D043B O SC1 (RC mode) 0.9 VDD —VDD V(Note 1)
IIL Input Leakage Current(2)
D060 I/O ports ± 0.1 ± 1μAVSS VPIN VDD,
Pin at high-impedance
D061 MCLR(3) ± 0.1 ± 5μAVSS VPIN VDD
D063 OSC1 ± 0.1 ± 5μAVSS VPIN VDD, XT, HS and
LP oscillator configuration
D070* IPUR GPIO Weak Pull-up Current 50 250 4 00 μAVDD = 5.0V, VPIN = VSS
VOL Output Low Voltage(5)
D080 I/O ports 0.6 V IOL = 8.5 mA, VDD = 4.5V (Ind.)
VOH Output High Voltage(5)
D090 I/O ports V DD – 0.7 V IOH = -3.0 mA, VDD = 4.5V (Ind.)
* These parameters are characterized but not tested.
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
no t te sted.
Note 1: In RC oscillator configuration, the O SC1/ CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: See Section 10.4.1 “Using the Data EEPROM” for additional information.
5: Including OSC2 in CLKOUT mode.
PIC12F683
DS41211D-page 122 © 2007 Microchip Technology Inc.
D100 IULP Ultra Low-Power Wake-Up
Current 200 nA S ee Application Note AN879,
Using the Microchip Ultra
Low-Power Wake-up Module
(DS00879)
Capacitive Loading Specs on
Output Pins
D101* COSC2 OSC2 pin 15 pF In XT, HS and LP modes when
external clock is used to drive
OSC1
D101A* CIO All I/O pins 50 pF
Data EEPROM Memory
D120 EDByte Endurance 100K 1M E/W -40°C TA +85°C
D120A EDByte Endurance 10K 100K E/W +85°C TA +125°C
D121 VDRW VDD for Read/Write VMIN 5.5 V Using EECON1 to read/write
VMIN = Minimum operating
voltage
D122 TDEW Erase/Write Cycle Time 5 6 ms
D123 TRETD Characteristic Retention 40 Year Provided no other specifications
are violated
D124 TREF Number of Total Erase/Write
Cycles before Refresh(4) 1M 10M E/W -40°C TA +85°C
Program Flash Memory
D130 EPCell Endurance 10K 100K E/W -40°C TA +85°C
D130A EDCell Endurance 1K 10K E/W +85°C TA +125°C
D131 VPR VDD for Read VMIN —5.5VVMIN = Minimum operating
voltage
D132 VPEW VDD for Erase/Write 4.5 5.5 V
D133 TPEW Erase/Write cycle time 2 2.5 ms
D134 TRETD Characteristic Retention 40 Year Provided no other specifications
are violated
15.5 DC Characteristi cs: PIC12F683-I (Industrial)
PIC12F683-E (Extended) (Continued)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Sym Characteristic Min Typ† Max Units Conditions
* These parameters are characterized but not tested.
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
no t te sted.
Note 1: In RC oscillator configuration, the O SC1/ CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: See Section 10.4.1 “Using the Data EEPROM” for additional information.
5: Including OSC2 in CLKOUT mode.
© 2007 Microchip Technology Inc. DS41211D-page 123
PIC12F683
15.6 Thermal Considerations
Standard Operating Conditions (unless otherwise stated)
Ope rati ng temperature - 40°C TA +125°C
Param
No. Sym Characteristic Typ Units Conditions
TH01 θJA Thermal Resistance
Junction to Ambient 84.6 °C/W 8-pin PDIP package
163.0 °C/W 8-pin SOIC package
52.4 °C/W 8-pin DFN-S 4x4x0.9 mm package
46.3 °C/W 8-pin DFN-S 6x5 mm package
TH02 θJC Thermal Resistance
Junction to Case 41.2 °C/W 8-pin PDIP package
38.8 °C/W 8-pin SOIC package
3.0 °C/W 8-pin DFN-S 4x4x0.9 mm package
2.6 °C/W 8-pin DFN-S 6 x 5 mm package
TH03 TJJunction Temperature 150 °C For derated power calculations
TH04 PD Power Dissipation W PD = PINTERNAL + PI/O
TH05 PINTERNAL Internal Power Dissipation W PINTERNAL = IDD x VDD
(NOTE 1)
TH06 PI/OI/O Power Dissipation W PI/O = Σ (IOL * V OL) + Σ (IOH * (VDD - VOH))
TH07 PDER Derated Power W PDER = (TJ - TA)/θJA
(NOTE 2, 3)
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature.
3: Maximum allowable power dissipation is the lower value of either the absolute maximum total power
dissipation or derated power (PDER).
PIC12F683
DS41211D-page 124 © 2007 Microchip Technology Inc.
15.7 Timing Parameter Symbology
The timing parameter symbols have been created with
one of the following formats:
FIGURE 15-3: LOAD CONDITIONS
1. TppS2ppS
2. TppS
TF Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O PORT t1 T1CKI
mc MCLR wr WR
Uppe rcase letters and th eir meanings:
SFFall PPeriod
HHigh RRise
I Invalid (High-impedance) V Valid
L Low Z High-impedance
V
SS
C
L
Legend: CL= 50 pF for all pins
15 pF for OSC2 output
Load Con dition
Pin
© 2007 Microchip Technology Inc. DS41211D-page 125
PIC12F683
15.8 AC Characteristics: PIC12F683 (Industrial, Extended)
FIGURE 15-4: CLOCK TIMING
TABLE 15-1: CLOCK OSCILLATOR TI MING REQUIREMENTS
Standard Operating Condi tions (unless o th erwise stated)
Operat i ng t em peratur e -40°C TA +125°C
Param
No. Sym Characteristic Min Typ† Max Units Conditions
OS01 FOSC Externa l CLKIN Freq uency(1) DC 37 kHz LP Oscillator m ode
DC 4 MHz XT Oscillator mode
DC 20 MHz HS Oscillator mode
DC 20 MHz EC Oscillator mode
Oscillator Frequency(1) 32. 768 kHz LP Osc i llator m ode
0.1 4 MHz XT Oscillator mode
1 20 MHz HS Oscillator mode
DC 4 MHz RC Oscillator mode
OS02 TOSC External CLKIN Period(1) 27 μs LP Oscillator m ode
250 n s XT Oscillator mode
50 ns HS Osc illat or mo de
50 ns EC Oscillator mo de
Oscillator Period(1) —30.5 μs LP Oscillator m ode
250 10,000 ns XT Oscillator m ode
50 1,000 ns HS Osc ill at or mo de
250 ns RC Oscillator mode
OS03 TCY Inst ruction C ycle Time(1) 200 TCY DC ns TCY = 4/FOSC
OS04* TosH,
TosL External CLKIN High,
External CLKIN Low 2—μs LP oscillator
100 ns XT oscillator
20 ns HS oscillator
OS05* TosR,
TosF External CLKIN Rise,
External CLKIN Fall 0 ns LP oscillator
0 ns XT oscillator
0 ns HS oscillator
* Thes e para m et er s ar e characterized but not tested.
Data in “T yp” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are no t tested.
Note 1: I nstru ct io n cycle pe ri od (TCY) equ als fo ur tim es the input oscillator t ime base period. All specified values are
based on chara ct er iz at ion data for that particul ar oscilla to r type un d er standard ope rating con di tio ns w i t h th e
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
highe r than expect ed current consumpt i on. Al l devi ces are test ed to operate at “min” va lu es with an ext er nal
clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for
all devi ces.
OSC1/CLKIN
OSC2/CLKOUT
Q4 Q1 Q2 Q3 Q4 Q1
OS02
OS03OS04 OS04
OSC2/CLKOUT
(LP,XT,HS Modes)
(CLKOUT Mode)
PIC12F683
DS41211D-page 126 © 2007 Microchip Technology Inc.
TABLE 15-2: OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No. Sym Characteristic Freq.
Tolerance Min Typ† Max Units Conditions
OS06 TWARM Internal Oscillator Switch
when running(3) ——2TOSC Slo w est clock
OS07 TSC Fail-Safe Sample Clock
Period(1) —21—msLFINTOSC/64
OS08 HFOSC Internal Calibrated
HFINTOSC Frequency(2) ±1% 7.92 8.0 8.08 MHz VDD = 3.5V, 25°C
±2% 7.84 8.0 8.16 MHz 2.5V VDD 5.5V,
0°C TA +85°C
±5% 7.60 8.0 8.40 MHz 2.0V VDD 5.5V,
-40°C TA +85°C (Ind.),
-40°C TA +125°C (Ext.)
OS09* LFOSC Internal Uncalibra ted
LFINTOSC Frequency 153145kHz
OS10* TIOSC
ST HFINTOSC Oscillator
W ake-up from Sleep
Start-up Time
5.5 12 24 μsVDD = 2.0V, -40°C to +8C
—3.5714μsVDD = 3.0V, -40°C to +85°C
—3611μsV
DD = 5.0V, -40°C to +85°C
* These parameters are characterized but not tested.
Data in “Typ” colum n i s at 5. 0V, 25°C unless oth er w i se s tated. These paramet ers are for de sign guida nc e onl y
and are not test ed.
Note 1: Ins t r uction cycl e period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device e xecuting co de. Exceedi ng these specified lim its ma y r esult in an unstab le oscillator operation and /o r
higher tha n expected current co nsumpti on . All devices are tes te d t o operate at “m in” v al ues with an ext ernal
clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock)
for all devi ces .
2: To ensure these oscillator frequency tolerances, VDD and VSS must be capaci tively decoupled as cl ose to the
device a s possible. 0. 1 μF and 0.01 μF valu es in paral le l are r ecommended.
3: By design .
© 2007 Microchip Technology Inc. DS41211D-page 127
PIC12F683
FIGURE 15-5: CLKOUT AND I/O TIMING
Fosc
CLKOUT
I/O pi n
(Input)
I/O pin
(Output)
Q4 Q1 Q2 Q3
OS11
OS19
OS13
OS15
OS18, OS19
OS20
OS21
OS17 OS16
OS14
OS12
OS18
Old Value New Value
Write Fetch Read ExecuteCycle
TABLE 15-3: CLKOUT AND I/O TIMING PARAMETERS
Standard Operating Conditi ons (unle ss otherw is e stated )
Operating Temperature -40°C TA +125°C
Param
No. Sym Characteristic Min Typ† Max Units Conditions
OS11 TOSH2CKLFOSC to CLKOUT (1) 70 ns VDD = 5.0V
OS12 TOSH2CKHFOSC to CLKOUT (1) 72 ns VDD = 5.0V
OS13 TCKL2IOVCLKOUT to Port out valid(1) 20 ns
OS14 TIOV2CKH Port input valid before CLKOUT(1) TOSC + 200 ns ns
OS15* TOSH2IOVFOSC (Q1 cycle) to Port out valid 50 70 ns VDD = 5.0V
OS16 TOSH2IOIFOSC (Q2 cycle) to Port input invalid
(I/O in hold time) 50 ns VDD = 5.0V
OS17 TIOV2OSH Port input valid to FOSC(Q2 cycle)
(I/O in setup time) 20 ns
OS18 TIOR Port output rise time(2)
15
40 72
32 ns VDD = 2.0V
VDD = 5.0V
OS19 TIOF Port output fall time(2)
28
15 55
30 ns VDD = 2.0V
VDD = 5.0V
OS20* TINP INT pin input high or low time 25 ns
OS21* TGPP GPIO interrupt-on-change new input
level time TCY ——ns
* These parameters are characterized but not tested.
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
2: Includes OSC2 in CLKOUT mode.
PIC12F683
DS41211D-page 128 © 2007 Microchip Technology Inc.
FIGURE 15-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
FIGURE 15-7: BROW N-OUT RESET TIMING AND CHARACTERISTICS
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Start-Up Time
Internal Reset(1)
Wat c hdog Timer
33
32
30
31
34
I/O pins
34
Note 1: Asserted low .
Reset(1)
VBOR
VDD
(Device in Brown-out Reset) (Device not in Brown-out Reset)
33*
37
* 64 ms delay only if PW RTE bit in the Configuration Word register is programmed to ‘0’.
Reset
(due to BOR)
VBOR + VHYST
© 2007 Microchip Technology Inc. DS41211D-page 129
PIC12F683
TABLE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditi ons (unle ss otherw is e stated )
Operating Temperature -40°C TA +125°C
Param
No. Sym Characteristic Min Typ† Max Units Conditions
30 TMCLMCLR Pulse Width (low) 2
5
μs
μsVDD = 5V, -40°C to +85°C
VDD = 5V
31 TWDT Wa tchdog Timer Time-out
Period (No Prescaler) 10
10 16
16 29
31 ms
ms VDD = 5V, -40°C to +85°C
VDD = 5V
32 TOST Oscillation Start-up Timer
Period(1, 2) 1024 TOSC (NOTE 3)
33* TPWRT Power-up Timer Period 40 65 140 ms
34* TIOZ I/O High-impedance from
MCLR Low or Watchdog Timer
Reset
——2.0μs
35 VBOR Brown-out Reset Voltage 2.0 2.2 V (NOTE 4)
36* VHYST Brown-out Reset Hysteresis 50 mV
37* TBOR Brown- out Reset Minimu m
Detection Period 100 μsVDD VBOR
* These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note 1: Instruction cy cle period (TCY) equals four times the input oscillator time base period. All specified values
are based on charac teri za tion data for that part ic ular oscillator typ e unde r st andard operating con di tion s
with the device executing code. Exceeding these specified limits may result in an unstable oscillator oper-
ation and/or higher than expected current consumption. All devices are tested to operate at “min” values
with an e xt erna l c loc k app li ed t o th e O SC 1 pin . Wh en an externa l c loc k inp ut is us ed, the “max” cycl e ti me
limit is “DC” (no clock) for all devices.
2: By design.
3: Period of the slow er clock.
4: To ensure thes e voltag e toleranc es, VDD and VSS must b e capa citively deco upled as c lose to th e device as
possible. 0.1 μF and 0.01 μF values in parallel are recommended.
PIC12F683
DS41211D-page 130 © 2007 Microchip Technology Inc.
FIGURE 15-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
TABLE 15-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No. Sym Characteristic Min Typ† Max Units Conditions
40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 ns
With Prescaler 10 ns
41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 ns
With Prescaler 10 ns
42* TT0P T0CKI Period Greater of:
20 or TCY + 40
N
ns N = prescale value
(2, 4, ..., 256)
45* TT1H T1CKI High
Time Synchronous, No Prescaler 0.5 TCY + 20 ns
Synchronous,
with Pr escaler 15 ns
Asynchronous 30 ns
46* TT1L T1CKI Low
Time Synchronous, No Prescaler 0.5 TCY + 20 ns
Synchronous,
with Pr escaler 15 ns
Asynchronous 30 ns
47* TT1P T1CKI Input
Period Synchronous Greater of:
30 or TCY + 40
N
ns N = prescale value
(1, 2, 4, 8)
Asynchronous 60 ns
48 FT1 Timer1 Oscillator Input Frequency Range
(oscillator enabled by setting bit T1OSCEN) 32.768 — kHz
49* TCKEZTMR1 Delay from External Clock Edge to Ti mer
Increment 2 TOSC —7 TOSC Timers in Sync
mode
* Thes e parameters are characte rized but not tested.
Data in “T yp” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
T0CKI
T1CKI
40 41
42
45 46
47 49
TMR0 or
TMR1
© 2007 Microchip Technology Inc. DS41211D-page 131
PIC12F683
FIGURE 15-9: CAPTURE/COMPARE/PWM TIMINGS (ECCP)
TABLE 15-6: CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP)
Standard Operating Conditi ons (unle ss otherw is e stated )
Operating Temperature -40°C TA +125°C
Param
No. Sym Characteristic Min Typ† Max Units Conditions
CC01* TccL CCP1 Input Low Time No Prescaler 0.5TCY + 20 ns
With Prescaler 20 ns
CC02* TccH CCP1 Input High Time No Prescaler 0.5TCY + 20 ns
With Prescaler 20 ns
CC03* TccP CCP1 Input Per iod 3TCY + 40
N ns N = prescale
value (1, 4 or
16)
* These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note: Refer to Figure 15-3 for load conditions.
(Capture mode)
CC01 CC02
CC03
CCP1
PIC12F683
DS41211D-page 132 © 2007 Microchip Technology Inc.
TABLE 15-7: COMPARATOR SPECIFICATIONS
TABLE 15-8: COMPARATOR VOLTAGE REFERENCE (CVREF) SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Operati ng Tem per ature -40°C TA +125°C
Param
No. Sym Characteristics Min Typ† Max Units Comments
CM01 VOS Input Offset Voltage ± 5.0 ± 10 mV (VDD - 1.5)/2
CM02 VCM Input Common Mode Voltage 0 VDD – 1.5 V
CM03* CMRR Common Mode Rejection Ratio +55 dB
CM04* TRT Response Time Falling 150 600 ns (NOTE 1)
Rising 200 1000 ns
CM05* TMC2COV Comparator Mode Change to
Output Valid —— 10 μs
* These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Respons e tim e is meas ured wi th one comp arator input at (VDD - 1.5)/2 - 100 mV to (VDD -1.5)/2+20mV.
S tandard Operating Conditi ons (unle ss othe rwis e stated)
Operati ng tem pera ture -40°C TA +125°C
Param
No. Sym Characteristics Min Typ† Max Units Comments
CV01* CLSB Step Size(2)
VDD/24
VDD/32
V
VLow Range (VRR = 1)
High Range (VRR = 0)
CV02* CACC Absolute Accuracy
± 1/2
± 1/2 LSb
LSb Low Range (VRR = 1)
High Range (VRR = 0)
CV03* CRUnit Resistor Value (R) 2k Ω
CV04* CST Se ttli ng Time(1) ——10μs
* These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’.
2: See Section 8.11 “Comparator Voltage Reference” for more information.
© 2007 Microchip Technology Inc. DS41211D-page 133
PIC12F683
TABLE 15-9: PIC12F683 A/D CONVERTER (ADC) CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Ope rati ng temperature -40°C TA +125°C
Param
No. Sym Characteristic Min Typ† Max Units Conditions
AD01 NRResolution 10 bits bit
AD02 EIL Integral Error ±1LSbVREF = 5.12V
AD03 EDL Differential Error ±1 LSb No missing codes to 10 bits
VREF = 5.12V
AD04 EOFF Offset Error ±1LSbVREF = 5.12V
AD07 EGN Gain Error ±1LSbVREF = 5.12V
AD06
AD06A VREF Reference Voltage(3) 2.2
2.7 ——
VDD VAbsolute mini mum to ensur e 1 LSb
accuracy
AD07 VAIN Full-Scale Range VSS —VREF V
AD08 ZAIN Recommended
Impedance of Analog
Voltage Source
—— 10kΩ
AD09* IREF VREF Input Current(3) 10 1000 μADuring VAIN acquisition.
Based on differential of VHOLD to VAIN.
—— 50μA During A/D conv ersion cyc le.
* These parameters are characterized but not tested.
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note 1: Total Absolute Error includes integral, differential, offset and gain errors.
2: The A/D conversion result never decreases with an increase in the input voltage and has no missing
codes.
3: ADC VREF is from external VREF or VDD pin, whichever is selected as reference input.
4: When ADC is off, it will not consume any current other than leakage current. The power-down current
specification includes any such leakage from the ADC module.
PIC12F683
DS41211D-page 134 © 2007 Microchip Technology Inc.
TABLE 15-10: PIC12F683 A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Ope rati ng temperature -40°C TA +125°C
Param
No. Sym Characteristic Min Typ† Max Units Conditions
AD130* TAD A/D Clock Period 1.6 9.0 μsTOSC-based, VREF 3.0V
3.0 9.0 μsTOSC-based, VREF full range
A/D Internal RC
Oscillator Period 3.0 6.0 9.0 μsADCS<1:0> = 11 (ADRC mode)
At V DD = 2.5V
1.6 4.0 6.0 μsAt VDD = 5.0V
AD131 TCNV Conversion Time
(not includin g
Acquisiti on Time)(1)
—11—TAD Set GO/DONE bit t o new data in A/D
Result register.
AD132* TACQ Acquisition Tim e 11.5 μs
AD133* TAMP Amplifier Settling Time 5 μs
AD134 TGO Q4 to A/D Clock Start
TOSC/2
TOSC/2 + TCY
If the A/D clock source is selected as
RC, a time of TCY is added before the
A/D clock st art s. This allo ws the SLEEP
instruction to be executed.
* These parameters are characterized but not tested.
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle.
2: See Section 9.3 “A/D Acquisition Requirements” for minimum conditions.
© 2007 Microchip Technology Inc. DS41211D-page 135
PIC12F683
FIGURE 15-10: PIC12F683 A/D CONVERSION TIMING (NORMAL MODE)
FIGURE 15-11: PIC12F683 A/D CONVERSION TIMING (SLEEP MODE)
AD131
AD130
BSF ADCON0, GO
Q4
A/D CLK
A/D Data
ADRES
ADIF
GO
Sample
OLD_DATA
Sampling Stopped
DONE
NEW_DATA
987 3210
Note 1: If the A/D c lock source is selected as R C, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
1 TCY
6
AD134 (TOSC/2(1))
1 TCY
AD132
AD132
AD131
AD130
BSF ADCON0, GO
Q4
A/D CLK
A/D Data
ADRES
ADIF
GO
Sample
OLD_DATA
Sampling Stopped
DONE
NEW_DATA
9 7 3210
Note 1: If the A/D clock sourc e is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
AD134
6
8
1 TCY
(TOSC/2 + TCY(1))
1 TCY
PIC12F683
DS41211D-page 136 © 2007 Microchip Technology Inc.
NOTES:
© 2007 Microchip Technology Inc. DS41211D-page 137
PIC12F683
16.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents
(mean + 3σ) or (mean - 3σ) respectively , where σ is a standard deviation, over each temperature range.
FIGURE 16-1: TYPICAL IDD vs. FOSC OVER VDD (EC MODE)
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only . Th e performance characteristic s listed herein are
not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
3.0V
4.0V
5.0V
5.5V
2.0V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz
FOSC
IDD (mA)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst -c ase Tem p) + 3σ
(-40°C to 125°C)
PIC12F683
DS41211D-page 138 © 2007 Microchip Technology Inc.
FIGURE 16-2: MAX IMU M IDD vs. FOSC OVER VDD (EC MODE)
FIGURE 16-3: TYPICAL IDD vs. FOSC OVER VDD (HS MODE)
EC Mode
3.0V
4.0V
5.0V
2.0V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz
FOSC
IDD (mA)
5.5V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst -c ase Tem p) + 3σ
(-40°C to 125°C)
Typical IDD vs. FOSC Over Vdd
HS Mode
3.0V
3.5V
4.0V
4.5V
5.0V
5.5V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4 MHz 10 MHz 16 MHz 20 MHz
FOSC
IDD (mA)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
© 2007 Microchip Technology Inc. DS41211D-page 139
PIC12F683
FIGURE 16-4: MAX IMU M IDD vs. FOSC OVER VDD (HS MODE)
FIGURE 16-5: TYPICAL IDD vs. VDD OVER FOSC (X T MODE)
Maximum IDD vs. FOSC Over Vdd
HS Mode
3.5V
4.0V
4.5V
5.0V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
4 MHz 10 MHz 16 MHz 20 MHz
FOSC
IDD (mA)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
3.0V
5.5V
XT Mode
0
100
200
300
400
500
600
700
800
900
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IDD (μA)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
4 MHz
1 MHz
PIC12F683
DS41211D-page 140 © 2007 Microchip Technology Inc.
FIGURE 16-6: MAX IMU M IDD vs. VDD OVER FOSC (XT MODE)
FIGURE 16-7: TYPICAL IDD vs. VDD OVER FOSC (EXTRC MODE)
XT Mode
0
200
400
600
800
1,000
1,200
1,400
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IDD (μA)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
4 MHz
1 MHz
EXTRC Mode
0
100
200
300
400
500
600
700
800
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IDD (μA)
1 MHz
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
4 MHz
© 2007 Microchip Technology Inc. DS41211D-page 141
PIC12F683
FIGURE 16-8: MAX IMU M IDD vs. VDD (EXTRC MODE)
FIGURE 16-9: IDD vs. VDD OVER FOSC (LFINTOSC MODE, 31 kHz)
EXTRC Mode
0
200
400
600
800
1,000
1,200
1,400
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IDD (μA)
Typical: Statistical Mean @25°C
Maximum: Mea n (Worst-c ase Tem p) + 3σ
(-40°C to 125°C)
4 MHz
1 MHz
LFINTOSC Mode, 31KHZ
Typical
Maximum
0
10
20
30
40
50
60
70
80
VDD (V)
IDD (μA)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
PIC12F683
DS41211D-page 142 © 2007 Microchip Technology Inc.
FIGURE 16-10 : IDD vs. VDD (LP MODE)
FIGURE 16-11: TYPICAL IDD vs. FOSC OVER VDD (HFINTOSC MODE)
LP Mode
0
10
20
30
40
50
60
70
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IDD (μA)
Typical: Statistical Mean @25°C
Maximum: Mea n (Worst-c ase Tem p) + 3σ
(-40°C to 125°C)
32 kHz Maximum
32 kHz Typical
HFINTOSC
2.0V
3.0V
4.0V
5.0V
5.5V
0
200
400
600
800
1,000
1,200
1,400
1,600
125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz
FOSC
IDD (μA)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
© 2007 Microchip Technology Inc. DS41211D-page 143
PIC12F683
FIGURE 16-12 : MAXIMUM IDD vs. FOSC OVER VDD (HFINTOSC MODE)
FIGURE 16-13: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
HFINTOSC
2.0V
3.0V
4.0V
5.0V
5.5V
0
200
400
600
800
1,000
1,200
1,400
1,600
1,800
2,000
125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz
FOSC
IDD (μA)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
Typical
(Sleep Mode all Peripherals Disabled)
0.0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (μA)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst -case Temp) + 3σ
(-40°C to 125°C)
PIC12F683
DS41211D-page 144 © 2007 Microchip Technology Inc.
FIGURE 16-14 : MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
FIGURE 16-15 : COMPARATOR IPD vs. VDD (BOTH COMPARATORS ENABLED)
Maximum
(Sleep Mode all Peripherals Disabled)
Max. 125°C
Max. 85°C
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (μA)
Maximum: Mean + 3σ
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
0
20
40
60
80
100
120
140
160
180
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (μA)
Maximum
Typical
Typical: Statistical Mean @25°C
Maximum: Mean (Wors t-c ase Tem p) + 3σ
(-40°C to 125°C)
© 2007 Microchip Technology Inc. DS41211D-page 145
PIC12F683
FIGURE 16-16 : BOR IPD vs. VDD OVER TEMP ERATURE
FIGURE 16-17: TYPICAL WDT IPD vs. VDD OVER TEMPERATURE
0
20
40
60
80
100
120
140
160
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (μA)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
Maximum
Typical
Typical
0.0
0.5
1.0
1.5
2.0
2.5
3.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (μA)
Typical: Statistical Mean @25°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
PIC12F683
DS41211D-page 146 © 2007 Microchip Technology Inc.
FIGURE 16-18: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE
FIGURE 16-19 : WDT PERIOD vs. VDD OVER TEMPERATURE
Maximum
Max. 125°C
Max. 85°C
0.0
5.0
10.0
15.0
20.0
25.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (μA)
Maximum: Mean (Wors t-case Tem p) + 3σ
(-40°C to 125°C)
Minimum
Typical
10
12
14
16
18
20
22
24
26
28
30
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Time (ms)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C) Max. (125°C)
Max. (85°C)
© 2007 Microchip Technology Inc. DS41211D-page 147
PIC12F683
FIGURE 16-20: WDT PERIOD vs. TEMPERATURE OVER VDD (5.0V)
FIGURE 16-21 : CVREF IPD vs. VDD OVER TEMPERATURE (HIGH RANGE)
Vdd = 5V
10
12
14
16
18
20
22
24
26
28
30
-40°C 25°C 85°C 125°C
Temperature (°C)
Time (ms)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
Maximum
Typical
Minimum
High Range
Typical
Max. 85°C
0
20
40
60
80
100
120
140
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (μA)
Max. 125°C
Typical: Statistical Mean @25°C
Maximum: Me an (Wors t-case Te mp) + 3σ
(-40°C to 125°C)
PIC12F683
DS41211D-page 148 © 2007 Microchip Technology Inc.
FIGURE 16-22 : CVREF IPD vs. VDD OVER TEMPERATURE (LOW RANGE)
FIGURE 16-23 : VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V )
Typical
Max. 85°C
0
20
40
60
80
100
120
140
160
180
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (μA)
Max. 125°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
(VDD = 3V, -40×C TO 125×C)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
IOL (m A)
VOL (V)
Max. 85°C
Max. 125°C
Typical 25°C
Min. -40°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst -cas e Tem p) + 3σ
(-40°C to 125°C)
© 2007 Microchip Technology Inc. DS41211D-page 149
PIC12F683
FIGURE 16-24 : VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V )
FIGURE 16-25 : VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V)
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
IOL (mA)
VOL (V)
Typical: Statistical Mean @25×C
Maximum: Means + 3 (-40×C to 125×C)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
Max. 85°C
Typ. 25°C
Min. -40°C
Max. 125°C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-4.0-3.5-3.0-2.5-2.0-1.5-1.0-0.50.0 IOH (mA)
VOH (V)
Typ. 25°C
Max. -40°C
Min. 125°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst -cas e Tem p) + 3σ
(-40°C to 125°C)
PIC12F683
DS41211D-page 150 © 2007 Microchip Technology Inc.
FIGURE 16-26 : VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V)
FIGURE 16-27: TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
(VDD = 5V, -40×C TO 125×C)
3.0
3.5
4.0
4.5
5.0
5.5
-5.0-4.5-4.0-3.5-3.0-2.5-2.0-1.5-1.0-0.50.0 IOH (mA)
VOH (V)
Max. -40°C
Typ. 25°C
Min. 125°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
(TTL Input, -40×C TO 125×C)
0.5
0.7
0.9
1.1
1.3
1.5
1.7
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
VIN (V)
Typ. 25°C
Max. -40°C
Min. 125°C
Typical: Statistical Mean @25°C
Maximum: Mean (Wors t-c ase Tem p) + 3σ
(-40°C to 125°C)
© 2007 Microchip Technology Inc. DS41211D-page 151
PIC12F683
FIGURE 16-28: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMP ERATURE
FIGURE 16-29 : T1OSC IPD vs. VDD OVER TEMPERATURE (32 kHz)
(ST Input, -40×C TO 125×C)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
VIN (V)
VIH Max. 125°C
VIH Min. -40°C
VIL Min. 125°C
VIL Max. -40°C
Typical: Statistical Mean @25°C
Maximum: Mean (Wors t-case Tem p) + 3σ
(-40°C to 125°C)
Typ. 25°C
Max. 85°C
Max. 125°C
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
40.0
45.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (mA)
Maximum: Mean + 3 (-40×C to 125×C)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
PIC12F683
DS41211D-page 152 © 2007 Microchip Technology Inc.
FIGURE 16-30: COMPARATOR RESPONSE TIME (RISING EDGE)
FIGURE 16-31: COMPARATOR RESPONSE TIME (FALLING EDGE)
531 806
0
100
200
300
400
500
600
700
800
900
1000
2.0 2.5 4.0 5.5
VDD (V)
Response Time (nS)
Max. 85°C
Typ. 25°C
Min. -40°C
Max. 125°C
Note:
V- input = Transition from VCM + 100MV to VCM - 20MV
V+ input = VCM
VCM = VDD - 1.5V)/2
0
100
200
300
400
500
600
700
800
900
1000
2.0 2.5 4.0 5.5
VDD (V)
Response Time (nS)
Max. 85°C
Typ. 25°C
Min. -40°C
Max. 125°C
Not e :
V- input = Transition from VCM - 100MV to VCM + 20MV
V+ input = VCM
VCM = VDD - 1.5V)/2
© 2007 Microchip Technology Inc. DS41211D-page 153
PIC12F683
FIGURE 16-32: LFINTOSC FREQUENCY vs. VDD OVER TEMPERATURE (31 kHz)
FIGURE 16-33: ADC CLOCK PERIOD vs. VDD OVER TEMPERATURE
LFINTOSC 31Khz
0
5,000
10,000
15,000
20,000
25,000
30,000
35,000
40,000
45,000
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Frequency (Hz)
Max. -40°C
Typ. 25°C
Min. 85°C
Min. 125°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
0
2
4
6
8
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Time (μs)
25°C
85°C
125°C
-40°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
PIC12F683
DS41211D-page 154 © 2007 Microchip Technology Inc.
FIGURE 16-34: TYPICAL HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
FIGURE 16-35: MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
0
2
4
6
8
10
12
14
16
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Time (μs)
85°C
25°C
-40°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
-40C to +85C
0
5
10
15
20
25
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Time (μs)
-40°C
85°C
25°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
© 2007 Microchip Technology Inc. DS41211D-page 155
PIC12F683
FIGURE 16-36: MINIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
FIGURE 16-37: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (25°C)
-40C to +85C
0
1
2
3
4
5
6
7
8
9
10
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Time (μs)
-40°C
25°C
85°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
-5
-4
-3
-2
-1
0
1
2
3
4
5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Cha n ge f r o m C a librat i on (%)
PIC12F683
DS41211D-page 156 © 2007 Microchip Technology Inc.
FIGURE 16-38: TYPICAL HFINTOSC FREQUENCY CHANGE OVER DEVICE VDD (85°C)
FIGURE 16-39: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (125°C)
-5
-4
-3
-2
-1
0
1
2
3
4
5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Change from Calibration (%)
-5
-4
-3
-2
-1
0
1
2
3
4
5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Change from Calibr a tion (%)
© 2007 Microchip Technology Inc. DS41211D-page 157
PIC12F683
FIGURE 16-40: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (-40°C)
-5
-4
-3
-2
-1
0
1
2
3
4
5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Change from Calibr a tion (%)
PIC12F683
DS41211D-page 158 © 2007 Microchip Technology Inc.
NOTES:
© 2007 Microchip Technology Inc. DS41211D-page 159
PIC12F683
17.0 PACKAGING INFORMATION
17.1 Package Marking Information
*Standard PIC® device marking consists of Microchip part number, year code, week code and traceability
code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip
Sales Office. For QTP devices, any special marking adders are included in QTP price.
XXXXXNNN
8-Lead PDIP
XXXXXXXX
YYWW I/P 017
Example
12F683
0415
8-Lead SOIC (.150”)
XXXXXXXX
XXXXYYWW
NNN
Example
12F683
I/SN0415
017
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designat or ( )
can be found on the outer packaging for this package.
Note: In the even t the full M icrochip p art numb er cann ot be marked o n one lin e, it wil l
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
XXXXXX
8-Lead DFN (4x4x0.9 mm)
XXXXXX
YYWW
NNN
12F683
Example
I/MD
0415
017
XXXXXXX
8-Lead DFN-S (6x5 mm)
XXXXXXX
XXYYWW
NNN
12F683
Example
I/MF
0415
017
3
e
3
e
3
e
3
e
PIC12F683
DS41211D-page 160 © 2007 Microchip Technology Inc.
17.2 Package Details
The following sections give the technical details of the packages.
8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]
Notes:
1. Pin 1 visual index feature may vary, but must be located with the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e .100 BSC
Top to Seating Plane A .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB .430
N
E1
NOTE 1
D
12
3
A
A1
A2
L
b1
b
e
E
eB
c
Microchip Technology Drawing C04-018
B
© 2007 Microchip Technology Inc. DS41211D-page 161
PIC12F683
8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC]
N
otes:
1
. Pin 1 visual index feature may vary, but must be located within the hatched area.
2
. § Significant Characteristic.
3
. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4
. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for inform ation purposes only.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 1.27 BSC
Overall Height A 1.75
Molded Package Thickness A2 1.25
Standoff §A1 0.10 0.25
Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 4.90 BSC
Chamfer (optional) h 0.25 0.50
Foot Length L 0.40 1.27
Footprint L1 1.04 REF
Foot Angle φ
Lead Thickness c 0.17 0.25
Lead Width b 0.31 0.51
Mold Draft Angle Top α 15°
Mold Draft Angle Bottom β 15°
D
N
e
E
E1
NOTE 1
12 3
b
A
A1
A2
L
L1
c
h
h
φ
β
α
Microchip Technology Drawing C04-057
B
PIC12F683
DS41211D-page 162 © 2007 Microchip Technology Inc.
8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN]
N
otes:
1
. Pin 1 visual index feature may vary, but must be located within the hatched area.
2
. Package may have one or more exposed tie bars at ends.
3
. Package is saw singulated.
4
. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for inform ation purposes only.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 0.80 BSC
Overall Height A 0.80 0 .90 1.00
Standoff A1 0.00 0.02 0.05
Contact Thickness A3 0.20 REF
Overall Length D 4.00 BSC
Exposed Pad Width E2 0.00 2.20 2.80
Overall Width E 4.00 BSC
Exposed Pad Length D2 0.00 3 .00 3.60
Contact Width b 0.25 0.30 0.35
Contact Length L 0.30 0.55 0.65
Contact-to-Exposed Pad K 0.20
D
N
E
NOTE 1
12
A3
A
A1
NOTE 2
NOTE 1
D2
1
2
E2
L
N
e
b
K
EXPOSED
PAD
TOP VIEW BOTTOM VIEW
Microchip Technology Drawing C04-131
C
© 2007 Microchip Technology Inc. DS41211D-page 163
PIC12F683
8-Lead Plastic Dual Flat, No Lead Package (MF) – 6x5 mm Body [DFN-S]
P
UNCH SINGULATED
N
otes:
1
. Pin 1 visual index feature may vary, but must be located within the hatched area.
2
. Package may have one or more exposed tie bars at ends.
3
. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for inform ation purposes only.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 1.27 BSC
Overall Height A 0.85 1.00
Molded Package Thickness A2 0.65 0.80
Standoff A1 0.00 0.01 0.05
Base Thickness A3 0.20 REF
Overall Length D 4.92 BSC
Molded Package Length D1 4.67 BSC
Exposed Pad Length D2 3.85 4 .00 4.15
Overall Width E 5.99 BSC
Molded Package Width E1 5.74 BSC
Exposed Pad Width E2 2.16 2.31 2.46
Contact Width b 0.35 0.40 0.47
Contact Length L 0.50 0.60 0.75
Contact-to-Exposed Pad K 0.20
Model Draft Angle Top φ 12°
φ
NOTE 2
A3
A2
A1
A
NOTE 1
NOTE 1
EXPOSED
PAD
BOTTOM VIEW
12
D2
21
E2
K
L
N
e
b
E
E1
D
D1
N
TOP VIEW
Microchip Technology Drawing C04-113
B
PIC12F683
DS41211D-page 164 © 2007 Microchip Technology Inc.
NOTES:
© 2007 Microchip Technology Inc. DS41211D-page 165
PIC12F683
APPENDIX A: DATA SHEET
REVISION HISTORY
Revision A
This is a new data sheet.
Revision B
Rewr ites of the Oscillat or and Sp ecial Fe atures of the
CPU sections. General corrections to Figures and
formatting.
Revision C
Revisions throughout document. Incorporated Golden
Chapters.
Revision D
Replaced Package Drawings; Revised Product ID
Section (SN packa ge to 3.90 mm ); Replac ed PICmic ro
with PIC; Replaced Dev Tool Section.
APPENDIX B: MIGRATING FROM
OTHER PIC®
DEVICES
This discusses some of the issues in migrating from
other PIC devices to the PIC12F683 device.
B.1 PIC16F676 to PIC12F683
TABLE B-1: FEATURE COMPARISON
Feature PIC16F676 PIC12F683
Max Operating
Speed 20 MHz 20 MHz
Max Program
Memory (Words) 1024 2048
SRAM (bytes) 64 128
A/D Resolution 10-bit 10-bit
Data EEPROM
(Bytes) 128 256
Timers (8/16-bit) 1/1 2/1
Oscillator Modes 8 8
Brown-out Reset Y Y
Internal Pull -up s RA0/1/2/4/5 GP0/1/2/4/ 5,
MCLR
Interrupt-on-change RA0/1/2/3/4/5 GP0/1/2/3/4/5
Comparator 1 1
ECCP N N
Ultra Low-Power
Wake-Up NY
Extended WDT N Y
Software Control
Option of WDT/BOR NY
INTO SC
Frequencies 4MHz 32kHz-
8MHz
Clock Switch in g N Y
Note: This device has been designed to perform
to the parameters of its data sheet. It has
been tested to an electrical specification
designed to determine its conformance
with these parameters. Due to process
differences in the manufacture of this
device, this device may have different
performan ce c harac teristi cs than it s ea rlier
version. These differences may cause this
device to perform differently in your
application than the earlier version of this
device.
PIC12F683
DS41211D-page 166 © 2007 Microchip Technology Inc.
NOTES:
© 2007 Microchip Technology Inc. DS41211D-page 167
PIC12F683
INDEX
A
A/D Specifications....................................................133, 134
Absolute Maximum Ratings..............................................115
AC Characteristics
Industrial and Extended............................................125
Load Conditions............................... .. .. .. .. .. .. ....... .. .. ..124
ADC ....................................................................................61
Acquisition Requirements ...........................................67
Associ a te d registers................ ............................ ........69
Block Diag ram............. ........................... .....................61
Calculating Acquisition Time.......................................67
Channel Selection.............................. .... .. .... ....... .. .... ..61
Configuration...............................................................61
Configuring Interrupt...................................................64
Conversi o n Clo ck...... .............. ..................... ...............62
Conversion Procedure ............................................ ....64
GPIO Configuration .....................................................61
Internal Sampling Switch (RSS) IMPEDANCE ................67
Interrupts.....................................................................63
Operation....................................................................63
Operation During Sleep ..............................................64
Reference Voltage (VREF)...........................................62
Result For matting............ ............... .............. ...............63
Source Impedance............................. .... .... ........... .... ..67
Special Event Trigger..................................................64
Starting an A/D Conversion ........................................63
ADCON0 Register ...............................................................65
ADRESH Register (ADFM = 0)...........................................66
ADRESH Register (ADFM = 1)...........................................66
ADRESL Register (ADFM = 0)............................................66
ADRESL Register (ADFM = 1)............................................66
Analog Input Connection Considerations............................52
Analog-to-Digital Converter. See ADC
ANSEL Register..................................................................33
Assembler
MPASM Assembler...................................................112
B
Block Diagrams
(CCP) Capture Mode Operation .................................76
ADC ............................................................................61
ADC Transfer Function...............................................68
Analog Input Model...............................................52, 68
CCP PWM...................................................................78
Clock Source...............................................................19
Comparator.................................................................51
Compare.....................................................................77
Crystal Operation........................................................22
External RC Mode.......................................................23
Fail-Safe Clock Monitor (FSCM).................................29
GP1 Pin.......................................................................37
GP2 Pin.......................................................................37
GP3 Pin.......................................................................38
GP4 Pin.......................................................................38
GP5 Pin.......................................................................39
In-Circuit Serial Programming Connections..............100
Inter rupt Logic............. ..................... ...........................93
MCLR Circuit................... ..................... ..................... ..86
On-Chip Rese t Circuit...................... ............... ............85
PIC12F683....................................................................5
Resonator Operation ...................................................22
Timer1.........................................................................44
Timer2 ........................................................................ 49
TMR0/WDT Prescaler ................................................ 41
Watchdog Timer (WDT).............................................. 96
Brown-o u t Re set (BOR)............... .............. ..................... .... 87
Associated.................................................................. 88
Calibration .................................................................. 87
Specifications ........................................................... 129
Timing and Characteristics................ .. ......... .. .... .. .... 128
C
C Compilers
MPLAB C18........ ........................... ..................... ...... 112
MPLAB C30........ ........................... ..................... ...... 112
Calibration Bits.................................................................... 85
Capture Module. See Capture/Compare /PWM (CCP)
Capture/Compare/P WM (CCP).......................... ................ 75
Associated registers w/ Capture, Compare
and Timer1 ......................................................... 81
Associated registers w/ PWM and Timer2.................. 81
Capture Mod e............. ..................... ..................... ...... 76
CCPx Pin Configu ration............... ............... ................ 76
Compare Mode....... ..................... ..................... .......... 77
CCPx Pin Configu ration......... ..................... ........ 77
Software Interrupt Mode............................... 76, 77
Special Event Trigger......................................... 77
Timer1 Mode Selection................................. 76, 77
Prescaler .................................................................... 76
PWM Mode................... ............................ .................. 78
Duty Cycle........ ..................... ..................... ........ 79
Effects of Reset............. ..................... ................ 80
Example PWM Frequencies and
Resolutions, 20 MHZ.................................. 79
Example PWM Frequencies and
Resolutions, 8 MHz.................................... 79
Operation in Sleep Mode............................ .... .. .. 80
Setup for Operation............................................ 80
System Clock Frequency Changes.................... 80
PWM Period ........................................ ....................... 79
Setup for PWM Operation .......................................... 80
Timer Resources........................................................ 75
CCP. See Capture/Compare/PWM (CCP)
CCP1CON Regis te r.............. ............... ..................... .......... 75
Clock Sources
External Modes........................................................... 21
EC ...................................................................... 21
HS ...................................................................... 22
LP....................................................................... 22
OST.................................................................... 21
RC ...................................................................... 23
XT....................................................................... 22
Internal Modes............................................................ 23
Frequency Selection......................................... .. 25
HFINTOSC......................................................... 23
INTOSC.............................................................. 23
INTOSCIO.......................................................... 23
LFINTOSC.......................................................... 25
Clock Switching.................................................................. 27
Code Examples
A/D Conver sion ............................. ..................... ........ 64
Assigni n g Prescale r to Timer0.................................... 42
Assigni n g Prescale r to WDT..................................... .. 42
Changing Between Capture Prescalers ..................... 76
Data EEPRO M Read...... ............... ........................... .. 73
Data EEPRO M Write.............................. .................... 73
PIC12F683
DS41211D-page 168 © 2007 Microchip Technology Inc.
Indirect Addressing .....................................................18
Initializing GPIO ..........................................................31
Saving STATUS and W Registers in RAM .................95
Ultra L o w - Pow e r Wake - u p In i tiali z atio n ...... .. ......... .....3 5
Write Verify .................................................................73
Code Protection ..................................................................99
Comparator.........................................................................51
C2OUT as T1 Gate.... ..................... ..................... .......57
Configurations.............................................................53
I/O Operating Modes....................... ..... .... .. .. .. .... .. .......53
Interrupts.....................................................................55
Operation ..............................................................51, 54
Operation During Sleep ..............................................56
Response Time.................................................. .........54
Synchronizing COUT w/Timer1 ..................................57
Comparator Module
Associ a te d registers.................... ............................ ....59
Comparator Voltage Reference (CVREF)
Response Time.................................................. .........54
Comparator Voltage Reference (CVREF)............................58
Effects of a Reset........................................................56
Specifications............................................................132
Comparators
C2OUT as T1 Gate.... ............... ..................... .............45
Effects of a Reset........................................................56
Specifications............................................................132
Compare Module. See Capture/Compare/ PWM (CCP)
CONFIG Regi ster.......................... ..................... .................84
Configuration Bits................................................................83
CPU Features .....................................................................83
Customer Change Notification Service .............................171
Custome r Notification Ser vice.................... ..................... ..171
Customer Support.............................................. .... .... .......171
D
Data EEPRO M Memor y
Associ a te d Re g i sters ........ ........................... ...............74
Code Protection ....................................................71, 74
Data Memory Organization.. .................................................7
Map of the PIC12F683..................................................8
DC and AC Characteristics
Graphs and Tables ...................................................137
DC Characteristics
Extended and Industrial............................................121
Industrial and Extended............................................117
Development Support .......................................................111
Device Overview...................................................................5
E
EEADR Register .................................................................71
EECON1 Regist e r........ ............... ..................... ...................72
EECON2 Regist e r........ ............... ..................... ...................72
EEDAT Regi ster.......................... ..................... ...................71
EEPROM Data Memory
Avoiding Spurious Write..............................................74
Reading.......................................................................73
Write Verify .................................................................73
Writing.........................................................................73
Effects of Reset
PWM mode............ ............................ ..................... ....80
Electrical Specifications ....................................................115
Enhanced Capture/Compare/PWM (ECCP)
Specifications............................................................131
Errata ....................................................................................3
F
Fail-Safe Clock Monitor ...................................................... 29
Fail-Safe Condition Clearing....................................... 29
Fail-Safe Detection..................................................... 29
Fail-Safe Operation..................................................... 29
Reset or Wak e-u p from Sleep ......... ..................... ...... 29
Firmware Instructions ....................................................... 101
Fuses. See Configuration Bits
G
General Purpose Register File ...................... .... ........... .... .... 8
GPIO................................................................................... 31
Additional Pin Functions............................................. 32
ANSEL Register ................................................. 32
Interrupt-on-Change ........................................... 32
Ultra Low-Power Wake-up ............................ 32, 35
Weak Pull-up...................................................... 32
Associ a te d Re g i st e rs...... ..................... ....................... 39
GP0 ............................................................................ 36
GP1 ............................................................................ 37
GP2 ............................................................................ 37
GP3 ............................................................................ 38
GP4 ............................................................................ 38
GP5 ............................................................................ 39
Pin Descriptions and Diagrams .................................. 36
Specifications ........................................................... 127
GPIO Regis te r ....... ............... ..................... ......................... 31
I
ID Locations........................................................................ 99
In-Circuit Debugger ........................................................... 100
In-Circuit Serial Programming (ICSP)............................... 100
Indirect Addressing, INDF and FSR Registers ................... 18
Instruction Format.............................................................101
Instruction Set................................................................... 101
ADDLW..................................................................... 103
ADDWF..................................................................... 103
ANDLW..................................................................... 103
ANDWF..................................................................... 103
BCF .......................................................................... 103
BSF........................................................................... 103
BTFSC...................................................................... 103
BTFSS...................................................................... 104
CALL......................................................................... 104
CLRF ........................................................................ 104
CLRW....................................................................... 104
CLRWDT .................................................................. 104
COMF....................................................................... 104
DECF........................................................................ 104
DECFSZ ................................................................... 105
GOTO....................................................................... 105
INCF ......................................................................... 105
INCFSZ..................................................................... 105
IORLW...................................................................... 105
IORWF...................................................................... 105
MOVF ....................................................................... 106
MOVLW.................................................................... 106
MOVWF.................................................................... 106
NOP.......................................................................... 106
RETFIE..................................................................... 107
RETLW..................................................................... 107
RETURN................................................................... 107
RLF........................................................................... 108
RRF .......................................................................... 108
SLEEP...................................................................... 108
© 2007 Microchip Technology Inc. DS41211D-page 169
PIC12F683
SUBLW.....................................................................108
SUBWF.....................................................................109
SWAPF.....................................................................109
XORLW.....................................................................109
XORWF.....................................................................109
INTCON Register................................................................14
Internal Oscillator Block
INTOSC
Specifications............................................126, 127
Internal Sampling Switch (RSS) IMPEDANCE ........................67
Inter n e t Ad d ress............ ........................... .........................171
Interrupts.............................................................................92
ADC ............................................................................64
Associ a te d Re g i sters.......... ..................... ...................94
Comparator.................................................................55
Context Saving............................................................95
Data EEPROM Mem o ry Write ......... ..................... ......72
GP2/INT......................................................................92
GPIO Interrupt-on-change ..........................................93
Interrupt-on-Change....................................................32
Timer0.........................................................................93
TMR1..........................................................................46
INTOSC Specifications .............................. .... ...... .....126, 127
IOC Register.......................................................................34
L
Load Conditions...................... .. .... .. ..... .. .. .... .. .. .. .. ..... .... .. ..124
M
MCLR..................................................................................86
Internal........................................................................86
Memory Organization
Data EEPROM Mem o ry...... ..................... ...................71
Microc h i p In ternet Web Site.... ..................... .....................171
Migra tin g from other PIC De vices...... ..................... ..........165
MPLAB ASM30 Assembler, Linker, Librarian ...................112
MPLAB ICD 2 In-Circuit Debugger ...................................113
MPLAB ICE 2000 High-Perform ance Universal
In-Circuit Emulator....................................................113
MPLAB ICE 4000 High-Perform ance Universal
In-Circuit Emulator....................................................113
MPLAB Integrated Development Environment Software..111
MPLAB PM3 Device Programmer ....................................113
MPLINK Object Linker/MPLIB Object Libraria n............ ....112
O
OPCODE Fiel d Descri p tions... ........ ............... ...................101
OPTION Register..........................................................13, 43
OSCCON Register..............................................................20
Oscillator
Associ a te d registers................ ............................ ..30, 48
Oscillator Module ................................................................19
EC...............................................................................19
HFINTOSC..................................................................19
HS...............................................................................19
INTOSC ......................................................................19
INTOSCIO...................................................................19
LFINTOSC..................................................................19
LP................................................................................19
RC...............................................................................19
RCIO...........................................................................19
XT ...............................................................................19
Oscillator Parameters .......................................................126
Oscillator Specifications....................................................125
Oscillator Start-up Timer (OST)
Specifications............................................................129
Oscillator Switching
Fail-Safe Clock Monitor.............................................. 29
Two-Spe ed Clock Start-up ......................... ................ 27
OSCTUNE Regis te r.............. ............... ..................... .......... 24
P
Packaging......................................................................... 159
Details....................................................................... 160
Marking..................................................................... 159
PCL and PCLATH............................................................... 18
Computed GOTO ....................................................... 18
Stack........................................................................... 18
PCON Register............................................................. 17, 88
PICSTART Plus Development Programmer..................... 114
PIE1 Register ..................................................................... 15
Pin Diagram.......................................................................... 2
Pinout Descriptions
PIC12F683 ................................................................... 6
PIR1 Register ..................................................................... 16
Power-Down Mode (Sleep)................................................. 98
Power-On Re set (POR)................... ............... .................... 86
Power-up Timer (PWRT).................................................... 86
Specifications ........................................................... 129
Precisio n In ternal Osci lla to r Pa rameters.............. ............ 127
Prescaler
Shared WDT/Timer0....... ..................... ..................... .. 42
Switching Prescaler Assignment................................ 42
Program Mem ory O rganization. .......................................... .. 7
Map and Stack for the PIC12F683............................... 7
Programming, Device Instructions.................................... 101
R
Reader Response............................................................. 172
Read-Modify-Write Operations......................................... 101
Registers
ADCON0 (ADC Control 0)...................... .............. ...... 65
ADRESH (ADC Result High) wi th ADFM = 0)............ 66
ADRESH (ADC Result High) wi th ADFM = 1)............ 66
ADRESL (ADC Result Low) with ADFM = 0).............. 66
ADRESL (ADC Result Low) with ADFM = 1).............. 66
ANSEL (Analog Select).............................................. 33
CCP1CON (CCP1 Cont rol) ............... ............... .......... 75
CMCON0 (Comparator Control) Register................... 56
CMCON1 (Comparator Control) Register................... 57
CONFIG (Configuration Word)................................... 84
EEADR (EEPROM Address)...................................... 71
EECON1 (EEPROM Control 1 )................ ........ .......... 72
EECON2 (EEPROM Control 2 )................ ........ .......... 72
EEDAT (EEPROM Data)............................................ 71
GPIO........................................................................... 31
INTCON (Interrupt Control) ........................................ 14
IOC (Interrupt-on-Change GPIO) ............................... 34
OPTION_R EG (OPTION)..................................... 13, 43
OSCCON (Oscillator Control)..................................... 20
OSCTUNE (Oscillator Tuning)..... ............... .............. .. 24
PCON (Power Control Register)................................. 17
PCON (Power Control)............................................... 88
PIE1 (Peripheral Interrupt Enable 1) .......................... 15
PIR1 (Peripheral Interrupt Register 1)........................ 16
Reset Value s............ ..................... ........................... .. 90
Reset Values (Special Registers)............................... 91
STATUS ..................................................................... 12
T1CON ....................................................................... 47
T2CON ....................................................................... 50
TRISIO (Tri-State GPIO) ............................................ 32
VRCON (Voltage Reference Control)......................... 58
PIC12F683
DS41211D-page 170 © 2007 Microchip Technology Inc.
WDTCON (Watchdog Tim er Contro l)..........................97
WPU (Weak Pull-Up GPIO) ........................................34
Resets.................................................................................85
Brown-out Reset (BOR)..............................................85
MCLR Reset, Normal Operation.............. ............... ....85
MCLR Reset, Slee p........................ ............................85
Power-on Res e t (POR)................... ..................... .......85
WDT Reset, Normal Op eration..... ......... .............. .......85
WDT Reset, Sleep ........ .............. ............................ ....85
Revision History................................................................165
S
Sleep
Power-Down Mode .....................................................98
Wake-up......................................................................98
Wake-up Using Interrupts...........................................98
Softwa re Simulator (MP L AB SIM)..... ..................... ...........112
Special Event Trigger..........................................................64
Special Function Registers ...................................................8
STATUS Regi ster....... ..................... ..................... ...............12
T
T1CON Regis te r... .............. ..................... ............... .............47
T2CON Regis te r... .............. ..................... ............... .............50
Thermal Considerations....................................................123
Time-out Sequence.............................................. .... .. .........88
Timer0.................................................................................41
Associ a te d Re g i sters .............. ..................... ...............43
External Clock.............................................................42
Interrupt .................................................................13, 43
Operation ..............................................................41, 44
Specifications............................................................130
T0CKI..........................................................................42
Timer1.................................................................................44
Associ a te d registers.................... ............................ ....48
Asynchronous Counter Mode .....................................45
Reading and Writing ..... .. .. .. .. .. ..... .. .. .. .. .. .. .. ....... ..45
Interrupt.......................................................................46
Modes of Operation .............. .. .... .. ......... .. .... .. .... .. .......44
Operation During Sleep ..............................................46
Oscillator.....................................................................45
Prescaler.....................................................................45
Specifications............................................................130
Timer1 Gate
Inverting Gate .....................................................45
Selectin g So u rce....... .............. ..................... .45, 57
Sync h ro n i z i n g C O U T w/Timer1 .. .. ...... ...... ..... .....5 7
TMR1H Register.........................................................44
TMR1L Register..........................................................44
Timer2
Associ a te d registers.................... ............................ ....50
Timers
Timer1
T1CON................................................................47
Timer2
T2CON................................................................50
Timing Diagrams
A/D Conversion............................. ..................... .......135
A/D Conversion (Sleep Mode) ..................................135
Brown-out Reset (BOR)............................................128
Brown-out Reset Situations ........................................87
CLKOUT and I/O.......................................................127
Clock Timing.............................................................125
Comparator Output..................... ..................... ...........51
Enhanced Capture/Compare/PWM (ECCP).............131
Fail-Safe Clock Monitor (FSCM).................................30
INT Pin Interrupt ......................................................... 94
Inte rn a l Oscillato r Sw i t c h Ti ming ...... .. ...... ..... ...... ...... . 26
Reset, WDT, OST and Power-up Timer................... 128
Time-out Sequence on Power-up (Delayed MCLR)...89
Time-out Sequence on Power-up (MCLR with VDD)..89
Timer0 and Timer1 External Clock........................... 130
Timer1 Incrementing Edge......................................... 46
Two Speed Start-up................ ..... .. .. .. .. .... .. .. ..... .. .... .. .. 28
Wake-up from Sleep Through Interrupt...................... 99
Timing Pa rameter Symb o l o g y ........ ............................ ...... 124
TRISIO Register ................................................................. 32
Two-Spe ed Clock Start-up Mod e....... .............. ................... 27
U
Ultra Low-Power Wake-up............................................ 32, 35
V
Voltage Reference. See Comparator Voltage
Reference (CVREF)
Voltage References
Associ a te d registers..... ..................... ......................... 59
VREF. SEE ADC Reference Voltage
W
Wake-up Using Interrupts................................................... 98
Watchdog Timer (WDT).................................................. .... 96
Associ a te d Re g i sters.... ............... ..................... .......... 97
Clock Source .............................................................. 96
Modes......................................................................... 96
Period ......................................................................... 96
Specifications ........................................................... 129
WDTCON Register......... ..................... ..................... .......... 97
WPU Register..................................................................... 34
WWW Addres s ........ ............................ ........................... ..171
WWW, On-Line Support....................................................... 3
© 2007 Microchip Technology Inc. DS41211D-page 171
PIC12F683
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PIC12F683
DS41211D-page 172 © 2007 Microchip Technology Inc.
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DS41211DPIC12F683
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© 2007 Microchip Technology Inc. DS41211D-page 173
PIC12F683
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device: PIC12F683(1), PIC12F683T (2)
VDD range 2.0V to 5.5V
Temperature
Range: I= -40°C to +85°C(Industrial)
E= -40°C to +125°C (Extended)
Package: P = Plastic DIP
MD = Dual-Flat, No Leads (DFN-S, 4x4x0.9 mm)
MF = Dual-Flat, No Leads (DFN-S, 6x5 mm)
SN = 8-lead Small Outline (3.90 mm)
Pattern: 3-digit Pattern Code for QTP (blank otherwise)
Examples:
a) PIC12F683-E/P 301 = Extended Temp., PDIP
package, 20 MHz, QTP patter n #301
b) PIC12F683-I/SN = Industrial Temp., SOIC
package, 20 MHz
Note 1: F = Standard Voltage Range
LF = Wide Voltage Range
2: T = in tape and reel PLCC, and TQFP
packages only.
DS41211D-page 174 © 2007 Microchip Technology Inc.
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12/08/06