‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Features
Preliminary‡
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152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN 1©2008 Micron Technology, Inc. All rights reserved.
NAND Flash and Mobile LPDRAM
152-Ball Package-on-Package (PoP)
Combination Memory (TI OMAP™)
MT29C Family
Current production part numbers: See Table 1 on page 3
Features
•Micron
® NAND Flash and Mobile LPDRAM
components
• RoHS-compliant, “green” package
• Separate NAND Flash and Mobile LPDRAM
interfaces
• S pace-saving package-on-package combination
• Low-voltage operation (1.70–1.95V)
• Industrial temperature range: –40°C to +85°C
NAND Flash-Specific Features
• Organization
–Page size
x8: 2112 bytes (2048 + 64 bytes)
x16: 1056 words (1024 + 32 words)
–Block size: 64 pages (128K + 4K bytes)
Mobile LPDRAM-Specific Features
• No external voltage reference r equired
• No minimum clock rate requirement
• 1.8V LVCMOS-compatible inputs
• Programmable burst lengths
• Partial-array self re fresh (PASR)
• Deep power-down (DPD) mode
• Selectable output drive strength
• STATUS REGISTER READ (SRR) supported1
Figure 1: PoP Block Diagram
Notes: 1. Contact factory for remapped SRR output.
2. CL = CAS (READ) latency.
Options Marking
•LP-DRAM
166 MHz CL32-6
133 MHz CL3 -75
NAND Flash
Device
NAND Flash
Power
NAND Flash
Interface
LP-DRAM Power LP-DRAM Interface
LP-DRAM
Device
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152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN 2©2008 Micron Technology, Inc. All rights reserved.
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Part Numbering Information – 152-Ball PoP
Preliminary
Part Numbering Information – 152-Ball PoP
Micron NAND Flash and LPDRAM devices are available in different configurations and
densities.
Figure 2: 152-Ball Part Number Chart
Note: Not all possible combinations are available. Contact factory for availability.
MT 29C 1G 24M A C J A CG – x IT ES
Micron Technology
Product Family
29C = NAND + LPDRAM MCP
NAND Density
1G = 1Gb
2G = 2Gb
4G = 4Gb
LPDRAM Density
12M = 512Mb
24M = 1024Mb
48M = 2048Mb
Operating Voltage Range
A = 1.8V (1.70–1.95V)
Production Status
Blank = Production
ES = Engineering sample
MS = Mechanical sample
Operating Temperature Range
IT = Industrial (–40° to +85°C)
LPDRAM Self Refresh Current
Blank = Standard
LPDRAM Access Time
–6 166 MHz CL3
–75 133 MHz CL3
Package Codes
CA = 152-ball PoP VFBGA (14 x 14 x 0.9mm)
CG = 152-ball PoP VFBGA (14 x 14 x 1.0mm)
JQ = 152-ball PoP TFBGA (14 x 14 x 1.1mm)
NAND Flash Configuration
Width Density Generation
C x8 1Gb First
D x16 1Gb First
J x8 2Gb Second
K x16 2Gb Second
N x8 4Gb First
P x16 4Gb First
U x8 1Gb Second
V x16 1Gb Second
Chip Count
CE#, CS# Chip Count
A 1, 1 1 NAND, 1 DRAM
B 1, 1 2 NAND, 1 DRAM
C 1, 2 1 NAND, 2 DRAM
D 1, 2 2 NAND, 2 DRAM
LPDRAM Configuration
Type Width Density Generation
J DDR x16 1Gb First
L DDR x32 1Gb First
N DDR x16 512Mb Second
R DDR x32 512Mb Second
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152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN 3©2008 Micron Technology, Inc. All rights reserved.
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Device Marking
Preliminary
Device Marking Due to the size of the package, the Micron-standard part number is not printed on the
top of the device. Instead, an abbrevia ted device mark consisting of a 5-digit alphanu-
meric code is used. The abbreviated device marks are cross-r efe renced to the Micron
part numbers at the FBGA Part Marking Decoder site: www.micron.com/decoder. To
view the location of the ab breviated m ark o n th e de vic e, refer to customer ser vice note
CSN-11, “Product Mark/Label,” at www.micron.com/csn.
Table 1: Produc tion Part Numbers
Part Number NAND Product LPDDR Product Physical Part
Marking
MT29C4G48MAPLCCA-6 IT MT46H32M32LFJG-6 IT MT29F4G16ABCWC-ET JW399
MT29C4G48MAPLCCA-75 IT MT46H32M32LFJG-6 IT MT29F4G16ABCWC-ET JW400
MT29C4G48MAPLCJQ-6 IT MT46H32M32LFJG-6 IT MT29F4G16ABCWC-ET JW297
MT29C4G48MAPLCJQ-75 IT MT46H32M32LFJG-6 IT MT29F4G16ABCWC-ET JW296
MT29C1G12MADRACG-6 IT MT46H16M32LFCM-6 IT MT29F1G16ABBHC-ET JW226
MT29C1G12MADRACG-75 IT MT46H16M32LFCM-6 IT MT29F1G16ABBHC-ET J W227
MT29C2G24MAKLACG-6 IT MT46H32M32LFJG-6 IT MT29F2G16ABDHC-ET JW188
MT29C2G24MAKLACG-75 IT MT46H32M32LFJG-6 IT MT29F2G16ABDHC-ET JW189
MT29C1G12MAURACA-6 IT MT46H16M32LFCM-6 IT MT29F1G08ABCHC-ET JW385
MT29C1G12MAURACA-75 IT MT46H16M32LFCM-6 IT MT29F1G08ABCHC-ET J W384
MT29C1G12MAVRACA-6 IT MT46H16M32LFCM-6 IT MT29F1G16ABCHC-ET JW375
MT29C1G12MAVRACA-75 IT MT46H16M32LFCM-6 IT MT29F1G16ABCHC-ET J W374
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152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN 4©2008 Micron Technology, Inc. All rights reserved.
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
General Description
Preliminary
General Description
Micron package-on-package (PoP) pr oducts combine NAND Flash and Mobile LPDRAM
devices in a single MCP. These products target mobile applications with low-power,
high-performance, and minim a l package-footprint design requirements. The NAND
Flash and Mobile LPDRAM devices are also members of the Micron disc rete memo ry
products portfolio.
The NAND Flas h and M obile LPDRAM devices ar e packaged with separ ate interfaces (no
shared address, control, data, or power balls). This bus architecture supports an opti-
mized inte rface to processors with separate NAND Flash and Mobile LPDRAM buses.
The NAND Flash and Mobile LPDRAM devices have separate core power conne ctions
and share a common ground (i.e., VSS is tied together on the two devices).
The bus architectur e of this device also supports separ a te NAND Flash and Mobile
LPDRAM functionality without concern for device interaction. Operational characteris-
tics for the NAND Flash and Mobile LPDRAM devices are found in the standard Micron
data sheets for each of th e di screte devices.
Fo r de vi ce spe cif i cat ions and complete Micron NAND Flash features documentation,
please refer to the component data sheet at www.micron.com/products/nand, or con-
tact your local Micron sales office.
For device specifications and complete Mobile LPDRAM features documentation,
please r efer to the component data sheet at www.micron.com/products/mobiledram, or
contact your local Micron sales office.
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152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN 5©2008 Micron Technology, Inc. All rights reserved.
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Ball Assignments and Descriptions
Preliminary
Ball Assignments and Descriptions
Figure 3: 152-Ball VFBGA Ball Assignments (NAND x8; LPDDR x16)
Note: Contact factory for availability of x16 LPDDR configuration.
1
NC
NC
V
SSQ
NC
NC
V
SSQ
NC
NC
V
DD
WE#
NC
NC
NC
NC
NC
NC
I/O1
I/O3
CE1#
NC
NC
1
2
NC
NC
NC
NC
NC
V
DDQ
NC
V
SS
NC
NC
RE#
V
SS
V
CC
NC
V
SS
V
CC
I/O0
I/O2
LOCK
NC
NC
2
3
V
DDQ
NC
I/O6
I/O4
3
4
LDM
NC
I/O7
I/O5
4
5
DQ5
V
DDQ
WP#
NC
5
6
DQ7
DQ1
V
SS
V
CC
6
7
V
SSQ
DQ6
V
CC
V
SS
7
8
DQ2
LDQS
NC
CE0#
8
9
DQ4
DQ3
NC
ALE
9
10
DQ8
DQ0
R/B#
CLE
10
11
DQ11
DQ9
V
SS
V
DD
11
12
CK
DQ10
A14
TQ
12
13
V
SS
CK#
CKE1
V
SS
13
14
UDM
V
SSQ
V
DD
V
DDQ
14
15
V
DDQ
UDQS
CKE0
A13
15
16
DQ13
V
DD
A10
V
SSQ
16
17
DQ12
DQ15
V
SS
V
DD
17
18
NC
DQ14
WE#
BA0
18
19
NC
NC
V
SSQ
V
DDQ
19
20
NC
NC
NC
NC
NC
V
SSQ
A0
V
SS
A2
A1
V
DDQ
A7
A8
V
SS
A5
CS1#
CAS#
BA1
V
SSQ
NC
NC
20
21
NC
NC
NC
NC
NC
V
DDQ
NC
V
DD
A3
A9
V
SSQ
A6
A11
V
DD
A12
CS0#
A4
RAS#
V
DDQ
NC
NC
21
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
Top View – Ball Down NAND LPDDR Supply Ground
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152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Ball Assignments and Descriptions
Preliminary
Figure 4: 152-Ball VFBGA Ball Assignments (NAND x16; LPDDR x32)
1
NC
NC
V
SSQ
DQ3
DQ0
V
SSQ
DQ4
DM0
V
DD
WE#
NC
I/O13
I/O10
I/O12
I/O8
I/O9
I/O1
I/O3
CE1#
NC
NC
1
2
NC
NC
DQS0
DQ5
DQ1
V
DDQ
DQ2
V
SS
I/O14
I/O15
RE#
V
SS
V
CC
I/O11
V
SS
V
CC
I/O0
I/O2
LOCK
NC
NC
2
3
V
DDQ
DQ6
I/O6
I/O4
3
4
DM1
DQ7
I/O7
I/O5
4
5
DQ13
V
DDQ
WP#
NC
5
6
DQ15
DQ9
V
SS
V
CC
6
7
V
SSQ
DQ14
V
CC
V
SS
7
8
DQ10
DQS1
NC
CE0#
8
9
DQ12
DQ11
NC
ALE
9
10
DQ16
DQ8
R/B#
CLE
10
11
DQ19
DQ17
V
SS
V
DD
11
12
CK
DQ18
RFU
TQ
12
13
V
SS
CK#
CKE1
V
SS
13
14
DM2
V
SSQ
V
DD
V
DDQ
14
15
V
DDQ
DQS2
CKE0
A13
15
16
DQ21
V
DD
A10
V
SSQ
16
17
DQ20
DQ23
V
SS
V
DD
17
18
DM3
DQ22
WE#
BA0
18
19
DQS3
DQ28
V
SSQ
V
DDQ
19
20
NC
NC
DQ24
DQ25
DQ27
V
SSQ
A0
V
SS
A2
A1
V
DDQ
A7
A8
V
SS
A5
CS1#
CAS#
BA1
V
SSQ
NC
NC
20
21
NC
NC
DQ26
DQ29
DQ31
V
DDQ
DQ30
V
DD
A3
A9
V
SSQ
A6
A11
V
DD
A12
CS0#
A4
RAS#
V
DDQ
NC
NC
21
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
Top View
(Ball Down) NAND LP-DRAM Supply Ground
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152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN 7©2008 Micron Technology, Inc. All rights reserved.
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Ball Assignments and Descriptions
Preliminary
Notes: 1. Balls marked RFU may or may not be connected internally. These balls should not be used.
Contact the factory for details.
Table 2: x8/x16 NAND Ball Descriptions
Symbol Type Description
ALE Input Address latch enable: When ALE is HIGH, addresses can be transferred to the on-chip address
register.
CE1#, CE0# Input Chip enable: Gates transfers between the host system and the NAND Flash device.
CLE Input Command latch enable: When CLE is HIGH, commands can be transferred to the on-chip
command register.
LOCK Input When LOCK is HIGH during power-up, the BLOCK LOCK function is enabled. To disable BLOCK
LOCK, connect LOCK to VSS during power-up, or leave it unconnected (internal pull-down).
RE# Input Read enable: Gates information from the NAND device to the host system.
WE# Input Write enable: Gates information from the host system to the NAND device.
WP# Input Write protect: Dri v in g WP# LOW blocks ERASE and PROGRAM operations.
I/O[7:0]
(x8)
I/O[15:0]
(x16)
Input/
output Data inputs/outputs: The bidirectional I/Os transfer addr ess, data, and instruction information.
Data is output only during READ ope rations; at other times the I/Os are inputs.
I/O[15:8] are RFU1 for NAND x8 devices.
R/B# Output Ready/busy: Open-drain, active-LOW output that indicates when an internal operation is in
progress.
VCC Supply VCC: NAND power supply.
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152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN 8©2008 Micron Technology, Inc. All rights reserved.
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Ball Assignments and Descriptions
Preliminary
Notes: 1. Balls marked RFU may or may not be connected internally. These balls should not be used.
Contact the factory for details.
Table 3: x16/x32 LPDDR Ball Descriptions
Symbol Type Description
A[14:0] Input Address inputs: Specifies the row or column address. Also used to load the mode registers. The
maximum LPDDR address is determined by density and configuration. Consult the LPDDR
product data sheet for the maximum address for a given density and configuration. Unused
address pins become RFU.
BA1, BA0 Input Bank address inputs: Specifies one of the 4 banks.
CAS# Input Column select: Specifies the command to execute.
CK, CK# Input CK is the system clock. CK and CK# are differential clock inputs. All address and co ntrol sign als
are sampled and referenced on the crossing of the rising edge of CK with the falling edge of
CK#.
CKE0, CKE1 Input Clock enable:
CKE0 is used for a single LPDDR product.
CKE1 is used for dual LPDDR products.
CS1#, CS0# Input Chip select:
CS0# is used for a single LPDDR product.
CS1# is used for dual LPDDR products and is co nsid ered RFU fo r sing le LPDDR MCPs.
LDM, UDM
(x16)
DM[3:0]
(x32)
Input Data mask: Determines which bytes are written during WRITE operations.
For x16 LPDDR, unused DM balls become RFU.
RAS# Input Row select: Specifies the command to execute.
WE# Input Write en able: Specifies the command to execute.
DQ[15:0]
(x16)
DQ[31:0]
(x32)
Input/
output Data bus: Data inputs/outputs.
DQ[31:16] are RFU for x16 LPDDR devices.
LDQS, UDQS
(x16)
DQS[3:0]
(x32)
Input/
output Data strobe: Coordinates REA D/WRITE transfers of data; one DQS per DQ byte.
For x16 LPDDR, unused DQS balls become RFU.
TQ Output Temperature sensor output: TQ HIGH when LPDDR TJ exceeds 85°C.
VDD Supply VDD: LPDDR power supply.
VDDQ Supply VDDQ: LPDDR I/O power supply.
VSSQ Supply VSSQ: LPDDR I/O ground.
Table 4: Non-Device-Specific Ball Descriptions
Symbol Type Description
VSS Supply VSS: Shared ground.
NC –No connect: Not internally connected.
RFU1–Reserved for future use.
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152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN 9©2008 Micron Technology, Inc. All rights reserved.
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Electrical Specifications
Preliminary
Electrical Specifications
Notes: 1. Supply voltage references either VCC,VDD, or VDDQ.
S t resses greater than thos e listed under “Absolute M a ximum Ratings” may cause perma-
nent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions abo ve those indicate d in the operational secti ons
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended period s may affe ct reliability.
Table 5: Absolute Maximum Ratings
Parameters/Conditions Symbol Min Max Unit
VCC, VDD, VDDQ Supply voltage
relative to VSS
VCC, VDD,
VDDQ
–1.0 2.4 V
Voltage on any pin
relative to VSS
VIN –0.5 2.4 or (supply voltage1 +
0.3V), whichever is less V
Storage temperature range – –55 +150 °C
Table 6: Recommended Operating Conditions
Parameters Symbol Min Typ Max Unit
Supply voltage VCC, VDD 1.70 1.80 1.95 V
I/O supply voltage VDDQ 1.70 1.80 1.95 V
Operating temperature range – –40 – +85 °C
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152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN 10 ©2008 Micron Technology, Inc. All rights reserved.
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Device Diagrams
Preliminary
Device Diagrams
Figure 5: 152-Ball Functional Block Diagram (Single LPDDR)
CE0#
CLE
ALE
RE#
WE#
WP#
LOCK
CS0#
CK
CK#
CKE0
RAS#
CAS#
WE#
Address,
BA0, BA1
VCC
I/O
R/B#
VSS
VDD
VDDQ
DM
DQ
DQS
TQ
VSSQ
NAND Flash
LPDDR
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152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN 11 ©2008 Micron Technology, Inc. All rights reserved.
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Device Diagrams
Preliminary
Figure 6: 152-Ball Functional Block Diagram (Dual LPDDR)
CE0#
CLE
ALE
RE#
WE#
WP#
CS0#, CS1#
CK
CKE0, CKE1
RAS#
CAS#
WE#
Address,
BA0, BA1
VCC
I/O
R/B#
VSS
VDD
VDDQ
DQM
DQ
TQ
VSS
VSSQ
NAND Flash
LPDDR
(Die 0 and 1)
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152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN 12 ©2008 Micron Technology, Inc. All rights reserved.
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Package Dimensions
Preliminary
Package Dimensions
Figure 7: 152-Ball VFBGA (Package Code: CA)
Note: All dimensions are in millimeters.
Ball A1 ID
0.46 ±0.1
Seating
plane
0.12 A
A
0.9 MAX
Ball A1 ID
0.65 TYP
0.65 TYP
13 CTR
Solder ball
material: SAC105.
Dimensions apply
to solder balls post-
reflow on Ø0.35
SMD ball pads.
152X Ø0.45
14 ±0.1
0.35 MIN
13
CTR
14 ±0.1
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
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152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN 13 ©2008 Micron Technology, Inc. All rights reserved.
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Package Dimensions
Preliminary
Figure 8: 152-Ball VFBGA (Package Code: CG)
Note: All dimensions are in millimeters.
Ball A1 ID
0.6 ±0.1
Seating
plane
0.1 A
A
1.0 MAX
Ball A1 ID
0.65 TYP
13 CTR
14 ±0.1
Solder ball
material: SAC105.
Dimensions apply
to solder balls post-
reflow on Ø0.35
SMD ball pads.
152X Ø0.46
0.35 MIN
13 CTR 14 ±0.1
0.65 TYP
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
Preliminary: This data sheet contains initial characterization limits that are subject to change upon full characterization of production
devices.
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Package Dimensions
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152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN 14 ©2008 Micron Technology, Inc. All rights reserved.
Preliminary
Figure 9: 152-Ball TFBGA (Package Code: JQ)
Notes: 1. All dimensions are in millimeters.
Ball A1 ID
0.75 ±0.1
Seating
plane
0.12 A A
1.1 MAX
0.35 MIN
Ball A1 ID
0.65 TYP
0.65 TYP
13 CTR
14 ±0.1
Solder ball
material: SAC105.
Dimensions apply
to solder balls post-
reflow on Ø0.35
SMD ball pads.
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
T
U
V
W
X
152X Ø0.45
13 CTR 14 ±0.1
PDF: 09005aef8326e5ac / Source: 09005aef8326e59a Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN 15 ©2008 Micron Technology, Inc. All rights reserved.
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Revision History
Preliminary
Revision History
Rev. E, Preliminary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/09
•“NAND Flash-Specific Features” on page 1: Deleted device s ize bullet.
•Figure 2: “152-Ball Part Number Chart,” on page 2: Added U and V options under
NAND Flash configurations; deleted low-pow er opti on under LPDRAM self refresh
current; added dimensions to package codes; added CS# to first column under chip
count; changed CE# from 2 to 1 for B and D under chip count.
•Table 1, “Production Part Numbers,” on page 3: Replaced former table 1.
•Figure 3: “152-Ball VFBGA Ball Assignments (NAND x8; LPDDR x16),” on page 5:
Updat ed figure.
•Figure 4: “152-Ball VFBGA Ball Assignments (NAND x16; LPDDR x32),” on page 6:
Updat ed figure.
•Table 2, “x8/x16 NAND Ball Descriptions,” on page 7: Updated table.
•Table 3, “x16/x32 LPDDR Ball Descriptions,” on page 8: Updated table.
•Table 4, “Non-Device-Specific Ball Descriptions,” on page 8: Up dated table.
•Table 5, “Absolute Maximum Ratings,” on page 9: Updated table.
•Table 6, “Recommended Operating Conditions,” on page 9: Updated table.
•Figure 5: “152-Ball Func tional Bloc k Diagra m (Single LPDDR),” on page 10: Updated
figure title; updated fi gure.
•Figure 6: “152-Ball Functi onal Block Diagram (Dual LPDDR),” on page 11: Added fig-
ure.
Rev. D, Preliminary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/08
• Updated template; ready for external publication.
Rev. C, Preliminary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8/08
• Added part number for JQ package code, page 1.
•Figure 2, Marketing Part Number Example, on page 2: added JQ packag e code.
• Added JQ package diag ram, Figure 9, 152-Ball TFBGA (Package Code: JQ), on page 14.
Rev. B, Preliminary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/08
•On page 1, added part number for CA package code.
•Figure 2: Marketing Part Number Example on page 2: Added CA package code.
• Removed former capacitance tab le s. See component data sh ee ts for capac itance.
•Figure 7: 152-Ball VFBGA (Package Code: CA) on page 12, and Figure 8: 152-Ball
VFBGA (Package Code: CG) on page 13: Updated figur es.
Rev. A, Preliminary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2/08
•Initial release.
