AT89C51-16QI - Atmel Corporation - Datasheet.Directory

PQFP/TQFP

P1.5

P1.6

P1.7

RST

(RXD) P3.0

(TXD) P3.1

(INT0) P3.2

(INT1) P3.3

(T0) P3.4

(T1) P3.5

PO.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

EA/VPP

ALE/PROG

PSEN

P2.7 (A15)

P2.6 (A14)

P2.5 (A13)

(WR)P3.6

(RD) P3.7

XTAL2

XTAL1

GND

(A8) P2.0

(A9) P2.1

(A10) P2.2

(A11) P2.3

(A12) P2.4

P1.4

P1.3

P1.2

P1.1 (T2 EX)

P1.0 (T2)

VCC

P0.0 (AD0)

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

Features

•Compatible with MCS-51™ Products

•4K Bytes of In-System Reprogrammable Flash Memory

– Endurance: 1,000 Write/Erase Cycles

•Fully Static Operation: 0 Hz to 24 MHz

•Three-level Program Memory Lock

•128 x 8-bit Internal RAM

•32 Programmable I/O Lines

•Two 16-b it Timer/Counters

•Six Interrupt Sources

•Programmable Serial Channel

•Low-power Idle and Power-down Modes

Description

The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K

bytes of Flash p rogra mmabl e and era sable re ad only memory ( PERO M). The de vice

is manufactured using Atmel’s high-density nonvolatile memory technology and i s

compatib le with th e in dus tr y-s tan dar d MCS -51 i ns tru ct ion set and pi nou t. The on -c hip

Flash allows the program memory to be reprogrammed in-system or by a conven-

tional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash

on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides

a highly-flexible and cost-effective solution to many embedded control applications.

PDIP

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

RST

(RXD) P3.0

(TXD) P3.1

(INT0) P3.2

(INT1) P3.3

(T0) P3.4

(T1) P3.5

(WR) P3.6

(RD) P3.7

XTAL2

XTAL1

GND

VCC

P0.0 (AD0)

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

P0.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

EA/VPP

ALE/PROG

PSEN

P2.7 (A15)

P2.6 (A14)

P2.5 (A13)

P2.4 (A12)

P2.3 (A11)

P2.2 (A10)

P2.1 (A9)

P2.0 (A8)

Rev. 0265G–02/00

8-bit

Microcontroller

with 4K Bytes

Flash

AT89C51

Not Recommended

for New Designs.

Use AT89S51.

Pin Configurations

PLCC

P1.5

P1.6

P1.7

RST

(RXD) P3.0

(TXD) P3.1

(INT0) P3.2

(INT1) P3.3

(T0) P3.4

(T1) P3.5

PO.4 (AD4)

P0.5 (AD5)

P0.6 (AD6)

P0.7 (AD7)

EA/VPP

ALE/PROG

PSEN

P2.7 (A15)

P2.6 (A14)

P2.5 (A13)

(WR)P3.6

(RD) P3.7

XTAL2

XTAL1

GND

(A8) P2.0

(A9) P2.1

(A10) P2.2

(A11) P2.3

(A12) P2.4

P1.4

P1.3

P1.2

P1.1

P1.0

VCC

P0.0 (AD0)

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

AT89C51

Block Diag ram

PORT 2 DRIVERS

PORT 2

LATCH

P2.0 - P2.7

FLASH

PORT 0

LATCH

RAM

PROGRAM

ADDRESS

BUFFER

INCREMENTER

PROGRAM

COUNTER

DPTR

RAM ADDR.

INSTRUCTION

INTERRUPT, SERIAL PORT,

AND TIMER BLOCKS

STACK

POINTER

ACC

TMP2 TMP1

ALU

PSW

TIMING

AND

CONTROL

PORT 3

LATCH

PORT 3 DRIVERS

P3.0 - P3.7

PORT 1

LATCH

PORT 1 DRIVERS

P1.0 - P1.7

OSC

GND

VCC

PSEN

LE/PROG

EA / VPP

RST

PORT 0 DRIVERS

P0.0 - P0.7

AT89C51

The AT89C 51 pro vides the follo wing st andar d featur es: 4K

bytes of Flash, 128 byte s of RAM, 32 I/O l ines, two 16-bit

timer/counters, a five vector two-level interrupt architecture,

a full duplex serial port, on-chip oscillator and clock cir-

cuitry. In addition, the AT89C51 is designed with static logic

for operation down to zero frequency and supports two

software selectable power saving modes. The Idle Mode

stops the CPU while allowing the RAM, timer/counters,

serial port and interrupt system to continue functioning. The

Power-down Mode saves the RAM contents but freezes

the osci ll ato r d isabl in g al l othe r c hi p fu nc tio ns unt il the n ex t

hardware reset.

Pin Description

VCC

Supply voltage.

GND

Ground.

Port 0

Port 0 i s an 8-b it open-dra in bi-dir ectional I/O po rt. As an

output port, eac h pin can s ink eight TT L inputs . When 1s

are written to port 0 pins, the pins can be used as high-

impedance inputs.

Por t 0 may al so be co nfigur ed to be t he mul tiplex ed low-

order address/data b us during accesses to external pro-

gram and data memory. In this mode P0 has internal

pullups.

Port 0 also receives the code bytes during Flash program-

ming, and outputs the code bytes during program

verific ation. Extern al pull ups are requi red dur ing pro gram

verification.

Port 1

Port 1 is an 8-bit bi-directional I/O port with internal pullups.

The Port 1 output buffers can sink/source four TTL inputs.

When 1s are written to Port 1 pins they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 1 pins that are externally being pulled low will source

current (IIL) because of the internal pullups.

Port 1 also receives the low-order address bytes during

Flash programming and verification.

Port 2

Port 2 is an 8-bit bi-directional I/O port with internal pullups.

The Port 2 output buffers can sink/source four TTL inputs.

When 1s are written to Port 2 pins they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 2 pins that are externally being pulled low will source

current (IIL) because of the internal pullups.

Port 2 emits the high-order address byte during fetches

from external program memory and during accesses to

externa l d ata m em or y that use 16-bi t ad dres se s ( MO VX @

DPTR). In this application, it uses strong internal pullups

when emitting 1s. During accesses to external data mem-

ory that use 8-bit addresses (MOVX @ RI), Port 2 emits the

contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some

control signals during Flash programming and verification.

Port 3

Port 3 is an 8-bit bi-directional I/O port with internal pullups.

The Port 3 output buffers can sink/source four TTL inputs.

When 1s are written to Port 3 pins they are pulled high by

the internal pullups and can be used as inputs. As inputs ,

Port 3 pins that are externally being pulled low will sourc e

current (IIL) because of the pull ups .

Port 3 also serv es the fun ctions of v arious speci al fea tures

of the AT89C51 as listed below:

Port 3 also receives some control signals for Flash pro-

gramming and verification.

RST

Reset input. A high on this pin for two machine cycles while

the oscillator is running resets the device.

ALE/PROG

Address Latch Enable output pulse for latching the low byte

of the address during accesses to external memory. This

pin is also the program pulse input (PROG) during Flash

programming.

In normal operation ALE is emitted at a constant rate of 1/6

the oscillator frequency, and may be used for external tim-

ing or clocking purposes. Note, however, that one ALE

Port Pin Alternate Functions

P3.0 RXD (serial input port)

P3.1 TXD (serial output port)

P3.2 INT0 (external interrupt 0)

P3.3 INT1 (external interrupt 1)

P3.4 T0 (timer 0 external input)

P3.5 T1 (timer 1 external input)

P3.6 WR (external data memory write strobe)

P3.7 RD (external data memory read strobe)

AT89C51

pulse is skipped during each access to external Data

Memory.

If desired, ALE operation can be disabled by setting bit 0 of

SFR loc ation 8 EH. Wi th the bit s et, ALE is active only dur -

ing a MOVX or MOVC instruction. Otherwise, the pin is

weakly pulled high. Setting the ALE-disable bit has no

effect if the microcontroller is in external execution mode.

PSEN

Program Store Enable is the read strobe to external pro-

gram memory.

When the AT89C51 is executing code from external pro-

gram memory, PSEN is activated twice each machine

cycle, except that two PSEN activations are sk i pped dur in g

each access to external data memory.

EA/VPP

External Access Enable. EA must be strapped to GND in

order to enable the device to fetch c ode from ex ternal pr o-

gram memory locations starting at 0000H up to FFFFH.

Note, however, that if lock bit 1 is programmed, EA will be

internally latched on reset.

EA should be strapped to VCC for internal program

executions.

This pin also receives the 12-volt programming enable volt-

age (VPP) during F lash pr ogramm ing, fo r parts th at requ ire

12-volt VPP.

XTAL1

Input to the inverting os cillator amplifi er and input to th e

internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Oscillator Characteristi cs

XTAL1 a nd XTAL2 ar e the inp ut and ou tput, resp ectively,

of an inver ting ampl ifi er whic h c an be c onfigur e d for use as

an on-c hip osci llator, as shown in Figure 1 . Eithe r a quartz

crystal or ceramic resonator may be used. To drive the

device from a n ext er nal cl ock so ur ce , XTAL 2 sh oul d be le ft

unconnected while XTAL1 is driv en as shown in Figure 2.

There are no requirements on the duty cycle of the external

clock signal, since the input to the internal clocking circuitry

is thr ough a d ivide-by -two flip- flop, but minimu m and m axi-

mum voltage high and low time specifications must be

observed.

Idle Mode

In idle mode, the CPU puts itsel f to sleep while all the on-

chip peripherals remain active. The mode is invoked by

software. T he content of the on-chip RAM and all the spe-

cial functions registers remain unchanged during this

mode. The idle mode can be terminated by any enabled

interrupt or by a hardware reset.

It should be noted that when idle is terminated by a hard

ware rese t, the device nor mally resume s program exec u-

tion, from where it left off, up to two mac hine cycles bef ore

the internal reset algorithm takes control. On-chip hardware

inhib its access to i nternal RA M in this even t, but acc ess to

the port pins is not inhibited. To eliminate the possibility of

an unexpected write to a port pin when Idle is terminated by

reset, the instruction following the one that invokes Idle

should n ot be one that wri tes to a port pin or to externa l

memory.

Figure 1. Osci ll ato r Conn ec tio ns

Note: C1, C2 = 30 pF ± 10 pF for Crystals

= 40 pF ± 10 pF for Ceramic Resonators

C2 XTAL2

GND

XTAL1

Status of External Pins During Idle and Power-down Modes

Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3

Idle Internal 1 1 Data Data Data Data

Idle External 1 1 Float Data Address Data

Power-down Internal 0 0 Data Data Data Data

Power-down External 0 0 Float Data Data Data

AT89C51

Figure 2. External Clock Drive Configuration

Power-down Mode

In the power -dow n mode, the osc illator is sto pped, an d the

instruc tion that invoke s powe r-down is the las t instru ction

executed. The on-chip RAM and Special Function Regis-

ters retain their values until the power-down mode is

termina ted. The only exit from po wer-down is a hardw are

reset. R eset red efines the SFRs but does not change th e

on-chip RAM. The reset should not be activated before VCC

is re stored to its no rmal o peratin g level and mu st be h eld

active long enough to allow the oscillator to restart and

stabilize.

Progra m Me mo ry Loc k Bi ts

On the chip are three lock bits which can be left unpro-

grammed (U) or can be programmed (P) to obtain the

additional features listed in the table below.

When lock bit 1 is programmed, the logic level at the EA pin

is sam pled and latch ed during r eset. If the de vice is pow-

ered up without a reset, the latch initia lizes to a random

value, and holds that value until reset is activated. It is nec-

essary that the latched value of EA be in agreement with

the current logi c level at tha t pin in order for the device to

function properly.

Lock Bit Protection Modes

Program Lock Bits

Protection TypeLB1 LB2 LB3

1 U U U No program lock features

2 P U U MOVC instructions executed from external program memor y are disabled from

fetching code bytes from internal memory, EA is sampled and latched on reset,

and further programming of the Flash is disabled

3 P P U Same as mode 2, also verify is disabled

4 P P P Same as mode 3, also external execution is disabl ed

AT89C51

Programming the Flash

The AT89C51 is normally shipped with the on-chip Flash

memory array in the erased state (that is, contents = FFH)

and ready to be programmed. The programming interface

accepts either a high-voltage (12-volt) or a low-voltage

(VCC) program enable signal. The low-voltage program-

ming mode provides a convenient way to program the

AT89C51 inside the us er’s system, whi le the high-voltage

progra mming m ode is co mpatib le with convent ional th ird-

party Flash or EPROM programmers.

The AT89C51 is shipped with either the high-voltage or

low-voltage programming mode enabled. The respective

top-sid e marking and devi ce sig nature code s are l isted in

the following table.

The AT89C 51 cod e memor y arr ay is pr ogra mmed byte- by-

byte in either programming mode. To progr am any non-

blank byte in the on-chip Flash Memory, the entire memory

must be erased using the Chip Erase Mode.

Programming Algorithm: Before programming the

AT89C51, the address, data and control signals should be

set up according to the Flash programming mode table and

Figure 3 and Figure 4. To program the AT89C51, take the

following steps.

1. Input the desired memory location on the address

lines.

2. Input the appropriate data byte on the data lines.

3. Activate the correct combination of control signals.

4. Raise EA/VPP to 12V for the high-voltage program-

ming mode.

5. Pulse ALE/PROG once to program a byte in the

Flash array or the lock bits. The byte-write cycle is

self-timed and typically takes no more than 1.5 ms.

Repeat steps 1 through 5, changing the address

and data for the entire array or until the end of the

object file is reached.

Data Polling: The AT89C51 features Data Polling to indi-

cate the end of a write cycle. During a write cycle, an

attempted read of the last byte written will result in the com-

plement of the written datum on PO.7. Once the write cycle

has be en com pl eted , true d ata a re va li d on a ll out puts , an d

the next c ycle may be gin. Data Polling may begin any time

after a write cycle has been initiated.

Ready/Busy: The progress of byte programming can also

be monito red by th e RDY /BS Y outp ut sig nal . P 3.4 is pul le d

low after ALE goes h igh during programming to indicate

BUSY. P3.4 is pulled high again when programming is

done to indicate READY.

Program Verify: If lock bits LB1 and LB2 have not been

programmed, the programmed code data can be read back

via the addr ess and da ta lines for verificati on. The lo ck bits

cannot be v erified directly . Verification of the lock bits is

achieved by observing that their features are enabled.

Chip Erase: The entire Flash array is erased electrically

by using the proper combi nation of control signals a nd by

holding ALE/PROG low for 10 ms . The code ar ray is writ ten

with all “1”s. The chip erase operation must be executed

before the code memory can be re-programmed.

Reading the Signature Bytes: The signature byt es are

read by the same procedure as a normal verification of

locations 030H, 031H, and 032H, except that P3.6 a nd

P3.7 must be pu lled to a logic low. The va lues return ed ar e

as follows.

(030H) = 1EH indicates manufactured by Atmel

(031H) = 51H indicates 89C51

(032H) = FFH indicates 12V programming

(032H) = 05H indicates 5V programming

Pr ogramming Interface

Every code byte in the Flash array ca n be written and the

entire ar ray c an be e rase d by us i ng the a pprop ri ate c omb i-

nation of control signals. T he write operation cycle is self-

timed and once initiated, will automatically time itself to

completion.

All maj or prog rammi ng ven dors off er world wide s uppor t for

the Atmel microcontroller series. Please contact your local

programming vendor for the appropriate software revision.

VPP = 12V VPP = 5V

Top-side Mark AT89C51

xxxx

yyww

AT89C51

xxxx-5

yyww

Signature (030H) = 1EH

(031H) = 51H

(032H) =F FH

(030H) = 1EH

(031H) = 51H

(032H) = 05H

AT89C51

Note: 1. Chip Erase requires a 10 ms PROG pulse.

Figure 3. Programming the Flash Figure 4. Verif ying the Flas h

Flash Programming Modes

Mode RST PSEN ALE/PROG EA/VPP P2.6 P2.7 P3.6 P3.7

Write Code Data H L H/12V L H H H

Read Code Data H L H H L L H H

Write Lock Bit - 1 H L H/12V H H H H

Bit - 2 H L H/12V H H L L

Bit - 3 H L H/12V H L H L

Chip Erase H L H/12V H L L L

Read Signature Byte H L H H L L L L

(1)

P2.6

P3.6

P2.0 - P2.3

A0 - A7

ADDR.

OOOOH/OFFFH

SEE FLASH

PROGRAMMING

MODES ABLE

3-24 MHz

A8 - A11 P0

+5V

P2.7

PGM

DATA

PROG

V/V

IH PP

VIH

ALE

P3.7

XTAL2 EA

RST

PSEN

XTAL1

GND

VCC

AT89C51

P2.6

P3.6

P2.0 - P2.3

A0 - A7

ADDR.

OOOOH/0FFFH

3-24 MHz

A8 - A11 P0

+5V

P2.7

PGM DATA

(USE 10K

PULLUPS)

VIH

ALE

P3.7

XTAL2 EA

RST

PSEN

XTAL1

GND

AT89C51

SEE FLASH

PROGRAMMING

MODES ABLE

AT89C51

Flash Programming and Verification Waveforms - High-voltage Mode (VPP = 12V)

Flash Programming and Verification Waveforms - Low-vo ltage Mode (VPP = 5V)

GLGH

GHSL

AVGL

SHGL

DVGL

GHAX

AVQV

GHDX

EHSH

ELQV

BUSY READY

GHBL

EHQZ

P1.0 - P1.7

P2.0 - P2.3

ALE/PROG

PORT 0

LOGIC 1

LOGIC 0

EA/V

P2.7

(ENABLE)

P3.4

(RDY/BSY)

PROGRAMMING

ADDRESS VERIFICATION

ADDRESS

DATA IN DATA OUT

GLGH

AVGL

SHGL

DVGL

GHAX

AVQV

GHDX

EHSH

ELQV

BUSY READY

GHBL

EHQZ

P1.0 - P1.7

P2.0 - P2.3

ALE/PROG

PORT 0

LOGIC 1

LOGIC 0

EA/V

P2.7

(ENABLE)

P3.4

(RDY/BSY)

PROGRAMMING

ADDRESS VERIFICATION

ADDRESS

DATA IN DATA OUT

AT89C51

Note: 1. Only used in 12-volt programming mode.

Flash Programming and Verification Characteristics

TA = 0°C to 70°C, VCC = 5.0 ± 10%

Symbol Parameter Min Max Units

VPP(1) Programming Enable Voltage 11.5 12.5 V

IPP(1) Programming Enable Current 1.0 mA

1/tCLCL Oscillator Freque nc y 324MHz

tAVGL Address Setup to PROG Low 48tCLCL

tGHAX Address Hold after PROG 48tCLCL

tDVGL Data Setup to PR O G Low 48tCLCL

tGHDX Data Hold after PROG 48tCLCL

tEHSH P2.7 (ENABLE) High to VPP 48tCLCL

tSHGL VPP Setup to PROG Low 10 µs

tGHSL(1) VPP Hold after PROG 10 µs

tGLGH PROG Width 1 110 µs

tAVQV Address to Data Valid 48tCLCL

tELQV ENABLE Low to Data Valid 48tCLCL

tEHQZ Data Float after ENABLE 0 48tCLCL

tGHBL PROG High to BUSY Low 1.0 µs

tWC Byte Write Cycle Time 2.0 ms

AT89C51

Absolute Maxim u m Ratings*

Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:

Maximum IOL per port pin: 10 mA

Maximum IOL per 8-bit port: P o rt 0: 26 mA

Ports 1, 2, 3: 15 mA

Maximum total IOL for all output pins: 71 mA

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test conditions.

2. Min imum VCC for Power-down is 2V.

Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device . This i s a stres s rat ing onl y and

funct ional ope rati on of the de vic e at these or an y

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditi ons for e xtended periods ma y affe ct device

reliability.

Storage Temperature..................................... -65°C to +150°C

Voltage on Any Pin

with Respect to Ground.....................................-1.0V to +7.0V

Maximu m Op er ati ng Voltage ...... ...... ..... ...... ...... ............... 6.6V

DC Output Current................. ..... ...... ..... ...... ............... 15.0 mA

DC Characteristics

TA = -40°C to 85°C, VCC = 5.0V ± 20% (unless otherwise noted)

Symbol Parameter Condition Min Max Units

VIL Input Low-voltage (Except EA) -0.5 0.2 VCC - 0.1 V

VIL1 Input Low-voltage (EA) -0.5 0.2 VCC - 0.3 V

VIH Input High-voltage (Except XTAL1, RST) 0.2 VCC + 0.9 VCC + 0.5 V

VIH1 Input High-voltage (XTAL1, RST) 0.7 VCC VCC + 0.5 V

VOL Output Low-voltage(1) (Ports 1,2,3) I OL = 1.6 mA 0.45 V

VOL1 Output Low-voltage(1)

(Port 0, ALE, PSEN)IOL = 3.2 mA 0.45 V

VOH Output High-voltage

(Port s 1,2,3, ALE, PSEN )

IOH = -60 µA, VCC = 5V ± 10% 2.4 V

IOH = -25 µA 0.75 VCC V

IOH = -10 µA 0.9 VCC V

VOH1 Output High-voltage

(Port 0 in Exter nal Bus Mo de)

IOH = -800 µA, VCC = 5V ± 10% 2.4 V

IOH = -300 µA0.75 V

CC V

IOH = -80 µA 0.9 VCC V

IIL Logical 0 Input Current (Ports 1,2,3) VIN = 0.45V -50 µA

ITL Logical 1 to 0 Transition Current

(Ports 1,2,3) VIN = 2V, VCC = 5V ± 10% -650 µA

ILI Input Leakage Current (Port 0, EA)0.45 < V

IN < VCC ±10 µA

RRST Reset Pull-down Resistor 50 300 KΩ

CIO Pin Capacitance Test Freq. = 1 MHz, TA = 25°C 10 pF

ICC

Power Supply Current Active Mode, 12 MHz 20 mA

Idle Mode, 12 MHz 5 mA

Power-down Mode(2) VCC = 6V 100 µA

VCC = 3V 40 µA

AT89C51

AC Characteristics

Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other

outputs = 80 pF.

External Program and Data Memory Characte ri stics

Symbol Parameter

12 MHz Oscillator 16 to 24 MHz Oscillator

UnitsMin Max Min Max

1/tCLCL Oscillator Frequency 0 24 MHz

tLHLL ALE Pulse Width 127 2tCLCL-40 ns

tAVLL Address Val id to ALE Low 43 tCLCL-13 ns

tLLAX Address Hold after ALE Low 48 tCLCL-20 ns

tLLIV ALE Low to Valid Instruction In 233 4tCLCL-65 ns

tLLPL ALE Low to PSEN Low 43 tCLCL-13 ns

tPLPH PSEN Pulse Width 205 3tCLCL-20 ns

tPLIV PSEN Low to Valid Instruction In 145 3tCLCL-45 ns

tPXIX Input Instruction Hold after PSEN 00ns

tPXIZ Input Instruction Float after PSEN 59 tCLCL-10 ns

tPXAV PSEN to Address Valid 75 tCLCL-8 ns

tAVIV Address to Valid Instruction In 312 5tCLCL-55 ns

tPLAZ PSEN Low to Address Float 10 10 ns

tRLRH RD Pulse Width 400 6tCLCL-100 ns

tWLWH WR Pulse Widt h 400 6tCLCL-100 ns

tRLDV RD Low to Valid Data In 252 5tCLCL-90 ns

tRHDX Data Hold after RD 00ns

tRHDZ Data Float after RD 97 2tCLCL-28 ns

tLLDV ALE Low to Valid Data In 517 8tCLCL-150 ns

tAVDV Address to Valid Data In 585 9tCLCL-165 ns

tLLWL ALE Low to RD or WR Low 200 300 3tCLCL-50 3tCLCL+50 ns

tAVWL Address to RD or WR Low 203 4tCLCL-75 ns

tQVWX Data Valid to WR Transition 23 tCLCL-20 ns

tQVWH Data Valid to WR High 433 7tCLCL-120 ns

tWHQX Data Hold after WR 33 tCLCL-20 ns

tRLAZ RD Low to Address Float 0 0 ns

tWHLH RD or WR High to ALE High 43 123 tCLCL-20 tCLCL+25 ns

AT89C51

External Program Memory Rea d Cycle

External Data Memory Read Cyc le

tLHLL

tLLIV

tPLIV

tLLAX tPXIZ

tPLPH

tPLAZ tPXAV

tAVLL tLLPL

tAVIV

tPXIX

ALE

PSEN

PORT 0

PORT 2

A8 - A15

A0 - A7 A0 - A7

A8 - A15

INSTR IN

LHLL

LLDV

LLWL

LLAX

WHLH

AVLL

RLRH

AVDV

AVWL

RLAZ

RHDX

RLDV

RHDZ

A0 - A7 FROM RI OR DPL

ALE

PSEN

PORT 0

PORT 2

P2.0 - P2.7 OR A8 - A15 FROM DPH

A0 - A7 FROM PCL

A8 - A15 FROM PCH

DATA IN INSTR IN

AT89C51

External Data Memory Write Cycle

External Clock Drive Waveforms

External Clock Drive

Symbol Parameter Min Max Units

1/tCLCL Oscillator Frequency 0 24 MHz

tCLCL Clock Period 41.6 n s

tCHCX High Time 15 ns

tCLCX Low Time 15 ns

tCLCH Rise Time 20 ns

tCHCL Fall Time 20 ns

LHLL

LLWL

LLAX

WHLH

AVLL

WLWH

AVWL

QVWX

QVWH

WHQX

A0 - A7 FROM RI OR DPL

ALE

PSEN

PORT 0

PORT 2

P2.0 - P2.7 OR A8 - A15 FROM DPH

A0 - A7 FROM PCL

A8 - A15 FROM PCH

DATA OUT INSTR IN

tCHCX tCHCX

tCLCX tCLCL

tCHCL

tCLCH

V - 0.5V

0.45V 0.2 V - 0.1V

0.7 V

AT89C51

Shift Register Mode Timing Waveforms

AC Testing Input/Output Waveforms(1)

Note: 1. AC Inputs during testing are driven at VCC - 0.5V f or a

logic 1 and 0.45 V fo r a logic 0. Tim ing measure ments

are made at VIH min. for a logic 1 and VIL max. for a

logic 0.

Float Waveforms(1)

Note: 1. For timing purposes, a por t pin is no longer floating

when a 100 mV change from load voltage occurs. A

port pin begins to float when 100 mV change from

the loaded VOH/VOL level occurs.

Serial Port Timing: Shift Register Mode Test Conditions

(VCC = 5.0 V ± 20%; Load Capacitance = 80 pF)

Symbol Parameter

12 MHz Osc Variable Oscillator Units

Min Max Min Max

tXLXL Serial Port Clock Cy c le Time 1.0 12tCLCL µs

tQVXH Output Data Setup to Clock Rising Edge 700 10tCLCL-133 ns

tXHQX Output Data Hold after Clock Rising Edge 50 2tCLCL-117 ns

tXHDX Input Data Hold after Clock Rising Edge 0 0 ns

tXHDV Clock Rising Edge to Input Data Valid 700 10tCLCL-133 ns

XHDV

QVXH

XLXL

XHDX

XHQX

ALE

INPUT DATA

CLEAR RI

OUTPUT DATA

WRITE TO SBUF

INSTRUCTION

CLOCK

SET TI

SET RI

VALID VALIDVALID VALIDVALID VALIDVALID VALID

0.45V

TEST POINTS

V - 0.5V

CC 0.2 V + 0.9V

0.2 V - 0.1V

VLOAD+ 0.1V

Timing Reference

Points

LOAD- 0.1V

LOAD VVOL+ 0.1V

VOL - 0.1V

AT89C51

Ordering In format ion

Speed

(MHz) Power

Supply Ordering Code Package Operation Range

12 5V ± 20% AT89C51-12AC 44A Commercia l

AT89C51-12JC 44J (0°C to 70°C)

AT89C51-12PC 40P6

AT89C51-12QC 44Q

AT89C51-12AI 44A Industrial

AT89C51-12JI 44J (-40°C to 85°C)

AT89C51-12PI 40P6

AT89C51-12QI 44Q

16 5V ± 20% AT89C51-16AC 44A Commercia l

AT89C51-16JC 44J (0°C to 70°C)

AT89C51-16PC 40P6

AT89C51-16QC 44Q

AT89C51-16AI 44A Industrial

AT89C51-16JI 44J (-40°C to 85°C)

AT89C51-16PI 40P6

AT89C51-16QI 44Q

20 5V ± 20% AT89C51-20AC 44A Commercia l

AT89C51-20JC 44J (0°C to 70°C)

AT89C51-20PC 40P6

AT89C51-20QC 44Q

AT89C51-20AI 44A Industrial

AT89C51-20JI 44J (-40°C to 85°C)

AT89C51-20PI 40P6

AT89C51-20QI 44Q

24 5V ± 20% AT89C51-24AC 44A Commercia l

AT89C51-24JC 44J (0°C to 70°C)

AT89C51-24PC 40P6

AT89C51-24QC 44Q

AT89C51-24AI 44A Industrial

AT89C51-24JI 44J (-40°C to 85°C)

AT89C51-24PI 40P6

AT89C51-24QI 44Q

Package Type

44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)

44J 44-lead, Plastic J-leaded Chip Carrier (PLCC)

40P6 40-lead, 0.600” Wide, Plastic Dual Inline Package (PDIP)

44Q 44-lead, Plastic Gull Wing Quad Flatpack (PQFP)

AT89C51

Packaging Information

Controlling dimension: millimeters

1.20(0.047) MAX

10.10(0.394)

9.90(0.386) SQ

12.21(0.478)

11.75(0.458) SQ

0.75(0.030)

0.45(0.018) 0.15(0.006)

0.05(0.002)

0.20(.008)

0.09(.003)

0.80(0.031) BSC

PIN 1 ID

0.45(0.018)

0.30(0.012)

.045(1.14) X 45° PIN NO. 1

IDENTIFY .045(1.14) X 30° - 45° .012(.305)

.008(.203)

.021(.533)

.013(.330)

.630(16.0)

.590(15.0)

.043(1.09)

.020(.508)

.120(3.05)

.090(2.29)

.180(4.57)

.165(4.19)

.500(12.7) REF SQ

.032(.813)

.026(.660)

.050(1.27) TYP

.022(.559) X 45° MAX (3X)

.656(16.7)

.650(16.5)

.695(17.7)

.685(17.4)SQ

2.07(52.6)

2.04(51.8) PIN

.566(14.4)

.530(13.5)

.090(2.29)

MAX

.005(.127)

MIN

.065(1.65)

.015(.381)

.022(.559)

.014(.356)

.065(1.65)

.041(1.04)

15 REF

.690(17.5)

.610(15.5)

.630(16.0)

.590(15.0)

.012(.305)

.008(.203)

.110(2.79)

.090(2.29)

.161(4.09)

.125(3.18)

SEATING

PLANE

.220(5.59)

MAX

1.900(48.26) REF

Controlling dimension: millimeters

13.45 (0.525)

12.95 (0.506)

0.50 (0.020)

0.35 (0.014)

PIN 1 ID

0.80 (0.031) BSC

10.10 (0.394)

9.90 (0.386) SQ

0.17 (0.007)

0.13 (0.005)

1.03 (0.041)

0.78 (0.030)

2.45 (0.096) MAX

0.25 (0.010) MAX

44A, 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad

Flatpack (TQFP)

Dimensions in Millimeters and (Inches)*

JEDEC STANDARD MS-026 ACB

44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)

Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-018 AC

40P6, 40- le ad, 0.60 0" Wide, Plastic Dual Inli ne

Package (PDIP)

Dimensions in Inches and (Millimeters)

44Q, 44-lead, Plastic Quad Flat Package (PQFP)

Dimensions in Millimeters and (Inches)*

JEDEC STANDARD MS-022 AB

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