PEEL22CV10ASI-10 - Anachip Corporation

1 of 10 04-02-010F

■

■■

■High Speed/Low Power

- Speeds ranging from 7ns to 25ns

- Power as low as 30mA at 25MHz

■

■■

■Electrically Erasable Technology

- Superior factory testing

- Reprogrammable in plastic package

- Reduces retrofit and development costs

■

■■

■Development/Programmer Support

- Third party software and programmers

- Anachip PLACE Development Software

■

■■

■Architectural Flexibility

- 132 product term X 44 input AND array

- Up to 22 inputs and 10 outputs

- Up to 12 configurations per macrocell

- Synchronous preset, asynchronous clear

- Independent output enables

- 24-pin DIP/SOIC/TSSOP and 28-pin PLCC

■

■■

■Application Versatility

- Replaces random logic

- Pin and JEDEC compatible with 22V10

- Enhanced Architecture fits more logic

than ordinary PLDs

Features

The PEEL™22CV10A is a Programmable Electrically Eras-

able Logi c (PEE L™) de vic e provid ing an attractiv e alte rna-

tive to ordinary PLDs. The PEEL™22CV10A offers the

performance, flexibility, ease of design and production

practicality needed by logic designers today. The

PEEL™22 CV1 0A is av aila ble i n 24-p in DIP, SOIC, T SSOP

and 28-pin PLCC packages (see Figure 1), with speeds

ranging from 7ns to 25ns and with power consumption as

low as 30mA. EE-reprogrammability provides the conve-

nience of instant reprogramming for development and a

reusable production inventory, minimizing the impact of

programming changes or errors. EE-reprogrammability

also improves factory testability, thus ensuring the highest

quality possib le. The PEEL™2 2CV10A is JEDEC fi le com-

patible with standard 22V10 PLDs. Eight additional configu-

rations per macrocell (a total of 12) are also available by

using the “+” software/programming option (i.e., 22CV10A+

& 22CV10A++). The additional macrocell configurations

allow more lo gic to be put into ev ery design. Pro gramming

and development support for the PEEL™22CV10A are pro-

vided by popular third-party programmers and develop-

ment software. Anachip also offers free PLACE

development software.

General Description

DIP

*Optional extra ground pin for

-7/I-7 speed grade.

PLCC

I/CLK

VCC

I/O

GND

I/O

TSSOP

SOIC

Figure 1. Pin Configuration Figure 2. Block Diagram

CMOS Programmable Electrically Erasable Logic Device

PEEL™ 22CV10A-7/-10/-15/-25

2 of 10 04-02-010F

131

124

130

111

121

110

I/CLK

MACRO

CELL

ASYNCHRONOUS CLEAR

(TO ALL MACROCELLS)

MACRO

CELL

MACRO

CELL

MACRO

CELL

MACRO

CELL

MACRO

CELL

MACRO

CELL

MACRO

CELL

MACRO

CELL

MACRO

CELL

SYNCHRONOUS PRESET

(TO ALL MACROCELLS)

I/O

Figure 3. PEEL™22CV10A Logic Array Diagram

3 of 10 04-02-010F

Function Description

The PEEL™22CV10A implements logic functions as sum-

of-products expressions in a programmable-AND/ fixed-OR

logic array. User-defined functions are created by program-

ming the connections of input signals into the array. User-

configur able o utput str uctu res in the fo rm of I/O ma croc ells

further incr eas e log ic flex ibili ty.

Architecture O verview

The PEEL™22CV10A architecture is illustrated in the block

diagram of Figure 2. Twelve dedicated inputs and 10 I/Os

provid e up to 22 inp uts and 10 o utputs for cr eation of logic

functions. At the core of the device is a programmable elec-

trically-erasable AND array which drives a fixed OR array.

With this structure, the PEEL™22CV10A can implement up

to 10 sum-of-products logic expressions.

Associated with each of the 10 OR functions is an I/O mac-

rocell which can be in depend ently programm ed to one of 4

different configurations. The programmable macrocells

allow each I/O to create sequential or combinatorial logic

functions with either active-high or active-low polarity.

AND/OR Logic Array

The programmable AND array of the PEEL™22CV10A

(shown in Figure 3) is formed by input lines intersecting

product terms. The in put lines a nd product ter ms are used

as follows:

44 Input Lines:

24 input lines carry the true and complement

of the signals applied to the 12 input pins

20 additional lines carry the true and complement

values of feedback or input signals from

the 10 I/Os

132 product terms:

120 product terms (arranged in 2 groups of 8,

10, 12, 14 and 16) used to form logical sums

10 output enable terms (one for each I/O)

1 global synchronous present term

1 global asynchronous clear term

At each input-line/product-term intersection there is an

EEPROM memory cell which determines whether or not

there is a logical connection at that intersection. Each prod-

uct term is es se nti all y a 44- input AND gate . A p r oduct term

which is c onnected to b oth the true and complement of an

input signal will always be FALSE, and thus will not affect

the OR fu nction th at it drive s. When al l the con nections o n

a product term are opened, a “don’t care” state exists and

that term will always be TRUE. When programming the

PEEL™22CV10A, the device programmer first performs a

bulk erase to remove the previous pattern. The erase cycle

opens every logical connection in the array. The device is

then configured to perform the user-defined function by

programming selected connections in the AND array. (Note

that PEEL™ device programmers automatically program

the connections on unused product terms so that they will

have no effect on the output function.)

Variable Product Term Distribution

The PEEL™ 22CV10A provi des 120 product ter ms to drive

the 10 OR functions. These product terms are distributed

among the outputs in groups of 8, 10, 12, 14 and 16 to form

logical sums (see Figure 3). This distribution allows opti-

mum use of device re-sources.

Programmable I/O Ma croce ll

The output macrocell provides complete control over the

architecture of each output. The ability to configure each

output independently permits users to tailor the configura-

tion of the P EE L™2 2CV 10A to the pr ecis e r eq uirem ents of

their designs.

Macrocell Architecture

Each I/O macroc ell, as shown in Figure 4, consists of a D-

type flip-flop and two signal-select multiplexers. The config-

uration of each macrocell is determined by the two

EEPROM bits contr olling these mu ltiplexers (refe r to Table

1). These bits determine output polarity and output type

(registered or non-registered). Equivalent circuits for the

four macro-cell configurations are illustrated in Figure 5.

Output Type

The sign al from the OR ar ra y ca n be fed di rect ly to the out-

put pin (combinatorial function) or latched in the D-type flip-

flop (registered function). The D-type flip-flop latches data

on the r ising e dge of the clock a nd is cont rolled by the glo-

bal preset and clear terms. When the synchronous preset

term is satisfied, the Q output of the register will be set

HIGH at the next rising edge of the clock input. Satisfying

the asyn chronou s clear te rm will set Q LOW, re gardless o f

the clock state. If both terms are satisfied simultaneously,

the clear will override the preset.

Output Polarity

Each macrocell can be configured to implement active-high

or active-low logic. Programmable polarity eliminates the

need for external inverters.

Output Enable

The output of each I/O macrocell can be enabled or dis-

abled under the control of its associated programmable

output enable product term. When the logical conditions

programmed on the output enable term are satisfied, the

output signal is propagated to the I/O pin. Otherwise, the

output buffer is driven into the high-impedance state.

Under the control of the output enable term, the I/O pin can

function as a dedicated input, a dedicated output, or a bi-

directional I/O. Opening every connection on the output

4 of 10 04-02-010F

enable term will permanently enable the output buffer and

yield a d edica ted outp ut. Conv erse ly, if eve ry conn ection is

intact, the enable term will always be logically false and the

I/O will function as a dedicated input.

Input/Feedback Select

When configuring an I/O macrocell to implement a regis-

tered function (configurations 1 and 2 in Figure 5), the Q

output o f the flip-flop drives the fee dback term . When con-

figuring an I/O macrocell to implement a combinatorial

function (configurations 3 and 4 in Figure 5), the feedback

signal i s tak en from t he I/O pin . In thi s cas e, the pin ca n b e

used as a dedicated input or a bi-directional I/O. (Refer

also to Table 1.)

Additional Macro Cell Configurations

Besides the standard four-configuration macrocell shown in

Figure 5, each PEEL™22CV10A provides an additional

eight configurations that can be used to increase design

flexibility. The configurations are the same as provided by

the PEEL™18CV8 and PEEL™22CV10AZ. However, to

maintain JEDEC file compatibility with standard 22V10

PLDs the additional configurations can only be utilized by

specifying the PEEL™22CV10A+ and PEEL22CV10A++

for logic assembly and programming. To reference these

additional configurations please refer to the specifications

at the end of this data sheet.

Design Security

The PEEL™22CV10A provides a special EEPROM secu-

rity bit that prevents unauthorized reading or copying of

designs pr ogr am med into the dev ic e. The s ecur ity bit i s se t

by the PLD programmer , either at the conclusion of the pro-

grammin g cycle or as a sepa rate step after the de vice has

been prog rammed. Onc e the secu rity bit is s et, it is impo s-

sible to ve rify (rea d) or program the PE EL ™ un til the enti re

device has first been erased with the bulk-erase function.

Signature Word

The si gnature word fe ature allows a 24-bit code to be pro-

grammed into the PEEL™22CV10A if the

PEEL™22CV10A+ software option is used. Also, the sig-

nature word feature allows a 64-bit code to be programmed

into the PEEL™22CV10A if the PEEL™22CV10A++ soft-

ware opti on i s used . The c ode ca n be r ea d ba ck ev en a fter

the security bit has been set. The signature word can be

used to identify the pattern programmed into the device or

to record the design revision, etc.

Figure 4. Block Diagram of the PEEL™ 22CV10A I/O Macrocell.

5 of 10 04-02-010F

Figure 5. Four Configurations of the PEEL™22CV10A I/O Macrocell

Table 1. PEEL™ 22CV10A Macrocell Configuration Bits

Configuration Input/Feedback Select Output Select

#A B

10 0 Register Feedback Register Active Low

21 0 Activ e High

30 1 Bi-Directional I/O Combinatorial Active Low

41 1 Activ e High

6 of 10 04-02-010F

Additional Macrocell Configurations

Besides the standard four-configuration macrocells, each

PEEL™22CV10A provides an additional eight configura-

tions (twelve total) that can be used to increase design flex-

ibility

(see Figure 6 and Table 2). For logi c assembly of all twelv e

configurations, specify PEEL™22CV10A+ and

PEEL22CV10A++.

Configuration Input/Feedback Select Output Select

#A B C D

1 1 1 1 1

Bi-Directional I/O

2 0 1 1 1 Active High

3 1 0 1 1 Combinatorial Active Low

4 0 0 1 1 Active High

5 1 1 1 0

Combinatorial Feedback

6 0 1 1 0 Active High

7 1 0 1 0 Combinatorial Active Low

8 0 0 1 0 Active High

9 1 1 0 0

10 1 0 0 0 Active High

11 1 0 0 0 Combinatorial Active Low

12 0 0 0 0 Active High

Figure 6. Twelve Configurations of the PEEL™22CV10A+ and PEEL22CV10A++ I/O Macrocell

Table 2. PEEL™ 22CV10A+ & A++ Macrocell Configuration Bits

7 of 10 04-02-010F

Table 6. Absolute Maximum Ratings

Symbol Parameter Conditions Ratings Unit

VCC Supply Voltage Relative to Ground -0.5 to + 7.0 V

VI, VOVoltage Applied to Any Pin2Relative to Ground1-0.5 to VCC + 0.6 V

IOOutput Current Per pin (IOL, IOH)±25mA

TST Storage Tem perat ure -65 to + 150 °C

TLT Lead Tem perature Soldering 10 seconds +300 °C

Table 7. Operating Ranges

Symbol Parameter Conditions Min Max Unit

VCC Supply Voltage Commercial 4.75 5.25 V

Industrial 4.5 5.5

TAAm bient Temperature Commercial 0 +70 °C

Industrial -40 +85

TRClock Rise Time See Note 3 20 ns

TFClock Fall Time See Note 3 20 ns

TRVCC VCC Rise Time See Note 3 250 ms

Table 8. D.C. Electrical Characteristics over the recommended operating conditions

Symbol Parameter Conditions Min Max Unit

VOH Output HIGH Voltage VCC = Min, IOH = -4.0mA 2.4 V

VOHC Output HIGH Voltage - CMOS13 VCC = Min, IOH = -10µA VCC - 0.3 V

VOL Output LOW Voltage - TTL VCC = Min , I OL = 16mA 0.5 V

VOLC Output LOW Voltage - CMOS13 VCC = Min, IOH = -10µA 0.15 V

VIH Input HIGH Level 2.0 VCC + 0.3 V

VIL Input LOW Level -0.3 0.8 V

IIL Input Leakage Current VCC = Max, VIN = GND ≤ VIN £ VCC ±10 µA

IOZ Output Leakage Current I/O = High-Z, GND ≤ VO ≤ VCC ±10 µA

ICC10 VCC Current

(See CR-1 for typical ICC)

VIN = 0V or 3V

f = 25MHz

All outputs disabled4

-7/I-7 90/100

-10/I-10 90/100

-15/I-15 135/145

-25/I-25 30/40

CIN7Input Capacitance TA = 25°C, VCC = 5.0V

@ f = 1 MHz

6pF

COUT7Output Capacitance 12 pF

This device has been designed and tested for the recommended

operating conditions. Proper operation outside of these levels is not

guaranteed. Exposure to absolute maximum ratings may cause per-

manent damage.

8 of 10 04-02-010F

Table 9. A.C. Electrical Characteristics

Symbol Parameter

-7 / I-7 -10 / I-10 -15 / I-15 -25 / I-25 Unit

Min Max Min Max Min Max Min Max

tPD Input5 to non-registered output 7.5 10 15 25 ns

tOE Input5 to output enable67.5 10 15 25 ns

tOD Input5 to output disable67.5 10 15 25 ns

tCO1 Clock to Output 5.5 6 8 15 ns

tCO2 Clock to comb. output delay via

internal registered feedback 10 12 17 35 ns

tCF Clock to Feedback 3.5 4 5 9 ns

tSC Input5 or Feedback Setup to Clock 35815ns

tHC Input5 Hold After Clock 0000ns

tCL, tCH Clock Low Time, Click High Time834613ns

tCP Min Clock Period Ext (tSC + tCO1) 8.5 11 18 30 ns

fMAX1 Internal Feedback (1tSC + tCF)12 142 111 76.9 41.6 MHz

fMAX2 External Feedback (1/tCP)12 117 90.9 62.5 33.3 MHz

fMAX3 No Feedback (1/tCL + tCH)12 166 125 83.3 38.4 MHz

tAW Asynchronous Reset Pulse Width 7.5 10 15 25 ns

tAP Input5 to Asynchronous Reset 7.5 10 15 25 ns

tAR Asynch. Reset recovery time 7.5 10 15 25 ns

tRESET Power-on Reset Time for

registers in Clear State 5555µs

Inputs, I/O,

Registered Feedback,

Synchronous Preset

Clock

Asynchronous

Reset

Registered

Outputs

Combinatorial

Outputs

Notes

1. Minimum DC input is -0.5V, however inputs may undershoot to -2.0V for

periods less than 20ns.

2. VI and VO are not specified for program/verify operation.

3. Test points for Clock and VCC in tR, t F are referenced at 10% and 90%

levels.

4. I/O pins are 0V and 3V.

5. “Input” refers to an Input pin signal.

6. tOE is measured from input transition to VREF ± 0.1V, tOD is measured

from input transition to VOH -0.1V or VOL +0.1V; VREF =VL see test loads

in Section 5 of the Data Book.

7. Capacitances are tested on a sample basis.

8. Test conditions assume: signal transition times of 3ns or less from the

10% and 90% points, timing reference levels of 1.5V (unless otherwise

specified).

9. Test one output at a time for a duration of less than 1sec.

10. ICC for a typical application: This parameter is tested with the device

programmed as an 8-bit Counter.

11. PEEL™ Device test loads are specified in Section 6 of this Data Book.

12. Parameters are not 100% tested. Specifications are based on initial

characterization and are tested after any design or process modifica-

tion which may affect operational frequency.

13. Available only for 22CV10A -15/I-15/-25/I-25 grades.

Switching Waveforms

Over the Operating Range8,11

9 of 10 04-02-010F

Table 6. Ordering Information

Part Number Speed Temperature Package

PEEL22CV10AP-7 7.5ns CP24

PEEL22CV10API-7 I

PEEL 22CV10AJ-7 7.5ns CJ28

PEEL 22CV10AJI -7 I

PEEL 22CV10AS-7 7.5ns CS24

PEEL 22CV10ASI -7 I

PEEL 22CV10AT-7 7.5ns CT24

PEEL 22CV10ATI-7 I

PEEL 22CV10AP-10 10ns CP24

PEEL 22CV10API -10 I

PEEL 22CV10AJ-10 10ns CJ28

PEEL 22CV10AJI -10 I

PEEL 22CV10AS-10 10ns CS24

PEEL 22CV10ASI -10 I

PEEL 22CV10AT-10 10ns CT24

PEEL 22CV10ATI-10 I

PEEL 22CV10AP-15 15ns CP24

PEEL 22CV10API -15 I

PEEL 22CV10AJ-15 15ns CJ28

PEEL 22CV10AJI -15 I

PEEL 22CV10AS-15 15ns CS24

PEEL 22CV10ASI -15 I

PEEL 22CV10AT-15 15ns CT24

PEEL 22CV10ATI-15 I

PEEL 22CV10AP-25 25ns CP24

PEEL 22CV10API -25 I

PEEL 22CV10AT-25 25ns CT24

PEEL 22CV10ATI-25 I

PEEL 22CV10AJ-25 25ns CJ28

PEEL 22CV10AJI -25 I

PEEL 22CV10AS-25 25ns CS24

PEEL 22CV10ASI -25 I

10 of 10 04-02-010F

Part Num ber Device

PEEL™ 22CV10A PI-25

Package

P = Plastic 300mil DIP

J = Plastic (J) Leaded Chip Carrier (PLCC)

S = SOIC

T = TSSO P

Temperature Range and Power Options

(Blank) = Commercial 0 to 70°C

I = Industrial -40 to +85°C

Speed

-7 = 7.5ns tpd

-10 = 10ns tpd

-15 = 15ns tpd

-25 = 25ns tpd

Suffix