Never stop thinking.
Microcontrollers
Data Sheet, V1.2, May 2002
TC1775
32-Bit Single-Chip Microcontroller
Edition 2002-05
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 2002.
All Rights Reserved.
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Microcontrollers
Data Sheet, V1.2, May 2002
Never stop thinking.
TC1775
32-Bit Single-Chip Microcontroller
TC1775 Data Sheet
Preliminary
Revision History: 2002-05 V1.2
Previous Versions: V1.1, 2001-08; V1.0, 2001-08;
Page Subjects (major changes since last revision)
Changes from V1.1, 2001-08 to V1.2, 2002-05
– Status of data sheet changed from “Advance Information” into “Preliminary”
36 ADC features: example of 10-bit ADC conversion time added
54 Note below Figure 16 added
59 Column “Jitter” in Table 8 removed; the jitter is now defined in “PLL
Parameters” on Page 82 and Figure 31; 2nd footnote for Table 8 added
60 Note on bottom extended “… specified by the crystal suppliers:”
66 Section “Package Parameters” added
68, 69, 70 Definition and values for pull-up/pull-down currents changed
71 Curves for pull-up/pull-down characteristics added
73 Formulas for conversion time tC corrected; fANA min./max. specification
added
73 Definition of IAOV and kA improved
76 Note 1) for IOZ added
77 IDD max corrected; IDD active for VDDSB added; note for IID and ISL added
78 tRFAnom (typ.) added
80 Figure 29 corrected
81 Figure 30 corrected
82, 83 PLL specification and parameters completed
84, 87, 89,
92, 94, 95
Several AC timing parameter values added or corrected: t10, t11, t15, t20,
t21, t25, t45, t46, t47, t55, t61, t62
95 Definition of t61 and t62 changed
several Formal changes
Changes from V1.0, 2001-08 to V1.1, 2001-08
84 Reference for t31 and t32 to Page 90 added
89 t50 and t51 changed into TBD; note changed into “Will be guaranteed …”
90 t31 and t32 (Data setup/hold to CLKIN in burst mode timing) changed;
note 1) added
95 t61 and t62 changed into TBD; note changed into “Will be guaranteed …”
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Data Sheet 1 V1.2, 2002-05
Preliminary
TC177532-Bit Single-Chip Microcontroller
TriCore Family
• High Performance 32-bit TriCore CPU with 4-Stage Pipeline
– 25 ns Instruction Cycle Time at 40 MHz CPU Clock
• Dual Issue super-scalar implementation
– Instruction triple issue
• Circular Buffer and bit-reverse addressing modes for DSP algorithms
• Flexible multi-master interrupt system
• Very fast interrupt response time
• Hardware controlled context switch for task switch and interrupts
• 72 Kbytes of on-chip SRAM for data and time critical code
• Independent Peripheral Control Processor (PCP) for low level driver support with
20 Kbytes code/parameter memory
• Built-in calibration support
• On-chip Flexible Peripheral Interface Bus (FPI Bus) for interconnections of functional
units
• Flexible External Bus Interface Unit (EBU) used for
– Communication with external data memories and peripheral units
– Instruction fetches from external Burst Flash program memories
• On-Chip Peripheral Units
– General Purpose Timer Array (GPTA) with a powerful set of digital signal filtering
and timer functionality to realize autonomous and complex I/O management
– Multifunctional General Purpose Timer Unit (GPTU) with three 32-bit timer/counters
– Two Asynchronous/Synchronous Serial Channels (ASC0, ASC1) with baud rate
generator, parity, framing and overrun error detection
– Two High Speed Synchronous Serial Channels (SSC0, SSC1) with programmable
data length and shift direction
– TwinCAN module with two interconnected CAN nodes for high efficiency data
handling via FIFO buffering and gateway data transfer
– Serial Data Link module (SDLM) compliant to SAE Class B J1850 specification
– Two Analog-to-Digital Converter Units (ADC0, ADC1) with 8-bit, 10-bit, or 12-bit
resolution and 16 analog inputs each
– Watchdog Timer and System Timer
– Real Time Clock
• Eleven 16-bit digital I/O ports and two 16-bit analog ports
• On-chip Debug Support
• Power Management System
• Clock Generation Unit with PLL
• Ambient temperature under bias: -40 °C to +125 °C
• P-BGA-329 package
TC1775
Data Sheet 2 V1.2, 2002-05
Preliminary
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies: the derivative itself, i.e. its function set,
the temperature range, and the package and the type of delivery.
The TC1775 is available with the following ordering code:
Type Ordering Code Package Description
SAK-TC1775-L40E Q67121-C2285-A701 P-BGA-329 32-Bit Single-Chip
Microcontroller
40 MHz
-40 °C to +125 °C
TC1775
Data Sheet 3 V1.2, 2002-05
Preliminary
Block Diagram
Figure 1 TC1775 Block Diagram
MCB04671
J1850
Twin
CAN
SSC0SSC1ASC0ASC1ADC0ADC1GPTA
433216
EBU
(External
Bus
Unit)
Port 4
12 16
Port 0
16 16
Port 1
16 16
Port 2
16 16 Addr.
[15:0]
Addr./
Data
[15:0]
Addr./
Data
(31:16]
Port 13
Port 10
16
16
Port 9
16
Port 8 Port 7 Port 6
16 16 2
GPTU
8
Port 11
16
16
Port 12
16
5
2
5
2
PCP
Core
OCDS
Interrupt
4 K Data-SRAM
FPI Interface
2
STM
BCU RTC
PLL
FPI Bus
CLKOUT
CLKIN
XTAL4
XTAL3
f
RTC
= 32 kHz
XTAL2
XTAL1
Control
f
CPUmax
=
40 MHz
Port 5
16
16
16
Cerberus
& JTAG
SCU
(PW R)
Power-
Watchdog-
Reset
5
JTAG IO
BRKOUT
BRKIN
Control 9
DMU
(Data Memory Unit)
32 KB SRAM +
8 KB Stand-by SRAM
(Overlay Functionality)
TriCore
CPU
Trace &
OCDS Interrupt
V
SS
V
DD
128 64
OCDSE
PMU
(Program Memory Unit)
8 KB Boot ROM
32 KB Scratch Pad RAM
1 KB Instruction Cache
FPI Bus
32
32
16 16 16 16 16 16
EBU
Control
10
Address
[25:16]
6
Port 3
4
16 K Code-SRAM
TC1775
Data Sheet 4 V1.2, 2002-05
Preliminary
Logic Symbol
Figure 2 TC1775 Logic Symbol
MCA04679
TC 1775
Port 0
16-Bit
Port 1
16-Bit
Port 2
16-Bit
Port 3
16-Bit
Port 4
16-Bit
Port 5
16-Bit
Port 6
16-Bit
Port 7
16-Bit
Port 8
16-Bit
Port 9
16-Bit
Port 10
16-Bit
Port 11
16-Bit
Port 12
16-Bit
Port 13
16-Bit
V
AREF0
V
AGND0
V
DDA0
V
SSA0
V
AREF1
V
AGND1
V
DDA1
V
SSA1
Alternate Functions
External
Bus Interface
TRACE
ADC0
ADC1
GPTA
ADC0/1
J1850 / ASC0/1
GPTU /
SSC0/1 / CAN
ADC0
Analog
Power Supply
ADC1
Analog
Power Supply
V
SSM
V
DDM
V
SSSC
V
DDSC
ADC0 / ADC1
Analog
Power Supply
V
SS
V
DDSB
V
DDSRAM
V
DDP813
V
DDP05
V
DD
10
5
6
2
29
Digital Circuitry
Power Supply
BRKOUT
BRKIN
OCDSE
TMS
TDO
TDI
TCK
TRST
JTAG / OCDS
V
SSPLL
V
DDPLL
V
SSOSC
V
DDOSC
XTAL4
XTAL3
XTAL2
XTAL1
Oscillators / PLL
3
CLKSEL
BYPASS
CFG
NMI
PORST
HDRST
CLKOUT
CLKIN
TESTMODE
4
General Control
3
N.C.1 7
N.C.2
TC1775
Data Sheet 5 V1.2, 2002-05
Preliminary
Pin Configuration
Figure 3 TC1775 Pinning: P-BGA-329 Package (top view)
MCP04680
AN
3AN
6AN
9
1234567
AN
11 AN
15
89
P12.
13
10 11
P12.
9P12.
5
12 13
P12.
1P13
15
14 15
P13.
11 P13.
8
16 17
P13.
4P13.
2
18 19
P11.
15 P11.
12
20 21
P11.
8P11.
5
22 23
P11.
4
V
SSA0
V
SSM
V
SSSC
V
DDSC
A
AN
16
BAN
17 AN
0AN
4AN
7AN
10 AN
13 P12.
15 P12.
12 P12.
7P12.
6P12.
2P13.
13 P13.
9P13.
6P13.
3P13.
0P11.
13 P11.
9P11.
6P11.
3
V
DDSB
AN
19
C
V
DDM
AN
20 AN
1AN
5AN
8AN
14 P12.
14 P12.
11 P12.
8P12.
4P12.
3N.C.
2P13.
14 P13.
10 P13.
7P13.
1P11.
14 P11.
10 P11.
0P11.
1
A
B
C
AN
23
DAN
24 AN
18 AN
2
AN
21
V
SS
AN
12
V
DD
P813
V
DDA0
N.C.
1P12.
10 P12.
0P13.
12
V
DD
V
DD
P813
P13.
5
V
SS
P11.
11 P11.
7N.C.
2P10.
13 P10.
14 D
AN
26
EAN
27 AN
22
AN
25
AN
29
FAN
30 AN
28
V
SS
V
AREF0
V
AGND0
V
AGND1
V
SSA1
V
AREF1
AN
31
G
V
DDA1
HP1.0 P1.1
V
DD
P05
P1.2
JP1.4 P1.5 P1.3
P1.6
KP1.7 N.C.
2
V
DD
P1.8
LP1.9 P1.10 N.C.
2
P1.12
MP1.13 P1.11
V
DD
P05
P0.0
NP1.14 P1.15 P0.1
P0.4
PP0.3 P0.2
V
DD
P0.6 P0.5 P0.7
CLK
OUT
R
P0.9 P0.8
CLK
IN
T
V
DD
P05
P0.13
UP0.11 P0.10 P0.12
V
DD
P0.15
VP0.14 P4.0
P4.2
WP4.1 P4.3 P4.6
P4.5
YP4.4 P4.7 P4.15 P2.2
V
SS
P2.12
V
DD
P05
P3.3
V
DD
P3.9
V
DD
P05
P5.3 N.C.
1P5.8 N.C.
2P5.15
V
DD
OCD
SE NMI PO
RST
CFG
1
TRST
CFG
0
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
E
P10.
15 P10.
12 P10.
10 P10.
11
V
DD
P10.
9P10.
7P10.
8
P10.
3P10.
4P10.
6
P10.
5
P10.
0P10.
1P10.
2
V
DD
P813
P9.14 P9.12 P9.13 P9.15
V
DD
P9.9 P9.10 P9.11
P9.6 P9.5 P9.7P9.8
V
DD
P813
P9.2 P9.4 P9.3
P9.1 P9.0 P8.15P8.14
V
DD
P8.13 P8.12 P8.11
P8.10 P8.9 P8.7P8.8
V
DD
P813
P8.6 P8.5 P8.4
P8.3 P8.2 P8.0P8.1
V
SS
CLK
SEL0 CLK
SEL2 CLK
SEL1
CFG
2BY
PASS CFG
3
HD
RST
AA P4.9 P4.8 P4.10 P2.1 P2.5 P2.8 P2.14 P3.1 P3.5 P3.8 P3.12 P3.13 P5.1 P5.4 P5.7 P5.10 P5.13 TDO XTAL
4
V
SS
OSC
V
DD
PLL
V
SS
PLL
AA
AB P4.14P4.11 P2.0 P2.4 P2.7 P2.10 P2.13 P3.0 P3.4 P3.7 P3.11 P3.15 P5.0 P5.5 P5.11 P5.14
N.C.
1
V
DD
SRAM
TCK TMS XTAL
3
N.C.
2TEST
MODE AB
P4.12 P4.13
AC N.C.
2P2.3 P2.6 P2.9 P2.11 P2.15 P3.2 P3.6 P3.10 P3.14 P5.2 P5.6 P5.9 P5.12
V
DD
SRAM
BRK
OUT TDI BRK
IN
V
DD
OSC
XTAL
2XTAL
1AC
1 2 3 4 5 6 7 8 9 1011121314151617181920212223
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD
P11.
2
V
DD
P813
TC1775
Data Sheet 6 V1.2, 2002-05
Preliminary
Table 1 Pin Definitions and Functions
Symbol Pin In
Out
Functions
P0
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P0.8
P0.9
P0.10
P0.11
P0.12
P0.13
P0.14
P0.15
N1
N4
P3
P2
P1
R3
R2
R4
T3
T2
U3
U2
U4
U1
V2
V1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port 0
Port 0 serves as 16-bit general purpose I/O port or as lower
external address/data bus AD[15:0] (multiplexed bus mode)
or data bus D[15:0] (demultiplexed bus mode) for the EBU.
Port 0 is used as data input by an external bus master when
accessing modules on the internal FPI Bus.
AD0 / D0 Address/data bus line 0 / Data bus line 0
AD1 / D1 Address/data bus line 1 / Data bus line 1
AD2 / D2 Address/data bus line 2 / Data bus line 2
AD3 / D3 Address/data bus line 3 / Data bus line 3
AD4 / D4 Address/data bus line 4 / Data bus line 4
AD5 / D5 Address/data bus line 5 / Data bus line 5
AD6 / D6 Address/data bus line 6 / Data bus line 6
AD7 / D7 Address/data bus line 7 / Data bus line 7
AD8 / D8 Address/data bus line 8 / Data bus line 8
AD9 / D9 Address/data bus line 9 / Data bus line 9
AD10 / D10 Address/data bus line 10 / Data bus line 10
AD11 / D11 Address/data bus line 11 / Data bus line 11
AD12 / D12 Address/data bus line 12 / Data bus line 12
AD13 / D13 Address/data bus line 13 / Data bus line 13
AD14 / D14 Address/data bus line 14 / Data bus line 14
AD15 / D15 Address/data bus line 15 / Data bus line 15
TC1775
Data Sheet 7 V1.2, 2002-05
Preliminary
P1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P1.8
P1.9
P1.10
P1.11
P1.12
P1.13
P1.14
P1.15
H2
H3
J1
J4
J2
J3
K1
K2
L1
L2
L3
M3
M1
M2
N2
N3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port 1
Port 1 serves as 16-bit general purpose I/O port or as upper
external address/data bus AD[31:16] (multiplexed bus mode)
or data bus D[31:16] (demultiplexed bus mode) for the EBU.
Port 1 is used as data input by an external bus master when
accessing modules on the internal FPI Bus.
AD16 / D16 Address/data bus line 16 / Data bus line 16
AD17 / D17 Address/data bus line 17/ Data bus line 17
AD18 / D18 Address/data bus line 18 / Data bus line 18
AD19 / D19 Address/data bus line 19 / Data bus line 19
AD20 / D20 Address/data bus line 20 / Data bus line 20
AD21 / D21 Address/data bus line 21 / Data bus line 21
AD22 / D22 Address/data bus line 22 / Data bus line 22
AD23 / D23 Address/data bus line 23 / Data bus line 23
AD24 / D24 Address/data bus line 24 / Data bus line 24
AD25 / D25 Address/data bus line 25 / Data bus line 25
AD26 / D26 Address/data bus line 26 / Data bus line 26
AD27 / D27 Address/data bus line 27 / Data bus line 27
AD28 / D28 Address/data bus line 28 / Data bus line 28
AD29 / D29 Address/data bus line 29 / Data bus line 29
AD30 / D30 Address/data bus line 30 / Data bus line 30
AD31 / D31 Address/data bus line 31 / Data bus line 31
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 8 V1.2, 2002-05
Preliminary
P2
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P2.8
P2.9
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
AB3
AA4
Y5
AC4
AB4
AA5
AC5
AB5
AA6
AC6
AB6
AC7
Y7
AB7
AA7
AC8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port 2
Port 2 serves as 16-bit general purpose I/O port or as lower
external address bus for the EBU. When used as address
bus, it outputs the addresses A[15:0] of an external access in
demultiplexed bus mode.
Port 2 is used as address input by an external bus master
when accessing modules on the internal FPI Bus.
A0 Address bus line 0
A1 Address bus line 1
A2 Address bus line 2
A3 Address bus line 3
A4 Address bus line 4
A5 Address bus line 5
A6 Address bus line 6
A7 Address bus line 7
A8 Address bus line 8
A9 Address bus line 9
A10 Address bus line 10
A11 Address bus line 11
A12 Address bus line 12
A13 Address bus line 13
A14 Address bus line 14
A15 Address bus line 15
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 9 V1.2, 2002-05
Preliminary
P3
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.101)
P3.111)
P3.121)
P3.131)
P3.141)
P3.151)
AB8
AA8
AC9
Y9
AB9
AA9
AC10
AB10
AA10
Y11
AC11
AB11
AA11
AA12
AC12
AB12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
Port 3
Port 3 serves as 16-bit general purpose I/O port or as upper
external address bus for the EBU. When used as address
bus, it outputs the addresses A[25:16] of an external access
in demultiplexed bus mode.
P3[9:0] is used as address input by an external bus master
when accessing modules on the internal FPI Bus.
Port 3 also provides chip select output lines CS0 - CS3,
CSEMU, and CSOVL.
A16 Address bus line 16
A17 Address bus line 17
A18 Address bus line 18
A19 Address bus line 19
A20 Address bus line 20
A21 Address bus line 21
A22 Address bus line 22
A23 Address bus line 23
A24 Address bus line 24
A25 Address bus line 25
CS3 Chip select output line 3
CS2 Chip select output line 2
CS1 Chip select output line 1
CS0 Chip select output line 0
CSEMU Chip select output for emulator region
CSOVL Chip select output for emulator overlay memory
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 10 V1.2, 2002-05
Preliminary
P4
P4.01)
P4.11)
P4.22)
P4.31)
P4.41)
P4.51)
P4.61)
P4.71)
P4.81)
P4.91)
P4.101)
P4.111)
P4.121)
P4.131)
P4.141)
P4.151)
V3
W2
W1
W3
Y2
Y1
W4
Y3
AA2
AA1
AA3
AB1
AC1
AC2
AB2
Y4
I/O
I/O
I/O
O
O
I/O
I/O
I/O
I/O
I
O
I
I
I/O
O
O
I/O
Port 4
Port 4 is used as general purpose I/O port but also serves as
control bus for the EBU control lines.
RD Read control line
RD/WR Write control line
ALE Address latch enable output
ADV Address valid output
BC0 Byte control line 0
BC1 Byte control line 1
BC2 Byte control line 2
BC3 Byte control line 3
WAIT/IND Wait input / End of burst input
BAA Burst address advance output
CSFPI Chip select FPI input
HOLD Hold request input
HLDA Hold acknowledge input/output
BREQ Bus request output
CODE Code fetch status output
SVM Supervisor mode input/output
The CODE signal has the same timing as the CSx signals
which are located at Port 3.
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 11 V1.2, 2002-05
Preliminary
P5
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P5.8
P5.9
P5.10
P5.11
P5.12
P5.13
P5.14
P5.15
AB13
AA13
AC13
Y13
AA14
AB14
AC14
AA15
Y15
AC15
AA16
AB16
AC16
AA17
AB17
Y17
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Port 5
Port 5 serves as 16-bit general purpose I/O port or as CPU
or PCP trace output port for the OCDS logic.
TRACE0 CPU or PCP trace output 0
TRACE1 CPU or PCP trace output 1
TRACE2 CPU or PCP trace output 2
TRACE3 CPU or PCP trace output 3
TRACE4 CPU or PCP trace output 4
TRACE5 CPU or PCP trace output 5
TRACE6 CPU or PCP trace output 6
TRACE7 CPU or PCP trace output 7
TRACE8 CPU or PCP trace output 8
TRACE9 CPU or PCP trace output 9
TRACE10 CPU or PCP trace output 10
TRACE11 CPU or PCP trace output 11
TRACE12 CPU or PCP trace output 12
TRACE13 CPU or PCP trace output 13
TRACE14 CPU or PCP trace output 14
TRACE15 CPU or PCP trace output 15
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 12 V1.2, 2002-05
Preliminary
P6
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
P6.8
P6.9
P6.10
P6.11
P6.12
P6.13
P6.14
P6.15
B3
C4
D5
A4
B4
C5
A5
B5
C6
A6
B6
A7
D7
B7
C7
A8
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Port 6
Port 6 provides the analog input lines for the AD Converter 0
(ADC0).
AN0 Analog input 0 / VAREF[1] input for ADC0
AN1 Analog input 1 / VAREF[2] input for ADC0
AN2 Analog input 2 / VAREF[3] input for ADC0
AN3 Analog input 3
AN4 Analog input 4
AN5 Analog input 5
AN6 Analog input 6
AN7 Analog input 7
AN8 Analog input 8
AN9 Analog input 9
AN10 Analog input 10
AN11 Analog input 11
AN12 Analog input 12
AN13 Analog input 13
AN14 Analog input 14
AN15 Analog input 15
P7
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
P7.8
P7.9
P7.10
P7.11
P7.12
P7.13
P7.14
P7.15
B1
B2
D4
C1
C2
D3
E4
D1
D2
E3
E1
E2
F3
F1
F2
G1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Port 7
Port 7 provides the analog input lines for the AD Converter 1
(ADC1).
AN16 Analog input 16 / VAREF[1] input for ADC1
AN17 Analog input 17 / VAREF[2] input for ADC1
AN18 Analog input 18 / VAREF[3] input for ADC1
AN19 Analog input 19
AN20 Analog input 20
AN21 Analog input 21
AN22 Analog input 22
AN23 Analog input 23
AN24 Analog input 24
AN25 Analog input 25
AN26 Analog input 26
AN27 Analog input 27
AN28 Analog input 28
AN29 Analog input 29
AN30 Analog input 30
AN31 Analog input 31
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 13 V1.2, 2002-05
Preliminary
P8
P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8.6
P8.7
P8.8
P8.9
P8.10
P8.11
P8.12
P8.13
P8.14
P8.15
U23
U20
U22
U21
T23
T22
T21
R23
R20
R22
R21
P23
P22
P21
N20
N23
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port 8
Port 8 is a 16-bit bidirectional general purpose I/O port which
also serves as input or output for the GPTA.
IN0 / OUT0 line of GPTA
IN1 / OUT1 line of GPTA
IN2 / OUT2 line of GPTA
IN3 / OUT3 line of GPTA
IN4 / OUT4 line of GPTA
IN5 / OUT5 line of GPTA
IN6 / OUT6 line of GPTA
IN7 / OUT7 line of GPTA
IN8 / OUT8 line of GPTA
IN9 / OUT9 line of GPTA
IN10 / OUT10 line of GPTA
IN11 / OUT11 line of GPTA
IN12 / OUT12 line of GPTA
IN13 / OUT13 line of GPTA
IN14 / OUT14 line of GPTA
IN15 / OUT15 line of GPTA
P9
P9.0
P9.1
P9.2
P9.3
P9.4
P9.5
P9.6
P9.7
P9.8
P9.9
P9.10
P9.11
P9.12
P9.13
P9.14
P9.15
N22
N21
M21
M23
M22
L22
L21
L23
L20
K21
K22
K23
J21
J22
J20
J23
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port 9
Port 9 is a 16-bit bidirectional general purpose I/O port which
also serves as input or output for the GPTA.
IN16 / OUT16 line of GPTA
IN17 / OUT17 line of GPTA
IN18 / OUT18 line of GPTA
IN19 / OUT19 line of GPTA
IN20 / OUT20 line of GPTA
IN21 / OUT21 line of GPTA
IN22 / OUT22 line of GPTA
IN23 / OUT23 line of GPTA
IN24 / OUT24 line of GPTA
IN25 / OUT25 line of GPTA
IN26 / OUT26 line of GPTA
IN27 / OUT27 line of GPTA
IN28 / OUT28 line of GPTA
IN29 / OUT29 line of GPTA
IN30 / OUT30 line of GPTA
IN31 / OUT31 line of GPTA
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 14 V1.2, 2002-05
Preliminary
P10
P10.0
P10.1
P10.2
P10.3
P10.4
P10.5
P10.6
P10.7
P10.8
P10.9
P10.10
P10.11
P10.12
P10.13
P10.14
P10.15
H21
H22
H23
G21
G22
G20
G23
F22
F23
F21
E22
E23
E21
D22
D23
E20
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port 10
Port 10 is a 16-bit bidirectional general purpose I/O port
which also serves as input or output for the GPTA.
IN32 / OUT32 line of GPTA
IN33 / OUT33 line of GPTA
IN34 / OUT34 line of GPTA
IN35 / OUT35 line of GPTA
IN36 / OUT36 line of GPTA
IN37 / OUT37 line of GPTA
IN38 / OUT38 line of GPTA
IN39 / OUT39 line of GPTA
IN40 / OUT40 line of GPTA
IN41 / OUT41 line of GPTA
IN42 / OUT42 line of GPTA
IN43 / OUT43 line of GPTA
IN44 / OUT44 line of GPTA
IN45 / OUT45 line of GPTA
IN46 / OUT46 line of GPTA
IN47 / OUT47 line of GPTA
P11
P11.0
P11.1
P11.2
P11.3
P11.4
P11.5
P11.6
P11.7
P11.8
P11.9
P11.10
P11.11
P11.12
P11.13
P11.14
P11.15
C22
C23
C21
B23
A23
A22
B22
D20
A21
B21
C20
D19
A20
B20
C19
A19
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port 11
Port 11 is a 16-bit bidirectional general purpose I/O port
which also serves as input or output for the GPTA.
IN48 / OUT48 line of GPTA
IN49 / OUT49 line of GPTA
IN50 / OUT50 line of GPTA
IN51 / OUT51 line of GPTA
IN52 / OUT52 line of GPTA
IN53 / OUT53 line of GPTA
IN54 / OUT54 line of GPTA
IN55 / OUT55 line of GPTA
IN56 / OUT56 line of GPTA
IN57 / OUT57 line of GPTA
IN58 / OUT58 line of GPTA
IN59 / OUT59 line of GPTA
IN60 / OUT60 line of GPTA
IN61 / OUT61 line of GPTA
IN62 / OUT62 line of GPTA
IN63 / OUT63 line of GPTA
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 15 V1.2, 2002-05
Preliminary
P12
P12.0
P12.1
P12.2
P12.3
P12.4
P12.5
P12.6
P12.7
P12.8
P12.9
P12.10
P12.11
P12.12
P12.13
P12.14
P12.15
D13
A13
B13
C13
C12
A12
B12
B11
C11
A11
D11
C10
B10
A10
C9
B9
I/O
O
O
O
O
O
O
I
I
I
I
I
O
I/O
O
I/O
O
Port 12
Port 12 is a 16-bit bidirectional general purpose I/O port or
serves as ADC control port and SDLM/ASC I/O port.
AD0EMUX0 ADC0 external multiplexer control 0
AD0EMUX1 ADC0 external multiplexer control 1
AD0EMUX2 ADC0 external multiplexer control 2
AD1EMUX0 ADC1 external multiplexer control 0
AD1EMUX1 ADC1 external multiplexer control 1
AD1EMUX2 ADC1 external multiplexer control 2
AD1EXTIN0 ADC1 external trigger input 0
AD1EXTIN1 ADC1 external trigger input 1
AD0EXTIN0 ADC0 external trigger input 0
AD0EXTIN1 ADC0 external trigger input 1
RXJ1850 SDLM receiver input
TXJ1850 SDLM transmitter output
RXD0A ASC0 receiver input/output A
TXD0A ASC0 transmitter output A
RXD1A ASC1 receiver input/output A
TXD1A ASC1 transmitter output A
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 16 V1.2, 2002-05
Preliminary
P13
P13.0
P13.1
P13.2
P13.3
P13.4
P13.5
P13.6
P13.7
P13.8
P13.9
P13.10
P13.11
P13.12
P13.13
P13.14
P13.15
B19
C18
A18
B18
A17
D17
B17
C17
A16
B16
C16
A15
D15
B15
C15
A14
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
I
O
Port 13
Port 13 is a 16-bit bidirectional general purpose I/O port that
is also used as input/output for the serial interfaces (ASC,
SSC, CAN) and timers (GPTU).
GPT0 GPTU I/O line 0
GPT1 GPTU I/O line 1
GPT2 GPTU I/O line 2
RXD0B ASC0 receiver input/output B
GPT3 GPTU I/O line 3
TXD0B ASC0 transmitter output B
GPT4 GPTU I/O line 4
RXD1B ASC1 receiver input/output B
GPT5 GPTU I/O line 5
TXD1B ASC1 transmitter output B
GPT6 GPTU I/O line 6
SCLK0 SSC0 clock input/output
GPT7 GPTU I/O line 7
MRST0 SSC0 master receive / slave transmit
input/output
MTSR0 SSC0 master transmit / slave receive
output/input
SCLK1 SSC1 clock input/output
MRST1 SSC1 master receive / slave transmit
input/output
MTSR1 SSC1 master transmit / slave receive
output/input
RXDCAN0 CAN receiver input 0
TXDCAN0 CAN transmitter output 0
RXDCAN1 CAN receiver input 1
TXDCAN1 CAN transmitter output 1
CLKSEL0
CLKSEL1
CLKSEL2
V21
V23
V22
I
I
I
PLL Clock Selection Inputs
These pins are sampled during power-on reset
(PORST = low); they determine the division rate in the
feedback path of the PLL (N-Factor). The latched values of
these input pins are available in the PLL Clock Control
Register PLL_CLC.
The combination BYPASS = 1 and CLKSEL[2:0] = 000B
during power-on reset is reserved.
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 17 V1.2, 2002-05
Preliminary
BYPASS W22 I PLL Bypass Control Input
BYPASS is used for direct drive mode operation of the clock
circuitry. This pin is sampled during power-on reset
(PORST = low). Its level is latched into the PLL Clock
Control Register PLL_CLC. The combination BYPASS = 1
and CLKSEL[2:0] = 000B during power-on reset is reserved.
CFG0
CFG1
CFG2
CFG3
Y23
Y22
W21
W23
I
I
I
I
Operation Configuration Inputs
The configuration inputs define the boot options of the
TC1775 after a hardware reset operation.
TRST3) AA19 I JTAG Module Reset/Enable Input
A low level at this pin resets and disables the JTAG module.
A high level enables the JTAG module.
TCK3) AB19 I JTAG Module Clock Input
TDI4) AC19 I JTAG Module Serial Data Input
TDO AA18 O JTAG Module Serial Data Output
TMS4) AB20 I JTAG Module State Machine Control Input
OCDSE4) Y19 I OCDS Enable Input
A low level on this pin during power-on reset (PORST =low)
enables the on-chip debug support (OCDS). In addition, the
level of this pin during power-on reset determines the boot
configuration.
BRKIN4) AC20 I OCDS Break Input
A low level on this pin causes a break in the chip’s execution
when the OCDS is enabled. In addition, the level of this pin
during power-on reset determines the boot configuration.
BRKOUT AC18 O OCDS Break Output
A low level on this pin indicates that a programmable OCDS
event has occurred.
NMI4) Y20 I Non-Maskable Interrupt Input
A high-to-low transition on this pin causes a NMI-Trap
request to the CPU.
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 18 V1.2, 2002-05
Preliminary
HDRST4) W20 I/O Hardware Reset Input/Reset Indication Output
Assertion of this bidirectional open-drain pin causes a
synchronous reset of the chip through external circuitry. This
pin must be driven for a minimum duration.
The internal reset circuitry drives this pin in response to a
power-on, hardware, watchdog and power-down wake-up
reset for a specific period of time. For a software reset,
activation of this pin is programmable.
PORST5) Y21 I Power-on Reset Input
A low level on PORST causes an asynchronous reset of the
entire chip. PORST is a fully asynchronous level sensitive
signal.
CLKIN T1 I EBU Clock Input
CLKIN must be connected externally with CLKOUT. For fine-
tuning of the external bus interface timing, this external
connection can be an external delay circuit.
CLKOUT R1 O Clock Output
TEST
MODE4) AB23 I Test Mode Select Input
For normal operation of the TC1775, this pin should be
connected to VDDP05.
XTAL1
XTAL2
AC23
AC22
I
O
Oscillator/PLL/Clock Generator Input/Output Pins
XTAL1 is the input to the main oscillator amplifier and input
to the internal clock generator. XTAL2 is the output of the
main oscillator amplifier circuit. For clocking the device from
an external source, XTAL1 is driven with the clock signal
while XTAL2 is left unconnected. For crystal oscillator
operation XTAL1 and XTAL2 are connected to the crystal
with the appropriate recommended oscillator circuitry.
XTAL3
XTAL4
AB21
AA20
I
O
Real Time Clock Oscillator Input/Output
XTAL3 and XTAL4 are the input and the output of the 32 kHz
oscillator that is used for the Real Time Clock.
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 19 V1.2, 2002-05
Preliminary
VDDOSC AC21 – Main Oscillator Power Supply (2.5 V)6)7)
VSSOSC AA21 – Main Oscillator Ground
VDDPLL AA22 – PLL Power Supply (2.5 V)6)7)
VSSPLL AA23 – PLL Ground
VSS F4, Y6,
V20,
D18,
K10
to
K14,
L10
to
L14,
M10
to
M14,
N10
to
N14,
P10
to
P14
–Ground
VDD K4, P4
V4, D6
Y10
D14
Y18
F20
K20
P20
–Core Power Supply (2.5 V)6)7)
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 20 V1.2, 2002-05
Preliminary
VDDP05 H4
M4
T4
Y8
Y12
–Ports 0 to 5 Power Supply (2.5 V)6)7)
VDDP813 D8
D12
D16
H20
M20
T20
–Port 8-13 and Dedicated Pins Power Supply (3.3 to 5 V)8)
VDDSRAM AC17,
AB18
–SRAM (RAMs of DMU, PMU, and PCP) Power Supply
(2.5 V)7)
VDDSB B14 – Stand-by Power Supply of 8 Kbyte SBSRAM (2.5 V)7)
VDDSC A1 – ADC Short Circuit/Broken Wire Logic Power Supply
(5 V)8)
VSSSC A2 – ADC Short Circuit/Broken Wire Logic Ground
VDDM C3 – ADC Analog Part Power Supply (5 V)8)
VSSM A3 – ADC Analog Part Ground
VDDA0 D9 – ADC0 Analog Part Power Supply (2.5 V)6)7)
VSSA0 A9 – ADC0 Analog Part Ground for VDDA0
VDDA1 H1 – ADC1 Analog Part Power Supply (2.5 V)6)7)
VSSA1 G3 – ADC1 Analog Part Ground for VDDA1
VAREF0 C8 – ADC0 Reference Voltage8)
VAGND0 B8 – ADC0 Reference Ground
VAREF1 G2 – ADC1 Reference Voltage8)
VAGND1 G4 – ADC1 Reference Ground
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 21 V1.2, 2002-05
Preliminary
N.C.1 AB15,
D10,
Y14
–Not Connected 1
These pins must not be connected.
N.C.2 AB22,
C14,
K3,
AC3,
L4,
D21,
Y16
–Not Connected 2
For compatibility reasons, these pins should not be
connected. Any connection to 5 V does not harm the device.
1) After reset, an internal pull-up device is enabled for this pin.
2) After reset, an internal pull-down device is enabled for this pin.
3) These pins have an internal pull-down device connected.
4) These pins have an internal pull-up device connected.
5) The TC1775 BA11 step has an internal pull-up device connected to this pin.
6) The voltage on power supply pins marked with 8) has to be raised earlier or at least at the same time as on
power supply pins marked with 6) (details see power supply section on Page 62).
7) In order to minimize the danger of latch-up conditions, these 2.5 V VDD power supply pins should be kept at
the same voltage level during normal operating mode. This condition is best achieved by generating the 2.5 V
power supplies from a single voltage source. The condition is also valid in normal operating mode if a separate
stand-by power supply VDDSB is used.
8) The voltage on power supply pins marked with 8) has to be raised earlier or at least at the same time as on
power supply pins marked with 6) (details see power supply section on Page 62).
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1775
Data Sheet 22 V1.2, 2002-05
Preliminary
Parallel Ports
The TC1775 has 196 digital input/output port lines, which are organized into twelve
parallel 16-bit ports, Port 0 to Port 5 with 2.5 V nominal voltage (pin class B), and Port 8
to Port 13 with 3.0 to 5.25 V voltage (pin class A). Additionally, 32 analog input port lines
are available, which are organized into two parallel 16-bit ports, Port 6 and Port 7.
The digital parallel ports can be all used as general purpose I/O lines or they can perform
input/output functions for the on-chip peripheral units.
Port 0 to Port 5 are especially dedicated for the on-chip External Bus Interface Unit to
communicate with external memories, external peripherals, or external debugging
devices via an external bus interface. Port 8 to Port 13 can be assigned to the on-chip
peripheral units for their specific I/O operations. An overview on the port-to-peripheral
unit assignment is shown in Figure 4.
Note: For further details on the three pin classes of the TC1775 I/O pins see also
Table 10 on Page 64:
Figure 4 Parallel Ports of the TC1775
MCA04734
TC 1775
Parallel
Ports
Port 8
Port 9
Port 10
Port 11
Port 12
Port 13
GPIO Alternate Functions
GPTA
GPTA
GPTA
GPTA
ADC0/1 / ASC0/1 / SDLM
SSC0/1 / ASC0/1 /
GPTU / CAN
Port 1
Port 0
Port 2
Port 3
Port 4
Port 5
GPIOAlternate Functions
OCDS Trace Lines
Bus Control Lines
Address Bus
Bus Control Lines
Address Bus
Address/Data Bus
Address/Data Bus
ADC0 ADC1
Port 6 Port 7
TC1775
Data Sheet 23 V1.2, 2002-05
Preliminary
Serial Interfaces
The TC1775 includes six serial peripheral interface units:
– Two Asynchronous/Synchronous Serial Interfaces (ASC0 and ASC1)
– Two High-Speed Synchronous Serial Interfaces (SSC0 and SSC1)
– One TwinCAN Interface
– One J1850 Serial Data Link Interface (SDLM)
Asynchronous/Synchronous Serial Interfaces
Figure 5 shows a global view of the functional blocks of the two Asynchronous/
Synchronous Serial interfaces ASC0 and ASC1.
Figure 5 General Block Diagram of the ASC Interfaces
MCB04485
Clock
Control
Address
Decoder
Interrupt
Control
f
ASC0
ASC0
Module
(Kernel)
Port 12
&
Port 13
Control
P12.12 /
RXD0A
RXD0
TXD0
P12.13 /
TXD0A
P13.3 /
TXD0B
P13.2 /
RXD0B
Clock
Control
Address
Decoder
Interrupt
Control
f
ASC1
ASC1
Module
(Kernel)
RXD1
TXD1
P12.14 /
RXD1A
P12.15 /
TXD1A
P13.5 /
TXD1B
P13.4 /
RXD1B
TC1775
Data Sheet 24 V1.2, 2002-05
Preliminary
Each ASC module, ASC0 and ASC1, communicates with the external world via two pairs
of two I/O lines each. The RXD line is the receive data input signal (in Synchronous Mode
also output). TXD is the transmit output signal. Clock control, address decoding, and
interrupt service request control are managed outside the ASC module kernel.
The Asynchronous/Synchronous Serial Interfaces provide serial communication
between the TC1775 and other microcontrollers, microprocessors or external
peripherals.
The ASC supports full-duplex asynchronous communication and half-duplex
synchronous communication. In Synchronous Mode, data is transmitted or received
synchronous to a shift clock which is generated by the ASC internally. In Asynchronous
Mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be
selected. Parity, framing, and overrun error detection are provided to increase the
reliability of data transfers. Transmission and reception of data are double-buffered. For
multiprocessor communication, a mechanism is included to distinguish address bytes
from data bytes. Testing is supported by a loop-back option. A 13-bit baud rate generator
provides the ASC with a separate serial clock signal that can be very accurately adjusted
by a prescaler implemented as a fractional divider.
Features:
• Full duplex asynchronous operating modes
– 8-bit or 9-bit data frames, LSB first
– Parity bit generation/checking
– One or two stop bits
– Baud rate from 2.5 Mbit/s to 0.6 Bit/s (@ 40 MHz clock)
– Multiprocessor mode for automatic address/data byte detection
– Loop-back capability
• Half-duplex 8-bit synchronous operating mode
– Baud rate from 5 Mbit/s to 406.9 Bit/s (@ 40 MHz clock)
• Double buffered transmitter/receiver
• Interrupt generation
– On a transmitter buffer empty condition
– On a transmit last bit of a frame condition
– On a receiver buffer full condition
– On an error condition (frame, parity, overrun error)
• Two pin pairs RXD/TXD for each ASC available at Port 12 or Port 13
TC1775
Data Sheet 25 V1.2, 2002-05
Preliminary
High-Speed Synchronous Serial Interfaces
Figure 6 shows a global view of the functional blocks of the two High-Speed
Synchronous Serial interfaces SSC0 and SSC1.
Figure 6 General Block Diagram of the SSC Interfaces
Each of the SSC modules has three I/O lines, located at Port 13. Each of the SSC
modules is further supplied by separate clock control, interrupt control, address
decoding, and port control logic.
The SSC supports full-duplex and half-duplex serial synchronous communication up to
20 Mbit/s (@ 40 MHz module clock). The serial clock signal can be generated by the
SSC itself (master mode) or can be received from an external master (slave mode). Data
width, shift direction, clock polarity, and phase are programmable. This allows
communication with SPI-compatible devices. Transmission and reception of data are
double-buffered. A 16-bit baud rate generator provides the SSC with a separate serial
clock signal.
MCB04486
Clock
Control
Address
Decoder
Interrupt
Control
f
SSC0
SSC0
Module
(Kernel)
Port
Control
P13.8 /
MTSR0
P13.7 /
MRST0
P13.6 /
SCLK0
Clock
Control
Address
Decoder
Interrupt
Control
f
SSC1
SSC1
Module
(Kernel)
RXD
TXD
Master
RXD
TXD
Slave
Slave
Master
SCLK
P13.11 /
MTSR1
P13.10 /
MRST1
P13.9 /
SCLK1
RXD
TXD
Master
RXD
TXD
Slave
Slave
Master
SCLK
TC1775
Data Sheet 26 V1.2, 2002-05
Preliminary
Features:
• Master and slave mode operation
– Full-duplex or half-duplex operation
• Flexible data format
– Programmable number of data bits: 2 to 16 bit
– Programmable shift direction: LSB or MSB shift first
– Programmable clock polarity: idle low or high state for the shift clock
– Programmable clock/data phase: data shift with leading or trailing edge of the shift
clock
• Baud rate generation from 20 Mbit/s to 305.18 Bit/s (@ 40 MHz module clock)
• Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baud rate, transmit error)
• Three-pin interface
– Flexible SSC pin configuration
TC1775
Data Sheet 27 V1.2, 2002-05
Preliminary
TwinCAN Interface
Figure 7 shows a global view of the functional blocks of the TwinCAN module.
Figure 7 General Block Diagram of the TwinCAN Module
The TwinCAN module has four I/O lines located at Port 13. The TwinCAN module is
further supplied by a clock control, interrupt control, address decoding, and port control
logic.
The TwinCAN module contains two Full-CAN nodes operating independently or
exchanging data and remote frames via a gateway function. Transmission and reception
of CAN frames are handled in accordance to CAN specification V2.0 part B (active).
Each of the two Full-CAN interfaces can receive and transmit standard frames with 11-bit
identifiers as well as extended frames with 29-bit identifiers.
Both CAN nodes share the TwinCAN module’s resources to optimize the CAN bus traffic
handling and to minimize the CPU load. The flexible combination of Full-CAN
functionality and the FIFO architecture reduces the efforts to fulfill the real-time
requirements of complex embedded control applications. Improved CAN bus monitoring
functionality as well as the increased number of message objects permit precise and
convenient CAN bus traffic handling.
Depending on the application, each of the thirty-two message objects can be individually
assigned to one of the two CAN nodes. Gateway functionality allows automatic data
exchange between two separate CAN bus systems to reduce CPU load and improve the
real time behavior of the entire system.
MCB04674
Clock
Control
Address
Decoder
Interrupt
Control
SR1
SR2
f
CAN
SR3
SR0
TwinCAN Module Kernel
Port
Control
P13.13 /
TXDCAN0
P13.12 /
RXDCAN0
SR7
SR6
SR5
P13.15 /
TXDCAN1
P13.14 /
RXDCAN1
Bitstream
Processor
Interrupt
Control
SR4
TXDC0
RXDC0
TXDC1
RXDC1
Timing
Control
Error
Handling
Control
Message
Buffers
TC1775
Data Sheet 28 V1.2, 2002-05
Preliminary
The bit timings for both CAN nodes are derived from the peripheral clock (fCAN) and are
programmable up to a data rate of 1 Mbit/s. A pair of receive and transmit pins connect
each CAN node to a bus transceiver.
Features:
• Full CAN functionality conforms to CAN specification V2.0 B active
• Dedicated control registers are provided for each CAN node
• A data transfer rate up to 1 Mbit/s is supported
• Flexible and powerful message transfer control and error handling capabilities are
implemented
• Full-CAN functionality: 32 message objects can be individually
– Assigned to one of the two CAN nodes
– Configured as transmit or receive objects
– Participate in a 2, 4, 8, 16 or 32 message buffer with FIFO algorithm
– Setup to handle frames with 11-bit or 29-bit identifiers
– Provided with programmable acceptance mask register for filtering
– Monitored via a frame counter
– Configured to Remote Monitoring Mode
• Up to eight individually programmable interrupt nodes can be used
• CAN Analyzer Mode for bus monitoring is implemented
TC1775
Data Sheet 29 V1.2, 2002-05
Preliminary
Serial Data Link Interface
Figure 8 shows a global view of the functional blocks of the Serial Data Link Interface
(SDLM).
Figure 8 General Block Diagram of the SDLM Interface
The SDLM module communicates with the external world via two I/O lines located at
Port 12, the J1850 bus. The RXD line is the receive data input signal and TXD is the
transmit data output signal.
The Serial Data Link module (SDLM) provides serial communication to a J1850 based
serial bus. J1850 bus transceivers must be implemented externally in a system. The
SDLM module conforms to the SAE Class B J1850 Specification and is compatible to
Class 2 protocol.
General SDLM Features:
• Compliant to SAE Class B J1850 Specification
• Full support of GM Class 2 protocol
• Variable Pulse Width (VPW) format with 10.4 kbit/s
• High speed receive/transmit 4x mode with 41.6 kbit/s
• Digital noise filter
• Support of single byte headers or consolidated headers
• CRC generation and check
• Support of Block Mode for receive and transmit
MCB04570
Clock
Control
Address
Decoder
Interrupt
Control
f
SDLM
SDLM
Module
(Kernel)
Port
Control
P12.10 /
RXJ1850
RXD
TXD P12.11 /
TXJ1850
TC1775
Data Sheet 30 V1.2, 2002-05
Preliminary
Data Link Operation Features:
• 11-byte transmit buffer
• Double buffered 11-byte receive buffer
• Support of In-Frame Response (IFR) types 1, 2, 3
• Advanced interrupt handling for RX, TX, and error conditions
• All interrupt sources can be enabled/disabled individually
• Support of automatic IFR Transmission for IFR types 1 and 2 for 3-byte consolidated
headers
Note: The SDLM module does not support the Pulse Width Modulation (PWM) data
format.
TC1775
Data Sheet 31 V1.2, 2002-05
Preliminary
Timer Units
The TC1775 includes two timer units:
– General Purpose Timer Unit (GPTU)
– General Purpose Timer Array (GPTA)
General Purpose Timer Unit
Figure 9 shows a global view of all functional blocks of the General Purpose Timer Unit
(GPTU) module.
Figure 9 General Block Diagram of the GPTU Interface
The GPTU consists of three 32-bit timers designed to solve such application tasks as
event timing, event counting, and event recording. The GPTU communicates with the
external world via eight inputs and eight outputs located at Port 13.
The three timers of the GPTU module (T0, T1, and T2) can operate independently from
each other, or can be combined:
General Features:
• All timers are 32-bit precision timers with a maximum input frequency of fGPTU
• Events generated in T0 or T1 can be used to trigger actions in T2
• Timer overflow or underflow in T2 can be used to clock either T0 or T1
• T0 and T1 can be concatenated to form one 64-bit timer
MCB04489
Clock
Control
Address
Decoder
Interrupt
Control
SR1
SR2
f
GPTU
SR3
SR0
GPTU
Module
(Kernel)
Port
Control
P13.1 / GPT1
SR7
SR6
SR5
SR4
IN1
IN2
IN3
IN0
IN7
IN6
IN5
IN4
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
IO1
P13.7 / GPT7
IO7
IO0 P13.0 / GPT0
IO2 P13.2 / GPT2
IO3 P13.3 / GPT3
P13.4 / GPT4
IO4
IO5 P13.5 / GPT5
IO6 P13.6 / GPT6
TC1775
Data Sheet 32 V1.2, 2002-05
Preliminary
Features of T0 and T1:
• Each timer has a dedicated 32-bit reload register with automatic reload on overflow
• Timers can be split into individual 8-, 16-, or 24-bit timers with individual reload
registers
• Overflow signals can be selected to generate service requests, pin output signals, and
T2 trigger events
• Two input pins can define a count option
Features of T2:
• Count up or down is selectable
• Operating modes:
–Timer
– Counter
– Quadrature counter (incremental/phase encoded counter interface)
• Options:
– External start/stop, one-shot operation, timer clear on external event
– Count direction control through software or an external event
– Two 32-bit reload/capture registers
• Reload modes:
– Reload on overflow or underflow
– Reload on external event: positive transition, negative transition, or both transitions
• Capture modes:
– Capture on external event: positive transition, negative transition, or both
transitions
– Capture and clear timer on external event: positive transition, negative transition, or
both transitions
• Can be split into two 16-bit counter/timers
• Timer count, reload, capture, and trigger functions can be assigned to input pins. T0
and T1 overflow events can also be assigned to these functions
• Overflow and underflow signals can be used to trigger T0 and/or T1 and to toggle
output pins
• T2 events are freely assignable to the service request nodes
TC1775
Data Sheet 33 V1.2, 2002-05
Preliminary
General Purpose Timer Array
Figure 10 shows a global block diagram of the General Purpose Timer Array (GPTA)
implementation.
Figure 10 GPTA Module Block Diagram
The GPTA module has 64 input lines and 64 output lines, which are connected with
Port 8, Port 9, Port 10, and Port 11.
The General Purpose Timer Array (GPTA) provides important digital signal filtering and
timer support whose combination enables autonomous and complex functionalities. This
architecture allows easy implementation and easy validation of any kind of timer
functions.
MCB04490
Clock
Control
Address
Decoder
A/D
Converter
PTIN01
PTIN10
f
GPTA
PTIN11
PTIN00
Interrupt
Control
SR01
SR52
SR53
SR00 Port
Control
IO62
IO63
P11.0
P11.1
P11.14
P11.15
GPTA Module Kernel
Clock Generation Unit
Filter &
Prescaler
Cells
Phase
Discriminator
Logic
Duty Cycle
Measurement Digital Phase
Locked Loop
Interrupt Control Unit
IO Sharing Unit with Emergency Shut-Off
Signal Generation Unit
Global
Timers
Global Timer
Cells Local Timer
Cells
OUT62
OUT63
IO48
IO49
IO46
IO47
P10.0
P10.1
P10.14
P10.15
IO32
IO33
IO30
IO31
P9.0
P9.1
P9.14
P9.15
IO16
IO17
IO14
IO15
P8.0
P8.1
P8.14
P8.15
IO0
IO1
IN0
IN1
OUT0
OUT1
IN63
IN62
AS0
AS1
AS62
AS63
TC1775
Data Sheet 34 V1.2, 2002-05
Preliminary
The General Purpose Timer Array (GPTA) provides a set of hardware modules required
for high speed digital signal processing:
• Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation.
• Phase Discrimination Logic units (PDL) decode the direction information output by a
rotation tracking system.
• Duty Cycle Measurement Cells (DCM) provide pulse width measurement capabilities.
• A Digital Phase Locked Loop unit (PLL) generates a programmable number of GPTA
module clock ticks during an input signal’s period.
• Global Timer units (GT) driven by various clock sources are implemented to operate
as a time base for the associated “Global Timer Cells”.
• Global Timer Cells (GTC) can be programmed to capture the contents of a Global
Timer on an event that occurred at an external port pin or at an internal FPC output.
A GTC may be also used to control an external port pin with the result of an internal
compare operation. GTCs can be logically concatenated to provide a common
external port pin with a complex signal waveform.
• Local Timer Cells (LTC) operating in Timer, Capture, or Compare Mode may be also
logically tied together to drive a common external port pin with a complex signal
waveform. LTCs — enabled in Timer Mode or Capture Mode — can be clocked or
triggered by
– A prescaled GPTA module clock,
– An FPC, PDL, DCM, PLL, or GTC output signal line,
– An external port pin.
Some input lines driven by processor I/O pads may be shared by an LTC and a GTC to
trigger their programmed operation simultaneously.
The following list summarizes all blocks supported:
Clock Generation Unit (GPTA)
• Filter and Prescaler Cell (FPC):
– Six independent units
– Three operating modes (Prescaler, Delayed Debounce Filter, Immediate Debounce
Filter)
–fGPTA down-scaling capability
–fGPTA/2 maximum input signal frequency in Filter Mode
• Phase Discriminator Logic (PDL):
– Two independent units
– Two operating modes (2 and 3 sensor signals)
–fGPTA/4 maximum input signal frequency in 2-sensor mode, fGPTA/6 maximum input
signal frequency in 3-sensor mode
• Duty Cycle Measurement (DCM):
– Four independent units
– 0 to 100% margin and time-out handling
TC1775
Data Sheet 35 V1.2, 2002-05
Preliminary
–fGPTA maximum resolution
–fGPTA/2 maximum input signal frequency
• Digital Phase Locked Loop (PLL):
– One unit
– Arbitrary multiplication factor between 1 and 65535
–fGPTA maximum resolution
–fGPTA/2 maximum input signal frequency
GPTA Signal Generation Unit
• Global Timers (GT):
– Two independent units
– Two operating modes (Free Running Timer and Reload Timer)
– 24-bit data width
–fGPTA maximum resolution
–fGPTA/2 maximum input signal frequency
• Global Timer Cell (GTC):
– 32 independent units
– Two operating modes (Capture, Compare and Capture after Compare)
– 24-bit data width
–fGPTA maximum resolution
–fGPTA/2 maximum input signal frequency
• Local Timer Cell (LTC):
– 64 independent units
– Three operating modes (Timer, Capture and Compare)
– 16-bit data width
–fGPTA maximum resolution
–fGPTA/2 maximum input signal frequency
Interrupt Control Unit
• 111 interrupt sources generating 54 service requests
I/O Sharing Unit
• Able to process lines from FPC, GTC, and LTC
• Emergency function
TC1775
Data Sheet 36 V1.2, 2002-05
Preliminary
Analog Digital Converters
The two on-chip Analog-to-Digital Converter (ADC) modules of the TC1775 offer 8-bit,
10-bit, or 12-bit resolution including sample-and-hold functionality. The A/D converters
operate using the method of the successive approximation. A multiplexer selects among
up to 16 analog input channels for each ADC. Conversion requests are generated either
under software control or by hardware. An automatic self-calibration adjusts the ADC
modules to changing temperatures or process variations.
Features:
• 8-bit, 10-bit, 12-bit A/D conversion
• Successive approximation conversion method
• Fast conversion times: e.g. 10-bit conversion (without sample time): 5.05 µs
• Total Unadjusted Error (TUE) of ±2 LSB @ 10-bit resolution
• Integrated sample-and-hold functionality
• Sixteen analog input channels
• Dedicated control and status registers for each analog channel
• Powerful conversion request sources
• Selectable reference voltages for each channel
• Programmable sample and conversion timing schemes
• Limit checking
• Broken wire – short circuit detection
• Flexible service request generation
• Synchronization of the two on-chip A/D Converters
• Automatic control of external analog multiplexer
• Equidistant samples initiated by timer
• External trigger inputs for conversion requests
• Two external trigger inputs, connected with the General Purpose Timer Array (GPTA)
• Power reduction and clock control
Figure 11 shows a global view of the ADC module kernels with the module specific
interface connections.
Each of the ADC modules communicates with the external world via five digital I/O lines
and sixteen analog inputs. Clock control, address decoding, and interrupt service
request control are managed outside the ADC module kernel. Two trigger inputs and a
synchronization bridge are used for internal control purposes.
TC1775
Data Sheet 37 V1.2, 2002-05
Preliminary
Figure 11 ADC0/ADC1 Modules with Interconnections
MCB04491
Clock
Control
Address
Decoder
Interrupt
Control
SR1
SR2
f
ADC0
SR3
GPTA
PTIN00
SR0
PTIN01
ADC0
Module
Kernel
Synchronization Bridge
ADC1
Module
Kernel
PTIN10
PTIN11
Clock
Control
Address
Decoder
Interrupt
Control
SR1
SR2
f
ADC1
SR3
SR0
Port
Control
P12.8 /
AD0EXTIN0
P12.9 /
AD0EXTIN1
P12.0 /
AD0EMUX0
P12.1 /
AD0EMUX1
P12.2 /
AD0EMUX2
P6.0 / AN0
P6.1 / AN1
P6.14 / AN14
P6.15 / AN15
Port
Control
P12.6 /
AD1EXTIN0
P12.7 /
AD1EXTIN1
P12.3 /
AD1EMUX0
P12.4 /
AD1EMUX1
P12.5 /
AD1EMUX2
P7.0 / AN16
P7.1 / AN17
P7.14 / AN30
P7.15 / AN31
V
AGND0
V
SSA0
V
DDA0
V
DDM
V
AREF0
V
SSM
V
AGND1
V
SSA1
V
DDA1
V
DDM
V
AREF1
V
SSM
AIN15
AIN14
AIN0
AIN1
AIN15
AIN14
AIN0
AIN1
TC1775
Data Sheet 38 V1.2, 2002-05
Preliminary
On-Chip Memories
The memory system of the TC1775 provides the following memories:
• Program Memory Unit (PMU) with
– 8 Kbytes Boot ROM (BROM)
– 32 Kbytes Code Scratch-Pad RAM (SPRAM)
– 1 Kbyte Instruction Cache (ICACHE)
• Data Memory Unit (DMU) with
– 40 Kbytes Data Memory (SRAM)
– Includes 8 Kbytes static RAM (SBSRAM) for standby operation using a battery
• Peripheral Control Processor (PCP) with
– 16 Kbytes Data Memory (PCODE)
– 4 Kbytes Parameter RAM (PRAM)
TC1775
Data Sheet 39 V1.2, 2002-05
Preliminary
Address Map
Table 2 defines the specific segment oriented address blocks of the TC1775 with its
address range, size, and PMU/DMU access view. Table 3 shows the block address map
of memory segment 15 which includes the on-chip peripheral units.
Table 2 TC1775 Block Address Map
Seg-
ment
Address
Range
Size Description DMU
Acc.
PMU
Acc.1)
0 to 7 0000 0000H –
7FFF FFFFH
2 GB Reserved – –
8 8000 0000H –
8FFF FFFFH
256 MB Reserved via
FPI
PMU
local
cached
9 9000 0000H –
9FFF FFFFH
256 MB Reserved DMU
local
via
FPI
10 A000 0000H –
AFFF FFFFH
256 MB External Memory Space via
FPI
via
EBU or
FPI
11
B000 0000H –
BDFF FFFFH
224 MB External Memory Space
mappable into segment 10
via
FPI
via
EBU
non-cached
BE00 0000H –
BEFF FFFFH
16 MB External Emulator Space via
FPI
BF00 0000H –
BFFF DFFFH
– Reserved
PMU
local
BFFF E000H –
BFFF FFFFH
8 KB Boot ROM
4 Kbytes general purpose
4 Kbytes factory test support
12
C000 0000H –
C000 7FFFH
32 KB Local Code Scratch-Pad RAM
(SPRAM)
via
FPI
PMU
local
C000 8000H –
C7FF FEFFH
– Reserved
C7FF FF00H –
C7FF FFFFH
256 B PMU Control Registers
C800 0000H –
CFFF FFFFH
128 MB Reserved
TC1775
Data Sheet 40 V1.2, 2002-05
Preliminary
13
D000 0000H –
D000 7FFFH
32 KB Local Data Memory (SRAM)
DMU
local
via
FPI
non-cached
D000 8000H –
D000 9FFFH
8 KB Local Data Memory for standby
operation (SBSRAM)
D000 A000H –
D000 BFFFH
8 KB SBSRAM mirrored
D000 C000H –
D000 DFFFH
8 KB SBSRAM mirrored
D000 E000H –
D000 FFFFH
8 KB SBSRAM mirrored
D000 A000H –
D7FF FEFFH
– Reserved
D7FF FF00H –
D7FF FFFFH
256 B DMU Registers
D800 0000H –
DFFF FFFFH
256 MB Reserved
14 E000 0000H –
EFFF FFFFH
256 MB External Peripheral and
Data Memory Space
via
FPI
not
possi-
ble
Table 2 TC1775 Block Address Map (cont’d)
Seg-
ment
Address
Range
Size Description DMU
Acc.
PMU
Acc.1)
TC1775
Data Sheet 41 V1.2, 2002-05
Preliminary
15
F000 0000H –
F000 3EFFH
16 KB On-Chip Peripherals & Ports
via
FPI
not
possi-
ble
non-cached
F000 3F00H –
F000 3FFFH
256 B PCP Registers
F000 4000H –
F000 FFFFH
– Reserved
F001 0000H –
F001 0FFFH
4 KB PCP Parameter Memory
(PRAM)
F001 1000H –
F001 FFFFH
– Reserved
F002 0000H –
F002 3FFFH
16 KB PCP Code Memory
(PCODE)
F002 4000H –
F00F FFFFH
– Reserved
F010 0000H –
F010 0BFFH
12 ×
256 B
CAN Module
F010 0C00H –
FFFE FEFFH
– Reserved
FFFE FF00H –
FFFE FFFFH
256 B CPU Slave Interface Registers
(CPS)
FFFF 0000H –
FFFF FFFFH
64 KB Core SFRs + GPRs
1) The PMU can access external memory directly (“via EBU”, only instruction accesses) or via the FPI Bus (“via
FPI”).
Table 2 TC1775 Block Address Map (cont’d)
Seg-
ment
Address
Range
Size Description DMU
Acc.
PMU
Acc.1)
TC1775
Data Sheet 42 V1.2, 2002-05
Preliminary
Table 3 Block Address Map of Segment 15
Symbol Description Address Range Size
SCU System Control Unit F000 0000H – F000 00FFH256 Bytes
RTC Real Time Clock F000 0100H – F000 01FFH256 Bytes
BCU Bus Control Unit F000 0200H – F000 02FFH256 Bytes
STM System Timer F000 0300H – F000 03FFH256 Bytes
OCDS On-Chip Debug Support F000 0400H – F000 04FFH256 Bytes
EBU External Bus Unit F000 0500H – F000 05FFH256 Bytes
– Reserved F000 0600H – F000 06FFH–
GPTU General Purpose Timer Unit F000 0700H – F000 07FFH256 Bytes
ASC0 Async./Sync. Serial Interface 0 F000 0800H – F000 08FFH256 Bytes
ASC1 Async./Sync. Serial Interface 1 F000 0900H – F000 09FFH256 Bytes
SSC0 High-Speed Synchronous
Serial Interface 0
F000 0A00H – F000 0AFFH256 Bytes
SSC1 High-Speed Synchronous
Serial Interface 1
F000 0B00H – F000 0BFFH256 Bytes
– Reserved F000 0C00H – F000 17FFH–
GPTA General Purpose Timer Array F000 1800H – F000 1FFFH8 × 256 Bytes
– Reserved F000 2000H – F000 21FFH–
ADC0 Analog-to-Digital Converter 0 F000 2200H – F000 23FFH512 Bytes
ADC1 Analog-to-Digital Converter 1 F000 2400H – F000 25FFH512 Bytes
SDLM Serial Data Link Module F000 2600H – F000 26FFH256 Bytes
– Reserved F000 2700H – F000 27FFH–
P0 Port 0 F000 2800H – F000 28FFH256 Bytes
P1 Port 1 F000 2900H – F000 29FFH256 Bytes
P2 Port 2 F000 2A00H – F000 2AFFH256 Bytes
P3 Port 3 F000 2B00H – F000 2BFFH256 Bytes
P4 Port 4 F000 2C00H – F000 2CFFH256 Bytes
P5 Port 5 F000 2D00H – F000 2DFFH256 Bytes
P6 Port 6 (no registers available) F000 2E00H – F000 2EFFH256 Bytes
P7 Port 7 (no registers available) F000 2F00H – F000 2FFFH256 Bytes
P8 Port 8 F000 3000H – F000 30FFH256 Bytes
P9 Port 9 F000 3100H – F000 31FFH256 Bytes
TC1775
Data Sheet 43 V1.2, 2002-05
Preliminary
P10 Port 10 F000 3200H – F000 32FFH256 Bytes
P11 Port 11 F000 3300H – F000 33FFH256 Bytes
P12 Port 12 F000 3400H – F000 34FFH256 Bytes
P13 Port 13 F000 3500H – F000 35FFH256 Bytes
– Reserved F000 3600H – F000 3EFFH–
PCP PCP Registers F000 3F00H – F000 3FFFH256 Bytes
Reserved F000 4000H – F000 FFFFH–
PCP Data Memory (PRAM) F001 0000H – F001 0FFFH4 Kbytes
Reserved F001 1000H – F001 FFFFH–
PCP Code Memory (PCODE) F002 0000H – F002 3FFFH16 Kbytes
– Reserved F002 4000H – F00F FFFFH–
CAN1) Controller Area Network
Module
F010 0000H – F010 0BFFH12 ×256 Bytes
– Reserved F010 0C00H – FFFE FEFFH–
CPU Slave Interface Registers
(CPS)
FFFE FF00H – FFFE FFFFH256 Bytes
Reserved FFFF 0000H – FFFF BFFFH–
Memory Protection Registers FFFF C000H – FFFF EFFFH12 Kbytes
Reserved FFFF F000H – FFFF FCFFH–
Core Debug Register (OCDS) FFFF FD00H – FFFF FDFFH256 Bytes
Core Special Function
Registers (CSFRs)
FFFF FE00H – FFFF FEFFH256 Bytes
General Purpose Register
(GPRs)
FFFF FF00H – FFFF FFFFH256 Bytes
1) Access to unused address regions within this peripheral unit don’t generate a bus error.
Table 3 Block Address Map of Segment 15 (cont’d)
Symbol Description Address Range Size
TC1775
Data Sheet 44 V1.2, 2002-05
Preliminary
Memory Protection System
The TC1775 memory protection system specifies the addressable range and read/write
permissions of memory segments available to the currently executing task. The memory
protection system controls the position and range of addressable segments in memory.
It also controls the kinds of read and write operations allowed within addressable
memory segments. Any illegal memory access is detected by the memory protection
hardware, which then invokes the appropriate Trap Service Routine (TSR) to handle the
error. Thus, the memory protection system protects critical system functions against both
software and hardware errors. The memory protection hardware can also generate
signals to the Debug Unit to facilitate tracing illegal memory accesses.
There are two Memory Protection Register Sets in the TC1775, numbered 0 and 1,
which specify memory protection ranges and permissions for code and data. The
PSW.PRS bit field determines which of these is the set currently in use by the CPU.
Because the TC1775 uses a Harvard-style memory architecture, each Memory
Protection Register Set is broken down into a Data Protection Register Set and a Code
Protection Register Set. Each Data Protection Register Set can specify up to four
address ranges to receive particular protection modes. Each Code Protection Register
Set can specify up to two address ranges to receive particular protection modes.
Each of the Data Protection Register Sets and Code Protection Register Sets
determines the range and protection modes for a separate memory area. Each contains
register pairs which determine the address range (the Data Segment Protection
Registers and Code Segment Protection Registers) and one register (Data Protection
Mode Register) which determines the memory access modes which apply to the
specified range.
TC1775
Data Sheet 45 V1.2, 2002-05
Preliminary
On-Chip FPI Bus
The FPI Bus interconnects the functional units of the TC1775, such as the CPU and
on-chip peripheral components. The FPI Bus also interconnects the TC1775 to external
components by way of the External Bus Controller Unit (EBU). The FPI Bus is designed
to be quick to acquire by on-chip functional units, and quick to transfer data. The low
setup overhead of the FPI Bus access protocol guarantees fast FPI Bus acquisition,
which is required for time-critical applications. The FPI Bus is designed to sustain high
transfer rates. For example, a peak transfer rate of up to 160 Mbyte/s can be achieved
with a 40 MHz bus clock and 32-bit data bus. Multiple data transfers per bus arbitration
cycle allow the FPI Bus to operate at close to its peak bandwidth.
Features:
• Supports multiple bus masters
• Supports demultiplexed address/data operation
• Address and data buses are 32 bits wide
• Data transfer types include 8-, 16-, and 32-bit sizes
• Single- and multiple-data transfers per bus acquisition cycle
• Designed to minimize EMI and power consumption
TC1775
Data Sheet 46 V1.2, 2002-05
Preliminary
External Bus Unit
The External Bus Unit (EBU) of the TC1775 is the interface between external memories
and peripheral units and the internal memories and peripheral units. The basic structure
of the EBU is shown in Figure 12.
Figure 12 EBU Structure and Interfaces
The EBU is primarily used for the following two operations:
• Communication with external memories or peripheral units via the FPI Bus
• Instruction fetches from the PMU to external Burst Flash program memories
The EBU controls all transactions required for these two operations and in particular
handles the arbitration between these two tasks.
The types of external devices/bus modes controlled by the EBU are:
• INTEL style peripherals (separate RD and WR signals)
• ROMs, EPROMs
• Static RAMs
• Demultiplexed A/D bus
• Multiplexed A/D bus
The PMU controls accesses to external code memories. It especially supports:
– Burst Mode Flash Memories (ROM)
Note: Instruction fetches of the PMU from external Burst Flash program memories are
only possible with 32-bit data bus width.
MCA04753
TriCore
CPU
PMU
with on-chip
Program Memory
DMU
with on-chip
Data Memory
EBU
Port 4
Port 3
Port 2
Port 1
Port 0
Control
Lines
A[25:16] and
Chip Select
A[15:0]
AD[31:16]
AD[15:0]
FPI Bus
Burst Mode
Instruction
Fetches
To Peripheral
Units and PCP
TC1775
Data Sheet 47 V1.2, 2002-05
Preliminary
Peripheral Control Processor
The Peripheral Control Processor (PCP) performs tasks that would normally be
performed by the combination of a DMA controller and its supporting CPU interrupt
service routines in a traditional computer system. It could easily be considered as the
host processor’s first line of defense as an interrupt-handling engine. The PCP can off-
load the CPU from having to service time-critical interrupts. This provides many benefits,
including:
• Avoiding large interrupt-driven task context-switching latencies in the host processor
• Lessening the cost of interrupts in terms of processor register and memory overhead
• Improving the responsiveness of interrupt service routines to data-capture and data-
transfer operations
• Easing the implementation of multitasking operating systems.
The PCP has an architecture that efficiently supports DMA type transactions to and from
arbitrary devices and memory addresses within the TC1775 and also has reasonable
stand alone computational capabilities.
The PCP is made up of several modular blocks as follows:
• PCP Processor Core
• Code Memory (PCODE)
• Parameter Memory (PRAM)
• PCP Interrupt Control Unit (PICU)
• PCP Service Request Nodes (PSRN)
• System bus interface to the FPI Bus
The PCP is fully interrupt-driven, meaning it is only activated through service requests;
there is no main program running in the background as with a conventional processor.
TC1775
Data Sheet 48 V1.2, 2002-05
Preliminary
Figure 13 PCP Block Diagram
Table 4 PCP Instruction Set Overview
Instruction Group Description
DMA primitives Efficient DMA channel implementation
Load/Store Transfer data between PRAM or FPI memory and the general
purpose registers, as well as move or exchange values
between registers
Arithmetic Add, subtract, compare and complement
Divide/Multiply Divide and multiply
Logical And, Or, Exclusive Or, Negate
Shift Shift right or left, rotate right or left, prioritize
Bit Manipulation Set, clear, insert and test bits
Flow Control Jump conditionally, jump long, exit
Miscellaneous No operation, Debug
MCB04784
PCP
Processor
Core
PCP Service
Req. Nodes
PSRNs
PCP Interrupt
Control Unit
PICU
Parameter
Memory
PRAM
Code
Memory
PCODE
FPI-Interface
PCP Interrupt
Arbitration Bus
CPU Interrupt
Arbitration Bus
FPI Bus
TC1775
Data Sheet 49 V1.2, 2002-05
Preliminary
System Timer
The STM within the TC1775 is designed for global system timing applications requiring
both high precision and long range. The STM provides the following features:
• Free-running 56-bit counter
• All 56 bits can be read synchronously
• Different 32-bit portions of the 56-bit counter can be read synchronously
• Driven by clock fSTM (identical with the system clock fSYS)
• Counting begins at power-on reset
• Continuous operation is not affected by any reset condition except power-on reset
The STM is an upward counter, running with the system clock frequency fSYS. It is
enabled per default after reset, and immediately starts counting up. Other than via reset,
it is not possible to affect the contents of the timer during normal operation of the
application, it can only be read, but not written to. Depending on the implementation of
the clock control of the STM, the timer can optionally be disabled or suspended for
power-saving and debugging purposes via a clock control register.
The maximum clock period is 256 ×1/fSTM. At fSTM = 40 MHz, for example, the STM
counts 57.1 years before overflowing. Thus, it is capable of continuously timing the entire
expected product life-time of a system without overflowing.
Figure 14 Block Diagram of the STM Module
STM Module
00
H
CAP
TIM6
TIM5
TIM4
TIM3
TIM2
TIM1
TIM0
00
H
55 47 39 31 23 15 7
56-Bit System Timer
Address
Decoder
Clock
Control
Enable/
Disable
PORST
f
STM
MCA04795
TC1775
Data Sheet 50 V1.2, 2002-05
Preliminary
Watchdog Timer
The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and
recover from software or hardware failure. The WDT helps to abort an accidental
malfunction of the TC1775 in a user-specified time period. When enabled, the WDT will
cause the TC1775 system to be reset if the WDT is not serviced within a user-
programmable time period. The CPU must service the WDT within this time interval to
prevent the WDT from causing a TC1775 system reset. Hence, routine service of the
WDT confirms that the system is functioning properly.
In addition to this standard “Watchdog” function, the WDT incorporates the EndInit
feature and monitors its modifications. A system-wide line is connected to the ENDINIT
bit implemented in a WDT control register, serving as an additional write-protection for
critical registers (besides Supervisor Mode protection).
A further enhancement in the TC1775’s Watchdog Timer is its reset prewarning
operation. Instead of immediately resetting the device on the detection of an error, as
known from standard Watchdogs, the WDT first issues an Non-maskable Interrupt (NMI)
to the CPU before finally resetting the device at a specified time period later. This gives
the CPU a chance to save system state to memory for later examination of the cause of
the malfunction, an important aid in debugging.
Features:
• 16-bit Watchdog counter
• Selectable input frequency: fSYS/256 or fSYS/16384
• 16-bit user-definable reload value for normal Watchdog operation, fixed reload value
for Time-Out and Prewarning Modes
• Incorporation of the ENDINIT bit and monitoring of its modifications
• Sophisticated password access mechanism with fixed and user-definable password
fields
• Proper access always requires two write accesses. The time between the two
accesses is monitored by the WDT and limited.
• Access Error Detection: Invalid password (during first access) or invalid guard bits
(during second access) trigger the Watchdog reset generation.
• Overflow Error Detection: An overflow of the counter triggers the Watchdog reset
generation.
• Watchdog function can be disabled; access protection and ENDINIT monitor function
remain enabled.
• Double Reset Detection: If a Watchdog induced reset occurs twice without a proper
access to its control register in between, a severe system malfunction is assumed and
the TC1775 is held in reset until a power-on reset. This prevents the device from being
periodically reset if, for instance, connection to the external memory has been lost
such that even system initialization could not be performed.
TC1775
Data Sheet 51 V1.2, 2002-05
Preliminary
• Important debugging support is provided through the reset prewarning operation by
first issuing an NMI to the CPU before finally resetting the device after a certain period
of time.
Real Time Clock
Figure 15 shows a global view of all functional blocks oft he RTC interface.
Figure 15 Block Diagram of the RTC Interface
The Real Time Clock (RTC) module is an independent timer chain that counts time ticks.
The base frequency of the RTC can be programmed via a reload counter. The RTC can
work asynchronously with the system frequency, and is optimized on low power
consumption.
Features:
• On-chip 32.768 kHz oscillator for counting current time and date
• Cyclic time-based interrupts
• Alarm interrupt for wake-up on a defined time
• 48-bit timer for long-term measurements
MCB04808
RTC
Oscillator
SCU
Address
Decoder
f
RTC_COUNT
RTC
Module
(Kernel)
Interrupt
Control
RTCINT
f
SYS
Mode_Select
XTAL3
XTAL4
32 kHz
TC1775
Data Sheet 52 V1.2, 2002-05
Preliminary
System Control Unit
The System Control Unit (SCU) of the TC1775 handles the system control tasks. All
these system functions are tightly coupled, thus, they are conveniently handled by one
unit, the SCU. The system tasks of the SCU are:
• Reset Control
– Generation of all internal reset signals
– Generation of external HDRST reset signal
• PLL Control
– PLL_CLC Clock Control Register
• Power Management Control
– Enabling of several power-down modes
– Control of the PLL in power-down modes
• Watchdog Timer
• Port 5 Trace Control
• Device Identification
TC1775
Data Sheet 53 V1.2, 2002-05
Preliminary
Interrupt System
An interrupt request can be serviced either by the CPU or by the Peripheral Control
Processor (PCP). These units are called “Service Providers”. Interrupt requests are
called “Service Requests” rather than “Interrupt Requests” in this document because
they can be serviced by either of the Service Providers.
Each peripheral in the TC1775 can generate service requests. Additionally, the Bus
Control Unit, the Debug Unit, the PCP, and even the CPU itself can generate service
requests to either of the two Service Providers. As shown in Figure 16, each TC1775
unit that can generate service requests is connected to one or multiple Service Request
Nodes (SRN). Each SRN contains a Service Request Control Register mod_SRCx,
where “mod” is the identifier of the service requesting unit and “x” an optional index. Two
buses connect the SRNs with two Interrupt Control Units, which handle interrupt
arbitration among competing interrupt service requests, as follows:
• The Interrupt Control Unit (ICU) arbitrates service requests for the CPU and
administers the CPU Interrupt Arbitration Bus.
• The Peripheral Interrupt Control Unit (PICU) arbitrates service requests for the PCP
and administers the PCP Interrupt Arbitration Bus.
Units, which can generate service requests are:
– General Purpose Timer Unit (GPTU) with 8 SRNs
– General Purpose Timer Array (GPTA) with 54 SRNs
– Two High-Speed Synchronous Serial Interfaces (SSC0/SSC1) with 3 SRNs each
– Two Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1) with 4 SRNs each
– TwinCAN controller with 8 SRNs
– Serial Data Link Module (SDLM) with 2 SRNs
– Two Analog/Digital Converters (ADC0/ADC1) with 4 SRNs each
– Real Time Clock (RTC) with 1 SRN
– Bus Control Unit (BCU) with 1 SRN
– Peripheral Control Processor (PCP) with 4 SRNs
– Central Processing Unit (CPU) with 4 SRNs
– Debug Unit (OCDS) with 1 SRN
The PCP can make service requests directly to itself (via the PICU), or it can make
service requests to the CPU. The Debug Unit can generate service requests to the PCP
or the CPU. The CPU can make service requests directly to itself (via the ICU), or it can
make service requests to the PCP. The CPU Service Request Nodes are activated
through software.
External interrupt inputs in TC1775 are available using the input pins connected to the
General-Purpose Timer Unit (GPTU). Each of the eight GPTU I/O pins can be used as
an external interrupt input, using the Service Request Nodes of the GPTU module. In
addition, such an external interrupt input can also trigger a timer function.
TC1775
Data Sheet 54 V1.2, 2002-05
Preliminary
Figure 16 Block Diagram of the TC1775 Interrupt System
Note: Depending on the selected system frequency fSYS, the number of clocks for
interrupt arbitration cycles must be selected as follows:
fSYS ≤30 MHz: ICR.CONECYC = 1
fSYS > 30 MHz: ICR.CONECYC = 0
MCB04779
54 SRNs
Int. Req.
8 SRNs
8
GPTU
54
GPTA
3 SRNs
3
SSC0
3 SRNs
3
SSC1
4 SRNs
4
ASC0
4 SRNs
4
ASC1
8 SRNs
8
CAN
2 SRNs
2
SDLM
4 SRNs
4
ADC0
4 SRNs
4
ADC1
1 SRN
1
RTC
1 SRN
1
BCU
Service
Request
Nodes
Service
Requestors
8
8
54
2
54
3
3
3
4
4
4
4
8
8
2
2
4
4
4
4
1
1
1
1
PCP
Interrupt
Arbitration Bus
CPU
Interrupt
Arbitration Bus
2 SRNs
2 SRNs
Interrupt
Control Units
2
PIPN
PCP
Int. Ack.
CCPN
2
Interrupt
Service
Providers
2
1
11 SRNs 1Debug
Unit
4
44 SRNs 4
Int. Req.
PIPN
CPU
CCPN
Int. Ack.
Software
Interrupt
ICU
PICU
3
TC1775
Data Sheet 55 V1.2, 2002-05
Preliminary
Boot Options
The TC1775 booting schemes provides a number of different boot options for the start
of code execution. Table 5 shows the boot options available in the TC1775.
Table 5 Boot Selections
OCDSE BRKIN CFG
[3]
CFG
[2:0]
Type of Boot Boot Source Initial
PC Value
11X000
BStart from Boot ROM Boot ROM BFFF FFFCH
001B
010B
0100
BExternal memory as
slave directly via EBU
External
Memory
(cached)
A000 0000H
1100
BExternal memory as
master directly via EBU
0101
BExternal memory as
slave via FPI Bus
1101
BExternal memory as
master via FPI Bus
X011
B
110B
111B
Reserved; don’t use these combinations;
010100
B
or
101B
Go to halt with EBU
enabled as slave
––
1 Go to halt with EBU
enabled as master
all other
combina-
tions
Go to halt with EBU
disabled
0 0 don’t care Go to external
emulator space
– BE00 0000H
1 0 don’t care Tri-state chip
(deep sleep)
––
TC1775
Data Sheet 56 V1.2, 2002-05
Preliminary
Power Management System
The TC1775 power management system allows software to configure the various
processing units so that they automatically adjust to draw the minimum necessary power
for the application.
There are four power management modes:
•Run Mode
• Idle Mode
• Sleep Mode
• Deep Sleep Mode
Table 6 describes these features of the power management modes.
Table 6 Power Management Mode Summary
Mode Description
Run The system is fully operational. All clocks and peripherals are enabled,
as determined by software.
Idle The CPU clock is disabled, waiting for a condition to return it to Run
Mode. Idle Mode can be entered by software when the processor has no
active tasks to perform. All peripherals remain powered and clocked.
Processor memory is accessible to peripherals. A reset, Watchdog Timer
event, a falling edge on the NMI pin, or any enabled interrupt event will
return the system to Run Mode.
Sleep The system clock continues to be distributed only to those peripherals
programmed to operate in Sleep Mode. Interrupts from operating
peripherals, the Watchdog Timer, a falling edge on the NMI pin, or a reset
event will return the system to Run Mode. Entering this state requires an
orderly shut-down controlled by the Power Management State Machine.
Deep Sleep The system clock is shut off; only an external signal will restart the
system. Entering this state requires an orderly shut-down controlled by
the Power Management State Machine (PMSM).
TC1775
Data Sheet 57 V1.2, 2002-05
Preliminary
On-Chip Debug Support
The On-Chip Debug Support of the TC1775 consists of four building blocks:
• OCDS module in the TriCore CPU
– On-chip breakpoint hardware
– Support of an external break signal
• OCDS module in the PCP
– Special DEBUG instruction for program execution tracing
• Trace module of the TriCore
– Outputs 16 bits per cycle with pipeline status information, PC bus information, and
breakpoint qualification information
• Debugger Interface (Cerberus)
– Provided for debug purposes of emulation tool vendors
– Accessible through a JTAG standard interface with dedicated JTAG port pins
Figure 17 shows a basic block diagram of the building blocks.
Figure 17 OCDS Support Basic Block Diagram
MCB04810
Cerberus &
JTAG
TRST
TCK
TMS
TDI
TDO
JTAG
I/O Lines
TriCore
CPU
OCDS
PCP
SCU
Trace
Control 16
BRKIN
BRKOUT
Port 5
TRACE[15:0]
OCDSE
FPI Bus
TC1775
Data Sheet 58 V1.2, 2002-05
Preliminary
Clock Generation Unit
The Clock Generation Unit (CGU) in the TC1775, shown in Figure 18, consists of an
oscillator circuit and a Phase-Locked Loop (PLL). The PLL can convert a low-frequency
external clock signal to a high-speed internal clock for maximum performance. The PLL
also has fail-safe logic that detects degenerate external clock behavior such as abnormal
frequency deviations or a total loss of the external clock. It can execute emergency
actions if it looses its lock on the external clock.
In general, the CGU is controlled through the System Control Unit (SCU) module of the
TC1775.
Figure 18 Clock Generation Unit Block Diagram
Besides the two XTAL pins for the oscillator, input pins CLKSEL[2:0] and BYPASS are
used for configuration of the clock generation unit. These inputs are checked by the SCU
which generates the appropriate control signals and latches the state of these signals
into register PLL_CLC.
MCA04713
Oscillator
Circuit
XTAL1
XTAL2
&
f
OSC
Phase
Detect. VCO
N
Divider
PLL
f
VCO
1
0
K
Divider
f
SYS
System_
CLK
Lock
Detector
OSC_OK PLL
Locked Deep
Sleep NDIV[2:0] VCO_
BYPASS KDIV[2:0] PLL_
BYPASS
CLKSEL[2:0]
BYPASS Register PLL_CLC
MUX
1
0
MUX
Clock Generation Unit
CGU
System Control Unit
SCU
TC1775
Data Sheet 59 V1.2, 2002-05
Preliminary
PLL Operation
The fVCO clock of the PLL has a frequency which is a multiple of the externally applied
clock fOSC. The factor for this is controlled through the value N applied to the divider in
the feedback path. N is defined through three PLL configuration inputs CLKSEL[2:0].
The K-Divider is a software controlled divider. Table 8 lists the possible values for K and
the resulting division factor.
Table 7 Input Frequencies and N Factor for fVCO
CLKSEL[2:0] N-Factor fVCO = 150 MHz fVCO = 160 MHz fVCO = 200 MHz
000B818.75 20 25
001B916.67 17.76 22.22
010B10 15 16 20
011B11 13.64 14.55 18.18
100B12 12.5 13.33 16.67
101B13 11.54 12.31 15.38
110B14 10.71 11.43 14.29
111B15 10 10.67 13.33
Shaded combinations should not be used because the maximum oscillator frequency of 16 MHz is exceeded.
Table 8 Output Frequencies fSYS Derived from Various Output Factors
K-Factor fSYS1)
1) Depending on the selected system frequency fSYS, the number of clocks for interrupt arbitration cycles must
be selected as follows: fSYS ≤30 MHz: ICR.CONECYC = 1, fSYS > 30 MHz: ICR.CONECYC = 0.
Duty
Cycle
[%]
Selected
Factor
KDIV fVCO =
150 MHz
fVCO =
160 MHz
fVCO =
200 MHz
2000
B75 80 100 50
4010
B37.5 40 50 50
52)
2) These odd K-Factors should not be used (not tested because of the unsymmetrical duty cycle).
011B30 32 40 40
6100
B24.5 26.67 33.33 50
8101
B18.75 20 25 50
92) 110B16.67 17.78 22.22 44
10 111B15 16 20 50
16 001B9.38 10 12.5 50
Shaded combinations cannot not be used because the maximum system clock frequency of 40 MHz is
exceeded.
TC1775
Data Sheet 60 V1.2, 2002-05
Preliminary
Recommended Oscillator Circuits
Figure 19 Oscillator Circuitries
For the main oscillator of the TC1775 the following external passive components are
recommended:
– Crystal: max. 16 MHz
–C1, C2: 10 pF
A block capacitor between VDDOSC and VSSOSC is recommended, too.
For the RTC oscillator of the TC1775 the following external passive components are
recommended:
– Crystal: 32.768 kHz
–C1, C2: 12 pF
Note: For crystal operation, it is strongly recommended to measure the negative
resistance in the final target system (layout) to determine the optimum parameters
for the oscillator operation. Please refer to the minimum and maximum values of
the negative resistance specified by the crystal supplier.
MCS04714
TC1775
Main
Oscillator
V
DDOSC
V
SSOSC
C
1
1-16
MHz
C
2
XTAL1
XTAL2
TC1775
Main
Oscillator
V
DDOSC
V
SSOSC
XTAL1
XTAL2
External
Clock Signal
MCS04716
TC1775
RTC
Oscillator
V
DD
V
SS
C
1
32.768
kHz
C
2
XTAL3
XTAL4
TC1775
Data Sheet 61 V1.2, 2002-05
Preliminary
Power Supply
Figure 20 shows the TC1775’s power supply concept, where certain logic modules are
individually supplied with power. This concept improves the EMI behavior by reduction
of the noise cross coupling. Also the operation margin is improved in sensitive modules
like the A/D converter by noise reduction.
Figure 20 TC1775 Power Supply Concept
TC1775
MCD04878
CPU &
Control &
Peripherals PLL OSC
V
DDOSC
(2.5 V)
V
DDOSC
V
DDPLL
(2.5 V)
V
SSPLL
V
DDP05
(2.5 V)
V
SS
V
DDP813
(3.3 - 5 V)
V
SS
V
DDSB
(2.5 V)
V
SS
V
DDSRAM
(2.5 V)
V
SS
Short Circuit /
Broken Wire Logic
Short Circuit /
Broken Wire Logic
ADC0
Control Logic
ADC1
Control Logic
V
DDA0
(2.5 V)
V
SSA0
V
DDM
(5 V)
V
SSM
V
DDSC
(5 V)
V
SSSC
V
DDA1
(2.5 V)
V
SSA1
PCP
Memory DMU PMU GPIO
Ports
(P8-P13)
EBU
Ports
(P0-P5)
V
DD
(2.5 V)
V
SS
TC1775
Data Sheet 62 V1.2, 2002-05
Preliminary
Ports Power Supply
The TC1775’s port power supply concept is shown in Figure 21. The ports assigned with
the External Bus Unit (EBU) are in a separate power supply group for 2.5 V nominal
operating voltage. The general purpose input/outputs (GPIOs) except the EBU provide
3.3 to 5 V input/output acceptance and drive characteristics.
Figure 21 Ports Power Supply Concept
Power-up Sequence
During Power-up the reset pin PORST has to be held active until both power supply
voltages have reached at least their minimum values.
During the Power-up time (rising of the supply voltages from 0 to their regular operating
values) it has to be ensured, that the difference between VDDP813 and VDDI (i.e.
VDDP813 -VDDI) never drops below -0.3 V (VDDI =VDD and VDDP05).
Power Loss
If VDDP813 is dropping below VDDI, external circuitry in the power supply has to ensure,
that VDDI is also limited to the same level.
If VDDI is dropping below the operating range, VDDP813 may stay active.
Powering Down
During powering down (falling of the supply voltages from their regular operating values
to zero), it has to be ensured, that the difference between VDDP813 and VDDI
(VDDP813 -VDDI) never drops below -0.3 V.
MCA04752
V
SS
Ports 0 to 5
(Pads)
&
Schmitt Trigger
Ports 8 to 13
(Pads)
&
Schmitt Trigger
V
DDP05
(2.5 V)
V
DDP813
(3.3 - 5 V)
Port Logic
V
DD
(2.5 V)
TC1775
Data Sheet 63 V1.2, 2002-05
Preliminary
Identification Register Values
Table 9 TC1775 Identification Registers
Short Name Address Value
PMU_ID C7FF FF08H0006 C002H
DMU_ID D7FF FF08H0007 C002H
SCU_ID F000 0008H0003 C002H
MANID F000 0070H0000 1820H
CHIPID F000 0074H0000 8002H
RTID F000 0078H0000 0000H
RTC_ID F000 0108H0000 5A01H
BCU_ID F000 0208H0000 6A05H
STM_ID F000 0308H0000 C002H
JPD_ID F000 0408H0000 6301H
EBU_ID F000 0508H0005 C002H (BA11-Step)
0005 C003H (BA21-Step)
GPTU_ID F000 0708H0001 C002H
ASC0_ID F000 0808H0000 4401H
ASC1_ID F000 0908H0000 4401H
SSC0_ID F000 0A08H0000 4503H
SSC1_ID F000 0B08H0000 4503H
GPTA_ID F000 1808H0002 C001H
ADC0_ID F000 2208H0000 3101H
ADC1_ID F000 2408H0000 3101H
SDLM_ID F000 2608H0000 4202H
PCP_ID F000 3F08H000D C001H
CAN_ID F010 0008H0000 4110H
CPU_ID FFFE FF08H0000 0202H
TC1775
Data Sheet 64 V1.2, 2002-05
Preliminary
Parameter Interpretation
The parameters listed on the following pages partly represent the characteristics of the
TC1775 and partly its demands on the system. To aid in interpreting the parameters
right, when evaluating them for a design, they are marked in column “Symbol”:
CC (Controller Characteristics):
The logic of the TC1775 will provide signals with the respective timing characteristics.
SR (System Requirement):
The external system must provide signals with the respective timing characteristics to
the TC1775.
Pin Classes
The TC1775 has three classes of digital I/O pins:
–Class A pins, which are 3.3 V to 5 V nominal voltage pins
–Class B pins, which are 2.5 V nominal voltage pins (input tolerant for 3.3 V)
–Class C pins, which are 2.5 V nominal voltage pins only
Table 10 shows the assignments of all digital I/O pins to pin classes and to VDD power
supply pins.
Table 10 Assignments of Digital Pins to Pin Classes and Power Supply Pins
Pins Pin Classes Power Supply
Port 8 to Port 13
CLKSEL[2:0], BYPASS,
CFG[3:0], HDRST
Class A
(nominal 3.0 to 5.25 V)
VDDP813 VSS
Port 0 to 5
TRST, TCK, TDI, TDO, TMS,
ODCSE, BRKIN, BRKOUT,
NMI, PORST,
CLKOUT, CLKIN
TESTMODE
Class B
(nominal 2.5 V, 3.3 V
tolerant)
VDDP05
Core supply, no pins assigned (nominal 2.5 V) VDD, VDDSRAM,
VDDSB
VDDPLL VSSPLL
XTAL1, XTAL2, XTAL3, XTAL4 Class C
(nominal 2.5 V)
VDDOSC VSSOSC
TC1775
Data Sheet 65 V1.2, 2002-05
Preliminary
Absolute Maximum Ratings
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN >VDD or VIN <VSS) the
voltage on VDD pins with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Parameter Symbol Limit Values Unit Notes
min. max.
Ambient temperature TA-40 125 °C under bias
Storage temperature TA-65 150 °C–
Junction temperature TJ–150°C under bias
Voltage on Class A power supply
pins with respect to VSS
VDD -0.5 6.2 V see
Table 10
Voltage on Class B and C power
supply pins with respect to VSS
VDD -0.5 3.25 V –
Voltage on power supply pins
“no pins assigned” with respect
to VSS
VDD -0.5 3.25 V –
Voltage on any Class A input pin
with respect to VSS
VIN -0.5 VDD + 0.5 V –
Voltage on any Class B input pin
with respect to VSS
VIN -0.5 3.7 V –
Voltage on any Class C input pin
with respect to VSS
VIN -0.5 VDDOSC
+ 0.5
V–
Input current on any pin during
overload condition
IIN -10 10 mA –
Absolute sum of all input currents
during overload condition ΣIIN – |100| mA –
TC1775
Data Sheet 66 V1.2, 2002-05
Preliminary
Package Parameters (P-BGA-329)
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the TC1775. All parameters specified in the following table refer to these
operating conditions, unless otherwise noticed.
Parameter Symbol Limit Values Unit Notes
min. max.
Power dissipation PDISS –1W–
Thermal resistance RTHA – 23 K/W Chip to ambient
Parameter Symbol Limit Values Unit Notes
min. max.
Digital supply voltage1) VDDP813 3.0 5.25 V Class A pins
VDD2) 2.3 2.75 V CPU Core and
Class B pins
VDDOSC 2.3 2.75 V Class C pins
VDDSB3) 2.25 2.75 V –
Digital ground voltage VSS 0V–
Ambient temperature under
bias
TA-40 +125 °C–
Analog supply voltages VDDA 2.25 2.75 V –
VDDM 4.5 5.25 V –
Analog reference voltage VAREF 4VDDM +
0.05
V4)
Analog ground voltage VAGND VSSA -
0.05
VSSA +
0.05
V5)
Analog input voltage VAIN VAGND VAREF V–
CPU clock fSYS –40MHz–
Overload current IOV -10 10 mA 6)7)8)
Short circuit current ISC -10 10 mA 3)4)9)
Absolute sum of overload +
short circuit currents
Σ|IOV|+
|ISC|
–|50|mA
7)
External load capacitance CL–50pF–
TC1775
Data Sheet 67 V1.2, 2002-05
Preliminary
1) Digital supply voltages applied to the TC1775 must be static regulated voltages which allow a typical voltage
swing of ±10%.
2) This VDD specification is applicable for the power supply pins: VDD, VDDOSC, VDDPLL, VDDSRAM, VDDP05, and
VDDSB. In order to minimize the danger of latch-up conditions, these 2.5 V VDD power supply pins should be
kept at the same voltage level during normal operating mode. This condition is typically achieved by generating
the 2.5 V power supplies from a single voltage source. The condition is also valid in normal operating mode if
a separate stand-by power supply VDDSB is used.
3) The minimum voltage at pin VDDSB during TC1775 power down mode is 1.8 V in order to keep the contents of
SBRAM valid. The core power supply VDD must be below the standby power supply VDD < VDDSB + 0.3 V.
4) The value of VAREF is permitted to be within the range of VSSA -0.05V<VAREF <VDDM + 0.05 V. The value
specified for the total unadjusted error (TUE) is not guaranteed while the VAREF is out of the specified range.
5) The value of VAGND is permitted to be within the range of VSSA -0.05V<VAGND <VDDM + 0.05 V. The value
specified for the total unadjusted error (TUE) is not guaranteed while the VAGND is out of the specified range.
6) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range (i.e. VOV >VDD + 0.5 V or VOV <VSS - 0.5 V). The absolute sum of input overload
currents on all port pins may not exceed 50 mA. The supply voltage must remain within the specified limits.
7) Not 100% tested, guaranteed by design and characterization.
8) Applicable for analog inputs.
9) Applicable for digital inputs.
TC1775
Data Sheet 68 V1.2, 2002-05
Preliminary
DC Characteristics
Input/Output DC-Characteristics
VSS = 0 V; TA = -40 °C to +125 °C;
Parameter1) Symbol Limit Values Unit Test Conditions
min. max.
Class A Pins (VDDP813 = 3.0 to 5.25 V)
Output low voltage2) VOL CC – 0.45 V IOL =2.4mA
3)
IOL =600µA4)
VDDP813 = 4.5 to 5.25 V
0.2 ×
VDDP813
VIOL =2.4mA
IOL =600µA4)
VDDP813 = 3.0 to 4.49 V
Output high voltage2) VOH CC 0.7 ×
VDDP813
–VIOH =-2.4mA
IOH =-600µA4)
VDDP813 = 4.5 to 5.25 V
VIOH =-2.4mA
IOH =-600µA4)
VDDP813 = 3.0 to 4.49 V
Input low voltage5) VIL SR -0.5 0.8 V VDDP813 = 4.5 to 5.25 V
(TTL)
0.43 ×
VDDP813
VVDDP813 = 4.5 to 5.25 V
(CMOS)
0.2 ×
VDDP813
VVDDP813 = 3.0 to 4.49 V
(CMOS)
Input high voltage5) VIH SR 2.0 VDDP813
+0.5
VVDDP813 = 4.5 to 5.25 V
(TTL)
0.73 ×
VDDP813
VVDDP813 = 3.0 to 5.25 V
(CMOS)
Pull-up current6) IPUH CC – 10 µAVOUT = VDDP813 -0.02 V
IPUL CC -120 – µAVOUT = 0.5 × VDDP813
Pull-down current7) IPDL CC 10 – µAVOUT = 0.02 V
IPDH CC – 120 µAVOUT = 0.5 × VDDP813
TC1775
Data Sheet 69 V1.2, 2002-05
Preliminary
Class B Pins (VDDP05 = 2.30 to 2.75 V)
Output low voltage VOL CC – 0.2 ×
VDDP05
VIOL =2.4mA
0.45 IOL =600µA
Output high voltage VOH CC 0.7 ×
VDDP05
–VIOH =-2.4mA
0.9 ×
VDDP05
–VIOH =-600µA
Input high voltage VIH SR 0.7 ×
VDDP05
3.7 V –
Input low voltage VIL SR -0.5 0.2 ×
VDDP05
V–
Pull-up current6) IPUH CC – 10 µAVOUT = VDDP05 - 0.02 V
IPUL CC -60 – µAVOUT = 0.5 × VDDP05
Pull-down current7) IPDL CC 10 – µAVOUT = 0.02 V
IPDH CC – 60 µAVOUT = 0.5 × VDDP05
Class A and B Pins
Input Hysteresis HYS CC 0.065 ×
VDDPx8) – V TTL and CMOS9)
Input leakage current
(Digital I/O)
IOZ2 CC – ±500 nA 0 V < VIN < VDDPx8)
Peak short-circuit
current
Peak back-drive
current
(per digital pin)
Peak time & period
time10)11)
ISCBDpeak
SR
–±20 mA 12)9)
Input/Output DC-Characteristics (cont’d)
VSS = 0 V; TA = -40 °C to +125 °C;
Parameter1) Symbol Limit Values Unit Test Conditions
min. max.
TC1775
Data Sheet 70 V1.2, 2002-05
Preliminary
Constant short-circuit
current
Constant back-drive
current
(per digital pin)
ISCBDcons
SR
–±10 mA 12)9)
Pin capacitance9)
(Digital I/O)
CIO CC – 10 pF f = 1 MHz
TA = 25 °C
Class C Pins (VDDOSC = 2.30 to 2.75 V), see Page 76
1) All Class A pins of the TC1775 are equipped with Low-Noise output drivers, which significantly improve the
device’s EMI performance. These Low-Noise drivers deliver their maximum current only until the respective
target output level is reached. After that the output current is reduced. This results in an increased impedance
of the driver, which attenuates electrical noise from the connected PCB tracks. The current, which is specified
in column “Test Conditions”, is delivered in any case.
2) This specification is not valid for outputs of GPIO lines, which are switched to open drain mode. In open drain
mode the output will float and the voltage results from the external circuitry.
3) Output drivers in high current mode.
4) Condition for output driver in dynamic current mode & low current mode – guaranteed by design
characterization.
5) Input characteristics can be switched between TTL and CMOS via register Px_PICON except for dedicated
pins which have CMOS input characteristics.
6) The maximum current can be drawn while the respective signal line remains inactive.
7) The minimum current must be drawn in order to drive the respective signal line active.
8) In case of Class B pins VDDx =VDDP05. In case of Class A pins VDDx =VDDP813.
9) Guaranteed by design characterization.
10) The max. peak-short-circuit current resp. max. peak-back-drive current is limited by max. 20 mA and the peak
period equivalent of 10 mA constant-short-circuit current resp. 10 mA constant-back-drive current. The integral
of ISCBDpeak over the peak period is thus limited to 10 mA (provided: ISCBDpeak ≤ 20 mA).
11) To be defined for Class B pads.
12) Short-circuit or back-drive conditions during operation occur if the voltage on the respective pin exceeds the
specified operating range (i.e. VSCBD >VDDPx +0.5V or VSCBD <VSS -0.5V) or a short circuit condition
occurs on the respective pin. The absolute sum of input ISCBD and IOV currents on all port pins must not exceed
100 mA at any time. The supply voltage (VDDPx and VSS) must remain within the specified limits. Under short-
circuit conditions the corresponding pin is not ready for use. In case of Class B pins VDDx =VDDP05. In case of
Class A pins VDDx =VDDP813.
Input/Output DC-Characteristics (cont’d)
VSS = 0 V; TA = -40 °C to +125 °C;
Parameter1) Symbol Limit Values Unit Test Conditions
min. max.
TC1775
Data Sheet 71 V1.2, 2002-05
Preliminary
Pull-Up/Pull-Down Characteristics
Figure 22 Pull-Up/Pull-Down Characteristics of Class A Pins
MCD05235
0
0
µA
I
V
V123456
Pull-up
0
0
µA
I
V
V123456
Pull-down
Best Case
Nominal
100
200
300
400
500
600
700
100
200
300
400
500
600
700
Worst Case
Nominal
Best Case
Worst Case
TC1775
Data Sheet 72 V1.2, 2002-05
Preliminary
Figure 23 Pull-Up/Pull-Down Characteristics of Class B Pins
Note: The pull-up/pull-down characteristics as shown in Figure 22 and Figure 23 are
guaranteed by design characterization.
MCD05236
0
0
50
100
150
200
250
µA
I
V
V0.5 1 1.5 2 2.5 3
Pull-up
0
0
50
100
150
200
250
µA
I
V
V0.5 1 1.5 2 2.5 3
Pull-down
Best Case
Nominal
Worst Case
Worst Case
Nominal
Best Case
TC1775
Data Sheet 73 V1.2, 2002-05
Preliminary
AD Converter Characteristics
TA = -40 °C to +125 °C; VSS =0V;
Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
Analog supply voltages VDDAx SR 2.25 2.5 2.75 V 1)
VDDM SR 4.5 5 5.25 V –
VDDSCSR VDDM -
0.05
–VDDM +
0.05
V–
Analog ground voltage VSSAx SR -0.1 – 0.1 V 2)
Analog reference voltage VAREFx
SR
4–
VDDM +
0.05
V3)
Analog reference ground VAGNDx
SR
VSSAx -
0.05
–VSSAx +
0.05
V4)
Analog input voltage
range
VAIN SR VAGNDx –VAREFx V–
Internal ADC clock fANA 0.5 – 2 MHz –
Power-up calibration time tPUC – – 3328 ×(3 +
CON.CPS)
×tBC
µs–
Sample time tSCC (3 + CON.CPS) ×
(CHCONn.STC + 2) × tBC
µs5)
6 × tBC –– µs
Conversion time tCCC tS + (30 + CON.CPS ×4)
× tBC + 2 × tDIV
µs for 8-bit conv.5)
tS + (36 + CON.CPS × 4)
× tBC + 2 × tDIV
µs for 10-bit conv.5)
ts + (42 + CON.CPS × 4)
× tBC + 2 × tDIV
µs for 12-bit conv.5)
Total unadjusted error TUE6) CC – – ±1 LSB for 8-bit conv.
––±2 LSB for 10-bit conv.
––±6 LSB for 12-bit conv.
Overload current7) IAOV1 CC
8) -2 – +5 mA –
-2 0 mA kA=1.0 × 10-3
0+5mAkA=1.0 × 10-4
IAOV2 CC
9) -4 – +10 mA –
-4 0 mA kA=1.0 × 10-3
0+10mAkA=1.0 × 10-4
TC1775
Data Sheet 74 V1.2, 2002-05
Preliminary
Overload coupling
factor10) kACC – – 1.0 × 10-3 –see IAOV1 and
IAOV2
1.0 × 10-4 –
Input leakage current at
analog inputs
IOZ1 CC – – ±200 nA 0 V < VIN <VDDA1)
Input leakage current at
VAGND and VAREF
IOZ2 CC – – ±500 nA 0 V < VIN <VDDA1)
Switched cap. at the
positive reference
voltage input
CAREFSW
CC
–1520 pF
11)
Switched cap. at the
negative reference
voltage input
CAGNDS
CC
–1520 pF
11)
Total cap. at the analog
voltage input
CAINTOT
CC
–1215 pF–
Switched cap. at the
analog voltage input
CAINSW
CC
– – 10 pF 12)
ON resistance of the
transmission gates in the
analog voltage path
RAIN CC – – 0.7 kΩ–
1) VDDAx = VDDA0 for A/D Converter ADC0 and VDDAx = VDDA1 for A/D Converter ADC1.
2) VSSAx = VSSA0 for A/D Converter ADC0 and VSSAx = VSSA1 for A/D Converter ADC1.
3) The value of VAREF is permitted to be within the range of VSSA - 0.05 V < VAREF < VDDM + 0.05 V. The value
specified for the total unadjusted error (TUE) is not guaranteed while the VAREF is out of the specified range.
4) The value of VAGND is permitted to be within the range of VSSA - 0.05 V < VAGND < VDDM + 0.05 V. The value
specified for the total unadjusted error (TUE) is not guaranteed while the VAGND is out of the specified range.
5) Definitions for CPS, STC, tBC and tDIV see Figure 25.
6) TUE is tested at VAREF =5V, VAGND = 0 V and VDDM =4.9V.
7) Analog overload conditions during operation occur if the voltage on the respective ADC pin exceeds the
specified operating range (i.e. VAOV >VDDM + 0.5 V or VAOV <VSSM - 0.5 V) or a short circuit condition occurs
on the respective ADC pin. The absolute sum of input currents on all port pins must not exceed 10 mA at any
time. The supply voltage (VDD, VDDA0, VDDA1 and VSS, VSSA0, VSSA1) must remain within the specified limits.
Under short-circuit conditions the corresponding pin is not ready for use.
8) Applies for one analog input pin.
9) Applies for two adjacent analog input pins.
AD Converter Characteristics (cont’d)
TA = -40 °C to +125 °C; VSS =0V;
Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
TC1775
Data Sheet 75 V1.2, 2002-05
Preliminary
Figure 24 Equivalent Circuitry of Analog Input
Note: This equivalent circuitry for an analog input is also valid for the reference inputs
VAREF and VAGND.
10) The overload coupling factor (kA) defines the worst case relation of an overload condition (IOV) at one pin to
the resulting leakage current (Ileak) into an adjacent pin: |Ileak| = kA × |IOV|.
Thus under overload conditions an additional error leakage voltage (UAEL) will be induced onto an adjacent
analog input pin due to the resistance of the analog input source (RAIN). That means UAEL = RAIN × |Ileak|.
See also section 7.1.6 “Error Through Overload Conditions” in the TC1775 Peripheral Units User’s Manual for
further explanations.
11) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage
at once. Instead of this smaller capacitances are successively switched to the reference voltage. Alternatively,
the redistributed charge could be specified.
12) The switched capacitance at the analog voltage input must be charged within the sampling time. Alternatively,
the redistributed charge could be specified.
MCS04879
R
AIN, Source
=
V
AIN
C
AIN, Block
R
AIN, On
C
AINTOT
-
C
AINSW
C
AINSW
A/D Converter
TC1775
Data Sheet 76 V1.2, 2002-05
Preliminary
Figure 25 ADC Clock Circuit
Note: The frequency of fADC is the system clock frequency (fSYS) divided by the value of
bit field ADCx_CLC.RMC.
Oscillator Pins (Class C Pins)
TA = -40 °C to +125 °C; VDDOSC = 2.30 to 2.75 V; VSSOSC = 0 V;
Parameter Symbol Limit Values Unit Test Conditions
min. max.
Input low voltage at
XTAL1, XTAL3
VILX SR -0.5 0.3 ×
VDDOSC
V–
Input high voltage at
XTAL1, XTAL3
VIHX SR 0.7 ×
VDDOSC
VDDOSC
+0.5
V–
Input current at XTAL1 IIX1 CC – ±20 µA0V < VIN < VDDOSC
Input current at XTAL3 IIX3 CC – ±0.5 µA0V < VIN < VDDOSC
Input leakage current
XTAL1, XTAL31)
1) Only applicable in deep sleep mode.
IOZ CC – ±200 nA 0 V< VIN < VDDOSC
MCA04657
Programmable
Clock Divider
(1:1) to (1:128)
4:1
3:1
f
BC
f
DIV
Peripheral
Clock Divider
(1:1) to (1:8)
f
ADC
f
ANA
Programmable
Counter
Sample
Time
t
S
CON.PCD CON.CTC CON.CPS CHCONn.STC
f
TIMER
Control/Status Logic
Interrupt Logic
External Trigger Logic
External Multiplexer Logic
Request Generation Logic
A/D Converter Module
Arbiter
(1:20) Control Unit
(Timer)
TC1775
Data Sheet 77 V1.2, 2002-05
Preliminary
Power Supply Current
TA = -40 °C to +125 °C;
Parameter Symbol Limit Values Unit Test Conditions
min. typ.1)
1) Parameters in this column are tested at 25 °C, 40 MHz system clock (if applicable) and nominal VDD voltages.
max.
Active mode supply
current
IDD CC – – 250 mA PORST =VIL2)3)
2) These parameters are tested at VDDmax and 40 MHz system clock with all outputs disconnected and all inputs
at VIL or VIH.
3) These power supply currents are defined as the sum of all currents at the VDD power supply lines:
VDD +VDDP05 +VDDP813 +VDDSRAM +VDDSB +VDDPLL +VDDOSC +VDDSC +VDDM +VDDA0 +VDDA1
– 266 320 mA Sum of IDDS4)
4) These power consumption characteristics are measured while running a typical application pattern. The power
consumption of modules can increase or decrease using other application programs. The PLL is inactive
during this measurement.
–36– mAIDD at VDDP054)
–4 – mAIDD at VDDP8134)
– 219 – mA IDD at VDD and
VDDSRAM4)
–3
4) 805)
5) This parameter has been evaluated at design characterization using an untypical test pattern that makes
extensive usage of the SBSRAM.
mA IDD at VDDSB
–4 – mAIDD at VDDSC and
VDDAx4)
Idle mode supply current IID CC – 80 200 mA PORST =VIH1)2)6)7)
6) All peripherals are enabled and in idle state.
7) Guaranteed by design characterization.
Sleep mode supply
current
ISL CC – 50 160 mA PORST =VIH1)2)7)
Deep sleep mode
supply current
IDS CC – 4 1000 µAPORST=VIH8)
8) IDS is the sum of all power supply currents except VDDSB.
Stand-by pin power
supply current
ISB CC – 1 200 µAIDD at VDDSB9)
9) TC1775 in deep sleep mode.
– 1 120 µA10)
10) All other VDD pins are at 0V; TJ=150 °C; VDDSB =2.0V.
TC1775
Data Sheet 78 V1.2, 2002-05
Preliminary
AC Characteristics
Output Rise/Fall Times
Class A drivers (GPIO/peripheral ports 8 to 13): VDDP813 = 4.5 to 5.25 V; VSS = 0 V
Class B drivers (Bus interface ports 0 to 5): VDDP05 = 2.30 to 2.75 V; VSS = 0 V
TA = -40 °C to +125 °C, unless otherwise noted; fSYS = 40 MHz
Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
Class A Pins
Nominal output rise/
fall time1)
1) Measured from 10% output level to 90% output level and vice versa.
tRFAnom
CC
–5–ns
TA = 25 °C, CL = 50 pF,
VDDP813 = 5.0 V
Px_POCON.PEC = 00B
Px_POCON.PDC = 0XB
Maximal output rise/
fall time1) tRFAmax
CC
––12ns
CL=50pF
Px_POCON.PEC = 00B
Px_POCON.PDC = 0XB
Slow output rise/fall
time1) tRFAslow
CC
––55ns
CL= 100 pF
Px_POCON.PEC = 01B
Px_POCON.PDC = 0XB
Class B Pins
Output rise/fall time1) tRFBmax
CC
––4nsfor CLKOUT
CL = 50 pF
– – 7 ns for all Class B pins
except CLKOUT
CL = 50 pF
TC1775
Data Sheet 79 V1.2, 2002-05
Preliminary
Testing Waveforms
TA = -40 °C to +125 °C; Frequency: max. 40 MHz;
Class A Pins: VDDP813 = 3.0 to 5.25 V; VSS = 0 V;
Figure 26 Testing Waveforms for Class A Pins
Class B and Class C Pins: VDD = 2.30 to 2.75 V; VSS =0V;
VDDOSC = 2.30 to 2.75 V; VSSOSC =0V;
Figure 27 Testing Waveforms for Class B and Class C Pins
Figure 28 Tri-State Testing Waveforms for Class B Pins
MCT04880
V
IHmin
V
ILmax
V
OHmin
V
OLmax
V
OHmin
V
OLmax
Test Points
AC inputs during testing are driven with VIHmin for a logic 1 and VILmax for a logic 0.
Timing measurements are made at VOHmin for a logic 1 and VOLmax for a logic 0.
Input and Output Low/High max./min. voltages are defined at Page 68.
MCT04881
V
IHmin
V
ILmax
V
DD
/ 2 Test Points V
DD
/ 2
AC inputs during testing are driven with VIHmin for a logic 1 and VILmax for a logic 0.
Timing measurements are made at VDD/2 for a logic 1 and for a logic 0.
Input Low/High max./min. voltages are defined at Page 69 and Page 76.
MCT05074
V
Load
+ 0.1 V
V
OH
- 0.1 V
Timing
Reference
Points
V
Load
- 0.1 V
V
OL
- 0.1 V
For timing purposes a port pin is no longer floating when a 100 mV change from load
voltage occurs, but begins to float when a 100 mV change from the loaded VOH/VOL
level occurs (IOH/IOL = 15 mA).
TC1775
Data Sheet 80 V1.2, 2002-05
Preliminary
Input Clock Timing
VDDOSC = 2.30 to 2.75 V; VSSOSC = 0 V; TA= -40 °C to +125 °C;
Figure 29 Input Clock Timing
Parameter Symbol Limit Values Unit
min. max.
Oscillator clock frequency direct drive fOSC SR
(= 1/tOSC)
116MHz
with PLL 10 16 MHz
Input clock frequency driving
at XTAL1
direct drive 1/tOSCDD
SR
–40MHz
with PLL 10 30 MHz
Input clock high time t1SR 7 – ns
Input clock low time t2SR 7 – ns
Input clock rise time t3SR – 4 ns
Input clock fall time t4SR – 4 ns
MCT04882
0.5
V
DDOSC
Input Clock
at XTAL1
t
OSC
t
1
t
2
V
IHX
V
ILX
t
4
t
3
TC1775
Data Sheet 81 V1.2, 2002-05
Preliminary
CLKOUT Timing
VSS =0V; VDDP05 = 2.30 to 2.75 V; TA=-40°C to +125 °C; CL= 50 pF;
Figure 30 CLKOUT Output Clock Timing
Parameter Symbol Limit Values Unit
min. typ. max.
Clock period tCLKOUT
CC
25––ns
Clock high time t5CC7.5––ns
Clock low time t6CC7.5––ns
Clock rise time t7CC––4ns
Clock fall time t8CC––4ns
Clock duty cycle t5/(t5 + t6)DC CC 45 50 55 %
0.9
V
DDP
MCT04883
0.5
V
DDP05
CLKOUT
t
CLKOUT
t
5
t
6
0.1
V
DDP
t
8
t
7
TC1775
Data Sheet 82 V1.2, 2002-05
Preliminary
PLL Parameters
Note: All PLL characteristics defined on this and the next page are guaranteed by design
characterization.
VSS =0V; VDD = 2.30 to 2.75 V; TA=-40 °C to +125 °C;
Phase Locked Loop Operation
When PLL operation is enabled and configured (see Figure 18 and Page 59), the PLL
clock fVCO (and with it the system clock fSYS) is constantly adjusted to the selected
frequency. The relation between fVCO and fSYS is defined by: fVCO =K×fSYS. The PLL
causes a jitter of fSYS and also of CLKOUT, which is directly derived from fSYS and which
has its frequency.
The following two formulas define the (absolute) approximate maximum value of jitter DN
in ns dependent on the K-factor, the system clock frequency fSYS in MHz, and the
number P of consecutive fSYS periods.
[1]
[2]
With rising number P of clock cycles the maximum jitter increases linearly up to a value
of P that is defined by the K-factor of the PLL. Beyond this value of P the maximum
accumulated jitter remains at a constant value. Further, a lower system clock frequency
fSYS results in a higher maximum jitter.
Figure 31 gives an example for the jitter curves with K=8.
Parameter Symbol Limit Values Unit
min. max.
Accumulated jitter DNsee Figure 31 –
VCO frequency range fVCO 150 200 MHz
PLL base frequency fPLLBASE 40 130 MHz
PLL lock-in time tL–200µs
for P < 23.5
K DN [ns] = ±3.9
fSYS [MHz]×P+ 1.2
for P > 23.5
K DN [ns] = ± 91.7
fSYS [MHz] × K+ 1.2
TC1775
Data Sheet 83 V1.2, 2002-05
Preliminary
Figure 31 Approximated Maximum Accumulated PLL Jitter (for K = 8)
Note: For safe clock generation and PLL operation the definitions and restrictions as
defined at pages 58, 59, and 80 must be regarded.
MCD05237
0
±1.0
P
ns
D
N
±1.2
±1.4
±1.6
±2.0
123456
D
N
P
K
K
= 8
20 MHz
25 MHz
33 MHz
40 MHz
= Max. jitter
= Number of consecutive
f
SYS
periods
= K-divider of PLL
TC1775
Data Sheet 84 V1.2, 2002-05
Preliminary
EBU Demultiplexed Timing
VSS =0V; VDDP05 = 2.30 to 2.75 V; TA=-40°C to +125 °C; CL= 50 pF;
Parameter Symbol Limit Values Unit
min. max.
Output delay from CLKOUT t10 CC 0 9 ns
Output delay from CLKOUT t11 CC -2 4 ns
Data setup to CLKOUT t12 SR 9 – ns
Data hold from CLKOUT 1)
1) Valid for EBU_BUSCONx.26 = 0.
t13 SR 1 – ns
Data valid after CLKOUT 1) t15 CC 2 – ns
Data setup to CLKIN 2)
2) Valid for EBU_BUSCONx.26 = 1 (early sample feature). Not applicable for TC1775 BA11 step.
t31 SR see Page 90 –ns
Data hold from CLKIN 2) t32 SR see Page 90 –ns
TC1775
Data Sheet 85 V1.2, 2002-05
Preliminary
Figure 32 EBU Demultiplexed Read Timing
Note: WAIT timing see Figure 36.
Address Valid
Data Valid
MCT05075
CLKIN
ADV
RD
RD/WR
D[31:0]
Normal
Sampling
BC[3:0]
t
10
t
11
t
11
t
10
t
12
t
13
t
11
t
10
t
11
t
10
t
11
t
11
t
10
A[25:0]
SVM
CODE
CSx
Data Valid
t
31
t
32
D[31:0]
Early
Sampling
CLKOUT
1)
1) Early sampling for D[31:0] not available in TC1775 BA11 step.
TC1775
Data Sheet 86 V1.2, 2002-05
Preliminary
Figure 33 EBU Demultiplexed Write Timing
Data Valid
MCT04885
CLKOUT
ADV
CSx
RD
RD/WR
D[31:0]
BC[3:0]
t
10
t
11
t
11
t
10
t
11
t
10
t
11
t
10
t
11
t
11
t
10
t
15
t
10
Address Valid
1)
CODE remains at high level during a demultiplexed write cycle
A[25:0]
CODE
1)
SVM
TC1775
Data Sheet 87 V1.2, 2002-05
Preliminary
EBU Multiplexed Timing
VSS =0V, VDDP05 = 2.30 to 2.75 V; TA=-40 °C to +125 °C; CL= 50 pF;
Figure 34 EBU Multiplexed Read Timing
Parameter Symbol Limit Values Unit
min. max.
Output delay from CLKOUT 1)
1) The following condition is always valid: t25 < t20
t20 CC -2 10 ns
Output delay from CLKOUT t21 CC -2 4 ns
Data setup to CLKOUT t22 SR 9 – ns
Data hold from CLKOUT t23 SR 1 – ns
Address and data valid after CLKOUT 1) t25 CC 2 – ns
Address Valid
MCT04886
CLKOUT
Data In
AD[31:0]
ALE
RD
RD/WR
BC[3:0]
t
20
t
25
t
22
t
23
t
20
t
20
t
20
t
21
t
21
t
20
t
21
t
21
t
20
CODE
SVM
t
20
t
20
CSx
TC1775
Data Sheet 88 V1.2, 2002-05
Preliminary
Figure 35 EBU Multiplexed Write Timing
Address Valid
MCT04887
CLKOUT
Data Out
AD[31:0]
ALE
CSx
RD
RD/WR
BC[3:0]
t
20
t
25
t
20
t
20
t
20
t
20
t
21
t
21
t
20
t
21
t
21
t
20
t
20
t
25
t
20
CODE
1)
SVM
1)
CODE remains at high level during a multiplexed write cycle
TC1775
Data Sheet 89 V1.2, 2002-05
Preliminary
WAIT Timing (FPI Bus to external Memory)
VSS =0V; VDDP05 = 2.30 to 2.75 V; TA=-40 °C to +125 °C; CL= 50 pF;
Figure 36 WAIT Timing (from FPI Bus to external Memory)
Parameter Symbol Limit Values Unit
min. max.
WAIT setup to CLKOUT t50 SR 141)
1) Guaranteed by design characterization.
–ns
WAIT hold from CLKOUT t51 SR 141) –ns
WAIT setup to CLKOUT t52 SR 7 – ns
WAIT hold from CLKOUT t53 SR 2 – ns
MCT04888
CLKOUT
t
50
t
51
t
50
t
51
WAIT
Synchronous Mode
CLKOUT
t
52
t
53
t
52
t
53
WAIT
Asynchronous Mode
TC1775
Data Sheet 90 V1.2, 2002-05
Preliminary
EBU Burst Mode Timing
VSS =0V, VDDP05 = 2.30 to 2.75 V; TA=-40°C to +125 °C; CL= 50 pF;
Figure 37 Burst Mode Timing (Instruction Read)
Note: Burst mode and external Flash related application hints are described in a
separate application note.
Parameter Symbol Limit Values Unit
min. max.
Output delay from CLKIN t30 CC 0 14 ns
Data setup to CLKIN t31 SR 21)
1) Guaranteed by design characterization.
–ns
Data hold from CLKIN t32 SR 31) –ns
Address Valid
ValidValid
MCT04889
CLKIN
t
30
t
30
t
30
t
30
t
30
t
30
t
30
t
32
t
31
t
32
t
31
A[25:2]
CS0
CODE
RD
BAA
ADV
D[15:0]
Note: WAIT must be 1 during a Burst Mode Read Cycle.
t
30
t
30
TC1775
Data Sheet 91 V1.2, 2002-05
Preliminary
EBU Arbitration Signal Timing
VSS =0V, VDDP05 = 2.30 to 2.75 V; TA=-40 °C to +125 °C; CL= 50 pF;
Figure 38 EBU Arbitration Signal Timing
Parameter Symbol Limit Values Unit
min. max.
Output delay from CLKOUT t40 CC – 3 ns
Data setup to CLKOUT t41 SR 8 – ns
Data hold from CLKOUT t42 SR 2 – ns
MCT04890
CLKOUT
HLDA Output
BREQ Output
t
40
t
40
t
40
t
40
CLKOUT
t
42
HOLD Input
t
41
t
42
t
41
HLDA Input
TC1775
Data Sheet 92 V1.2, 2002-05
Preliminary
EBU External Access Timing
VSS =0V, VDDP05 = 2.30 to 2.75 V; TA=-40 °C to +125 °C; CL= 50 pF;
Parameter Symbol Limit Values Unit
min. max.
CSFPI, BC[3:0], A[23:2] setup
before RD or RD/WR
t43 SR 3 – ns
Data valid after RD t44 CC 2 × tCLKOUT –ns
WAIT active after RD or RD/WR t45 CC – 11 ns
RD/WAIT float after RD or RD/WR t46 CC – 20 ns
Data setup to RD/WR t47 SR 3 – ns
Data hold from RD/WR t48 SR 3 – ns
TC1775
Data Sheet 93 V1.2, 2002-05
Preliminary
Figure 39 EBU External Access Timing (external Master to FPI Bus)
Data Valid
Data Valid
MCT04891
t
43
t
44
t
46
t
45
A[23:2]
BC[3:0]
CSFPI
RD
RD/WR
AD[31:0]
WAIT
Read Timing
Valid Address & Byte Control
t
43
t
45
A[23:2]
BC[3:0]
CSFPI
RD
RD/WR
AD[31:0]
WAIT
Write Timing
Valid Address & Byte ControlValid Address & Byte Control
t
48
t
47
t
46
t
46
TC1775
Data Sheet 94 V1.2, 2002-05
Preliminary
Port 5 (Trace Port) Timing
This timing is applicable for Port 5 when CPU or PCP trace mode is enabled
(SCU_CON.ETEN = 1).
VSS =0V; VDDP05 = 2.30 to 2.75 V; TA=-40 °C to +125 °C; CL= 50 pF;
Figure 40 Port 5 Timing
Parameter Symbol Limit Values Unit
min. max.
Port 5 lines high/low from CLKOUT t55 CC -4 5 ns
MCT04892
CLKOUT
t
55
P5[15:0] Old State New State
TC1775
Data Sheet 95 V1.2, 2002-05
Preliminary
SSC Master Mode Timing
VSS =0V; VDDP813 = 4.5 to 5.25 V; TA= -40 °C to +125 °C; CL= 50 pF;
Figure 41 SSC Master Mode Timing
Parameter Symbol Limit Values Unit
min. max.
SCLK/MTSR low/high from CLKOUT 1)
1) This parameter is valid for high current mode output driver characteristic and normal timing edge characteristic
(P13_POCON.PECx = 00B and P13_POCON.PDCx = 00B).
t60 CC – 7 ns
MRST setup to SLCK rising/falling edge t61 SR 142)
2) Guaranteed by design characterization.
–ns
MRST hold from SLCK rising/falling edge t62 SR 142) –ns
State n
MCT04893
CLKOUT
SCLK
t
60
MTSR
t
60
t
61
t
62
Data Valid
State n-1 State n+1
t
CLKOUT
t
60
MRST
Note: The timing diagram assumes the highest possible baud rate operation.
(
f
SSC
=
f
CLKOUT
, SSCx_CLC.RMC = 1, SSCx_BR.BR_VALUE = 0000
H
)
TC1775
Data Sheet 96 V1.2, 2002-05
Preliminary
Package Outlines
0.35
4 x 1.27 = 5.08
ø0.15
329x
22 x 1.27 = 27.94
1.95 x 45˚
4x
26
31
±0.2
±1
0.6
(0.56)
1.17
±0.05
±0.1
+0.14
-0.16
ø0.76
30˚
ø0.3
22 x 1.27 = 27.94
4 x 1.27 = 5.08
A23
1.27
2.52 MAX.
Index Marking
B
A
26
31
±1
±0.2
B
M
M
C
AC
C
0.2 C
AC1
A1
P-BGA-329
(Plastic Ball Grid Array Package)
GPA09280
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
SMD = Surface Mounted Device
http://www.infineon.com
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