Cinayv vipex SP7512 and HS3120 SIGNAL PROCESSING EXCELLENCE DoubleBuffered 12-Bit Multiplying DAC @ Monolithic Construction @ 12-Bit Resolution @ 0.01% Non-Linearity @ FourQuadrant Multiplication @ Latch-up Protected @ Low Power 30mW @ Single +15V Power Supply DESCRIPTION... The SP7512 and HS3120 are precision 12-bit multiplying DACs, doublebuffered for easy interfacing with microprocessor busses. Both unipolar and bipolar operation can be accommo- dated with a minimum of external components. The SP7512 is available for use in commercial and industrial temperature ranges, packaged in a 28-pin SOIC. The HS3120 is available in commercial and military temperature ranges, packaged in a 28-pin side-brazed DIP. (MSB} (LSB) Bt 2 3 4 5 6 7 8 9 10 11 8712 VREF 10 14 12 13) 14 16 17| 18 19; 20 4 INPUT REGISTER INPUT REGISTER INPUT REGISTER CONTROL LOGIC LDAC DAC REGISTER 12 BIT MDAC SP7512, HS3120 Vob1 VDD2 LDTR [Wun 113 SIGNAL PROCESSING EXCELLENCECAUTION: ESD (ElectroStatic Discharge) sensitive device. Permanent damage may occur on x / unconnected davices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. Personnel should be property grounded prior to handling this device. The protective foam SPECIFICATIONS socketheloredaveos are removed, (Typical @ 25C, nominal power supply, V,,, = +10V, unipolar, unless otherwise nated) PARAMETER MIN. TYP, MAX. UNITS CONDITIONS DIGITAL INPUT Resolution 12 Bits 2-Quad, Unipolar Coding Binary & Comp. Binary The input coding is comple- | | mentary binary if Ip, is used. 4Quad, Bipolar Coding Offset Binary Logic Compatibility CMOS, TTL Digital input voltage must not exceed supply voltage or go below 0.5V ; 0 <0.8V; 2.4V <1" Von Input Current +1 HA Data Set-up Time 250 ns All strobes are level triggered. See Timing Diagram; GBD* Strobe Width 250 ns All strobes are level triggered. See Timing Diagram; GBD* Data Hold Time 0 ns All strobes are level triggered. See Timing Diagram; GBD* REFERENCE INPUT Voltage Range +25 Vv Input Impedance 4 12 KOhms ANALOG OUTPUT Scale Factor 62.5 187.5 WAN ore Scale Factor Accuracy +0.4 % Using the intemal feedback resistor and an extemal op amp. Output Leakage 10 nA At 25C; the output leakage current will create an offset voltage at the extemal op amps output. It doubles every 10C temperature increase. Output Capacitance Coyr 1, all inputs high 80 pF Cour 1, all inputs low 40 pF Coy7 2, all inputs high 40 pF Cou 2, all inputs low 80 pF STATIC PERFORMANCE Integral Linearity SP7512BN/KN, HS3120-2 +0.015 % FSR Differential Linearity SP7512BN/KN, HS3120-2 +0,024 %FSR Monotonicity SP7512BN/KN, HS31202 Guaranteed to 12 bits STABILITY (Typ, tO Tara) Scale Factor 2 ppm FSR/&C Note 1 Integral Linearity 0.2 ppm FSR/C Differential Linearity 0.2 ppm FSRC STABILITY (Tyany 10 Taya) Monotonicity Temp. Range SP7512KN, HS3120C_ 0 +70 C SP7512BN 40 +85 C HS3120B_ -55 +125 C 114 ipex SIGNAL PROGESSING EXCELLENCESPECIFICATIONS (continued) (Typical @ 25C, nominal power supply, V, REF = +10V, unipolar unless otherwise noted) PARAMETER MIN. TYP. MAX. UNITS CONDITIONS DYNAMIC PERFORMANCE Digital Small Signal Settling 1.0 pS Full Scale Transition Settling 2.0 us fo 0.01% (strobed) Reference Feedthrough Error (Veer = 20Vpp) @ 1kHz <1 mV @ 10kHz 2 mV Delay to output from Bits input 100 ns Delay times are twice the from LDAC 200 ns amount shown at T, = +125 C from CE 120 ns POWER SUPPLY (V,,,) Operating Voltage +15 +5% Vv specifications guaranteed Voltage Range +5 +16 Vv Current 25 mA Rejection Ratio 0.002 %ol%o ENVIRONMENTAL AND MECHANICAL Operating Temperature SP7512K 0 +70 C SP7512B 40 +85 C HS3120-C 0 +70 C HS3120-B 55 +125 C HS3120-B/883 55 +125 C Storage Temperature -65 +150 C Package SP7512_N 28-pin SOIC HS3120-C 28-pin Plastic DIP HS3120-B 28-pin Side-Brazed DIP Notes: 1. Using the internal feedback resistor, output leakage current creates an offset, which doubles every 10C rise in temperature. SIDSX 115 SIGNAL PROCESSING EXCELLENCEPIN ASSIGNMENTS Pin | FB, Feedback Bipolar Operation Pin 2 - LDTR Ladder Termination Pin 3 FB, Feedback Bipolar Operation Pin 4 ~ V,..,, Reference Voltage Input Pin 5 FB, Feedback, Unipolar/Bipolar Pin 6 I,,, Current out into virtual ground Pin 7 I, Current out-complement of I), Pin 8 V..Ground, Analog and DAC Register Pin 9 DB, , MSB, Data Bit I Pin 10 DB,, Data Bit 2 Pin 11 DB, Data Bit 3 Pin 12 - DB, ~ Data Bit 4 Pin 13 DB, Data Bit 5 Pin 14 DB, Data Bit 6 Pin 15 DB, Data Bit 7 Pin 16 - DB, Data Bit 8 Pin 17 DB, Data Bit 9 Pin 18 DB, Data Bit 10 Pin 19 DB, Data Bit 11 Pin 20 - DB, LSB, Data Bit 12 Pin 21 ~ LDAC Transfers data from input to DAC register; a logic O latches data into registers; a logic 1 allows data to change (transfer to) register. Pin 22 CE Chip Enable, active low Pin 23 LBE - Bit 12 to Bit 9 Enable Pin 24 MBE - Bit 8 to Bit 5 Enable Pin 25 HBE -~ Bit 4 to Bit 1 Enable Pin 26 Vpp2 ~ Supply Analog and DAC Register Pin 27 Vc, Pin 28 V,,,, Supply input latches NOTE: Pins 8 and 27, and pins 26 and 28 must be connected externally. Ground input latches FEATURES... The SP7512 and HS3120 are precision 12-bit multiplying DACs with internal two-stage input storage registers for easy interfacing with mi- croprocessor busses. The DACs are implemented as a one-chip CMOS circuit with a resistor ladder network designed for 0.01% linearity without laser trimming. The input registers are sectioned into 3 seg- ments of 4 bits each, all individually address- able. The DAC-register, following the input registers, is a parallel 12-bit register for holding the DAC data while the input registers are up- dated. Only the data held in the DAC register determines the analog output value of the con- verter. The SP7512 and HS3120 have been designed for great flexibility in connecting to bus-ori- ented systems. The 12 data inputs are organized into 3 independent addressable 4-bit input reg- isters such that the DACs can be connected to either a 4, 8 or 16-bit data bus. The control logic of the DACs includes chip enable and latch enable inputs for flexible memory mapping. All controls are level-triggered to allow static or dynamic operation. A total of 5 output lines are provided on the DACs to allow unipolar and bipolar output connection with a minimum of external compo- nents. The feedback resistor is internal. The resistor ladder network termination is exter- nally available, thus eliminating an external resistor for the 1 LSB offset in bipolar mode. The SP7512 is available for use in commercial and industrial temperature ranges, packaged in 400n +15V VREF l ' ' DIGITAL INPUTS l SP7512 t i t 1 oO CE ol LBE O__ = LDAC Figure 1. Unipolar Operation 116 Sipex SIGNAL PROCESSING EXCELLENCE15 +15V | 20KQ 40012 ADJUSTMENT VaEE 18V RANGE 0.2% Oo IN Puts [}-O. vouT al LBE O___+ = VOUTI Aq. Ag, LFAL1ACN Figure 2. Bipolar Operation a 28-pin SOIC. The HS3120 is available in commercial and military temperature ranges, packaged in a 28pin side~brazed DIP. For product processed and screened to the require- ments of MIL-M-38510 and MIL-STD--883C, please consult the factory (HS3120B only). APPLICATIONS INFORMATION Unipolar Operation Figure I shows the interconnections for unipo- lar operation. Connect I), and FB, as shown in diagram. Tie I, (Pin 7), FB, (Pin 3), and FB, (Pin 1) to Ground (Pin 8), To maintain specified linearity, external amplifiers must be zeroed. This is best done with V,,.,. set to zero and, with the DAC register loaded with all bits at zero, adjust Rog for Voy, = OV TRANSFER FUNCTION (N=12) BINARY INPUT | UNIPOLAR OUTPUT| BIPOLAR OUTPUT 14414 Voge 1-2) | Vpee (1-2 8-9) 100...001 Voge (V2 +24) Voge (28-1) 100...000 Voge (2 0 O14. Mace (1/2 2-4) Veer (2 8-9) 000...000 0 Veer Table I. Transfer Function Bipolar Operation Figure 2 shows the interconnections for bipolar operation. Connect Toy Igo FB FB,, FB 4 as shown in diagram. Tie LDTR to Ip,. To main- tain specified linearity, external amplifiers must be zeroed. This is best done with V pp, set to Zero and, the DAC register loaded with 10...0 (MSB = 1), set Rog, for Voury = OV. Then set Rog, for Vout = OV. Grounding Connect all GND pins to system analog ground and tie this to digital ground. All unused input pins must be grounded. sipex SIGNAL PROCESSING EXCELLENCETIMING R RA r DADA P DATA SXXXR) RRR SOS | CE LBE MBE HBE LDAC | te \t OUTPUT ! p tg TIME AXIS NOT TO SCALE. ALL STROBES ARE LEVEL TRIGGERED. t,; Data Setup Time, Time data must be stable before strobe (byte enable/ LDAC) goes to 0, t, (min) = 250ns. tL; Strobe Width. t, (min) = 250ns. (CE, LBE, MBE, HBE, LDAC). t, Hold Time. Time data must be stable after strobe goes to 0, t, = Ons. t,; Delay from LDAC to Output, t, = 200ns. NOTE: Minimum common active time for CE and any byte enable is 250ns. ORDERING INFORMATION Me) .....sccssssessecseesesssnssersnesentseteanastetsecceseatensenents MOnotonicity ......ccreoreescrssseesarees Temperature Range .........cscceesesesssecneteees Package Double-Buffered 12-Bit Multiplying DAC SP7512BN i 28-pin, 0.3" SOIC SP7512KN 12-Bit 0C to +70C ... 28-pin, 0.3" SOIC HS3120C-2N. 12-Bit . OC to +70C .... 28-pin, 0.6" Plastic DIP HS3120C-20 .... TOBit eect cece teers neeetetees OC to +70C ... 28-pin, 0.6" Side-Brazed DIP HS31 20B-2Q oo... eesescccsesssnssecseasesessennsssareetenteeerssnanees 12-Bit .. ~55C to +125C .. .. 28-pin, 0.6" Side-Brazed DIP HS3120B-2/883 12-Bit oo. eects 58C to +125C cece 28-pin, 0.6" SideBrazed DIP / 118 Ssipex (Conporaivon SIGNAL PROCESSING EXCELLENCE