TLV320DAC23IPWRG4 - Texas Instruments

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February 2004 Digital Audio Products

Data M anua

SLES001C

iii

Contents

Section Title Page

1 Introduction 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Features 1−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Functional Block Diagram 1−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Terminal Assignments 1−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Ordering Information 1−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Terminal Functions 1−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Specifications 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Absolute Maximum Ratings Over Operating Free-Air Temperature

Range 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Recommended Operating Conditions 2−1. . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Electrical Characteristics Over Recommended Operating

Conditions 2−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.1 DAC 2−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.2 Analog Line Input to Line Output 2−2. . . . . . . . . . . . . . . . . . . . . .

2.3.3 Stereo Headphone Output 2−3. . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.4 Analog Reference Levels 2−3. . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.5 Digital I/O 2−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.6 Supply Current 2−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Digital-Interface Timing 2−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.1 Audio Interface (Master Mode) 2−4. . . . . . . . . . . . . . . . . . . . . . .

2.4.2 Audio Interface (Slave-Mode) 2−5. . . . . . . . . . . . . . . . . . . . . . . .

2.4.3 Three-Wire Control Interface (SDI) 2−6. . . . . . . . . . . . . . . . . . . .

2.4.4 Two-Wire Control Interface 2−6. . . . . . . . . . . . . . . . . . . . . . . . . . .

3 How to Use the DAC23 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Control Interfaces 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.1 SPI 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.2 2-Wire 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.3 Register Map 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Analog Interface 3−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.1 Line Inputs 3−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.2 Line Outputs 3−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.3 Headphone Output 3−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Digital Audio Interface 3−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.1 Digital Audio-Interface Modes 3−5. . . . . . . . . . . . . . . . . . . . . . . .

3.3.2 Audio Sampling Rates 3−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.3 Digital Filter Characteristics 3−10. . . . . . . . . . . . . . . . . . . . . . . . . .

A Mechanical Data A−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Illustrations

Figure Title Page

2−1 System-Clock Timing Requirements 2−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−2 Master-Mode Timing Requirements 2−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−3 Slave-Mode Timing Requirements 2−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−4 Three-Wire Control Interface Timing Requirements 2−6. . . . . . . . . . . . . . . . . .

2−5 Two-Wire Control Interface Timing Requirements 2−6. . . . . . . . . . . . . . . . . . .

3−1 SPI Timing 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−2 2-Wire Compatible Timing 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−3 Analog Line Input Circuit 3−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−4 Right Justified Mode Timing 3−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−5 Left Justified Mode Timing 3−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−6 I2S Mode Timing 3−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−7 DSP Mode Timing 3−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−8 Digital De-Emphasis Filter Response − 44.1 kHz Sampling 3−10. . . . . . . . . . .

3−9 Digital De-Emphasis Filter Response − 48 kHz Sampling 3−11. . . . . . . . . . . .

3−10 DAC Digital Filter Response 0: USB Mode 3−11. . . . . . . . . . . . . . . . . . . . . . . . .

3−11 DAC Digital Filter Ripple 0: USB Mode 3−11. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−12 DAC Digital Filter Response 1: USB Mode Only 3−12. . . . . . . . . . . . . . . . . . . .

3−13 DAC Digital Filter Ripple 1: USB Mode Only 3−12. . . . . . . . . . . . . . . . . . . . . . . .

3−14 DAC Digital Filter Response 2: USB Mode and Normal Modes 3−12. . . . . . . .

3−15 DAC Digital Filter Ripple 2: USB Mode and Normal Modes 3−13. . . . . . . . . . .

3−16 DAC Digital Filter Response 3: USB Mode Only 3−13. . . . . . . . . . . . . . . . . . . .

3−17 DAC Digital Filter Ripple 3: USB Mode Only 3−13. . . . . . . . . . . . . . . . . . . . . . . .

1−1

1 Introduction

The TLV320DAC23 is a high performance stereo DAC with highly integrated analog functionality. The DACs within

the TLV320DAC23 are comprised of multibit sigma-delta technology with integrated over-sampling digital

interpolation filters. Supported data transfer word lengths are 16, 20, 24, and 32 bits with sample rates from 8 kHz

to 96 kHz. The DAC sigma-delta modulator features a second order multibit architecture with up to 100 dBA SNR

at audio sample rates up to 96 kHz. This enables high quality digital audio playback capability while consuming less

than 19 m W during playback only. The TLV320DAC23 is the ideal choice for portable digital audio player applications

such as MP3 digital audio players.

Integrated analog features consist of stereo line inputs with an analog bypass path and a stereo headphone amplifier

with analog volume control and mute. The headphone amplifier is capable of delivering 30 mW per channel into 32 Ω.

The analog bypass path allows use of the stereo line inputs and the headphone amplifier with analog volume control

while completely bypassing the DAC, thus enabling further design flexibility such as integrated FM tuners.

While the TLV320DAC23 supports the industry standard over-sample rates of 256 fs and 384 fs, unique over-sample

rates of 250 fs and 272 fs are provided which optimize interface considerations in designs using TI C54x DSPs and

USB data interfaces. A single 12-MHz crystal can be used to supply clocking to the DSP, USB, and DAC. The

TLV320DAC23 features an internal oscillator which, when connected to a 12-MHz external crystal, will provide a

system clock to the DSP and other peripherals at either 12 MHz or 6 MHz using an internal clock buf fer and selectable

divider. Audio sample rates of 48 kHz and CD standard rates of 44.1 kHz are directly supported from a 12-MHz master

clock with 250 fs and 272 fs over-sample rates.

Low power consumption and flexible power management allow selective shutdown of DAC functions, thus extending

battery life in portable applications. Couple this design solution with the industry’ s smallest package, the TI proprietary

MicroStar Junior using only 25 mm2 of board area, powerful portable stereo audio designs are easily realizable in

a cost effective, space saving total analog solution.

MicroStar Junior is a trademark of Texas Instruments.

1−2

1.1 Features

•High-Performance Stereo DAC

− 100-dB SNR multibit sigma-delta ADC (A-weighted at 48 kHz)

− 1.42 V – 3.6 V digital supply: compatible with TI C54x DSP core voltages

− 2.7 V – 3.6 V analog supply: compatible TI C54x DSP buffer voltages

− 8-kHz – 96-kHz sampling-frequency support

•Software control via TI McBSP-compatible multiprotocol serial port

− 2-wire-compatible and SPI-compatible serial port protocols

− Glueless interface to TI McBSPs

•Audio data input/output via TI McBSP compatible programmable audio interface

−I

2S-compatible interface

− Standard I2S, MSB, or LSB justified data transfers

− 16/20/24/32-bit word lengths

− Audio master/slave timing capability optimized for TI DSPs (250/272 fs)

− Industry-standard master/slave support also provided (256/384 fs)

− Glueless interface to TI McBSPs

•Stereo line inputs

•Stereo line outputs

− Analog stereo mixer for DAC and analog bypass path

•Analog volume control with mute

•Highly efficient linear headphone amplifier

− 30 mW into 32 Ω from a 3.3-V analog supply voltage

•Flexible power management under total software control

− 18-mW power consumption during playback mode

− Standby power consumption <150 µW

− Power-down power consumption <15 µW

•Industry’s smallest package: 32-Pin TI proprietary MicroStar Junior

−25 mm

2 total board area

− 28-Pin TSSOP available (62 mm2 total board area)

− 28-Pin QFN available (25 mm2 total board area)

•Ideally suitable for portable solid-state audio players and recorders

1−3

1.2 Functional Block Diagram

Control

Interface

Digital

Filters

Digital

Audio

Interface

Σ−∆

DAC

6 to −73 dB,

1-dB Steps

Headphone

Driver

Σ−∆

DAC

6 to −73 dB,

1-dB Steps

Headphone

Driver

CLKIN

Divider

(1x, 1/2x)

OSC

SDI

SCLK

MODE

DVDD

BVDD

DGND

LRCIN

DIN

BCLK

AVDD

VMID

AGND

RLINEIN

LLINEIN

HPVDD

HPGND

RHPOUT

ROUT

LOUT

LHPOUT

XTI/MCLK

XTO

CLKOUT

TLV320DAC23

1.0X

VMID

50 kΩ

VDAC

1.0X

VDAC

CLKOUT

(1x, 1/2x)

DAC

Select

Bypass

1−4

1.3 Terminal Assignments

LRCIN

123456789

25 24 23 22 21 20 19 18 17

HPVDD

LHPOUT

RHPOUT

HPGND

XTI/MCLK

SCLK

SDIN

MODE

LLINEIN

RLINEIN

LOUT

ROUT

AVDD

AGND

VMID

DIN

BCLK

CLKOUT

BVDD

DGND

DVDD

XTO

GQE PACKAGE

(TOP VIEW)

BVDD

CLKOUT

BCLK

DIN

LRCIN

HPVDD

LHPOUT

RHPOUT

HPGND

LOUT

ROUT

AVDD

DGND

DVDD

XTO

XTI/MCLK

SCLK

SDIN

MODE

LLINEIN

RLINEIN

VMID

AGND

PW PACKAGE

(TOP VIEW)

NC − No internal connection

1−5

BCLK

CLKOUT

BVDD

DGND

DVDD

XTO

XTI/MCLK

HPGND

LOUT

ROUT

AVDD

AGND

VMID

DIN

LRCIN

HPVDD

LHPOUT

RHPOUT

SCLK

SDIN

MODE

LLINEIN

RLINEIN

RHD PACKAGE

(TOP VIEW)

NC − No internal connection

1.4 Ordering Information

PACKAGE

TA32-Pin

MicroStar Junior GQE 28-Pin

TSSOP PW 28-Pin

QFN RHD

−10°C to 70°C TLV320DAC23GQE TLV320DAC23PW TLV320DAC23RHD

−40°C to 85°C TLV320DAC23IGQE TLV320DAC23IPW TLV320DAC23IRHD

1−6

1.5 Terminal Functions

TERMINAL

NAME

NUMBER

I/O

DESCRIPTION

NAME

GQE PW RHD

I/O

DESCRIPTION

AGND 5 15 12 − Analog supply return

AVDD 4 14 11 −Analog supply input. Voltage level is 3.3 V nominal.

BCLK 23 3 28 I/O I2S serial-bit clock. In audio master mode, the DAC23 generates this signal and sends it to the

DSP. In audio slave mode, the signal is generated by the DSP.

BVDD 21 1 26 − Buffer supply input. Voltage range is from 2.7 V to 3.6 V.

CLKOUT 22 2 27 O Clock output. This is a buffered version of the XTI input and is available in 1X or 1/2X

frequencies of XTI. Frequency selection is controlled by bit X in control register XX.

CS 12 21 18 I Control port input latch/address select. For SPI control mode this input acts as the data latch

control. For 2-wire control mode this input defines the seventh bit in the device address field.

See Section 3.1 for details.

DIN 24 4 1 I I2S format serial data input to the sigma-delta stereo DAC

DGND 20 28 25 − Digital supply return

DVDD 19 27 24 − Digital supply input. Voltage range is 1.4 V to 3.6 V.

HPGND 32 11 8 − Analog headphone amplifier supply return

HPVDD 29 8 5 − Analog headphone amplifier supply input. Voltage level is 3.3 V nominal.

LHPOUT 30 9 6 O Left stereo mixer-channel amplified headphone output. Nominal 0-dB output level is 1.0 VRMS.

Gain of –73 dB to 6 dB is provided in 1-dB steps.

LLINEIN 11 20 17 I Left stereo-line input channel

LOUT 2 12 9 O Left stereo mixer-channel line output. Nominal output level is 1.0 VRMS.

LRCIN 26 5 2 I/O I2S DAC-word clock signal. In audio master mode, the DAC23 generates this framing signal

and sends it to the DSP. In audio slave mode, the signal is generated by the DSP.

MODE 13 22 19 I Serial interface mode input. See Section 3.1 for details.

NC 1, 7, 8,

9, 17,

25, 27,

6, 7,

17,18 3, 4,

14, 15 −Not Used—No internal connection

RHPOUT 31 10 7 O Right stereo mixer-channel amplified headphone output. Nominal 0-dB output level is

1.0 VRMS. Gain of −73 dB to 6 dB is provided in 1-dB steps.

RLINEIN 10 19 16 I Right stereo-line input channel

ROUT 3 13 10 O Right stereo mixer-channel line output. Nominal output level is 1.0 VRMS.

SCLK 15 24 21 I Control port serial data clock. For both SPI and 2-wire control modes this is the serial clock

input. See Section 3.1 for details.

SDIN 14 23 20 I Control port serial data input. For both SPI and 2-wire control modes this is the serial data input

and also is used to select the control protocol after reset. See Section 3.1 for details.

VMID 6 16 13 I Midrail voltage decoupling input. 10-µF and 0.1-µF capacitors should be connected in parallel

to this terminal for noise filtering. Voltage level is 1/2 AVDD nominal.

XTI/MCLK 16 25 22 I Crystal or external clock input. Used for derivation of all internal clocks on the DAC23.

XTO 18 26 23 O Crystal output. Connect to external crystal for applications where the DAC23 is the audio timing

master. Not used in applications where external clock source is used.

2−1

2 Specifications

2.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless

otherwise noted)†

Supply voltage range, AVDD to AGND, DVDD to DGND, BVDD to DGND, HPVDD to HPGND

(see Note 1) −0.3 V to + 3.63 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog supply return to digital supply return, AGND to DGND −0.3 V to + 0 .3 V. . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, all input signals: Digital −0.3 V to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog −0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA−10°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: DVDD may not exceed BVDD + 0.3V; BVDD may not exceed AVDD + 0.3V or HPVDD + 0.3.

2.2 Recommended Operating Conditions

MIN NOM MAX UNIT

Analog supply voltage, AVDD, HPVDD (see Note 2) 2.7 3.3 3.6 V

Digital buffer supply voltage, BVDD (see Note 2) 2.7 3.3 3.6 V

Digital core supply voltage, DVDD (see Note 2) 1.42 1.5 3.6 V

Analog input voltage, (AVDD = 3.3 V) 1 VRMS

Stereo line output load resistance 10 kΩ

Headphone amplifier output load resistance 0Ω

CLKOUT digital output load capacitance 20 pF

All other digital output load capacitance 10 pF

Stereo-line output load capacitance 50 pF

XTI master clock Input 18.43 MHz

DAC conversion rate 96 kHz

Operating free-air temperature, TA−10 70 °C

NOTE 2: Digital voltage values are with respect to DGND; analog voltage values are with respect to AGND.

2−2

2.3 Electrical Characteristics Over Recommended Operating Conditions, AVDD,

HPVDD, BVDD = 3.3 V, DVDD = 1.5 V, Master Mode, XTI = 12 MHz,

(unless otherwise stated)

2.3.1 DAC

2.3.1.1 Load = 10 kΩ, 50 pF

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

0-dB full-scale output voltage 1.0 VRMS

AVDD = 3.3 V

fs = 44.1kHz 90 100

Signal-to-noise ratio, A-weighted, 0-dB gain (see Notes 3, 4, and 5) AVDD = 3.3 V fs = 96 kHz 98 dB

Signal-to-noise ratio, A-weighted, 0-dB gain (see Notes 3, 4, and 5)

AVDD = 2.7 V

fs = 44.1 kHz

= 2.7 V f

= 44.1 kHz 93

Dynamic range, A-weighted (see Note 5)

AVDD = 3.3 V

Dynamic range, A-weighted (see Note 5) AV

= 3.3 V 85 90 dB

AVDD = 3.3 V

1 kHz, 0 dB –88 –80

Total harmonic distortion (THD)

AVDD = 3.3 V 1 kHz, −3 dB −92 dB

Total harmonic distortion (THD)

AVDD = 2.7 V

1 kHz, 0 dB −88 −80

AVDD = 2.7 V 1 kHz, −3 dB −92 dB

Power supply rejection ratio 1 kHz, 100 mVpp 50 dB

DAC channel separation 100 dB

THD+N AVDD=3.3 V, 1 kHz, 0dB −84 −79 dB

2.3.2 Analog Line Input to Line Output

2.3.2.1 Load = 10 kΩ, 50 pF, no gain on input

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

0-dB full-scale output voltage 1.0 VRMS

Signal-to-noise ratio, (SNR) A-weighted, 0-dB gain (see Notes 3, 5)

AVDD = 3.3 V

Signal-to-noise ratio, (SNR) A-weighted, 0-dB gain (see Notes 3, 5) AV

= 3.3 V 90 95 dB

AVDD = 3.3 V

1 kHz, 0 dB –86 –80

Total harmonic distortion (THD)

AVDD = 3.3 V 1 kHz, −3 dB −92 −86 dB

Total harmonic distortion (THD)

AVDD = 2.7 V

1 kHz, 0 dB −86

AVDD = 2.7 V 1 kHz, −3 dB −92 dB

Power supply rejection ratio 1 kHz, 100 mVpp 50 dB

Mute attenuation 1 kHz, 0 dB 80 dB

Input resistance 10 k 24 k Ω

2−3

2.3.3 Stereo Headphone Output

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

0-dB full-scale output voltage 1.0 VRMS

Maximum output power, PORL = 32 Ω30

RL = 16 Ω40 mW

Signal-to-noise ratio, A-weighted (see Note 4) AVDD = 3.3 V 90 97 dB

Total harmonic distortion

AVDD = 3.3 V,

1 kHz output, into

PO = 10 mW −60

Total harmonic distortion

1 kHz output, into

32ΩPO = 20 mW −40 dB

Power supply rejection ratio 1 kHz, 100 mVpp 50 dB

Programmable gain 1 kHz output −73 6 dB

Programmable-gain step size 1 dB

Mute attenuation 1 kHz output 80 dB

NOTES: 3. Ratio o f output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz

to 20-kHz bandwidth using an audio analyzer.

4. All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter

results in higher THD + N and lower SNR and dynamic range readings than shown in the electrical characteristics. The low-pass

filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.

5. Ratio of output level with 1-kHz full-scale input, to the output level with all zeros into the digital input, measured A-weighted over

a 20-Hz to 20-kHz bandwidth.

2.3.4 Analog Reference Levels

PARAMETER MIN TYP MAX UNIT

Reference voltage, VMID AVDD/2 − 50 mV AVDD/2 + 50 mV V

Divider resistance, RVMID 40 50 60 kΩ

2.3.5 Digital I/O

PARAMETER MIN TYP MAX UNIT

VIL Input low level 0.3 × BVDD V

VIH Input high level 0.7 × BVDD V

VOL Output low level 0.1 × BVDD V

VOH Output high level 0.9 × BVDD V

2.3.6 Supply Current

PARAMETER MIN TYP MAX UNIT

Line playback only (Clk power off, 50 Ω) 6 8

Total supply current, no input signal

Line playback only (Clk power on, 50 Ω) 15

TOT

Total supply current, no input signal

(3.3 V supply)

Analog bypass (line in to line out) 3mA

ITOT

(3.3 V supply)

Power down

Oscillator enabled 1.5

Power down Oscillator disabled 0.01 0.025

2−4

2.4 Digital-Interface Timing

PARAMETER MIN TYP MAX UNIT

tw(1)

System-clock pulse duration, MCLK/XTI

High 18

tw(2) System-clock pulse duration, MCLK/XTI Low 18 ns

tc(1) System-clock period, MCLK/XTI 54 ns

Duty cycle, MCLK/XTI 40/60% 60/40%

tpd(1) Propagation delay, CLKOUT 0 10 ns

tc(1)

tw(1) tw(2)

tpd(1)

MCLK/XTI

CLKOUT

(Div 2)

Figure 2−1. System-Clock Timing Requirements

2.4.1 Audio Interface (Master Mode)

PARAMETER MIN TYP MAX UNIT

tpd(2) Propagation delay, LRCIN 0 10 ns

tsu(1) Setup time, DIN 10 ns

th(1) Hold time, DIN 10 ns

BCLK

LRCIN

DIN

tpd(2)

tsu(1) th(1)

Figure 2−2. Master-Mode Timing Requirements

2−5

2.4.2 Audio Interface (Slave-Mode)

PARAMETER MIN TYP MAX UNIT

tw(3)

Pulse duration, BCLK

High 20

tw(4) Pulse duration, BCLK Low 20 ns

tc(2) Clock period, BCLK 50 ns

tsu(2) Setup time, DIN 10 ns

th(2) Hold time, DIN 10 ns

tsu(3) Setup time, LRCIN 10 ns

th(3) Hold time, LRCIN 10 ns

BCLK

LRCIN

DIN

tc(2)

tw(4) tw(3)

tsu(3)

th(3)

tsu(2)

th(2)

Figure 2−3. Slave-Mode Timing Requirements

2−6

2.4.3 Three-Wire Control Interface (SDI)

PARAMETER MIN TYP MAX UNIT

tw(5)

Clock pulse duration, SCLK

High 20

tw(6) Clock pulse duration, SCLK Low 20 ns

tc(3) Clock period, SCLK 80 ns

tsu(4) Clock rising edge to CS rising edge, SCLK 60 ns

tsu(5) Setup time, SDIN to SCLK 20 ns

th(4) Hold time, SCLK to SDIN 20 ns

tw(7)

Pulse duration, CS

High 20

tw(8)

Pulse duration, CS

Low 20

LSB

tw(8)

tc(3)

tw(6)

tw(5) tsu(4)

th(4)

tsu(5)

SCLK

DIN

Figure 2−4. Three-Wire Control Interface Timing Requirements

2.4.4 Two-Wire Control Interface

PARAMETER MIN TYP MAX UNIT

tw(9)

Clock pulse duration, SCLK

High 1.3 µs

tw(10) Clock pulse duration, SCLK Low 600 ns

f(sf) Clock frequency, SCLK 0 400 kHz

th(5) Hold time (start condition) 600 ns

tsu(6) Setup time (start condition) 600 ns

th(6) Data hold time 900 ns

tsu(7) Data setup time 100 ns

trRise time, SDIN, SCLK 300 ns

tfFall time, SDIN, SCLK 300 ns

tsu(8) Setup time (stop condition) 600 ns

SCLK

DIN

tw(9) tw(10)

th(5) th(6) tsu(7) tsu(8)

Figure 2−5. Two-Wire Control Interface Timing Requirements

3−1

3 How to Use the DAC23

3.1 Control Interfaces

The TLV320DAC23 has many programmable features. The control interface is used to program the registers of the

device. The control interface complies with SPI (three-wire operation) and two-wire operation specifications. The

state of the MODE terminal selects the control interface type. The MODE pin must be hardwired to the required level.

MODE INTERFACE

0 2-wire

1 SPI

3.1.1 SPI

In SPI mode, SDI carries the serial data, SCLK is the serial clock and CS latches the data word into the

TLV320DAC23. The interface is compatible with microcontrollers and DSPs with an SPI interface.

A control word consists of 16 bits, starting with the MSB. The data bits are latched on the rising edge of SCLK. A rising

edge on CS after the sixteenth rising clock edge latches the data word into the DAC (see Figure 3-1).

The control word is divided into two parts. The first part is the address block, the second part is the data block:

B[15:9] Control address bits

B[8:0] Control data bits

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MSB LSB

SCLK

SDI

Figure 3−1. SPI Timing

3.1.2 2-Wire

In 2-wire mode, the data transfer uses SDI for the serial data and SCLK for the serial clock. The start condition is a

falling edge on SDIN while SCLK is high. The seven bits following the start condition determine the device on the

2-wire bus that receives the data. R/W determines the direction of the data transfer. The TLV320DAC23 is a write

only device and responds only if R/W is 0. The device operates only as a slave device whose address is selected

by setting the state of the CS pin as follows.

CS STATE

(Default = 0) ADDRESS

0 0011010

1 0011011

The device that recognizes the address responds by pulling SDI low during the ninth clock cycle, acknowledging the

data transfer. The control follows in the next two eight-bit blocks. The stop condition after the data transfer is a rising

edge on SDI when SCLK is high (see Figure 3-2).

3−2

The 16-bit control word is divided into two parts. The first part is the address block, the second part is the data block:

B[15:9] Control address bits

B[8:0] Control data bits

SCLK

SDI ADDR R/W ACK B15 − B8 ACK B7 − B0 ACK

Start Stop

1789189189

Figure 3−2. 2-Wire Compatible Timing

3.1.3 Register Map

The TLV320DAC23 has the following set of registers, which are used to program the modes of operation.

ADDRESS REGISTER

0000000 Left line input channel control

0000001 Right line input channel control

0000010 Left channel headphone volume control

0000011 Right channel headphone volume control

0000100 Analog audio path control

0000101 Digital audio path control

0000110 Power down control

0000111 Digital audio interface format

0001000 Sample rate control

0001001 Digital interface activation

0001111 Reset register

Left Line Input Channel Control (Address: 0000000)

BIT D8 D7 D6 D5 D4 D3 D2 D1 D0

Function LRS LIM X X X X X X X

Default 0 1 0 0 0 0 0 0 0

LRS Left/right line simultaneous volume/mute update

Simultaneous update 0 = Disabled 1 = Enabled

LIM Left line input mute 0 = Normal 1 = Muted

X Reserved

Right Line Input Channel Control (Address: 0000001)

BIT D8 D7 D6 D5 D4 D3 D2 D1 D0

Function RLS RIM X X X X X X X

Default 0 1 0 0 0 0 0 0 0

RLS Right/left line simultaneous volume/mute update

Simultaneous update 0 = Disabled 1 = Enabled

RIM Right line input mute 0 = Normal 1 = Muted

X Reserved

3−3

Left Channel Headphone Volume Control (Address: 0000010)

BIT D8 D7 D6 D5 D4 D3 D2 D1 D0

Function LRS LZC LHV6 LHV5 LHV4 LHV3 LHV2 LHV1 LHV0

Default 0 1 1 1 1 1 0 0 1

LRS Left/right headphone channel simultaneous volume/mute update

Simultaneous update 0 = Disabled 1 = Enabled

LZC Left-channel zero-cross detect

Zero-cross detect 0 = Off 1 = On

LHV[6:0] Left Headphone volume control (1111001 = 0 dB default)

1111111 = +6 dB, 79 steps between +6 dB and −73 dB (mute), 0110000 = −73 dB (mute),

any thing below 0110000 does nothing − you are still muted

Right Channel Headphone Volume Control (Address: 0000011)

BIT D8 D7 D6 D5 D4 D3 D2 D1 D0

Function RLS RZC RHV6 RHV5 RHV4 RHV3 RHV2 RHV1 RHV0

Default 0 1 1 1 1 1 0 0 1

RLS Right/left headphone channel simultaneous volume/mute Update

Simultaneous update 0 = Disabled 1 = Enabled

RZC Right-channel zero-cross detect

Zero-cross detect 0 = Off 1 = On

RHV[6:0] Right headphone volume control (1111001 = 0 dB default)

1111111 = +6 dB, 79 steps between +6 dB and −73 dB (mute), 0110000 = −73 dB (mute),

any thing below 0110000 does nothing − you are still muted

Analog Audio Path Control (Address: 0000100)

BIT D8 D7 D6 D5 D4 D3 D2 D1 D0

Function X X X X DAC BYP X X X

Default 0 0 0 0 0 1 0 1 0

DAC DAC select 0 = DAC off 1 = DAC selected

BYP Bypass 0 = Disabled 1 = Enabled

X Reserved

Digital Audio Path Control (Address: 0000101)

BIT D8 D7 D6 D5 D4 D3 D2 D1 D0

Function X X X X X DACM DEEMP1 DEEMP0 X

Default 0 0 0 0 0 1 0 0 0

DACM DAC soft mute 0 = Disabled 1 = Enabled

DEEMP[1:0] De-emphasis control 00 = Disabled 01 = 32 kHz 10 = 44.1 kHz 11 = 48 kHz

X Reserved

Power Down Control (Address: 0000110)

BIT D8 D7 D6 D5 D4 D3 D2 D1 D0

Function X OFF CLK OSC OUT DAC X X LINE

Default 0 0 0 1 1 1 1 1 1

OFF Power 0 = On 1 = Off

CLK Clock 0 = On 1 = Off

OSC Oscillator 0 = On 1 = Off

OUT Outputs 0 = On 1 = Off

DAC DAC 0 = On 1 = Off

LINE Line input 0 = On 1 = Off

X Reserved

3−4

Digital Audio Interface Format (Address: 0000111)

BIT D8 D7 D6 D5 D4 D3 D2 D1 D0

Function X X MS LRSWAP LRP IWL1 IWL0 FOR1 FOR0

Default 0 0 0 0 0 0 0 0 1

MS Master/slave mode 0 = Slave 1 = Master

LRSWAP DAC left/right swap 0 = Disabled 1 = Enabled

LRP DAC left/right phase 0 = Right channel on, LRCIN high

1 = Right channel on, LRCIN low

IWL[1:0] Input bit length 00 = 16 bit 01 = 20 bit 10 = 24 bit 11 = 32 bit

FOR[1:0] Data format 11 = DSP format, frame sync followed by two data words

10 = I2S format, MSB first, left – 1 aligned

01 = MSB first, left aligned

00 = MSB first, right aligned

X Reserved

NOTES: 1. In Master mode, the TLV320AIC23 supplies the BCLK and LRCIN. In Slave mode, BCLK and LRCIN are supplied to the

TLV320AIC23.

2. In normal mode, BCLK = MCLK/4 for all sample rates except for 88.2 kHz and 96 kHz. For 88.2 kHz and 96 kHz sample rate,

BCLK = MCLK.

3. In USB mode, bit BCLK = MCLK

Sample Rate Control (Address: 0001000)

BIT D8 D7 D6 D5 D4 D3 D2 D1 D0

Function X CLKOUT CLKIN SR3 SR2 SR1 SR0 BOSR USB/Normal

Default 0 0 0 0 0 0 0 0 0

CLKOUT Clock output divider 0 = MCLK 1 = MCLK/2

CLKIN Clock input divider 0 = MCLK 1 = MCLK/2

SR[3:0] Sampling rate control (see Sections 3.3.2.1 AND 3.3.2.2)

BOSR Base oversampling rate

USB mode: 0 = 250 fs1 = 272 fs

Normal mode: 0 = 256 fs1 = 384 fs

USB/Normal Clock mode select: 0 =Normal 1 = USB

X Reserved

Digital Interface Activation (Address: 0001001)

BIT D8 D7 D6 D5 D4 D3 D2 D1 D0

Function X X X X X X X X ACT

Default 0 0 0 0 0 0 0 0 0

ACT Activate interface 0 = Inactive 1 = Active

X Reserved

Reset Register (Address: 0001111)

BIT D8 D7 D6 D5 D4 D3 D2 D1 D0

Function RES RES RES RES RES RES RES RES RES

Default 0 0 0 0 0 0 0 0 0

RES Write to this register triggers reset

3.2 Analog Interface

3.2.1 Line Inputs

The TLV320DAC23 has line inputs for the left and the right audio channels (RLINEIN and LLINEIN). Both line inputs

have independently programmable mutes. Active and passive filters for the two channels prevent high frequencies

from folding back into the audio band.

3−5

The line inputs are biased internally to VMID. When the line inputs are muted or the device is set to standby mode,

the line inputs are kept biased to VMID using special antithump circuitry. This reduces audible clicks that otherwise

might be heard when reactivating the inputs.

For interfacing to a CD system, the line input should be scaled to 1 VRMS to avoid clipping, using the circuit shown

in Figure 3-3.

C2 +

CDIN LINEIN

AGND

Where:

R1 = 5 kΩ

R2 = 5 kΩ

C1 = 47 pF

C2 = 470 nF

Figure 3−3. Analog Line Input Circuit

R1 and R2 divide the input signal by two, reducing the 2 VRMS from the CD player to the nominal 1 VRMS of the DAC23

inputs. C1 filters high-frequency noise, and C2 removes any dc component from the signal.

3.2.2 Line Outputs

The TLV320DAC23 has two low-impedance line outputs (LLINEOUT and RLINEOUT) capable of driving line loads

with 10-kΩ and 50-pF impedances.

The DAC full-scale output voltage is 1.0 VRMS at AVDD = 3.3 V. The full-scale range tracks linearly with the analog

supply voltage AVDD. The DAC is connected to the line outputs via a low-pass filter that removes out-of-band

components. No further external filtering is required in most applications.

The DAC outputs and the line inputs are summed into the line outputs. The line outputs are muted by either muting

the DAC (analog) or soft muting (digital) and disabling the bypass path (see Section 3.1.3).

3.2.3 Headphone Output

The TLV320DAC23 has stereo headphone outputs (LHPOUT and RHPOUT), and is designed to drive 16-Ω or 32-Ω

headphones. The headphone output includes a high-quality volume control and mute function.

The headphone volume is logarithmically adjustable from 6 dB to –73 dB in 1-dB steps. Writing 000000 to the

volume-control registers (see Section 3.1.3) mutes the headphone output. When the headphone output is muted or

the device is placed in standby mode, the dc voltage is maintained at the outputs to prevent audible clicks.

A zero-cross detection circuit is provided under the control of the LZC and RZC bits. If this circuit is enabled, the

volume-control values are updated only when the input signal to the gain stage is close to the analog ground level.

This minimizes audible clicks as the volume is changed or the device is muted. This circuit has no time-out, so if only

dc levels are being applied to the gain stage input of more than 20 mV, the gain is not updated.

The gain is independently programmable on the left and right channels. Both channels can be locked to the same

value by setting the RLS and LRS bits (see Section 3.1.3).

3.3 Digital Audio Interface

3.3.1 Digital Audio-Interface Modes

The TLV320DAC23 supports four audio-interface modes.

•Right justified

•Left justified

•I2S mode

•DSP mode

3−6

The four modes are MSB first and operate with a variable word width between 16 to 32 bits (except right-justified

mode, which does not support 32 bits).

The digital audio interface consists of clock signal BCLK, data signals DIN and and the synchronization signal LRCIN.

BCLK is an output in master mode and an input in slave mode.

3.3.1.1 Right-Justified Mode

In right-justified mode, the LSB is available on the rising edge of BCLK, preceding a falling edge on LRCIN (see

Figure 3-4).

LRCIN

BCLK

DIN n n−1 01 n−1n

1/fs

Left Channel Right Channel

1 00

MSB LSB

Figure 3−4. Right Justified Mode Timing

3.3.1.2 Left-Justified Mode

In left-justified mode, the MSB is available on the rising edge of BCLK, following a rising edge on LRCIN (see

Figure 3-5)

LRCIN

BCLK

DIN n n−1 01 n−1n

1/fs

Left Channel Right Channel

1 0 n

MSB LSB

Figure 3−5. Left Justified Mode Timing

3.3.1.3 I2S Mode

In I 2S mode, the MSB is available on the second rising edge of BCLK, after the falling edge on LRCIN (see Figure 3-6).

LRCIN

BCLK

DIN n n−1 01 n−1n

1/fs

Left Channel Right Channel

1 0

MSB LSB

1BCLK

Figure 3−6. I2S Mode Timing

3−7

3.3.1.4 DSP Mode

The DSP mode is compatible with the McBSP ports of TI DSPs. LRCIN must be connected to the Frame Sync signal

of the McBSP. A falling edge on LRCIN starts the data transfer. The left-channel data consists of the first data word,

which is immediately followed by the right channel data word (see Figure 3-7).

LRCIN

BCLK

DIN n n−1 01 n−1n

Left Channel Right Channel

1 0

MSB LSB MSB LSB

Figure 3−7. DSP Mode Timing

3.3.2 Audio Sampling Rates

The TLV320DAC23 can operate in master or slave clock mode. In the master mode, the TLV320DAC23 clock and

sampling rates are derived from a 12-MHz MCLK signal. This 12-MHz clock signal is compatible with the USB

specification. The TLV320DAC23 can be used directly in a USB system.

In the slave mode, the TLV320DAC23 clock and sample rates are controlled by using an appropriate MCLK or crystal

frequency and the sample rate control register settings.

The settings in the sample rate control register control the clock mode and sampling rates.

Sample Rate Control (Address: 0001000)

BIT D8 D7 D6 D5 D4 D3 D2 D1 D0

Function X CLKOUT CLKIN SR3 SR2 SR1 SR0 BOSR USB/Normal

Default 0 0 0 0 0 0 0 0 0

CLKOUT Clock output divider 0 = MCLK 1 = MCLK/2

CLKIN Clock input divider 0 = MCLK 1 = MCLK/2

SR[3:0] Sample rate control (see Sections 3.3.2.1 and 3.3.2.2)

BOSR Base oversampling rate

USB mode: 0 = 250 fs1 = 272 fs

Normal mode: 0 = 256 fs1 = 384 fs

USB/Normal Clock mode select: 0 =Normal 1 =USB

X Reserved

The clock circuit of the DAC23 has two internal dividers. The first, controlled by CLKIN, applies to the sampling-rate

generator of the DAC. The second, controlled by CLKOUT, applies only to the CLKOUT terminal. By setting CLKIN

to 1, the entire DAC is clocked with half the frequency, effectively dividing the resulting sampling rates by two.

3−8

3.3.2.1 USB-Mode Sampling Rates

In the USB mode, the following DAC sampling rates are available:

(MCLK = 12 MHz)

SAMPLING RATE

FILTER

SAMPLING-RATE CONTROL SETTINGS

FILTER

TYPE

SAMPLING-RATE CONTROL SETTINGS

kHz

FILTER

TYPE SR3 SR2 SR1 SR0 BOSR CLKIN

96 3 0 1 1 1 0 0

88.235 2 1 1 1 1 1 0

48 0 0 0 0 0 0 0

44.118 1 1 0 0 0 1 0

32 0 0 1 1 0 0 0

8.021 1 1 0 1 1 1 0

8 0 0 0 1 1 0 0

48 3 0 1 1 1 0 1

44.118 2 1 1 1 1 1 1

24 0 0 0 0 0 0 1

22.059 1 1 0 0 0 1 1

16 0 0 1 1 0 0 1

4.0105 1 1 0 1 1 1 1

4 0 0 0 1 1 0 1

(MCLK = 6 MHz)

SAMPLING RATE

FILTER

SAMPLING-RATE CONTROL SETTINGS

FILTER

TYPE

SAMPLING-RATE CONTROL SETTINGS

kHz

FILTER

TYPE SR3 SR2 SR1 SR0 BOSR CLKIN

48 3 0 1 1 1 0 0

44.118 2 1 1 1 1 1 0

24 0 0 0 0 0 0 0

22.059 1 1 0 0 0 1 0

16 0 0 1 1 0 0 0

4.0105 1 1 0 1 1 1 0

4 0 0 0 1 1 0 0

24 3 0 1 1 1 0 1

22.059 2 1 1 1 1 1 1

12 0 0 0 0 0 0 1

11.029 1 1 0 0 0 1 1

8 0 0 1 1 0 0 1

2.005 1 1 0 1 1 1 1

2 0 0 0 1 1 0 1

3−9

3.3.2.2 Normal-Mode Sampling Rates

In Normal mode, the following DAC sampling rates, depending on the MCLK frequency, are available:

MCLK = 12.288 MHz

SAMPLING RATE

FILTER

SAMPLING-RATE CONTROL SETTINGS

FILTER

TYPE

SAMPLING-RATE CONTROL SETTINGS

kHz

FILTER

TYPE SR3 SR2 SR1 SR0 BOSR CLKIN

96 2 0 1 1 1 0 0

48 1 0 0 0 0 0 0

32 1 0 1 1 0 0 0

8 1 0 0 1 1 0 0

48 2 0 1 1 1 0 1

24 1 0 0 0 0 0 1

16 1 0 1 1 0 0 1

4 1 0 0 1 1 0 1

MCLK = 11.2896 MHz

SAMPLING RATE

FILTER

SAMPLING-RATE CONTROL SETTINGS

FILTER

TYPE

SAMPLING-RATE CONTROL SETTINGS

kHz

FILTER

TYPE SR3 SR2 SR1 SR0 BOSR CLKIN

88.2 2 1 1 1 1 0 0

44.1 1 1 0 0 0 0 0

8.021 1 1 0 1 1 0 0

44.1 2 1 1 1 1 0 1

22.05 1 1 0 0 0 0 1

4.0105 1 1 0 1 0 0 1

MCLK = 18.432 MHz

SAMPLING RATE

FILTER

SAMPLING-RATE CONTROL SETTINGS

FILTER

TYPE

SAMPLING-RATE CONTROL SETTINGS

kHz

FILTER

TYPE SR3 SR2 SR1 SR0 BOSR CLKIN

96 2 0 1 1 1 1 0

48 1 0 0 0 0 1 0

32 1 0 1 1 0 1 0

8 1 0 0 1 1 1 0

48 2 0 1 1 1 1 1

24 1 0 0 0 0 1 1

16 1 0 1 1 0 1 1

4 1 0 0 1 1 1 1

MCLK = 16.9344 MHz

SAMPLING RATE

FILTER

SAMPLING-RATE CONTROL SETTINGS

FILTER

TYPE

SAMPLING-RATE CONTROL SETTINGS

kHz

FILTER

TYPE SR3 SR2 SR1 SR0 BOSR CLKIN

88.2 2 1 1 1 1 1 0

44.1 1 1 0 0 0 1 0

8.021 1 1 0 1 1 1 0

44.1 2 1 1 1 1 1 1

22.05 1 1 0 0 0 1 1

4.0105 1 1 0 1 1 1 1

3−10

3.3.3 Digital Filter Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DAC Filter Characteristics (48-kHz Sampling Rate)

Passband ±0.03 dB 0.416 fsHz

Stopband −6 dB 0.5 fsHz

Passband ripple ±0.03 dB

Stopband attenuation f > 0.584 fs−50 dB

DAC Filter Characteristics (44.1-kHz Sampling Rate)

Passband ±0.03 dB 0.4535 fsHz

Stopband −6 dB 0.5 fs Hz

Passband ripple ±0.03 dB

Stopband attenuation f > 0.5465 fs−50 dB

−6

−8

−10

Filter Response − dB

−4

−2

Normalized Audio Sampling Frequency − Hz

0 0.1 0.2 0.3 0.4 0.5

Figure 3−8. Digital De-Emphasis Filter Response − 44.1 kHz Sampling

3−11

−6

−8

−10 0 0.10 0.20 0.30

Filter Response − dB

−4

−2

Normalized Audio Sampling Frequency − Hz

0.40 0.50

Figure 3−9. Digital De-Emphasis Filter Response − 48 kHz Sampling

−90 0 0.5 1 1.5

2 2.5 3

−10

−30

−50

−70

Filter Response − dB

Normalized Audio Sampling Frequency − Hz

Figure 3−10. DAC Digital Filter Response 0: USB Mode

−0.04

−0.10 0 0.05 0.1 0.15 0.2 0.25 0.3

0.08

0.10

0.35 0.4 0.45 0.5

0.06

0.04

0.02

−0.02

−0.06

−0.08

Filter Response − dB

Normalized Audio Sampling Frequency − Hz

Figure 3−11. DAC Digital Filter Ripple 0: USB Mode

3−12

−50

−90 0 0.5 1 1.5

−30

−10

2 2.5 3

−70

Filter Response − dB

Normalized Audio Sampling Frequency − Hz

Figure 3−12. DAC Digital Filter Response 1: USB Mode Only

−0.04

−0.10 0 0.05 0.1 0.15 0.2 0.25 0.3

0.06

0.08

0.10

0.35 0.4 0.45 0.5

0.04

0.02

−0.02

−0.06

−0.08

Filter Response − dB

Normalized Audio Sampling Frequency − Hz

Figure 3−13. DAC Digital Filter Ripple 1: USB Mode Only

−50

−90 0 0.5 1 1.5

−30

−10

2 2.5 3

−70

Filter Response − dB

Normalized Audio Sampling Frequency − Hz

Figure 3−14. DAC Digital Filter Response 2: USB Mode and Normal Modes

3−13

−0.2

−0.4 0 0.05 0.1 0.15 0.2 0.25 0.3

0.2

0.3

0.4

0.35 0.4 0.45 0.5

0.1

−0.1

−0.3

Filter Response − dB

Normalized Audio Sampling Frequency − Hz

Figure 3−15. DAC Digital Filter Ripple 2: USB Mode and Normal Modes

−70

−90 0 0.5 1 1.5

−30

−10

2 2.5 3

−50

Filter Response − dB

Normalized Audio Sampling Frequency − Hz

Figure 3−16. DAC Digital Filter Response 3: USB Mode Only

−0.2

−0.4 0 0.05 0.1 0.15 0.2 0.25 0.3

0.3

0.4

0.35 0.4 0.45 0.5

0.2

0.1

−0.1

−0.3

Filter Response − dB

Normalized Audio Sampling Frequency − Hz

Figure 3−17. DAC Digital Filter Ripple 3: USB Mode Only

3−14

PACKAGE OPTION ADDENDUM

www.ti.com 28-Aug-2010

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

TLV320DAC23GQE ACTIVE BGA

MICROSTAR

JUNIOR

GQE 80 360 TBD SNPB Level-2A-235C-4 WKS Request Free Samples

TLV320DAC23IPW ACTIVE TSSOP PW 28 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples

TLV320DAC23IPWG4 ACTIVE TSSOP PW 28 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples

TLV320DAC23IPWR ACTIVE TSSOP PW 28 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples

TLV320DAC23IPWRG4 ACTIVE TSSOP PW 28 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples

TLV320DAC23IRHD ACTIVE VQFN RHD 28 73 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples

TLV320DAC23IRHDG4 ACTIVE VQFN RHD 28 73 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples

TLV320DAC23IRHDR ACTIVE VQFN RHD 28 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples

TLV320DAC23IRHDRG4 ACTIVE VQFN RHD 28 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples

TLV320DAC23PW ACTIVE TSSOP PW 28 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples

TLV320DAC23PWG4 ACTIVE TSSOP PW 28 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples

TLV320DAC23PWR ACTIVE TSSOP PW 28 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples

TLV320DAC23PWRG4 ACTIVE TSSOP PW 28 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples

TLV320DAC23RHD ACTIVE VQFN RHD 28 73 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Contact TI Distributor

or Sales Office

TLV320DAC23RHDG4 ACTIVE VQFN RHD 28 73 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Contact TI Distributor

or Sales Office

TLV320DAC23RHDR ACTIVE VQFN RHD 28 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples

PACKAGE OPTION ADDENDUM

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Addendum-Page 2

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

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& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TLV320DAC23IPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1

TLV320DAC23IRHDR VQFN RHD 28 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2

TLV320DAC23PWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1

TLV320DAC23RHDR VQFN RHD 28 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TLV320DAC23IPWR TSSOP PW 28 2000 367.0 367.0 38.0

TLV320DAC23IRHDR VQFN RHD 28 3000 338.1 338.1 20.6

TLV320DAC23PWR TSSOP PW 28 2000 367.0 367.0 38.0

TLV320DAC23RHDR VQFN RHD 28 3000 338.1 338.1 20.6

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

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