General Description
The MAX5853 dual, 10-bit, 80Msps digital-to-analog
converter (DAC) provides superior dynamic performance
in wideband communication systems. The device inte-
grates two 10-bit DAC cores, and a 1.24V reference. The
converter supports single-ended and differential modes
of operation. The MAX5853 dynamic performance is
maintained over the entire 2.7V to 3.6V power-supply
operating range. The analog outputs support a -1.0V to
+1.25V compliance voltage.
The MAX5853 can also operate in interleave data mode
to reduce the I/O pin count. This allows the converter to
be updated on a single, 10-bit bus.
The MAX5853 features digital control of channel gain
matching to within ±0.4dB in sixteen 0.05dB steps.
Channel matching improves sideband suppression in
analog quadrature modulation applications. The on-
chip 1.24V bandgap reference includes a control
amplifier that allows external full-scale adjustments of
both channels through a single resistor. The internal ref-
erence can be disabled and an external reference may
be applied for high-accuracy applications.
The MAX5853 features full-scale current outputs of 2mA
to 20mA and operates from a 2.7V to 3.6V single supply.
The DAC supports three modes of power-control opera-
tion: normal, low-power standby, and complete power-
down. In power-down mode, the operating current is
reduced to 1µA.
The MAX5853 is packaged in a 40-pin thin QFN with
exposed paddle (EP) and is specified for the extended
(-40°C to +85°C) temperature range.
Pin-compatible, higher speed, and lower resolution
versions are also available. Refer to the MAX5854
(10-bit, 165Msps), the MAX5852** (8-bit, 165Msps), and
the MAX5851** (8-bit, 80Msps) data sheets for more
information. See Table 4 at the end of the data sheet.
Applications
Communications
SatCom, LMDS, MMDS, HFC, DSL, WLAN,
Point-to-Point Microwave Links
Wireless Base Stations
Quadrature Modulation
Direct Digital Synthesis (DDS)
Instrumentation/ATE
Features
♦10-Bit, 80Msps Dual DAC
♦Low Power
77mW with IFS = 5mA at fCLK = 80MHz
♦2.7V to 3.6V Single Supply
♦Full Output Swing and Dynamic Performance at
2.7V Supply
♦Superior Dynamic Performance
78dBc SFDR at fOUT = 20MHz
♦Programmable Channel Gain Matching
♦Integrated 1.24V Low-Noise Bandgap Reference
♦Single-Resistor Gain Control
♦Interleaved Data Mode
♦Single-Ended and Differential Clock Input Modes
♦Miniature 40-Pin Thin QFN Package, 6mm x 6mm
♦EV Kit Available—MAX5854 EV Kit
MAX5853
Dual, 10-Bit, 80Msps, Current-Output DAC
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-3196; Rev 0; 2/04
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
PART TEMP RANGE PIN-PACKAGE
MAX5853ETL -40°C to +85°C
40 Thin QFN-EP*
40 36373839
EP
18
21
23
22
24
25
19 2016 17
6
5
4
3
2
1
7
8
9
10
11 12 13 14 15
26
27
28
29
30
3132
33
3435
DA0
DB8
AGND
MAX5853
THIN QFN
TOP VIEW
AVDD
OUTPA
OUTNA
AGND
OUTPB
OUTNB
AVDD
REFR
REFO
DB9
DB6
DB7
DVDD
DB5
DB4
DGND
DB2
DB3
CVDD
CGND
CLK
CVDD
CLKXN
CLKXP
DCE
CW
DB0
DB1
DA1
DA2/G0
DA3/G1
DA4/G2
DA5/G3
DA6/REN
DA7/IDE
DA8/DACEN
DA9/PD
Pin Configuration
*EP = Exposed paddle.
**Future product—contact factory for availability.
MAX5853
Dual, 10-Bit, 80Msps, Current-Output DAC
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 80Msps, differential clock, external reference, VREF = 1.2V, IFS =
20mA, differential output, output amplitude = 0dBFS, TA= TMIN to TMAX, unless otherwise noted. TA ≥+25°C, guaranteed by produc-
tion test. TA < +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD to AGND .........................................................-0.3V to +4V
DVDD to DGND.........................................................-0.3V to +4V
CVDD to CGND.........................................................-0.3V to +4V
AVDD to DVDD .............................................................-4V to +4V
AGND to DGND.....................................................-0.3V to +0.3V
AGND to CGND.....................................................-0.3V to +0.3V
DGND to CGND ....................................................-0.3V to +0.3V
DA9–DA0, DB9–DB0, CW, DCE to DGND ...............-0.3V to +4V
CLK to CGND ..........................................-0.3V to (CVDD + 0.3V)
CLKXN, CLKXP to CGND.........................................-0.3V to +4V
REFR, REFO to AGND .............................-0.3V to (AVDD + 0.3V)
OUTPA, OUTNA to AGND..........(AVDD - 4.8V) to (AVDD + 0.3V)
OUTPB, OUTNB to AGND..........(AVDD - 4.8V) to (AVDD + 0.3V)
Maximum Current into Any Pin
(excluding power supplies) ..........................................±50mA
Continuous Power Dissipation (TA= +70°C)
40-Pin Thin QFN (derate 26.3mW/°C above +70°C)....2105mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
STATIC PERFORMANCE
Resolution N 10 Bits
Integral Nonlinearity INL RL = 0
-1.0 ±0.25 +1.0
LSB
Differential Nonlinearity DNL Guaranteed monotonic, RL = 0
-0.5 ±0.2 +0.5
LSB
Offset Error VOS
-0.5 ±0.1 +0.5
LSB
Internal reference (Note1)
-11.0 ±1.5 +6.8
Gain Error (See Also Gain Error
Definition Section) GE External reference
-6.25 ±0.7 +4.10
%FSR
Internal reference
±150
Gain-Error Temperature Drift External reference
±100
ppm/°C
DYNAMIC PERFORMANCE
fOUT = 10MHz
69.5
78
fOUT = 20MHz 78
fCLK = 80MHz,
AOUT = -1dBFS fOUT = 30MHz 72
fCLK = 44MHz,
AOUT = -1dBFS fOUT = 10MHz 78
Spurious-Free Dynamic Range to
Nyquist SFDR
fCLK = 25MHz,
AOUT = -1dBFS fOUT = 1MHz 79
dBc
fCLK = 80MHz, fOUT = 10MHz,
AOUT = -1dBFS, span = 10MHz 85
fCLK = 65MHz, fOUT = 5MHz,
AOUT = -1dBFS, span = 2.5MHz 82
Spurious-Free Dynamic Range
Within a Window SFDR
fCLK = 25MHz, fOUT = 1MHz,
AOUT = -1dBFS, span = 2MHz 82
dBc
Multitone Power Ratio to Nyquist
MTPR 8 tones at 400kHz spacing, fCLK = 78MHz,
fOUT = 15MHz to 18.2MHz 74 dBc
MAX5853
Dual, 10-Bit, 80Msps, Current-Output DAC
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 80Msps, differential clock, external reference, VREF = 1.2V, IFS =
20mA, differential output, output amplitude = 0dBFS, TA= TMIN to TMAX, unless otherwise noted. TA ≥+25°C, guaranteed by produc-
tion test. TA < +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
Multitone Spurious-Free Dynamic
Range Within a Window
8 tones at 811kH z sp aci ng , fC LK = 80M H z,
fOU T = 10.8M H z to 17.2M H z, sp an = 15M H z
76 dBc
fOUT = 10MHz -76
fOUT = 20MHz -75
fCLK = 80MHz,
AOUT = -1dBFS fOUT = 30MHz -70
fCLK = 44MHz,
AOUT = -1dBFS fOUT = 10MHz -76
Total Harmonic Distortion to
Nyquist (2nd- Through 8th-Order
Harmonics Included)
THD
fCLK = 25MHz,
AOUT = -1dBFS fOUT = 1MHz -76
dBc
Output Channel-to-Channel
Isolation fOUT = 10MHz 90 dB
Channel-to-Channel Gain
Mismatch fOUT = 10MHz, G[3:0] = 1000
0.025
dB
Channel-to-Channel Phase
Mismatch fOUT = 10MHz
0.05
fCLK = 80MHz, fOUT = 5MHz, IFS = 20mA 62
Signal-to-Noise Ratio to Nyquist SNR fCLK = 80MHz, fOUT = 5MHz, IFS = 5mA 62 dB
Interleaved mode disabled, IDE = 0 80
Maximum DAC Conversion Rate
fDAC Interleaved mode enabled, IDE = 1 80
Glitch Impulse 5
Output Settling Time tSTo ±0.1% error band (Note 3) 12 ns
Output Rise Time 10% to 90% (Note 3) 2.2 ns
Output Fall Time 90% to 10% (Note 3) 2.2 ns
ANALOG OUTPUT
Full-Scale Output Current Range
IFS 220mA
Output Voltage Compliance
Range
-1.00 +1.25
V
Output Leakage Current Shutdown or standby mode -5 +5 µA
REFERENCE
Internal-Reference Output
Voltage VREFO REN = 0
1.13 1.24 1.32
V
Internal-Reference Supply
Rejection AVDD varied from 2.7V to 3.6V 0.5
Internal-Reference Output-
Voltage Temperature Drift
TCVREFO
REN = 0
±50
MAX5853
Dual, 10-Bit, 80Msps, Current-Output DAC
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 80Msps, differential clock, external reference, VREF = 1.2V, IFS =
20mA, differential output, output amplitude = 0dBFS, TA= TMIN to TMAX, unless otherwise noted. TA ≥+25°C, guaranteed by produc-
tion test. TA < +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
Internal-Reference Output Drive
Capability REN = 0 50 µA
External-Reference Input Voltage
Range REN = 1
0.10
1.2
1.32
V
Current Gain
IFS/IREF
32
LOGIC INPUTS (DA9–DA0, DB9–DB0, CW)
Digital Input-Voltage High VIH
0.65 x
DVDD
V
Digital Input-Voltage Low VIL 0.3 x
DVDD
V
Digital Input Current IIN -1 +1 µA
Digital Input Capacitance CIN 3pF
SINGLE-ENDED CLOCK INPUT/OUTPUT AND DCE INPUT (CLK, DCE)
Digital Input-Voltage High VIH DCE = 1 0.65 x
CVDD
V
Digital Input-Voltage Low VIL DCE = 1 0.3 x
CVDD
V
Digital Input Current IIN DCE = 1 -1 +1 µA
Digital Input Capacitance CIN DCE = 1 3 pF
Digital Output-Voltage High VOH DCE = 0, ISOURCE = 0.5mA, Figure 1
0.9 x
CVDD
V
Digital Output-Voltage Low VOL DCE = 0, ISINK = 0.5mA, Figure 1
0.1 x
CVDD
V
DIFFERENTIAL CLOCK INPUTS (CLKXP/CLKXN)
Differential Clock Input Internal
Bias CVDD / 2 V
Differential Clock Input Swing 0.5 V
Clock Input Impedance Measured single ended 5 kΩ
POWER REQUIREMENTS
Analog Power-Supply Voltage AVDD 2.7 3 3.6 V
Digital Power-Supply Voltage DVDD 2.7 3 3.6 V
Clock Power-Supply Voltage CVDD 2.7 3 3.6 V
IFS = 20mA (Note 2), single-ended clock
mode
43.2
46
IFS = 20mA (Note 2), differential clock mode 43.2
IFS = 2mA (Note 2), single-ended clock
mode 5
Analog Supply Current IAVDD
IFS = 2mA (Note 2), differential clock mode
5
mA
MAX5853
Dual, 10-Bit, 80Msps, Current-Output DAC
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 80Msps, differential clock, external reference, VREF = 1.2V, IFS =
20mA, differential output, output amplitude = 0dBFS, TA= TMIN to TMAX, unless otherwise noted. TA ≥+25°C, guaranteed by produc-
tion test. TA < +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
IFS = 20mA (Note 2), single-ended clock
mode 3.4 4
Digital Supply Current IDVDD
IFS = 20mA (Note 2), differential clock mode
3.4
mA
Single-ended clock mode (DCE = 1)
(Note 2)
11.1 13.5
Clock Supply Current ICVDD
Differential clock mode (DCE = 0) (Note 2)
16.7
mA
Total Standby Current
ISTANDBY
IAVDD + IDVDD + ICVDD 3.1 3.7 mA
Total Shutdown Current ISHDN IAVDD + IDVDD + ICVDD 1µA
IFS = 20mA (Note 2) 173
191
Single-ended clock
mode (DCE = 1) IFS = 2mA (Note 2) 58
IFS = 20mA (Note 2) 190
Differential clock
mode (DCE = 0) IFS = 2mA (Note 2) 75
Standby 9.3
11.1
Total Power Dissipation PTOT
Shutdown
0.003
mW
TIMING CHARACTERISTICS (Figures 5 and 6)
Propagation Delay 1
S i ng l e- end ed cl ock m od e ( D CE = 1) ( N ote 4)
1.2
DAC Data to CLK Rise/Fall
Setup Time tDCS Differential clock mode (DCE = 0) (Note 4) 2.7 ns
S i ng l e- end ed cl ock m od e ( D CE = 1) ( N ote 4)
0.8
DAC Data to CLK Rise/Fall
Hold Time tDCH Differential clock mode (DCE = 0) (Note 4)
-0.5
ns
Control Word to CW Rise
Setup Time tCS 2.5 ns
Control Word to CW Rise
Hold Time tCW 2.5 ns
CW High Time tCWH 5ns
CW Low Time tCWL 5ns
MAX5853
Dual, 10-Bit, 80Msps, Current-Output DAC
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 80Msps, differential clock, external reference, VREF = 1.2V, IFS =
20mA, differential output, output amplitude = 0dBFS, TA= TMIN to TMAX, unless otherwise noted. TA ≥+25°C, guaranteed by produc-
tion test. TA < +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
DACEN = 1 to VOUT Stable Time
(Coming Out of Standby) tSTB 3µs
PD = 0 to VOUT Stable Time
(Coming Out of Power-Down) tSHDN
500
µs
Maximum Clock Frequency at
CLKXP/CLKXN Input fCLK 80
MHz
Clock High Time tCXH CLKXP or CLKXN input 3 ns
Clock Low Time tCXL CLKXP or CLKXN input 3 ns
CLKXP Rise to CLK Output
Rise Delay tCDH DCE = 0 2.7 ns
CLKXP Fall to CLK Output
Fall Delay tCDL DCE = 0 2.7 ns
Note 1: Including the internal reference voltage tolerance and reference amplifier offset.
Note 2: fDAC = 80Msps, fOUT = 10MHz.
Note 3: Measured single ended with 50Ωload and complementary output connected to ground.
Note 4: Guaranteed by design, not production tested.
TO OUTPUT
PIN
5pF
0.5mA
0.5mA
1.6V
Figure 1. Load Test Circuit for CLK Outputs
MAX5853
Dual, 10-Bit, 80Msps, Current-Output DAC
_______________________________________________________________________________________ 7
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 80MHz)
MAX5853 toc01
fOUT (MHz)
SFDR (dBc)
353020 2510 155
35
40
45
50
55
60
65
70
75
80
85
90
30
040
0dBFS
-6dBFS
-12dBFS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 44MHz)
MAX5853 toc02
fOUT (MHz)
SFDR (dBc)
201814 1646810 122
35
40
45
50
55
60
65
70
75
80
85
90
30
022
0dBFS -6dBFS
-12dBFS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 25MHz)
MAX5853 toc03
fOUT (MHz)
SFDR (dBc)
119753
35
40
45
50
55
60
65
70
75
80
85
90
30
113
0dBFS -6dBFS
-12dBFS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 65MHz)
MAX5853 toc04
fOUT (MHz)
SFDR (dBc)
302515 20105
35
40
45
50
55
60
65
70
75
80
85
90
30
035
0dBFS
-12dBFS
-6dBFS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 80MHz)
MAX5853 toc05
fOUT (MHz)
SFDR (dBc)
353020 2510 155
35
40
45
50
55
60
65
70
75
80
85
90
30
040
IOUT = 20mA
IOUT = 10mA IOUT = 5mA
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 80MHz)
MAX5853 toc06
fOUT (MHz)
SFDR (dBc)
3530510 15 20 25
55
60
65
70
75
80
85
90
50
040
AVDD = DVDD = CVDD = 2.7V
AVDD = DVDD = CVDD = 3.6V
AVDD = DVDD = CVDD = 3V
AVDD = DVDD = CVDD = 3V
SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE
(fCLK = 80MHz, fOUT = 10MHz, AOUT = 0dBFS)
MAX5853 toc07
TEMPERATURE (°C)
SFDR (dBc)
6035-15 10
76
77
78
79
80
81
82
83
75
-40 85
Typical Operating Characteristics
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, external reference, IFS = 20mA, differential output, differential clock
(unless otherwise noted), TA= +25°C.)
TWO-TONE INTERMODULATION DISTORTION
(fCLK = 80MHz, 8MHz WINDOW)
MAX5853 toc08
fOUT (MHz)
AMPLITUDE (dB)
10.59.57.5 8.55.5 6.54.5
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
3.5 11.5
fOUT1 = 8.2519MHz
fOUT2 = 8.7030MHz
fOUT1 fOUT2
2fOUT1 - fOUT2 2fOUT2 - fOUT1
MAX5853
Dual, 10-Bit, 80Msps, Current-Output DAC
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, external reference, IFS = 20mA, differential output, differential clock
(unless otherwise noted), TA= +25°C.)
SINGLE-TONE SFDR
(fCLK = 80MHz, 10MHz WINDOW)
MAX5853 toc10
fOUT (MHz)
AMPLITUDE (dB)
131197
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
515
fOUT = 10.0572MHz
AOUT = -1dBFS
SINGLE-TONE SFDR
(fCLK = 25MHz, 2MHz WINDOW)
MAX5853 toc11
fOUT (MHz)
AMPLITUDE (dB)
1.71.30.90.5
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
100
0.1 2.1
fOUT = 1.0132MHz
AOUT = -1dBFS
SINGLE-TONE SFDR
(fCLK = 65MHz, 2.5MHz WINDOW)
MAX5853 toc12
fOUT (MHz)
AMPLITUDE (dB)
5.85.34.84.3
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
3.8 6.3
fOUT = 4.9901MHz
AOUT = -1dBFS
SINGLE-TONE FFT PLOT
(fCLK = 80MHz, NYQUIST WINDOW)
MAX5853 toc13
OUTPUT TONE FREQUENCY (MHz)
AMPLITUDE (dB)
3.95MHz/div
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
0.5 40
fOUT = 10MHz
AOUT = 0dBFS
8-TONE SFDR PLOT
(fCLK = 80MHz, 15MHz WINDOW)
MAX5853 toc09
fOUT (MHz)
AMPLITUDE (dB)
18.515.512.59.5
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
6.5 21.5
fT4
fT3
fT2
fT1
fT5
fT6
fT7
fT8
fT1 = 10.825MHz
fT2 = 11.475MHz
fT3 = 12.425MHz
fT4 = 13.175MHz
fT5 = 14.825MHz
fT6 = 15.675MHz
fT7 = 16.475MHz
fT8 = 17.375MHz
MAX5853
Dual, 10-Bit, 80Msps, Current-Output DAC
_______________________________________________________________________________________ 9
REFERENCE VOLTAGE vs. TEMPERATURE
MAX5853 toc19
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
603510-15
1.20
1.21
1.22
1.23
1.24
1.25
1.19
-40 85
DYNAMIC RESPONSE RISE TIME
MAX5853 toc20
100mV/div
10ns/div
DYNAMIC RESPONSE FALL TIME
MAX5853 toc21
100mV/div
10ns/div
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 80MHz)
MAX5853 toc22
fOUT (MHz)
SFDR (dBc)
353020 2510 155
35
40
45
50
55
60
65
70
75
80
85
90
30
040
0dBFS -6dBFS
-12dBFS
SINGLE-ENDED CLOCK DRIVE
Typical Operating Characteristics (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, external reference, IFS = 20mA, differential output, differential clock
(unless otherwise noted), TA= +25°C.)
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5853 toc14
DIGITAL INPUT CODE
INL (LSB)
900750450 600300150
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-0.5
0 1050
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5853 toc15
DIGITAL INPUT CODE
DNL (LSB)
900750450 600300150
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-0.5
0 1050
POWER DISSIPATION vs. CLOCK FREQUENCY
(fOUT = 10MHz, AOUT = 0dBFS)
MAX5853 toc16
fCLK (MHz)
POWER DISSIPATION (mW)
7570656055504540353025
150
160
170
180
190
200
140
20 80
DIFFERENTIAL
CLOCK DRIVE
SINGLE-ENDED
CLOCK DRIVE
POWER DISSIPATION vs. SUPPLY VOLTAGES
(fCLK = 80MHz, fOUT = 10MHz)
MAX5853 toc17
SUPPLY VOLTAGES (V)
POWER DISSIPATION (mW)
3.453.303.153.002.85
150
160
170
180
190
200
210
220
230
240
250
140
2.70 3.60
DIFFERENTIAL
CLOCK DRIVE
SINGLE-ENDED
CLOCK DRIVE
REFERENCE VOLTAGE vs. SUPPLY VOLTAGES
(fCLK = 80MHz, fOUT = 10MHz)
MAX5853 toc18
SUPPLY VOLTAGES (V)
REFERENCE VOLTAGE (V)
3.453.303.153.002.85
1.22670
1.22690
1.22710
1.22730
1.22750
1.22650
2.70 3.60
MAX5853
Dual, 10-Bit, 80Msps, Current-Output DAC
10 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 DA9/PD Channel A Input Data Bit 9 (MSB)/Power-Down
2
DA8/DACEN
Channel A Input Data Bit 8/DAC Enable Control
3 DA7/IDE Channel A Input Data Bit 7/Interleaved Data Enable
4
DA6/REN
Channel A Input Data Bit 6/Reference Enable. Setting REN = 0 enables the internal reference. Setting
REN = 1 disables the internal reference.
5 DA5/G3 Channel A Input Data Bit 5/Channel A Gain Adjustment Bit 3
6 DA4/G2 Channel A Input Data Bit 4/Channel A Gain Adjustment Bit 2
7 DA3/G1 Channel A Input Data Bit 3/Channel A Gain Adjustment Bit 1
8 DA2/G0 Channel A Input Data Bit 2/Channel A Gain Adjustment Bit 0
9 DA1 Channel A Input Data Bit 1
10 DA0 Channel A Input Data Bit 0 (LSB)
11 DB9 Channel B Input Data Bit 9 (MSB)
12 DB8 Channel B Input Data Bit 8
13 DB7 Channel B Input Data Bit 7
14 DB6 Channel B Input Data Bit 6
15 DB5 Channel B Input Data Bit 5
16 DVDD D i g i tal P ow er Inp ut. S ee the P ow er S up p l i es, Byp assi ng , D ecoup l i ng , and Layout secti on for m or e d etai l s.
17 DGND Digital Ground
18 DB4 Channel B Input Data Bit 4
19 DB3 Channel B Input Data Bit 3
20 DB2 Channel B Input Data Bit 2
21 DB1 Channel B Input Data Bit 1
22 DB0 Channel B Input Data Bit 0 (LSB)
23 CW Active-Low Control Word Write Pulse. The control word is latched on the rising edge of CW.
24 DCE
Active-Low Differential Clock Enable Input. Drive DCE low to enable the differential clock inputs
CLKXP and CLKXN. Drive DCE high to disable the differential clock inputs and enable the single-
ended CLK input.
25 CLKXP Positive Differential Clock Input. With DCE = 0, CLKXP and CLKXN are enabled. With DCE = 1, CLKXP
and CLKXN are disabled. Connect CLKXP to CGND when the differential clock is disabled.
26 CLKXN Negative Differential Clock Input. With DCE = 0, CLKXP and CLKXN are enabled. With DCE = 1, CLKXP
and CLKXN are disabled. Connect CLKXN to CVDD when the differential clock is disabled.
27, 30 CVDD Clock Power Input. See the Power Supplies, Bypassing, Decoupling, and Layout section for more
28 CLK
Single-Ended Clock Input/Output. With the differential clock disabled (DCE = 1), CLK becomes a
single-ended conversion clock input. With the differential clock enabled (DCE = 0), CLK is a single-
ended output that mirrors the differential clock inputs CLKXP and CLKXN. See the Clock Modes section
for more information on CLK.
29 CGND Clock Ground
31 REFO
Reference Input/Output. REFO serves as a reference input when the internal reference is disabled. If the
internal 1.24V reference is enabled, REFO serves as an output for the internal reference. When the
internal reference is enabled, bypass REFO to AGND with a 0.1µF capacitor
MAX5853
Dual, 10-Bit, 80Msps, Current-Output DAC
______________________________________________________________________________________ 11
Detailed Description
The MAX5853 dual, high-speed, 10-bit, current-output
DAC provides superior performance in communication
systems requiring low-distortion analog-signal recon-
struction. The MAX5853 combines two DACs and an on-
chip 1.24V reference (Figure 2). The current outputs of
the DACs can be configured for differential or single-
ended operation. The full-scale output current range is
adjustable from 2mA to 20mA to optimize power dissi-
pation and gain control.
The MAX5853 accepts an input data and a DAC con-
version rate of 80MHz. The inputs are latched on the
rising edge of the clock whereas the output latches on
the following rising edge.
The MAX5853 features three modes of operation: normal,
standby, and power-down (Table 2). These modes allow
efficient power management. In power-down, the
MAX5853 consumes only 1µA of supply current. Wake-
up time from standby mode to normal DAC operation
is 3µs.
Programming the DAC
An 8-bit control word routed through channel A’s data
port programs the gain matching, reference, and the
operational mode of the MAX5853. The control word is
latched on the rising edge of CW. CW is independent
of the DAC clock. The DAC clock can always remain
running when the control word is written to the DAC.
Table 1 and Table 2 represent the control word format
and function.
The gain on channel A can be adjusted to achieve gain
matching between two channels in a user’s system.
The gain on channel A can be adjusted from -0.4dB to
0.35dB in steps of 0.05dB by using bits G3 to G0 (see
Table 3).
Pin Description (continued)
PIN NAME FUNCTION
32 REFR Full-Scale Current Adjustment. To set the output full-scale current, connect an external resistor RSET
between REFR and AGND. The output full-scale current is equal to 32 x VREFO/RSET.
33, 39 AVDD Anal og P ow er Inp ut. S ee the P ow er S up p l i es, Byp assi ng , D ecoup l i ng , and Layout secti on for m or e d etai l s.
34 OUTNB Channel B Negative Analog Current Output
35 OUTPB Channel B Positive Analog Current Output
36, 40 AGND Analog Ground
37 OUTNA Channel A Negative Analog Current Output
38 OUTPA Channel A Positive Analog Current Output
—EP Exposed Paddle. Connect EP to the common point of all ground planes.
10-BIT
DACA
CHANNEL A
GAIN
CONTROL
DA0
DA1
DA2/G0
DA3/G1
DA4/G2
DA5/G3
DA6/REN
DA7/IDE
DA8/DACEN
DA9/PD
DACA INPUT REGISTER
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DACB INPUT REGISTER
CONTROL WORD
CW
G0
G1
G2
OPERATING
MODE
CONTROLLER
DACEN
PD
G3
INPUT DATA
INTERLEAVER
10-BIT
DACB
CLOCK
DISTRIBUTION
1.24V REFERENCE
AND CONTROL
AMPLIFIER
CLOCK
POWER
MANAGEMENT
DCE
CLKXP
CLKXN
CLK
DIGITAL
POWER
MANAGEMENT
ANALOG
POWER
MANAGEMENT
MAX5853
DVDD
DGND
CVDD
CGND
IDE
REN
REFR
REFO
RSET
AGND
OUTNB
OUTPB
OUTNA
OUTPA
AGND
AVDD
Figure 2. Simplified Diagram
MAX5853
Dual, 10-Bit, 80Msps, Current-Output DAC
12 ______________________________________________________________________________________
Device Power-Up and
States of Operation
At power-up, the MAX5853’s default configuration is inter-
nal reference, noninterleaved input mode with a gain of
0dB and a fully operational converter. In shutdown, the
MAX5853 consumes only 1µA of supply current, and in
standby the current consumption is 3.1mA. Wake-up time
from standby mode to normal operation is 3µs.
Clock Modes
The MAX5853 allows both single-ended CMOS and dif-
ferential clock mode operation, and supports update
rates of up to 80Msps. These modes are selected
through an active-low control line called DCE. In single-
ended clock mode (DCE = 1), the CLK pin functions as
an input, which accepts a user-provided single-ended
clock signal. Data is written to the converter on the rising
edge of the clock. The DAC outputs (previous data) are
updated simultaneously on the same edge.
If the DCE pin is pulled low, the MAX5853 operates in
differential clock mode. In this mode, the clock signal
has to be applied to the differential clock input pins
CLKXP/CLKXN. The differential input accepts an input
range of ≥0.5VP-P and a common-mode range of 1V to
(CVDD - 0.5V), making the part ideal for low-input ampli-
tude clock drives. CLKXP/CLKXN also help to minimize
the jitter, and allow the user to connect a crystal oscilla-
tor directly to the MAX5853.
The CLK pin now becomes an output, and provides a sin-
gle-ended replica of the differential clock signal, which
may be used to synchronize the input data. Data is writ-
ten to the device on the rising edge of the CLK signal.
CONTROL WORD
FUNCTION
PD Power-Down. The part enters power-down mode if PD = 1.
DACEN DAC Enable. When DACEN = 0 and PD = 0, the part enters standby mode.
IDE
Interleaved Data Mode. IDE = 1 enables the interleaved data mode. In this mode, digital data for both
channels is applied through channel A in a multiplexed fashion. Channel B data is written on the falling edge
of the clock signal and channel A data is written on the rising edge of the clock signal.
REN Reference Enable Bit. REN = 0 activates the internal reference. REN = 1 disables the internal reference and
requires the user to apply an external reference between 0.1V to 1.32V.
G3 Bit 3 (MSB) of Gain Adjust Word
G2 Bit 2 of Gain Adjust Word
G1 Bit 1 of Gain Adjust Word
G0 Bit 0 (LSB) of Gain Adjust Word
Table 1. Control Word Format and Function
GAIN ADJUSTMENT ON
CHANNEL A (dB)
G3
G2
G1
G0
+0.4 0000
0 1000
-0.35 1111
Table 3. Gain Difference Setting
X = Don’t care.
MSB LSB
PD
DACEN
IDE REN G3 G2 G1 G0 X X
Table 2. Configuration Modes
MODE
PD DACEN IDE
REN
Normal operation;
noninterleaved inputs;
internal reference active
0100
Normal operation;
noninterleaved inputs;
internal reference disabled
0101
Normal operation;
interleaved inputs;
internal reference disabled
0111
Standby 0 0
X
X
Power-down 1 X
X
X
Power-up 0 1
X
X
MAX5853
Dual, 10-Bit, 80Msps, Current-Output DAC
______________________________________________________________________________________ 13
IFS
CCOMP*
REFR IREF
REFO
MAX4040 1.24V
BANDGAP
REFERENCE
CURRENT-
SOURCE
ARRAY
*COMPENSATION CAPACITOR (CCOMP ≈ 100nF).
OPTIONAL EXTERNAL BUFFER
FOR HEAVIER LOADS
MAX5853
IREF =VREF
RSET
RSET
AGND
AGND
REN = 0
Figure 3. Setting IFS with the Internal 1.24V Reference and the
Control Amplifier
Internal Reference and Control Amplifier
The MAX5853 provides an integrated 50ppm/°C, 1.24V,
low-noise bandgap reference that can be disabled and
overridden with an external reference voltage. REFO
serves either as an external reference input or an inte-
grated reference output. If REN = 0, the internal refer-
ence is selected and REFO provides a 1.24V (50µA)
output. Buffer REFO with an external amplifier, when
driving a heavy load.
The MAX5853 also employs a control amplifier
designed to simultaneously regulate the full-scale out-
put current (IFS) for both outputs of the devices.
Calculate the output current as:
IFS = 32 ✕IREF
where IREF is the reference output current (IREF =
VREFO / RSET) and IFS is the full-scale output current. RSET
is the reference resistor that determines the amplifier out-
put current of the MAX5853 (Figure 3). This current is mir-
rored into the current-source array where IFS is equally
distributed between matched current segments and
summed to valid output current readings for the DACs.
External Reference
To disable the internal reference of the MAX5853, set
REN = 1. Apply a temperature-stable, external reference
to drive the REFO pin and set the full-scale output
(Figure 4). For improved accuracy and drift performance,
choose a fixed output voltage reference such as the
1.2V, 25ppm/°C MAX6520 bandgap reference.
Detailed Timing
The MAX5853 accepts an input data and DAC con-
version rate of up to 80Msps. The input latches on the
rising edge of the clock, whereas the output latches
on the following rising edge.
Figure 5 depicts the write cycle of the two DACs in non-
interleaved mode.
The MAX5853 can also operate in an interleaved data
mode. Programming the IDE bit with a high level activates
this mode (Tables 1 and 2). In interleaved mode, data for
both DAC channels is written through input port A.
Channel B data is written on the falling edge of the clock
signal and then channel A data is written on the following
rising edge of the clock signal. Both DAC outputs (chan-
nel A and B) are updated simultaneously on the next fol-
lowing rising edge of the clock. The interleaved data
mode is attractive for applications where lower data rates
are acceptable and interfacing on a single 10-bit bus is
desired (Figure 6).
AVDD
EXTERNAL
1.2V
REFERENCE
MAX6520
AGND
0.1µF10µF
AVDD
AGND
IFS
REFR IREF
REFO
1.24V
BANDGAP
REFERENCE
CURRENT-
SOURCE
ARRAY
MAX5853
RSET
AGND
REN = 1
Figure 4. MAX5853 with External Reference
MAX5853
Dual, 10-Bit, 80Msps, Current-Output DAC
14 ______________________________________________________________________________________
CLKXN
CLKXP
CLK
OUTPUT
CW
DA0–DA9
OUTPA
OUTNA
OUTPB
OUTNB
tCXL tCXH
tCDH tCDL
tDCS tDCH tDCS tDCH tCS tCW
tCWL
DACA DACB + 1 DACA + 1 CONTROL
WORD DACB + 2 DACA + 2
DACA - 1
DACB - 1
DACA
DACB
DACA + 1
DACB + 1
Figure 6. Timing Diagram for Interleaved Data Mode (IDE = 1)
CLKXN
CLKXP
CLK
OUTPUT
CW
DA0–DA9
OUTPA
OUTNA
DB0–DB9
OUTPB
OUTNB
DACA - 1
DACB - 1
DACA
DACB
DACA + 1
DACB + 1
DACA + 2
DACB + 2
CONTROL
WORD
XXXX
DACA + 3
DACB + 3
DACA - 1
DACB - 1
DACA
DACB
DACA + 1
DACB + 1
DACA + 2
DACB + 2
XXXX
(CONTROL WORD DATA)
XXXX
DACA + 3
DACB + 3
tCXH tCXL
tCDH
tCDL
tDCS tDCH
tDCS tDCH
tCWL
tCS tCW
Figure 5. Timing Diagram for Noninterleaved Data Mode (IDE = 0)
MAX5853
Dual, 10-Bit, 80Msps, Current-Output DAC
______________________________________________________________________________________ 15
DA0–DA9
10 MAX5853
1/2
50Ω
100Ω
50Ω
OUTPA
OUTNA
VOUTA,
SINGLE ENDED
DB0–DB9
10 MAX5853
1/2
50Ω
100Ω
50Ω
OUTPB
OUTNB
VOUTB,
SINGLE ENDED
CVDD
DVDD
AVDD
CGNDDGNDAGND
Figure 7. Application with Output Transformer Performing
Differential-to-Single-Ended Conversion
DA0–DA9
10 MAX5853
1/2
1/2
50Ω
50Ω
CVDD
DVDD
AVDD
CGNDDGNDAGND
OUTPA
OUTNA
DB0–DB9
10 MAX5853
50Ω
50Ω
OUTPB
OUTNB
Figure 8. Application with DC-Coupled Differential Outputs
Applications Information
Differential-to-Single-Ended Conversion
The MAX5853 exhibits excellent dynamic performance
to synthesize a wide variety of modulation schemes,
including high-order QAM modulation with OFDM.
Figure 7 shows a typical application circuit with output
transformers performing the required differential-to-
single-ended signal conversion. In this configuration,
the MAX5853 operates in differential mode, which
reduces even-order harmonics, and increases the
available output power.
Differential DC-Coupled Configuration
Figure 8 shows the MAX5853 output operating in differ-
ential, DC-coupled mode. This configuration can be
used in communication systems employing analog
quadrature upconverters and requiring a baseband
sampling, dual-channel, high-speed DAC for I/Q syn-
thesis. In these applications, information bandwidth can
extend from 10MHz down to several hundred kilohertz.
DC-coupling is desirable to eliminate long discharge
time constants that are problematic with large, expen-
sive coupling capacitors. Analog quadrature upcon-
verters have a DC common-mode input requirement of
typically 0.7V to 1.0V. The MAX5853 differential I/Q out-
puts can maintain the desired full-scale level at the
required 0.7V to 1.0V DC common-mode level when
powered from a single 2.85V (±5%) supply. The
MAX5853 meets this low-power requirement with mini-
mal reduction in dynamic range while eliminating the
need for level-shifting resistor networks.
Power Supplies, Bypassing,
Decoupling, and Layout
Grounding and power-supply decoupling strongly influ-
ence the MAX5853 performance. Unwanted digital
crosstalk can couple through the input, reference,
MAX5853
Dual, 10-Bit, 80Msps, Current-Output DAC
16 ______________________________________________________________________________________
*Vias connect the land pattern to internal or external copper planes.
power-supply, and ground connections, which can
affect dynamic specifications, like signal-to-noise ratio
or spurious-free dynamic range. In addition, electro-
magnetic interference (EMI) can either couple into or
be generated by the MAX5853. Observe the grounding
and power-supply decoupling guidelines for high-
speed, high-frequency applications. Follow the power
supply and filter configuration to realize optimum
dynamic performance.
Use of a multilayer printed circuit (PC) board with sepa-
rate ground and power-supply planes is recommend-
ed. Run high-speed signals on lines directly above the
ground plane. The MAX5853 has separate analog and
digital ground buses (AGND, CGND, and DGND,
respectively). Provide separate analog, digital, and
clock ground sections on the PC board with only one
point connecting the three planes. The ground connec-
tion points should be located underneath the device
and connected to the exposed paddle. Run digital sig-
nals above the digital ground plane and analog/clock
signals above the analog/clock ground plane. Digital
signals should be kept away from sensitive analog,
clock, and reference inputs. Keep digital signal paths
short and metal trace lengths matched to avoid propa-
gation delay and data skew mismatch.
The MAX5853 includes three separate power-supply
inputs: analog (AVDD), digital (DVDD), and clock
(CVDD). Use a single linear regulator power source to
branch out to three separate power-supply lines (AVDD,
DVDD, CVDD) and returns (AGND, DGND, CGND).
Filter each power-supply line to the respective return
line using LC filters comprising ferrite beads and 10µF
capacitors. Filter each supply input locally with 0.1µF
ceramic capacitors to the respective return lines.
Note: To maintain the dynamic performance of the
Electrical Characteristics, ensure the voltage differ-
ence between DVDD, AVDD, and CVDD does not
exceed 150mV.
Thermal Characteristics and Packaging
Thermal Resistance
40-lead thin QFN-EP:
θJA = 38°C/W
The MAX5853 is packaged in a 40-pin thin QFN-EP
package, providing greater design flexibility, increased
thermal efficiency, and optimized AC performance of
the DAC. The EP enables the implementation of
grounding techniques, which are necessary to ensure
highest performance operation.
In this package, the data converter die is attached to an
EP leadframe with the back of this frame exposed at the
package bottom surface, facing the PC board side of
the package. This allows a solid attachment of the pack-
age to the PC board with standard infrared (IR) flow sol-
dering techniques. A specially created land pattern on
the PC board, matching the size of the EP (4.1mm ✕
4.1mm), ensures the proper attachment and grounding
of the DAC. Designing vias* into the land area and
implementing large ground planes in the PC board
design allows for highest performance operation of the
DAC. Use an array of 3 ✕3 vias (≤0.3mm diameter per
via hole and 1.2mm pitch between via holes) for this 40-
pin thin QFN-EP package (package code: T4066-1).
Dynamic Performance
Parameter Definitions
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of all essential harmon-
ics (within a Nyquist window) of the input signal to the
fundamental itself. This can be expressed as:
where V1is the fundamental amplitude, and V2through
VNare the amplitudes of the 2nd through Nth order har-
monics. The MAX5853 uses the first seven harmonics
for this calculation.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier fre-
quency (maximum signal component) to the RMS value
of their next-largest spectral component. SFDR is usu-
ally measured in dBc with respect to the carrier fre-
quency amplitude or in dBFS with respect to the DAC’s
full-scale range. Depending on its test condition, SFDR
is observed within a predefined window or to Nyquist.
Multitone Power Ratio (MTPR)
A series of equally spaced tones are applied to the DAC
with one tone removed from the center of the range.
MTPR is defined as the worst-case distortion (usually a
3rd-order harmonic product of the fundamental frequen-
cies), which appears as the largest spur at the frequency
of the missing tone in the sequence. This test can be per-
formed with any number of input tones; however, four and
eight tones are among the most common test conditions
for CDMA- and GSM/EDGE-type applications.
THD
VVV V
V
N
=×
++ +
log
... ...
20
2232422
1
MAX5853
Dual, 10-Bit, 80Msps, Current-Output DAC
______________________________________________________________________________________ 17
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in dBc of either out-
put tone to the worst 3rd-order (or higher) IMD products.
Static Performance Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. For a DAC,
the deviations are measured at every individual step.
Differential Nonlinearity (DNL)
Differential nonlinearity (DNL) is the difference between
an actual step height and the ideal value of 1 LSB. A
DNL error specification no more negative than -1 LSB
guarantees monotonic transfer function.
Offset Error
Offset error is the current flowing from positive DAC
output when the digital input code is set to zero. Offset
error is expressed in LSBs.
Gain Error
A gain error is the difference between the ideal and the
actual full-scale output current on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step. The ideal current is
defined by reference voltage at VREFO / IREF x 32.
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles to its
new output value to within the converter’s specified
accuracy.
Glitch Impulse
A glitch is generated when a DAC switches between
two codes. The largest glitch is usually generated
around the midscale transition, when the input pattern
transitions from 011…111 to 100…000. This occurs due
to timing variations between the bits. The glitch impulse
is found by integrating the voltage of the glitch at the
midscale transition over time. The glitch impulse is usu-
ally specified in pV-s.
Chip Information
TRANSISTOR COUNT: 9,035
PROCESS: CMOS
Table 4. Part Selection Table
PART SPEED (Msps) RESOLUTION
MAX5851 80 8-bit, dual
MAX5852 165 8-bit, dual
MAX5853 80 10-bit, dual
MAX5854 165 10-bit, dual
MAX5853
Dual, 10-Bit, 80Msps, Current-Output DAC
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
QFN THIN 6x6x0.8.EPS
e e
LL
A1 A2 A
E/2
E
D/2
D
E2/2
E2
(NE-1) X e
(ND-1) X e
e
D2/2
D2
b
k
k
L
C
L
C
L
C
L
C
L
D
1
2
21-0141
PACKAGE OUTLINE
36,40L THIN QFN, 6x6x0.8 mm
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
9. DRAWING CONFORMS TO JEDEC MO220.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
3. N IS THE TOTAL NUMBER OF TERMINALS.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
NOTES:
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
D
2
2
21-0141
PACKAGE OUTLINE
36, 40L THIN QFN, 6x6x0.8 mm