155 Mbps UTP#5 Complete PHY Interface AD6816 a FEATURES Complete ATM Transceiver for 155 Mbps for UTP#5 or Fiber Meets ATM Forum UNI 3.1 Requirements Meets SONET/SDH Jitter Requirements Meets FCC Class B Emissions Requirements Drives up to 110M Category #5 UTP/FTP Adjustable Line Driver Output Current Equalizes up to 110M Category #5 UTP/FTP Baseline Restoration Function Eliminates Baseline Wander 19.44 MHz Oscillator Circuit Frequency Synthesizer for 155 MHz Tx Bit Clock 155 Mbps Clock Recovery and Data Retiming Phase Continuous Switch at Frequency Synthesizer Output Single Supply Operation: +5 V or -5.2 V Low Power: 400 mW 10KH ECL Compatible Output Package: 44-Pin Thin Quad Flatpack within the IC allow the user to perform loop-back, bypass the data retiming function and select the frequency reference for the transmit bit clock (independent timing or loop timing). The line equalization and baseline restoration block compensates for up to 110M Category #5 UTP and transformer, respectively. This block has a Signal Detect output, SDOUT, that when low indicates a loss of input signal at RX, RXN. The AD6816 supports application with a fiber optic receiver or transceiver. In this case, the line equalizer block adapts to provide no equalization. The line driver has a differential ECL input stage providing controlled current output suitable for driving a Category #5 UTP system. A single resistor from the line driver output current control pin to ground controls the output current. The user has the option to disable the line driver output. A signal multiplexer allows the user to loop back the line driver input signal through the clock recovery and data retiming PLL for test purposes. The clock recovery and data retiming PLL has a factory trimmed VCO center frequency and an integrated frequency control loop that combine to ensure signal acquisition. This eliminates reliance on external components, like a crystal or an SAW filter, to aid frequency acquisition. At frequency lock, the frequency error is zero and the frequency detector has no effect. At this point, the PLL works to ensure that the output phase tracks the input PRODUCT DESCRIPTION The AD6816 provides a single chip solution for interfacing an ATM User-Network Interface IC to either a Category #5 Unshielded Twisted Pair (UTP) system or a fiber optic system. The IC provides line equalization and baseline restoration, line driver, clock recovery and data retiming, local reference clock oscillator and frequency synthesis functions. Signal multiplexers (Continued on page 4) TX LINE DRIVER 19.44 MHz OSCILLATOR MUX CFS2 CFS1 RXCLKSEL ECLFREFIN ECLFREFINN OSCOUT FREFIN XTALIN2 XTALIN1 DRIVEINN DRIVEIN TXAMPSET FUNCTIONAL BLOCK DIAGRAM 155MHz FREQUENCY SYNTHESIZER TXCLKOUT TXCLKOUTN TXN RX RXN CEQ1 CEQ2 DIVIDE BY 8 AD6816 DRVROFF EQUALIZER, BASELINE RESTORATION AND LOS MUX RXCLKOUT CLOCK RECOVERY AND DATA RETIMING PHASE-LOCKED LOOP RXCLKOUTN MUX RXDATOUT RXDATOUTN DRBYPASS CCR2 CCR1 LBSEL SDOUT REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1997 = T to T , V = V AD6816-SPECIFICATIONS (Tunless otherwise noted) A Parameter RECEIVER Input Signal Range Differential Input Voltage Transitionless Data Run Equalizer Time Constant SIGNAL DETECT Trip Level Release Level Response Time SDOUT Output Logic High SDOUT Output Logic Low LINE DRIVER Differential Input Common-Mode Input Voltage Output Current Maximum Current Variation Common-Mode Current Rise and Fall Times Rise and Fall Times INPUT CONTROL SIGNALS Input Logic Low, VIL Input Logic High, V IH CLOCK RECOVERY PLL Output Clock Jitter Static Phase Error Bandwidth Setup Time (tSU) Hold Time (tH) OSCILLATOR CIRCUIT Center Frequency Frequency Deviation Output Duty Cycle Output Drive High Output Drive Low FREQUENCY SYNTHESIZER Reference Input Frequency Duty Cycle Tolerance Bandwidth Time Constant Output Clock Jitter ECLFREFIN/N Common-Mode Input Signal Differential Input Signal FREF IN Logic Low, VIL FREF IN Logic High, VIH MIN MAX S MIN to VMAX, CCR = 0.1 mF, CEQ = 0.1 mF, CFS = 0.0047 mF, Condition Min Signal Into Up to 110 M UTP #5 0.764 Typ CEQ = 0.1 F 223-1 PRN, 0 M Cable 223-1 PRN Input, 0 M Cable 30 M Cable, Figure 22. Evaluation Circuit Load = +4 mA Load = -2.2 mA Refer to Figure 2 Output Current Variation < 1% Max Units 1.06 1.5 400 1 V p-p Volts Bit Periods sec 0.4 mV p-p mV p-p s Volts Volts 98 118 12.9 3.6 0.150 2 1 4 20 5.0 1.13 k 1% Resistor-to-Ground at TXAMPSET Percentage of Output Drive Current 50 Collector Loads at TX and TXN, TA = +25C 10%-90%, Device Only 10%-90%, Transformer Output, Refer to Figure 22 2.5 7 2.1 2.7 V p-p V mA % % % ns ns Refer to Table I 0.8 Volts Volts 2.0 4 100 3.0 3.4 3.5 20 Degrees rms Degrees kHz ns ns 19.44 22 43 19.442 82 2 223-1 PRN Input 223-1 PRN Input 223-1 PRN Input Figure 1 Figure 1 2.4 2.9 Crystal RSERIES 40 Series Mode Crystal Accuracy 50 ppm 19.437 400 to 2 V Load 400 to 2 V Load 400 to 2 V Load 3.5 4.0 3.6 0.4 19.44 or 9.72 20 80 200 800 1.8 2.8 MHz ppm % Volts Volts MHz % kHz ns Degrees rms FREFIN Pin @ Ground VCC - 2 200 VCC ECLFREF & ECLFREFN Pins @ Ground 0.8 2 PECL OUTPUT Output Logic High, VOH Output Logic Low, V OL Pins 10, 11, 13, 14, 17, 18 Referred to VCC Referred to VCC -1.2 -2.0 POWER SUPPLY VOLTAGE VMIN to VMAX 4.5 POWER SUPPLY CURRENT VCC = 5.0 V, VEE = GND, TA = +25C OPERATING TEMPERATURE RANGE TMIN to TMAX -1.0 -1.8 77 0 Volts mV Volts Volts -0.7 -1.7 Volts Volts 5.5 Volts 95 mA 70 C Specifications subject to change without notice. -2- REV. A AD6816 Table I. Control Functions (NC = No Connection) ABSOLUTE MAXIMUM RATINGS* Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12 V Input Voltage (Pin 43 or Pin 44 to VCC) . . . . . . . VCC + 0.6 V Maximum Junction Temperature . . . . . . . . . . . . . . . . +165C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 10 sec) . . . . . . . +300C ESD Rating (Human Body Model) . . . . . . . . . . . . . . . 1500 V *Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Input Signal Mnemonic Function Disable Line Driver DRVROFF Logic 1 Disables Line Driver Output Logic 0 or NC Enables Line Driver Output Loop-Back LBSEL Logic 1 Enables Loop-Back from DRIVEIN/N Logic 0 or NC Disables Loop-Back Bypass Data Retiming DRBYPASS Logic 1 Bypassing Data Retiming Logic 0 or NC Enables Data Retiming Reference Frequency Select for Frequency Synthesizer RXCLKSEL Logic 1 Selects Reference Frequency Derived from Recovered Clock Thermal Characteristics 44-Pin Thin Quad Flatpack Package: JA = 50C/Watt, JC = 10C/Watt SETUP HOLD tSU tH RXDATAOUT 50% (PIN 13) RXCLKOUT 50% (PIN 10) Logic 0 or NC Selects External Frequency Reference Figure 1. Clock Recovery PLL Setup and Hold Time Table II. Configuring the Frequency Synthesizer for Different Oscillator Types VDN3 TXAMPSET TX VDP3 TXN DRVROFF LBSELECT RXCLKSEL DRBYPASS RX RXN PIN CONFIGURATION 44 43 42 41 40 39 38 37 36 35 34 SDOUT 1 33 DRIVEIN PIN 1 IDENTIFIER 32 DRIVEINN VAN1 2 CEQ1 3 31 VAN2 CEQ2 4 30 XTALIN2 CCR1 5 Oscillator Output Type Apply to Input Pin(s) TTL (Single Ended Including On-Chip Oscillator) PECL FREFIN (Pin 25) 29 XTALIN1 AD6816 CCR2 6 Description ECLFREFIN/ ECLFREFINN (Pins 24 & 23) Ground Pin(s) ECLFREFIN/ ECLFREFINN (Pins 24 & 23) FREFIN (Pin 25) 28 VDN2 TOP VIEW (Not to Scale) ORDERING GUIDE 27 VDP2 VAP1 7 VDP4 8 26 OSCOUT VDN4 9 25 FREFIN Model Temperature Range Package Description Package Option 24 ECLFREFIN RXCLKOUT 10 23 ECLFREFINN RXCLKOUTN 11 AD6816KST 0C to +70C 44-Pin Thin Quad Flatpack ST-44 CFS2 VAP2 CFS1 VDP1 TXCLKOUT TXCLKOUTN VDPECL2 VDN1 RXDATAOUTN VDPECL1 RXDATAOUT 12 13 14 15 16 17 18 19 20 21 22 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6816 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. A -3- WARNING! ESD SENSITIVE DEVICE AD6816 PIN DESCRIPTION (continued from page 1) phase. The two loops work in harmony with each other, requiring no control signals for enabling or disabling. Shorting the clock recovery and data retiming PLL damping factor capacitor, CCR, brings the recovered clock output signal to the clock recovery VCO center frequency. The crystal oscillator circuit provides an accurate 19.44 MHz output with a series mode, 19.44 MHz crystal. This circuit requires no capacitive tuning and can provide a 19.44 MHz, 100 ppm output, capable of driving up to five TTL gates or 50 pF load capacitance. The frequency synthesizer processes either a 19.44 MHz or a 9.72 MHz input signal at the FREF, ECLFREF/ECLFREFN pins, or the 19.44 MHz byte clock derived from the 155.52 MHz RXCLKOUT & RXCLKOUTN signal. The RXCLKSEL signal determines whether or not the derived byte clock is used by the frequency synthesizer. When the RXCLKSEL signal is high, the frequency synthesizer processes the derived byte clock. When the RXCLKSEL signal is left unconnected, or held low, the frequency synthesizer processes the reference signal at the FREFIN or ECLFREFIN/ECLFREFINN pins (refer to Table II). Having the frequency synthesizer loop process either the derived byte clock or a reference eliminates runt pulses that may occur when switching between two 155.52 MHz bit clocks. The synthesizer can be configured to accept an external frequency reference in either TTL/CMOS format or in PECL format. This selection is made by sensing the common-mode voltage at Pins 23 and 24. If valid PECL levels are present at Pins 23 and 24, this signal is used as the frequency reference and any signal present at Pin 25 is ignored. If Pins 23 and 24 are connected to ground (VDN1, Pin 15), the TTL/CMOS input (Pin 25) is enabled and used as the frequency reference for the synthesizer. The AD6816 is packaged in a 44-pin Thin Quad Flatpack (TQFP), having lead frame dimensions 0.55" x 0.55". -4- Pin No. Mnemonic Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Signal Detect Output Analog Ground--Clock Recovery and Equalizer Equalizer Loop Filter Capacitor Equalizer Loop Filter Capacitor Clock Recovery Loop Damping Capacitor Clock Recovery Loop Damping Capacitor Analog Supply--Clock Recovery and Equalizer Digital Supply--Clock Recovery Logic and Mux Digital Ground--Clock Recovery Logic and Mux Differential Recovered Clock Output Differential Recovered Clock Output Digital Supply--Clock and Data Output Drivers Differential Recovered Data Output Differential Recovered Data Output Digital Ground--Synthesizer Logic Digital Supply--Synthesizer Driver Differential Synthesized Clock Output Differential Synthesized Clock Output Digital Supply--Synthesizer Logic Synthesizer Loop Filter Capacitor Synthesizer Loop Filter Capacitor Analog Supply--Synthesizer & Oscillator Differential ECL Input to Synthesizer Differential ECL Input to Synthesizer CMOS/TTL Input to Synthesizer Crystal Oscillator CMOS/TTL Output Digital Supply--Oscillator Output Digital Ground--Oscillator Output Crystal Connection Crystal Connection Analog Ground--Synthesizer and Oscillator Line Driver Differential ECL Input Line Driver Differential ECL Input Digital Ground--Line Driver Line Driver Output Current Control Digital Supply--Line Driver Line Driver Collector Output Line Driver Collector Output Line Driver Disable (CMOS/TTL) Synthesizer Frequency Reference Select Loop-Back Select Data Retiming Bypass Differential Equalizer Input Differential Equalizer Input SDOUT VAN1 CEQ1 CEQ2 CCR1 CCR2 VAP1 VDP4 VDN4 RXCLKOUT RXCLKOUTN VDPECL1 RXDATAOUT RXDATAOUTN VDN1 VDPECL2 TXCLKOUT TXCLKOUTN VDP1 CFS1 CFS2 VAP2 ECLFREFINN ECLFREFIN FREFIN OSCOUT VDP2 VDN2 XTALIN1 XTALIN2 VAN2 DRIVEINN DRIVEIN VDN3 TXAMPSET VDP3 TX TXN DRVROFF RXCLKSEL LBSELECT DRBYPASS RX RXN REV. A AD6816 DEFINITION OF TERMS Maximum, Minimum and Typical Specifications Specifications for every parameter are derived from statistical analyses of data taken on multiple devices from multiple wafer lots. Typical specifications are the mean of the distribution of the data for that parameter. If a parameter has a maximum (or a minimum), that value is calculated by adding to (or subtracting from) the mean six times the standard deviation of the distribution. This procedure is intended to tolerate production variations: if the mean shifts by 1.5 standard deviations, the remaining 4.5 standard deviations still provide a failure rate of only 3.4 parts per million. For all tested parameters, the test limits are guardbanded to account for tester variation to guarantee that no device is shipped outside of data sheet specifications. Signal Detect: Response Time Response time is the delay between removal of a dc-coupled input signal (at RX & RXN) and indication of loss of signal (LOS) at SDOUT. Clock Recovery PLL: Static Phase Error This is the steady-state phase difference, in degrees, between the recovered clock sampling edge and the optimum sampling instant, which is assumed to be halfway between the rising and falling edges of a data bit. Gate delays between the signals that define static phase error and IC input and output signals prohibit direct measurement of static phase error. Data Transition Density, r This is a measure of the number of data transitions, from "0" to "1" and from "1" to "0," over many clock periods. is the ratio (0 < < 1) of data transitions to bit periods. The 223-1 PRN input data pattern has = 1/2. Time Constant The Frequency Synthesizer PLL time constant (800 ns = 1/bandwidth) determines the output frequency drift after switching the reference frequency input. The time constant works to smooth the output frequency response to change in reference input guaranteeing no runt pulses at the output. Crystal Oscillator The AD6816 integrated oscillator circuit is specified to provide a 19.44 MHz output frequency with 100 ppm frequency accuracy using a 19.44 MHz 50 ppm series mode crystal with series resistance less than 40 . A series mode crystal oscillator is used instead of the more common parallel mode circuit. The primary advantage of the series mode oscillator is that shunt capacitance has no effect since the crystal presents a low impedance at resonance. All the accuracy inherent in the crystal can be achieved by the series mode circuit. In contrast, the parallel mode circuit requires a trimmer capacitor shunt to the crystal to compensate stray capacitances. In addition, these stray and trim capacitances must be stable over temperature for high accuracy. Crystal vendors easily supply either type of crystal. It is necessary to specify that a series mode crystal is needed. Oscillator Circuit: Duty Cycle Duty cycle is calculated as (100 x on time)/period, where on time equals the time the clock signal is greater than the midpoint between its "0" level and its "1" level. Line Driver Differential Input (Refer to Figure 2) The line driver is specified to provide output current variation less than 1% with a 3 V input common-mode signal and a differential input signal between 150 mV and 1 V p-p. PLL Jitter This is the dynamic displacement of digital signal edges from their long term average positions, measured in degrees rms or Unit Intervals (UI). DIFFERENTIAL INPUT = 150mV p-p MINIMUM VCM = 3V Output Jitter SCOPE PROBE This is the jitter on the clock recovery PLL or frequency synthesizer PLL output clock, in degrees rms, due to a specific pattern or some pseudo random input data sequence (PRN sequence). DRIVEIN 33 Jitter Transfer DRIVEINN 32 AD6816 LINE DRIVER The clock recovery PLL and frequency synthesizer PLL both exhibit a low-pass filter response to jitter applied to their respective inputs. VCM Bandwidth This describes the frequency at which the clock recovery PLL or frequency synthesizer PLL attenuate sinusoidal input jitter by 3 dB. Figure 2. Line Driver Differential Input (Single-Ended Measurement Shown) Frequency Synthesizer PLL: Duty Cycle Tolerance The frequency synthesizer PLL exhibits a duty cycle tolerance that is measured by applying an input signal (nominal input frequency) with a known duty cycle imbalance, and then measuring the output frequency and jitter. REV. A -5- AD6816 AD6816-Typical Characteristic Curves 50 45 OUTPUT CURRENT - mA 40 35 OUTPUT 30 223-1 PRN INPUT 25 20 2 OC-3/STV1 MASK 15 10 5 644ps/div 29.49ns 0 0 1 2 3 4 5 6 RTXAMPSET - k 7 8 9 35.93ns 10 Figure 3. Line Driver Output Current vs. RTXAMPSET Figure 6. Line Driver Eye Diagram (Measurement at XFMR Output) 0 45 223 -1 PRN INPUT 40 R = 2.32k -10 35 -20 MAGNITUDE - dB I OUT - mA 30 25 20 R = 1.51k 15 -40 -50 -60 10 R = 536 -70 5 0 -30 0 10 20 30 40 50 TEMPERATURE - C 60 -80 10.0E+3 70 Figure 4. Line Driver Output Current vs. Temperature 100.0E+3 1.0E+6 10.0E+6 FREQUENCY - Hz 100.0E+6 1.0E+9 Figure 7. Line Driver Output Frequency Spectrum (Measurement at XFMR Output) -20 155Mb/s NRZ CAT5 CMT's FREQUENCY SYNTHESIZER OUTPUT PHASE NOISE (DCFM METHOD) -40 CLASS B LIMIT LINE, PEAK HOLD HEIGHT SCAN H AND V 0 AND 90 DEG WRT ANTENNA CAT 5 WALL JACK 10 dB/ POS PK L(f) - dBc/Hz -60 OFFSET -10.0 dB OSCILLATOR OUTPUT PHASE NOISE (EFC METHOD) -80 -100 -120 1E+07 1E+06 1E+05 1E+04 1E+03 1E+02 1E+01 -140 1E+00 NOISE FLOOR (EFC VCO TUNING METHOD) START 30 MHz RES BW 1 MHz STOP 300 MHz VBW 1 MHz SWP 200 ms FREQUENCY - Hz Figure 8. UTP #5 Emissions & FCC Class B Limit Line Figure 5. Oscillator Circuit and Frequency Synthesizer Phase Noise -6- REV. A AD6816 1000 2.5 100 OUTPUT JITTER - Degrees rms JITTER TOLERANCE - UI 2.4 AD6816 10 1 OC-3/STM1 JITTER TOLERANCE MASK 2.3 2.2 2.1 2.0 JITTER - Degrees rms 1.9 1.8 1.7 1.6 0.1 1.5 1 10 100 1k 10k 100k FREQUENCY - Hz 10M 1M 0 20 40 60 80 CABLE LENGTH - M 100 120 Figure 12. Receive Channel Output Jitter vs. Cable Length (Measured at RXCLKOUT/N) Figure 9. Clock Recovery PLL Jitter Tolerance 1.025 1.020 OUTPUT VOLTAGE - V (Normalized) PEAK 0.12 0.08 0.06 0.04 0.02dB/DIV CCR 0.1 0.15 0.22 0.33 1.015 1.010 1.005 0.995 0.990 0.985 0.980 10 100 1k FREQUENCY - kHz 10k NORMALIZED DRIVER OUTPUT LEVEL 1.000 20k 0 10 20 30 50 40 TEMPERATURE - C 60 70 Figure 13. Driver Output Level vs. Temperature (Normalized to 1 V @ +25C) Figure 10. Clock Recovery Jitter Transfer vs. CCR 50 0.3 CLOCK RECOVERY OUTPUT JITTER - ps rms 0.35 100 METER JITTER - UI p-p 0.25 50 METER 0.2 0.15 30 METER 10 METER 0.1 0.05 45 40 35 25 20 15 10 5 0 0.6 0 0.7 0.75 0.8 0.85 0.9 0.95 1 1.05 1.1 TRANSMIT AMPLITUDE - Volts p-p 1.15 1.2 Figure 11. Equalize Jitter vs. Transmit Amplitude REV. A JITTER 30 0.7 0.8 1.3 0.9 1.0 1.1 1.2 TRANSMIT AMPLITUDE - V p-p 1.4 1.5 Figure 14. Receive Channel Output Jitter vs. Transmit Amplitude (2E7-1 PRN Data Input into 100 M UTP#5 Cable) -7- AD6816 Frequency Synthesizer PLL and Clock Recovery PLL Differential Output Stage TXCLKOUT/TXCLKOUTN, RXCLKOUT/RXCLKOUTN, RXDATAOUT/RXDATAOUTN VAP1 Receiver Differential Input Stage 14k 14k VDPECL1 OR VDPCEL2 RX 450 RXN 70A 450 70A VAN1 DIFFERENTIAL OUTPUT VAP1 IOH 2.5mA Receiver Signal Detect Output (SDOUT) VEE 150 Oscillator Circuit OSC OUT SDOUT 150 VDP2 IOL IOH NOTE: PROVIDE NO CONNECTION TO XTALIN1 AND XTALIN2 IF NOT USING THE OSCILLATOR VAN1 Control Signal Input (LBSEL, DRBYPASS, TXSALVESEL,DRVROFF) 20 OSCOUT 20 IOL VDP# 2 x ITTL 2 x ITTL 80A OR 0A 80A OR 0A VDN2 Line Driver DRIVEIN/DRIVEINN +5V 600A 2k 500 10k 10k 100A 20k VDN# DRIVEIN 33 Frequency Synthesizer ECLFREFIN/ECLFREFINN PECL Input (FREFIN @ VEE) VIL_MIN = 3 * VBE + 0.18 = 2.6V DRIVEINN 32 TO TX OUT 0.18V 300 300 15k 15k VDP1 3.75k 3.75k ITTL= 0mA ITTL Line Driver TXAMPSET Output Current Control 500 500 BIAS OUTPUT CURRENT TXAMPSET 80A + 40A 1.2V BANDGAP REFERENCE VDN1 RTXAMPSET EXTERNAL - VDN3 Frequency Synthesizer FREFIN TTL/CMOS Input (ECLFREFIN & ECLFREFINN @ VEE) ITTL TX Line Driver TX/TXN Output VDP1 ITTL= 80mA 2k TXN VOL_MIN = 3*VBE + 0.18V 2.6V FROM DRIVEN 500 VDN3 VDN1 Figure 15. Simplified Schematics -8- REV. A AD6816 RX/RXN DATA INPUT THEORY OF OPERATION Line Driver The line driver accepts differential input data between 100 mV and 1.0 V peak (ac coupled or ECL common mode), and transmits the 155 Mbps NRZ data signal through a transformer and up to 110 M of Category #5 Unshielded Twisted Pair cable (UTP#5) per ATM Forum UNI 3.1 requirements. The user sets output current, IOUT, between 4 mA and 40 mA (cable removed and 100 resistor across transformer) with a single external resistor. A 1.0 V p-p output signal is obtained with an IOUT of 20 mA, corresponding to an RTXAMPSET = 1114 . Generally, IOUT = 22.3 / RTXAMPSET. The line driver does not share any power supplies or biases with other blocks of the AD6816. This, and techniques used to stabilize the effective beta of transistors during switching, keeps output common mode current to < 3%. Synthesizer Phase-Locked Loop The synthesizer PLL provides a 155 MHz PECL output clock from a 19.44 MHz or 9.72 MHz reference frequency. The synthesizer PLL automatically selects x8 or x16 synthesis, based on the frequency present at FREFIN(N) pins. A signal multiplexer at the synthesizer PLL input allows the user to select a 19.44 MHz reference frequency derived from the 155.52 MHz recovered clock (loop timing application) or an independent reference frequency. The device can be configured to support a PECL/TTL/CMOS-level reference frequency. The synthesizer PLL gives phase continuous switching between independent and loop timing. The 200 kHz time constant of the PLL smooths the clock output response due to an instantaneous change in frequency at its input (as in the case of a switch between loop timing and independent timing). This guarantees no runt clock pulses due to switching timing references. Receiver (Equalizer, Baseline Restoration and Loss of Signal Detect Circuits) The Receiver processes an NRZ data stream from a transformer and up to 110 M of Category #5 Unshielded Twisted Pair cable (UTP#5). The receiver (Figure 16) consists of an adaptive equalizer, a baseline restore loop and a loss of signal (LOS) detector. The adaptive equalizer compensates for intersymbol interference and distortion caused by the cable. The baseline restore loop corrects for base line wander due to the transformer. The LOS detector indicates a cable break. The incoming data chooses either the high pass path, shown as E(s), the straight path or some combination of both. The strength of each path is determined by the control variable, x. The loop works by comparing the amplitude of the equalizer output to the expected value. If the amplitude is too small, the signal is underequalized and the control variable x is decreased to choose more of the high pass path. The signal is equalized when the output amplitude equals the reference value. The time constant of the loop is slow enough so that the equalization remains constant if the signal amplitude decreases due to the absence of transitions. REV. A X ADAPTIVE EQUALIZER TO CLOCK RECOVER PLL A COMP X 1-X AMPLITUDE DETECTOR X LOW PASS FILTER BASELINE RESTORE LOOP SDOUT (LOS) REFERENCE LOW PASS FILTER LOW PASS FILTER THRESHOLD COMP LOS DETECTOR INTEGRATOR /ZERO Figure 16. Receiver (Equalizer, Baseline Restoration, Signal Level Detect) Block Diagram Crystal Oscillator The oscillator circuit works with a 19.44 MHz 50 ppm series mode crystal to provide a TTL level 19.44 MHz 100 ppm clock output without needing adjustment. Start-up is guaranteed for crystals with series mode resistance < 40 . Typical start-up time for a crystal with series mode resistance is 2 ms. Power in the crystal is limited to 1 W rms. E(s) HIGH PASS FILTER The baseline restore loop also compensates for the baseline wander caused by the transformer (ac coupling) used to terminate the cable. This loop adjusts the slice level of the data signal for lengthy transitionless data runs to ensure that no bit errors are made upon new transitions. This loop also compensates for a dc offset that could be created by the transformer processing non- 50% duty cycle, repetitive data patterns (baseline wander). The circuit works by subtracting the comparator input signal from the output signal. The error signal output of the subtracter is added to offset the incoming signal and to keep the average value equal to the average output. If the equalizer output goes to zero, this loop will servo the comparator input to the last logic level. The LOS detector monitors the output amplitude of the equalizer and trips when it falls below a predetermined threshold. The low-pass filter is slow enough that the detector will not trip for less than 800 missing edges. Clock Recovery Phase-Locked Loop The phase-locked loop recovers clock and retimes data from NRZ data. The architecture uses a frequency detector to aid initial frequency acquisition; refer to Figure 17 for a block diagram. Note that the frequency detector is always in the circuit. When the PLL is locked, the frequency error is zero and the frequency detector has no further effect. Since the frequency detector is always in the circuit, no control functions are needed to initiate acquisition or change mode after acquisition. The frequency detector delivers pulses of current to the charge pump to either raise or lower the frequency of the VCO. During the frequency acquisition process the frequency detector output is a series of pulses of width equal to the period of the VCO. These pulses occur on the cycle slips between the data frequency and the VCO frequency. With a maximum density data pattern (1010. . . ), every cycle slip will produce a pulse at the frequency detector output. With random data, however, not every cycle slip produces a pulse. The density of pulses at the frequency detector output increases with the density of data transitions. The probability that a cycle slip will produce a pulse increases as the frequency error approaches zero. After the frequency error has been reduced to zero, the frequency detector output will have no further pulses. At this point the PLL begins the process of phase acquisition, with a settling time of roughly 2000 bit periods. -9- AD6816 FROM EQUALIZER AND ZERO RESTORATION DET APPLICATIONS 1 s s +1 Application with Fiber Optic Receivers/Transceivers The AD6816 receiver (adaptive equalizer and baseline restore loop) can be configured to receive a signal from a fiber optic receiver or transceiver that provides full PECL or ECL outputs. By properly adjusting the common mode and amplitude level, the AD6816 receiver will be essentially transparent to the (P)ECL inputs. The common-mode input voltage should be between 1.5 V and 1.9 V referred to VCC. The differential input amplitude should be between 0.7 V and 1.1 V. The commonmode issue can be addressed simply by ac coupling. The amplitude of the (P)ECL signal should be attenuated by two to meet the above requirement. Figure 18 provides a simple solution that satisfies the above requirements as well as providing proper 50 terminations for transmission lines when needed. The circuit also allows a convenient way to double pad a PC board for either fiber or copper cable applications. VCO FDET RECOVERED CLOCK OUTPUT RETIMED DATA OUTPUT RETIMING DEVICE Figure 17. PLL Block Diagram Jitter caused by variations of density of data transitions (pattern jitter) is virtually eliminated by use of a new phase detector (patented). Briefly, the measurement of zero phase error does not cause the VCO phase to increase to above the average run rate set by the data frequency. The jitter created by a 27-1 pseudo random code is 1/2 degree; this is small compared to random jitter. The jitter bandwidth for the PLL is 0.07% of the center frequency. This figure is chosen so that sinusoidal input jitter at 110 kHz will be attenuated by 3 dB. The damping ratio of the PLL is user programmable with a single external capacitor. At 155 MHz, a damping ratio of 5 is obtained with a 0.15 F capacitor. More generally, the damping ratio scales as (fDATA x CD)1/2. A lower damping ratio allows a faster frequency acquisition; generally the acquisition time scales directly with the capacitor value. However, at damping ratios approaching one, the acquisition time no longer scales directly with capacitor value. The acquisition time has two components: frequency acquisition and phase acquisition. The frequency acquisition always scales with capacitance, but the phase acquisition is set by the loop bandwidth of the PLL and is independent of the damping ratio. Thus, the 0.07% fractional loop bandwidth sets a minimum acquisition time of 2000 bit periods. Note the acquisition time for a damping factor of one 15,000 bit periods. This comprises 13,000 bit periods for frequency acquisition and 2,000 bit periods for phase acquisition. Compare this to the 400,000 bit periods acquisition time for a damping ratio of 5; this consists entirely of frequency acquisition, and the 2,000 bit periods of phase acquisition is negligible. R1 0 RD 16 PULSE PE-68517 RD MAGNETICS 15 HP HFBR5205 OPTICAL TRANSCEIVER 43 RX R3 100 R2 0 44 RXN C1 10nF RD R4 50 RD R5 50 APPLICATION R6 270 R7 270 AD6816 C2 10nF UTP DISMOUNT CAPACITORS C1 AND C2, MOUNT 0 RESISTORS R1 AND R2. OPTICAL DISCONNECT 0 RESISTORS R1 AND R2, MOUNT CAPACITORS C1 AND C2. Figure 18. Fiber Optic Receiver PECL/ECL Output Interface to AD6816 Receiver Schematic Generation of 19.44 MHz TTL-Level Byte Clock from 155.52 MHz Recovered Clock Some applications require that a local master clock at 19.44 MHz be generated from the 155.52 MHz recovered clock. Figure 19 shows a circuit schematic for such an application. The circuit uses one ECL (PECL) IC to divide the recovered 155 MHz clock by eight, and one ECL/TTL converter IC to deliver the 19.44 MHz TTL output. While a lower damping ratio affords faster acquisition, it also allows more peaking in the jitter transfer response (jitter peaking). For example, with a damping ratio of 10 the jitter peaking is 0.02 dB, but with a damping ratio of 1, the peaking is 2 dB. 19.44 MHz TTL CLOCK +5V +5V R4 130 5 IN NC MC GND C2 0.1F IN VCC SW OUT 1 2 3 4 C3 0.1F +5V 14 13 COUT CIN CIN 1 ECL VCC 2 AOUT 3 AIN 4 AIN Z2 DIN 11 MC10H350 ECL TO TTL DOUT 10 TRANSLATOR +5V C4 0.1F R5 80 +5V R6 130 RXCLKOUT DIVIDED BY 8 C5 0.1F R7 80 DIN 12 GND 6 15 BOUT 7 16 BIN RCLKOUT (AD6816 PIN 10) 8 Z1 MC12026A or B 1.1 GHz MODULATOR PRESCALAR +5V R3 80 +5V TTL VCC R2 130 C7 0.1F C6 0.1F C1 0.1F BIN RCLKOUTN (AD6816 PIN 11) R1 80 5 6 7 8 OE 9 R8 130 Figure 19. Generation of 19.44 MHz TTL-Level Byte Clock from 155.52 MHz Recovered Clock-Circuit Schematic -10- REV. A AD6816 PECL Output Compatibility with ATM User-Network Interface IC Inputs The PECL outputs (RXCLKOUT/N, RXDATAOUT/N) are more than adequate for driving UNI IC PECL inputs. A focus on PECL output specifications and on UNI IC PECL input dc characteristics, given below, demonstrates this. Typical UNI ICs have VIH MIN and VIL MAX dc specifications that require differential drive (VIH MIN-VIL MAX) > 0.4 V. One UNI IC has VIH MIN and VIL MAX specifications that require differential drive > 0.6 V. The AD6816 PECL outputs have the differential swing (0.72 V minimum) to drive these UNI ICs comfortably, and with adequate margin. The PECL output levels, specified in single-ended terms over 0C to +70C (VOH and VOL), should not be taken at face value. Since the output signals that VOH and VOL refer to are differentially processed (typical UNI IC "self-biased" PECL Inputs require ac coupling), the differential voltage swing between VOH and VOL determine compatibility. Simply combining the VOH MIN specification with the VOL MAX specification, however, confuses a compatibility analysis since both VOH and VOL track with temperature. This means VOH MIN and VOL MAX do not occur simultaneously, but at opposite temperature extremes (refer to Figure 20). Note that the differential voltage swing (VOH-VOL) remains > 0.93 V over temperature. 0 -0.2 -0.4 VOH VOLTAGE - V -0.6 VOH MIN -0.8 -1.0 -1.2 0.94V 0.93V -1.4 VOL -1.6 -1.8 Test results of identical PECL outputs over temperature reveal that minimum differential voltage swings at -40C and at +85C equal 0.72 V and 0.81 V, respectively (with 6 confidence). -2.0 -60 VOL MAX -40 -20 0 20 40 60 80 TEMPERATURE - C 100 120 140 Figure 20. PECL Output Levels-Simulation Graph Figure 21. Evaluation/Test Circuit Assembly Drawing REV. A -11- IN007 IN002 IN001 1 TP2 IN003 IN005 5 2 IN006 6 3 IN007 7 IN004 IN008 R3 50 TP1 50 MATCHED R4 50 R2 50 R1 50 50 MATCHED IN008 8 1 2 3 IN006 4 IN005 5 IN004 6 IN003 7 8 J1 TOP 4 RJ45 J1 RJ45 IN002 IN001 +5V C20 10F R6 50 R5 50 C1 0.1F R8 75 R7 75 J17 J16 J15 J14 C5 0.1F 1 3 1 3 1 3 1 3 14 15 10 16 13 12 1 2 9 +5V U1 68517 3 11 6 8 7 5 4 C3 0.1F R10 50 C4 0.1F 2 R11 100 50 MATCHED SW4 2 SW3 2 SW2 2 SW1 C2 0.1F R9 50 +5V +5V 44 43 42 41 40 39 38 37 36 35 34 LED 50 MATCHED R12 1.1k VDP3 TXST RX RX 1 3 C30 0.1F 2 CRBYPAS LOOPSEL CLKSEL DRVOFF TXN TX R16 130 R14 80 CR1 19.44MHz +5V 33 32 31 30 29 28 27 26 25 24 23 VDN R15 130 R13 80 VAN2 CEQ1 C31 0.1F +5V 5 6 7 U2 AD6816 C29 0.1F 4 CRYS2 CEQ2 +5V VDP2 VA 50 MATCHED C27 0.1F C28 0.1F VDD CRDATA CRDATA VDN1 VDPECL SYNCLK SYNCLK VDP1 CSYN1 12 13 14 15 16 17 18 19 20 21 22 +5V C6 0.1F CSYN2 9 10 11 +5V 8 VDP4 2. THIS SCHEMATIC HAS INCORRECT MNEMONICS AT AD6816 PINS 37 AND 38, AND AT PINS 32 AND 33. SEE PIN CONFIGURATION, PIN DESCRIPTION AND FIGURES 28 AND 29 CORRECT DESCRIPTION. CRYS1 C_CR1 DRVIN SDOUT VDN2 C_CR2 DRVIN VAN1 OSC VAP1 SYNECL NOTES: 1. PECL OUTPUTS ARE BACK TERMINATED ON EVALUATION BOARD SYNCMOS VDN4 SYNECL CRCLK -12- CRCLK C11 0.1F R35 154 R31 154 C26 0.1F +5V +5V C16 0.1F 1 3 R19 80 R34 69.8 R29 154 R18 130 R20 80 R38 154 C19 0.1F +5V R33 150 R32 150 R36 150 +5V +5V R27 150 R24 150 +5V +5V R21 150 +5V R39 50 C17 0.1F C18 0.1F R25 69.8 R37 69.8 R28 69.8 R23 154 R22 69.8 50 MATCHED C13 0.1F R30 69.8 +5V R17 130 R26 154 50 MATCHED C25 0.1F +5V C12 0.0047F SW5 2 C24 0.1F C23 0.1F C22 0.1F C21 0.1F C15 0.1F C14 0.1F C10 0.1F C9 0.1F C8 0.1F C7 0.1F J13 J12 J11 J10 J9 J8 J7 J6 J5 J4 J3 J2 CRCLK CRCLK CRDATA CRDATA SYNCLK SYNCLK SYNECL SYNECL SYNCMOS OSC DRVIN DRVIN AD6816 Figure 22. Evaluation/Test Circuit Schematic REV. A AD6816 Figure 23. Evaluation/Test Circuit PCB Layer 1 Signal Traces Figure 24. Evaluation/Test Circuit PCB Layer Three Power Plane REV. A -13- AD6816 0.1F CHIP CAP 50 50 27 VDP2 28 VDN2 34 VDN3 31 VAN2 0.1F CHIP CAP VAP2 35 TXAMPSET VDP1 1 2 PULSE PE-68517 MAGNETICS 0.1F CHIP CAP 36 19 VDP3 0.1F CHIP CAP 0.1F CHIP CAP AD6816 VDPECL2 16 0.1F CHIP CAP 2 7 VDN4 VDP4 VAN1 VDN1 15 VAP1 3 22 R12 1.1k VDPECL1 12 0.1F CHIP CAP 9 8 0.1F CHIP CAP +5V 10F TO PECL TERMINATION OF CLOCK AND DATA OUTPUTS NOTES: (1) ALL GROUNDS TIED TO GROUND PLANE. (2) CONNECT ALL VCC TRACES AS SHOWN. (3) CONNECT ALL BYPASS CAPS AS CLOSE TO AD6816 AS POSSIBLE. (4) CONNECT R12 AS CLOSE AS POSSIBLE TO AD6816 Figure 25. Power and Ground Recommendations -14- REV. A AD6816 Using the AD6816 to Interface ATM to Optical and Electrical Media: Examples Example 1: ATM UNI PHY Layer(s) Using AD6816 & IgT WAC-013 (or IgT WAC-413) The following system implementation examples show how to implement a 155 Mbps ATM User Network Interface (UNI) to Category #5 Unshielded Twisted Pair cable (UTP#5) using the AD6816 and either the IgT WAC-013 ATM UNI Processor (single channel) or the IgT WAC-413 Quad ATM UNI Processor (four channels). Contact Integrated Telecom Technology (IgT), Gaithersburg, MD, US, (301)990-9890, for information on the WAC-013 or WAC-413 devices beyond that provided below. Figures 26 and 27 show generic block diagrams of the single channel and four channel ATM PHY interface circuit. The ATM PHY interface circuit is made up of a Physical Medium Dependent (PMD) block and a Transmission Convergence (TC) block. The PMD interface block provides the digital baseband communication between ATM user devices and ATM network equipment. The TC block interfaces with the PHY layer aspects that are independent of the transmission medium characteristics. The PMD blocks for these applications use the AD6816 which provides the UTP#5 line interface (Tx: Line Driver, Rx: Equalizer & Baseline Restoration) and provides an interface to the TC Layer (Tx: 155 MHz Transmit Clock, Rx: 155 MHz Recovered Clock and 155 Mbps Retimed Data). The TC block for these applications use the IgT WAC-013 (single channel) or the IgT WAC-413 (four channel). These devices process and generate ATM cells over SONET/ SDH frames. TRANSMISSION CONVERGENCE (TC) BLOCK PHYSICAL MEDIUM DEPENDENT (PMD) INTERFACE BLOCK UTP#5 CONNECTOR AD6816 TRANSFORMER AND FILTER 155Mbps UTP#5 INTERFACE LOCAL BUS IgT* WAC-013 155Mbps SONET ATM UNI PROCESSOR RX UTOPIA TX UTOPIA *NOTE: MANUFACTURER'S DATA SHEET IS SUBJECT TO CHANGE. CONFIRM SPECIFICATIONS BEFORE USING THIS DEVICE. Figure 26. Single Channel ATM PHY Block Diagram (AD6816 with IgT WAC-013) PHYSICAL MEDIUM DEPENDENT (PMD) INTERFACE BLOCK UTP#5 CONNECTOR UTP#5 CONNECTOR UTP#5 CONNECTOR UTP#5 CONNECTOR TRANSFORMER AND FILTER TRANSFORMER AND FILTER TRANSFORMER AND FILTER TRANSMISSION CONVERGENCE (TC) BLOCK AD6816 155Mbps UTP#5 INTERFACE LOCAL BUS AD6816 155Mbps UTP#5 INTERFACE AD6816 155Mbps UTP#5 INTERFACE IgT* WAC-413 155Mbps SONET ATM UNI PROCESSOR RX UTOPIA TX UTOPIA AD6816 TRANSFORMER AND FILTER 155Mbps UTP#5 INTERFACE *NOTE: MANUFACTURER'S DATA SHEET IS SUBJECT TO CHANGE. CONFIRM SPECIFICATIONS BEFORE USING THIS DEVICE. Figure 27. Four Channel ATM PHY Block Diagram (AD6816 with IgT WAC-413) REV. A -15- AD6816 Single Channel ATM UNI PHY In the receive section, the NRZ data enters the RJ45 connector and passes through an isolation transformer and band-limiting filter. The adaptive equalizer in the AD6816 compensates for the amplitude and phase distortion incurred from up to 110M UTP#5. The AD6816 baseline restoration loop compensates for the dc wander that the transformer introduces to its input data. Once the signal has been equalized and had its dc level restored, the AD6816 recovers clock and retimes data. The AD6816 differential recovered clock signal and retimed differential data are fed directly to the WAC-013. Figure 28 shows a more detailed block diagram of the single channel application. The AD6816 provides the WAC-013 with a 155 MHz Tx clock at PECL levels. The WAC-013 processes 155 Mbps Tx data directly from this 155 MHz clock. The WAC-013 generates 155 Mbps differential NRZ data at CMOS levels. These differential data output signals data are PECLlevel translated using the 3-resistor network (refer to Figure 25). The AD6816 processes the NRZ data through its line driver. The line driver output data is processed through an external lowpass filter and transformer before entering the RJ45 connector. +5V 7 255 50 DRIVEINN 32 TX- 8 38 TXN 2 7 +5V 97 TS_SER_DATA +5V 68 37 TX 1 8 200 DRIVEIN 33 50 TX+ 68 +5V +5V PULSE PE68517* RJ45* 200 98 TS_SER_DATA- 255 100 +5V 3 9 RX+ 1 TXCLKOUT 17 43 RX 16 AD6816 10 2 +5V 44 RXN 15 +5V 94 TS_SER_CLK+ 100 TXCLKOUTN 18 100 RX- 150 IgT* WAC-013 155Mbps SONET ATM UNI PROCESSOR 93 TS_SER_CLK- 150 100 RXDATAOUT 13 CONTACT ASSIGNMENT 6 87 5 CONTACT # 2 43 1 2 3 4 5 6 7 8 1 150 ATM NETWORK EQUIPMENT 76 RS_SER_DATA+ 100 RXDATAOUTN 14 RECEIVE+ RECEIVE- NOTE 1 NOTE 1 NOTE 1 NOTE 1 TRANSMIT+ TRANSMIT- JACK +5V +5V 75 RS_SER_DATA- 150 100 RXCLKOUT 10 150 +5V 79 RS_SER_CLK+ 100 RXCLKOUTN 11 78 RS_SER_CLK- 150 *NOTE: MANUFACTURER'S DATA SHEET IS SUBJECT TO CHANGE. CONFIRM SPECIFICATIONS BEFORE USING THIS DEVICE. Figure 28. UTP#5 Application with IgT WAC-013 IgT* WAC-413 QUAD 155Mbps SONET ATM UNI PROCESSOR (1/4) +5V +5V PULSE PE68517* RJ45* 50 50 7 8 1 37 TX TX- 8 7 2 38 TXN RX+ 1 9 +5V 2 10 TXCLKOUT/N 5V PECL TO 3.3V PECL (SEE FIG 30) TX_SER_CLK+/- RXDATAOUTN 5V PECL TO 3.3V PECL (SEE FIG 30) RX_SER_DATA+/- RXCLKOUTN 5V PECL TO 3.3V PECL (SEE FIG 30) RX_SER_CLK+/- 43 RX 16 100 RX- TX_SER_DATA+/- AD6816 TX+ 3 3.3V PECL TO 5V PECL (SEE FIG 31) DRIVEIN/N 44 RXN 15 SDOUT LOCK *NOTE: MANUFACTURER'S DATA SHEET IS SUBJECT TO CHANGE. CONFIRM SPECIFICATIONS BEFORE USING THIS DEVICE. Figure 29. UTP#5 Application with IgT WAC-413 -16- REV. A AD6816 In the receive section, the NRZ data enters the RJ45 connector and passes through an isolation transformer and band-limiting filter. The adaptive equalizer in the AD6816 compensates for the amplitude and phase distortion incurred from up to 110M UTP#5. The AD6816 baseline restoration loop compensates for the dc wander that the transformer introduces to its input data. Once the signal has been equalized and had its dc level restored, the AD6816 recovers clock and retimes data. The AD6816 produces a 5 V PECL differential recovered clock signal and a 5 V PECL retimed differential data signal that get level shifted using a three resistor network (Figure 30) to drive the WAC-413 RX_SER_CLK and RX_SER_DATA inputs, respectively. Four-Channel ATM UNI PHY Figure 29 shows a block diagram of the AD6816 and one channel of the IgT WAC-413 Quad ATM UNI Processor. The AD6816 provides the WAC-413 with a 155 MHz Tx clock at 5 V PECL levels. The 5 V PECL levels are level-shifted using a 3-resistor network (Figure 30) to drive the WAC-413 TX_SER_CLK inputs. The WAC-413 processes 155 Mbps data directly from this 155 MHz clock. The WAC-413 generates 155 Mbps differential NRZ data at 3.3 V PECL levels. The 3.3 V PECL signals are level-shifted to 5 V PECL using a 3-resistor network (Figure 31) to drive the AD6816 line driver. The AD6816 processes the NRZ data through its line driver. The line driver output data is processed through an external low-pass filter and transformer before entering the RJ45 connector. FERRITE BEAD PECL 5V (1/4) +5V AD6816 0.01F 91 TXCLKOUT RXDATAOUT RXCLKOUT TRANSMISSION LINE (50 PCB TRACE) TXCLKOUTN RXDATAOUTN RXCLKOUTN 91 IgT WAC-413 QUAD 155Mbps SONET ATM UNI PROCESSOR 51 TX_SER_CLK+ RX_SER_DATA+ RX_SER_CLK+ NOTE: TO ENSURE PROPER IMPEDANCE MATCHING, ALL COMPONENTS SHOULD BE PLACED AS CLOSE TO THE WAC-413 DESTINATION PINS AS POSSIBLE. 51 62 62 TX_SER_CLK- RX_SER_DATA- RX_SER_CLK- Figure 30. AD6816 5 V PECL to WAC-413 3.3 V PECL Resistor Network FERRITE BEAD PECL 5V +5V 0.01F 100 100 DRIVEIN 51 DRIVEINN TS_SER_DATA+ TRANSMISSION LINE (50 PCB TRACE) 51 TS_SER_DATA- (1/4) IgT WAC-413 QUAD 155Mbps SONET ATM UNI PROCESSOR 75 NOTE: TO ENSURE PROPER IMPEDANCE MATCHING, ALL COMPONENTS SHOULD BE PLACED AS CLOSE TO THE WAC-413 DESTINATION PINS AS POSSIBLE. 75 AD6816 Figure 31. WAC-413 3.3 V PECL to AD6816 5 V PECL Resistor Network REV. A -17- AD6816 Using these equations, and rounding the resistor values to the nearest standard 5% resistors, results in the circuit of Figure 31. This circuit will result in a source voltage swing between 1.66 V and 2.4 V and a destination voltage swing between 2.79 V and 3.28 V. This exceeds the minimum required voltage swing, with plenty of margin. 5 V PECL to 3.3 V PECL Interface Analysis The following three equations must be satisfied for this interface (in the following example: RH = Resistor connected to PECL 5 V, RM = Resistor connected between termination line and destination pin, and RL = Resistor connected to ground): 1. Termination Impedance must match trace impedance: 4. Also, the current required by the driver must be less than 17 mA: Termination impedance = (RH x (RM + RL))/ (RH + RM + RL) = 50 . IDRIVE = (2.4/RL) - [(5 - VTERM_DESTINATION_HIGH)/RH 2. Resistors need to provide the correct voltage levels: In this case, the current of the driver is 15 mA. (VSOURCE - VTERM_DESTINATION)/RM = VTERM_DESTINATION)/RL, Example 2: 155 Mbps NIC (Fiber or UTP#5) Using AD6816 & Siemens* ATM Chip Set where VSOURCE = 3.67 V (PECL 5 V midpoint) and VTERM_DESTINATION = 2.0 V PECL 3.3 V midpoint). The following circuit implementation example shows how to implement a 155 Mbps ATM Network Interface Card (NIC) to Fiber Optics or to Category #5 Unshielded Twisted Pair cable (UTP#5) using the AD6816 with the Siemens PXB 4240 Synchronous Digital Hierarchy Transceiver IC (SDHT) and the PXB 4110 Segmentation and Reassembly Element IC (SARE). Contact Siemens Semiconductor, Dusseldorf, Germany, (49) 203 74201 45 for information on the NIC implementation or PXB 4240/PXB 4110 chipset beyond the information provided below. 3. Desired driver current of 25 mA: IDRIVE = [(4 - VDEST_HIGH)/RM] - [(5-4)/RH], where VDEST_HIGH = (4 x RL)/(RM + RL) and IDRIVE = 0.025. The midpoints are used to ensure that the waveforms are centered at the critical levels. The waveform is attenuated at the destination because of the voltage divider. Rounding the resistor values to the nearest standard 5% resistors results in the circuit of Figure 30. A 3.2 V to 4.0 V input swing into this circuit creates an output swing between 1.8 V and 2.2 V. AD6816 Interface to Fiber or to UTP#5 3.3 V PECL to 5 V PECL Interface Analysis The common-mode rejection area of the AD6816 line driver input requires the input signal voltage swing to be above 2.6 V. This is lower than standard PECL and helps simplify the termination resistor network (less driver current is required). In the following example: RH = Resistor connected to PECL 5 V, RM = Resistor connected between termination line and destination pin, and RL = Resistor connected to ground). The following three equations need to be satisfied for this interface: 1. The voltage swings need to be centered at the correct voltage levels: (5 - VMID_DESTINATION)/RH = (VMID_DESTINATION - VMID_SOURCE)/RM, where VMID_DESTINATION = 3.0 V and VMID_SOURCE = 2.0 V. 2. Termination Impedance must match trace impedance: Termination impedance = (RL x (RM + RH ))/ (RH + RM + RL) = 50 . 3. The voltage for the driver should be within 5% of 1.7 V for the proper swing: VSOURCE = (5 x RL)/(RH + RM + RL), where VSOURCE = 1.7 V. The NIC is designed to interface to either Fiber (via a 1 x 9 Fiber Optic Transceiver) or to UTP#5 (via transformer assembly and RJ45 connector). The unused interface is disconnected by jumpers. AD6816 Interface to Siemens SDHT The AD6816 delivers both recovered clock (associated with the receive data) and transmit clock to the SDHT. The AD6816 recovers the receive clock from the data coming in via the fiber or the UTP#5 and generates the local clock from a 19.44 MHz quartz. The AD6816 provides the ability to create the local 155 MHz clock (system clock) from either the 19.44 MHz crystal, an 19.44 MHz PECL- or TTL-level signal, or the 155 MHz recovered clock. The AD6816 high speed signal inputs and outputs operate at PECL levels. The Siemens SDHT is a 3.3 V CMOS device that uses IEEE LVDS levels (Low Voltage Differential Signal) for its high speed signal inputs and outputs. Refer to the paragraphs below and to Figures 33 and 34 for the description of the interface between the AD6816 and the Siemens SDHT IC. SDHT/SARE/PCI Bus Interfaces Interfacing to the PCI bus does not require any external components. Nor do the two UTOPIA interfaces between SARE and SDHT. SARE is master and drives the ATMCLK. The connection of the SDHT to the SARE's Local Bus Interface needs a piece of glue logic to adapt bus cycles. *All trademarks are properties of their respective holders. -18- REV. A AD6816 SIEMENS PXB 4240 SDHT SIEMENS PXB 4110 SARE AD6816 LOCAL BUS 155Mbps UTP#5 INTERFACE IC TRANSMIT CLOCK CLOCK GENERATOR RX UTOPIA TRANSMIT CLOCK UTP#5 CONNECTOR TX: LINE DRIVER TRANSFORMER AND FILTER RECEIVE CLOCK RX: EQUALIZER BASELINE RESTORATION CLOCK RECOVERY OPTICAL TRANSCEIVER MODULE SONET/ SDH FRAMING RECEIVE DATA SEGMENTATION SDH REASSEMBLY PCI BUS TX UTOPIA TRANSMIT DATA Figure 32. NIC Block Diagram: AD6816 with Siemens ATM Chipset VCC = +5V VCC = +5V LVDS to PECL Conversion LVDS levels from the Siemens SDHT can be shifted to PECL levels to the AD6816 using capacitive coupling (Figure 33). This scheme assumes the LVDS output drives the "long" portion of the transmission line. The passive shifting and termination network is located as close to the PECL input as possible. 82 100nF DRIVEINN LVDS_OUT SIEMENS SDHT PXB4240 AD6816 DRIVEIN 100 VCC = +5V NOTE: TO ENSURE PROPER IMPEDANCE MATCHING, 160 ALL COMPONENTS SHOULD BE PLACED AS CLOSE TO THE AD6816 DESTINATION PINS AS 470 POSSIBLE. 1k 1k 100nF LVDS_IN PECL_OUT 100nF TRANSMISSION LINE (50 PCB TRACE) 100nF LVDS_IN TRANSMISSION LINE (50 PCB TRACE) 120 LVDS_OUT 82 PECL_OUT AD6816 120 NOTE: TO ENSURE PROPER IMPEDANCE MATCHING, ALL COMPONENTS SHOULD BE PLACED AS CLOSE TO THE AD6816 DESTINATION PINS AS POSSIBLE. VCC = +3.3V 220 120 1k 1k 10nF BRIEF ANALYSIS: 1. TERMINATION IS DONE BY A PARALLEL THEVENIN SCHEME. 2. THE 100nF CAPACITORS PROVIDE AC COUPLING. 3. THE RESISTOR DIVIDER NETWORK FIXES NEW OFFSET VOLTAGE AT 1.2V. 10nF a. BRIEF ANALYSIS: 1. TERMINATION IS DONE BY THE 100 RESISTOR BETWEEN THE DIFFERENTIAL LINES. 2. THE 100nF CAPACITORS PROVIDE AC COUPLING TO THE SDHT OUTPUT. 3. THE RESISTOR DIVIDER GENERATES THE NEW OFFSET VOLTAGE (VBB, IN CENTER BETWEEN PECL VIH VIL) OF APPROXIMATELY 3.7V. 4. THE TWO 1k RESISTORS ARE USED FOR DECOUPLING THE TWO SIGNALS. 5. PECL COMMON-MODE VOLTAGE EXTERNALLY SUPPLIED. COMPONENTS ARE NOT REQUIRED. FERRITE BEAD PECL 5V (VCC) +5V 0.01F 82 82 PECL_OUT TRANSMISSION LINE (50 PCB TRACE) Figure 33. LVDS to PECL Conversion 82 PECL levels from the AD6816 can be shifted to LVDS levels to the Siemens SDHT using either ac coupling or dc coupling (Figures 34a and 34b). These schemes assume that the PECL output drives the "long" portion of the transmission line. The passive shifting and termination network is located as close to the LVDS input as possible. AD6816 SIEMENS SDHT PXB4240 LVDS_IN PECL_OUT PECL to LVDS Conversion NOTE: TO ENSURE PROPER IMPEDANCE MATCHING, ALL COMPONENTS SHOULD BE PLACED AS CLOSE TO THE SDHT DESTINATION PINS AS POSSIBLE. 82 LVDS_IN 47 47 BRIEF ANALYSIS: 1. SHIFTING NETWORK BASED ON THEVENIN SCHEME WITH LOWER RESISTOR REPLACED BY DIVIDER. 2. COMMON MODE VOLTAGE TRANSFORMED FROM 3.7V DOWN TO 1.4V. 3. DIFFERENTIAL VOLTAGE SWING ATTENUATED FROM 600mV MINIMUM (PECL) TO 220mV MINIMUM FOR LVDS. b. Figure 34. PECL to LVDS Conversion REV. A SIEMENS SDHT PXB4240 -19- AD6816 SEQUENCE GENERATOR CSA 907T The AD6816 Evaluation PCB supports error free (< 1 x 10-11 BER) transmission over up to 110M UTP#5 cable or L120 cable. Figures 35, 36, 37 below show the different configurations tested. Table III provides the test results. Note that to properly terminate the L120 cable (120 impedance line), the following resistor changes were made to the PCB: R9 = 60 , R10 = 60 , R11 = 120 . DRIVEINN J9 J9 J3 J4 CRDATA J3 J4 J5 J11 J13 CRCLK CRDATA 5M DRIVERIN JUMPER DRIVERINN CABLE J9 J2 J3 J4 J5 UTP#5 PHYSICAL MEDIUM OR L120 DEPENDENT (PMD) CABLE RJ RJ J1 INTERFACE CARD 45 45 AD6816 4 PAIRS EVALUATION BOARD "USER END" TX: PAIR #1 (1.2) J11 J13 J12 RX: PAIR #4 (7.8) CRDATA CRCLK CRCLKN OSCILLOSCOPE TDS 820 DRIVERINN J5 PHYSICAL MEDIUM DEPENDENT (PMD) INTERFACE CARD J1 AD6816 EVALUATION BOARD "NETWORK END" J11 J2 5M JUMPER CABLE BER ANALYZER CSA 907R DRIVEINN J2 DRIVEIN PHYSICAL MEDIUM DEPENDENT (PMD) INTERFACE CARD J1 AD6816 EVALUATION BOARD "NETWORK END" SEQUENCE GENERATOR CSA 907T DRIVEIN SEQUENCE GENERATOR CSA 907T J13 CRCLK J9 RJ 45 UTP#5 OR L120 CABLE 4 PAIRS 5M JUMPER CABLE BER ANALYZER CSA 907R RJ 45 5M JUMPER CABLE DRIVERIN J2 J3 J4 Figure 36. Configuration Test Block Diagram: Loop-Back with Work Station--End Transmitting Data J5 PHYSICAL MEDIUM DEPENDENT (PMD) J1 INTERFACE CARD AD6816 EVALUATION BOARD "USER END" J11 CRDATA BER ANALYZER CSA 907R C2206a-2-1/97 AD6816 Evaluation PCB Test Results Over UTP#5 Cable and L120 Cable (Foil Twisted Pair) SEQUENCE GENERATOR CSA 907T DRIVEINN J10 CRDATAN J9 TX: PAIR #1 (1.2) RX: PAIR #4 (7.8) SEQUENCE GENERATOR CSA 907T DRIVEIN J2 J3 J4 J5 PHYSICAL MEDIUM DEPENDENT (PMD) INTERFACE CARD J1 AD6816 EVALUATION BOARD "NETWORK END" Figure 35. Configuration Test Block Diagram: Loop-Back J11 J13 CRCLK CRDATA 5M DRIVERIN JUMPER DRIVERINN CABLE J9 J2 J3 J4 J5 UTP#5 PHYSICAL MEDIUM OR L120 DEPENDENT (PMD) CABLE RJ RJ J1 INTERFACE CARD 45 45 AD6816 4 PAIRS EVALUATION BOARD "USER END" TX: PAIR #1 (1.2) J11 J13 RX: PAIR #4 (7.8) CRDATA CRCLK 5M JUMPER CABLE BER ANALYZER CSA 907R OSCILLOSCOPE TDS 820 BER ANALYZER CSA 907R Figure 37. Configuration Test Block Diagram: Dual Simplex Table III. BER vs. UTP#5 & L120 Cable Length UTP#5 (100 V) 145 M Configuration Path(s) Tested 100 M Loop-Back (Figure 32) Tx & Rx < 1.00E-11 Loop-Back with WS Data (Figure 33) Tx Rx Dual Simplex (Figure 34) Tx Rx L120 (120 V) 175 M 150 M 100 M 190M < 1.00E-11 < 1.00E-11 < 1.00E-11 < 1.00E-11 7.50E-06 < 1.00E-11 < 1.00E-11 < 1.00E-11 < 1.00E-11 6.70E-08 < 1.00E-11 < 1.00E-11 < 1.00E-11 < 1.00E-11 < 1.00E-11 1.00E-07 1.00E-10 < 1.00E-11 < 1.00E-11 < 1.00E-11 < 1.00E-11 8.10E-08 < 1.00E-11 < 1.00E-11 < 1.00E-11 < 1.00E-11 < 1.00E-11 2.80E-06 7.00E-10 OUTLINE DIMENSIONS PRINTED IN U.S.A. Dimensions shown in inches and (mm). 44-Pin Thin Quad Flatpack Package (ST-44) 0.063 (1.60) MAX (12.00 0.20) 0.472 (12.00) SQ 0.030 (0.75) 0.018 (0.45) 33 23 34 22 SEATING PLANE (10.0 0.10) 0.394 (10.0) SQ TOP VIEW (PINS DOWN) 44 12 1 0.006 (0.15) 0.002 (0.05) 0.057 (1.45) 0.053 (1.35) 11 0.031 (0.80) BSC -20- 0.018 (0.45) 0.012 (0.30) REV. A