Standard Products UT54LVDS032LVT Low Voltage Quad Receiver with Integrated Termination Resistor Preliminary Data Sheet February 14, 2003 FEATURES INTRODUCTION q q q q q q q q q The UT54LVDS032LV Quad Receiver is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 400.0 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology. The UT54LVDS032LV accepts low voltage (340mV) differential input signals and translates them to 5V TTL o utput levels. The receiver supports a three-state function that may be used to multiplex outputs. The receiver also supports OPEN, shorted and terminated (100 ) input fail-safe. Receiver output will be HIGH for all fail-safe conditions. EN T The UT54LVDS032LV and companion quad line driver UT54LVDS031LV provides new alternatives to high power pseudo-ECL devices for high speed point-to-point interface applications. All pins have Cold Spare buffers. These buffers will be high impedance when V DD is tied to VSS . EL O PM An integrated termination resistor will reduce component count and save board space. RIN1+ + RIN1- EV q q D q IN q >400.0 Mbps (200 MHz) switching rates +340mV differential signaling 3.3 V power supply TTL compatible outputs Cold spare all pins Nominal 105 Integrated Termination Resistor 3.3ns maximum propagation delay 0.35ns maximum differential skew Radiation-hardened design; total dose irradiation testing to MIL-STD-883 Method 1019 - Total-dose: 300 krad(Si) and 1Mrad(Si) - Latchup immune (LET > 100 MeV-cm2 /mg) Packaging options: - 16-lead flatpack (dual in-line) Standard Microcircuit Drawing TBD - QML Q and V compliant part Compatible with IEEE 1596.3SCI LVDS Compatible with ANSI/TIA/EIA 644-1996 LVDS Standard R1 ROUT1 R2 ROUT2 R3 ROUT3 R4 ROUT4 - RIN2+ + RIN2- - RIN3+ + RIN3- - RIN4+ + RIN4- - EN EN Figure 1. UT54LVDS032LV Quad Receiver Block Diagram 1 APPLICATIONS INFORMATION 1 R IN1- 16 VDD R IN1+ 2 15 R IN4- R OUT1 3 14 R IN4+ 13 12 R OUT4 EN UT54LVDS032LV Receiver The UT54LVDS032LVT receiver's intended use is primarily in an uncomplicated point-to-point configuration as is shown in Figure 3. This configuration provides a clean signaling environment for quick edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic impedance of the media is in the range of 100. An integrated termination resistor of 105 is used to match the media . The termination resistor converts the current sourced by the driver into voltages that are detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities, as well as ground shifting, noise margin limits, and total termination loading must be taken into account. R OUT2 4 5 R IN2+ 6 11 R OUT3 R IN2- 7 10 R IN3+ V SS 8 9 R IN3- EN Figure 2. UT54LVDS032LVT Pinout ENABLE Output EN RIN+ - R IN - ROUT L H X Z VID > 0.1V H V ID < -0.1V L Full Fail-safe OPEN/SHORT or Terminated H All other combinations of ENABLE inputs PIN DESCRIPTION Name Description 2, 6, 10, 14 RIN+ Non-inverting receiver input pin 1, 7, 9, 15 RIN- Inverting receiver input pin 3, 5, 11, 13 ROUT Receiver output pin 4 EN 12 EN Active low enable pin, OR-ed with EN VDD Power supply pin, +3.3 + 0.3V V SS Ground pin 8 + - DATA OUTPUT 1/4 UT54LVDS031LV Figure 3. Point-to-Point Application The UT54LVDS032LVT differential line receiver is capable of detecting signals as low as 100mV, over a + 1V common-mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V. The driven signal is centered around this voltage and may shift +1V around this center point. The +1V shifting may be the result of a ground potential difference between the driver's ground reference and the receiver's ground reference, the common-mode effects of coupled noise or a combination of the two. Both receiver input pins should honor their specified operating input voltage range of 0V to +2.4V (measured from each pin to ground). EV Pin No. The integrated termination resistor is a nominal 105 when V DD is 3.0 to 3.6V. In cold spare mode, the integrated termination resistor is 145. D Active high enable pin, OR-ed with EN IN 16 RT 100 EL O EN DATA INPUT EN Input 1/4 UT54LVDS032LV PM Enables T TRUTH TABLE 2 2. Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a three-state or power-off condition, the receiver output will again be in a HIGH state, even with the end of cable 100 integrated termination resistor across the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable picks up more than 10mV of differential noise, the receiver may see the noise as a valid signal and switch. To insure that any noise is seen as common-mode and not differential, a balanced interconnect should be used. Twisted pair cable offers better balance than flat ribbon cable. Receiver Fail-Safe The UT54LVDS032LVT receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to TTL logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal. The receiver's internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver inputs. 1. Open Input Pins. The UT54LVDS032LVT is a quad receiver device, and if an application requires only 1, 2 or 3 receivers, the unused channel(s) inputs should be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by internal high value pull up and pull down resistors to set the output to a HIGH state. This internal circuitry will guarantee a HIGH, stable output state for open inputs. IN D EV EL O PM EN T 3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V differential input voltage, the receiver output remains in a HIGH state. Shorted input fail-safe is not supported across the common-mode range of the device (VSS to 2.4V). It is only supported with inputs shorted and no external common-mode voltage applied. 3 ABSOLUTE MAXIMUM RATINGS 1 (Referenced to VSS ) SYMBOL PARAMETER LIMITS V DD DC supply voltage V I/O Voltage on any pin during operation -0.3 to (VDD + 0.3V) Voltage on any pin during cold spare -.3 to 4.0V TSTG -0.3 to 4.0V Storage temperature -65 to +150C PD Maximum power dissipation 1.25 W TJ Maximum junction temperature2 +150C Thermal resistance, junction-to-case3 10C/W DC input current 10mA JC II EN T Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. Maximum junction temperature may be increased to +175 C during burn-in and life test. 3. Test per MIL-STD-883, Method 1012. SYMBOL PM RECOMMENDED OPERATING CONDITIONS PARAMETER Positive supply voltage TC Case temperature range V IN DC input voltage, receiver inputs DC input voltage, logic inputs IN D EV EL O V DD 4 LIMITS 3.0 to 3.6V -55 to +125C 2.4V 0 to VDD for EN, EN DC ELECTRICAL CHARACTERISTICS (V DD = 3.3V + 0.3V; -55C < T C < +125C) SYMBOL 1 PARAMETER CONDITION MIN MAX V IH High-level input voltage (TTL) V IL Low-level input voltage (TTL) 0.8 V V OL Low-level output voltage I OL = 2mA, V DD = 3.0V 0.25 V V OH High-level output voltage I OH = -0.4mA, VDD = 3.0V 2.7 Logic input leakage current Enables = EN/EN = 0 and 3.6V, V DD = 3.6 -10 +10 A Receiver input Current V IN = 2.4V -15 +15 Cold Spare Leakage Current V IN =3.6V, V DD =VSS -20 +20 V TH 3 Differential Input High Threshold V CM = +1.2V +100 mV V TL3 Differential Input Low Threshold V CM = +1.2V IOZ 3 Output Three-State Current Disabled, V OUT = 0 V or V DD V CL Input clamp voltage I C L = +18mA Output Short Circuit Current Enabled, V OUT = 0 V 2 ICC 3 Supply current, receivers enabled EN, EN = V DD or VSS Inputs Open ICCZ 3 Supply current, receivers disabled EN = V SS , EN = V DD Inputs Open RTERM 4 Termination Resistor T EN IOS 2, 3 V DD = 3.0V to 3.6V V V -100 -10 mV +10 -1.5 -15 PM I CS O II EL I IN 2.0 UNIT V -130 mA 15 mA mA 4 90 128 IN D EV Notes: 1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground. 2. Output short circuit current (IO S) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed maximum junction temperature specification. 3. Guaranteed by characterization. 4. R TERM = 145 in cold spare mode (V DD = 0V). 5 AC SWITCHING CHARACTERISTICS1, 2, 3 (V DD = +3.3V + 0.3V, TA = -55 C to +125 C) SYMBOL PARAMETER MIN MAX UNIT Differential Propagation Delay High to Low CL = 10pf (figures 4 and 5) 1.0 4.0 ns tPLHD 6 Differential Propagation Delay Low to High CL = 10pf (figures 4 and 5) 1.0 4.0 ns tSKD4 Differential Skew (tPHLD - tPLHD ) (figures 4 and 5) 0 0.35 ns tSK1 4 Channel-to-Channel Skew1 (figures 4 and 5) 0 0.5 ns tSK2 4 Chip-to-Chip Skew5 (figures 4 and 5) 1.5 ns tTLH 4 Rise Time (figures 4 and 5) 1.2 ns tTHL 4 Fall Time (figures 4 and 5) 1.2 ns tPHZ4 Disable Time High to Z (figures 6 and 7) 12 ns tPLZ 4 Disable Time Low to Z (figures 6 and 7) 12 ns tPZH 4 Enable Time Z to High (figures 6 and 7) 12 ns tPZL 4 Enable Time Z to Low (figures 6 and 7) 12 ns PM EN T tPHLD 6 IN D EV EL O Notes: 1. Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in t he same chip with an event on the inputs. 2. Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z0 = 50, tr and t f (0% - 100%) < 1ns for RIN and tr and tf < 1ns for EN or EN. 3. CL includes probe and jig capacitance. 4. Guaranteed by characterization. 5. Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays. 6. May be tested at higher load capacitance and the limit interpolated from characterization data to guarantee this parameter. 6 R IN+ Generator R IN- R R OUT 10pF 50 50 Receiver Enabled Figure 4. Receiver Propagation Delay and Transition Time Test Circuit or Equivalent Circuit R IN- +1.3V 0V Differential +1.2V V ID = 200mV R IN+ +1.1V V OH EN T tPHLD tPLHD 80% 80% 50% 50% PM R OUT 20% O tTLH 20% V OL tTHL IN D EV EL Figure 5. Receiver Propagation Delay and Transition Time Waveforms 7 EN V DD 2K R IN+ R IN- 10pf T 2K EN when EN = VDD tPZL 50% IN VOZ V OL tPHZ tPZH D EV 0.5V Output when VID = +100mV V DD 0V tPLZ Output when VID = -100mV 0V 1.5V 1.5V EN when EN = V SS VDD 1.5V EL O 1.5V PM EN Figure 6. Receiver Three-State Delay Test Circuit or Equivalent Circuit 0.5V VOH 50% V OZ Figure 7. Receiver Three-State Delay Waveform 8 D EV EL O PM EN T PACKAGING IN Notes: 1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535. 2. The lid is electrically connected to VSS. 3. Lead finishes are in accordance to MIL-PRF-38535. 4. Package dimensions and symbols are similar to MIL-STD-1835 variation F-5A. 5. Lead position and coplanarity are not measured. 6. ID mark symbol is vendor option. 7. With solder, increase maximum by 0.003. Figure 8. 16-pin Ceramic Flatpack 9 ORDERING INFORMATION UT54LVDS032LVT QUAD RECEIVER: UT 54LVDS032LV- * * * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory option (gold or solder) Screening: (C) = Military Temperature Range flow (P) = Prototype flow T Package Type: (U) = 16-lead Flatpack (dual-in-line) Device Type: UT54 LVDS032LVT LVDS PM EN Access Time: Not applicable IN D EV EL O Notes: 1 . Lead finish (A,C, or X) must be specified. 2 . If an "X" is specified when ordering, then the part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3 . Prototype flow per UTMC Manufacturing Flows Document. Tested at 25 C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed. 4 . Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -55C, room temp, and 125 C. Radiation neither tested nor guaranteed. 10 UT54LVDS032LVT QUAD RECEIVER: SMD 5962 - TBD ** * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory Option (gold or solder) Case Outline: (Y) = 16 lead Flatpack (dual-in-line) Class Designator: (Q) = QML Class Q (V) = QML Class V Device Type 01 = LVDS Receiver, 300k, 500k and 1M Rad(Si) 02 = LVDS Receiver, 100k Rad(Si) Drawing Number: TBD Federal Stock Class Designator: No Options EN T Total Dose (R) = 1E5 rad(Si) (F) = 3E5 rad(Si) (G) = 5E5 rad(Si) (H) = 1E6 rad(Si) IN D EV EL O PM Notes: 1.Lead finish (A,C, or X) must be specified. 2.If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. 11