STM32F405xx STM32F407xx ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera Features FBGA Core: ARM 32-bit CortexTM-M4 CPU with FPU, Adaptive real-time accelerator (ART AcceleratorTM) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/ 1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions Memories - Up to 1 Mbyte of Flash memory - Up to 192+4 Kbytes of SRAM including 64Kbyte of CCM (core coupled memory) data RAM - Flexible static memory controller supporting Compact Flash, SRAM, PSRAM, NOR and NAND memories LCD parallel interface, 8080/6800 modes Clock, reset and supply management - 1.8 V to 3.6 V application supply and I/Os - POR, PDR, PVD and BOR - 4-to-26 MHz crystal oscillator - Internal 16 MHz factory-trimmed RC (1% accuracy) - 32 kHz oscillator for RTC with calibration - Internal 32 kHz RC with calibration Low power - Sleep, Stop and Standby modes - VBAT supply for RTC, 20x32 bit backup registers + optional 4 KB backup SRAM 3x12-bit, 2.4 MSPS A/D converters: up to 24 channels and 7.2 MSPS in triple interleaved mode 2x12-bit D/A converters General-purpose DMA: 16-stream DMA controller with FIFOs and burst support Up to 17 timers: up to twelve 16-bit and two 32bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input Debug mode - Serial wire debug (SWD) & JTAG interfaces - Cortex-M4 Embedded Trace MacrocellTM LQFP64 (10 x 10 mm) LQFP100 (14 x 14 mm) LQFP144 (20 x 20 mm) LQFP176 (24 x 24 mm) WLCSP90 UFBGA176 (10 x 10 mm) Up to 140 I/O ports with interrupt capability - Up to 136 fast I/Os up to 84 MHz - Up to 138 5 V-tolerant I/Os Up to 15 communication interfaces - Up to 3 x I2C interfaces (SMBus/PMBus) - Up to 4 USARTs/2 UARTs (10.5 Mbit/s, ISO 7816 interface, LIN, IrDA, modem control) - Up to 3 SPIs (37.5 Mbits/s), 2 with muxed full-duplex I2S to achieve audio class accuracy via internal audio PLL or external clock - 2 x CAN interfaces (2.0B Active) - SDIO interface Advanced connectivity - USB 2.0 full-speed device/host/OTG controller with on-chip PHY - USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI - 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII 8- to 14-bit parallel camera interface up to 54 Mbytes/s True random number generator CRC calculation unit 96-bit unique ID RTC: subsecond accuracy, hardware calendar Table 1. Reference Device summary Part number STM32F405xx STM32F405RG, STM32F405VG, STM32F405ZG STM32F407xx STM32F407VG, STM32F407IG, STM32F407ZG, STM32F407VE, STM32F407ZE, STM32F407IE 1. The WLCSP90 package will soon be available. January 2012 Doc ID 022152 Rev 2 1/167 www.st.com 1 Contents STM32F405xx, STM32F407xx Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2/167 2.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.1 ARM(R) CortexTM-M4F core with embedded Flash and SRAM . . . . . . . . 18 2.2.2 Adaptive real-time memory accelerator (ART AcceleratorTM) . . . . . . . . 18 2.2.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 19 2.2.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.9 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.10 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 21 2.2.11 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.13 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.14 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.15 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.16 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.17 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . 26 2.2.18 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.2.19 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.2.20 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.2.21 Inter-integrated circuit interface (IC) 2.2.22 Universal synchronous/asynchronous receiver transmitters (USART) . 31 2.2.23 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.2.24 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.2.25 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.26 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . 33 2.2.27 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . 33 2.2.28 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.29 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . 34 Doc ID 022152 Rev 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 31 STM32F405xx, STM32F407xx Contents 2.2.30 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . 34 2.2.31 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2.32 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2.33 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2.34 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.2.35 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.2.36 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.2.37 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.2.38 Embedded Trace MacrocellTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 68 5.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 68 5.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 69 5.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.3.7 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . . 92 5.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Doc ID 022152 Rev 2 3/167 Contents 6 7 STM32F405xx, STM32F407xx 5.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 97 5.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.3.20 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 5.3.22 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 5.3.23 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 5.3.24 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 5.3.25 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.3.26 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 144 5.3.27 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 144 5.3.28 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Appendix A Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 8 4/167 A.1 Main applications versus package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 A.2 Application example with regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . 155 A.3 USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 156 A.4 USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . 158 A.5 Complete audio player solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 A.6 Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F405xx and STM32F407xx: features and peripheral counts. . . . . . . . . . . . . . . . . . 12 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 STM32F40x pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 67 VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 68 Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 68 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 69 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM . . . . . . . . . . . . . . . . . . . 72 Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 75 Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 76 Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 76 Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 77 Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Doc ID 022152 Rev 2 5/167 List of tables Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. 6/167 STM32F405xx, STM32F407xx NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Characteristics of TIMx connected to the APB1 domain . . . . . . . . . . . . . . . . . . . . . . . . . 104 Characteristics of TIMx connected to the APB2 domain . . . . . . . . . . . . . . . . . . . . . . . . . 105 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 SCL frequency (fPCLK1= 42 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 USB OTG FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 USB FS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 ULPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Ethernet DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 116 Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 117 Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 118 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 ADC accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 127 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 128 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 134 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Switching characteristics for PC Card/CF read and write cycles in attribute/common space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Switching characteristics for PC Card/CF read and write cycles in I/O space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 144 DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 147 LQPF100 - 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 148 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 149 UFBGA176+25 - ultra thin fine pitch ball grid array 10 x 10 x 0.6 mm mechanical data . 150 LQFP176, 24 x 24 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 151 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Main applications versus package for STM32F407xx microcontrollers . . . . . . . . . . . . . . 154 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Compatible board design between STM32F10xx/STM32F4xx for LQFP64 . . . . . . . . . . . . 14 Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Compatible board design between STM32F2xx and STM32F4xx for LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 STM32F40x block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Regulator ON/internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 26 Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 26 STM32F40x LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 STM32F40x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 STM32F40x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 STM32F40x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 STM32F40x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Typical current consumption vs temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF . . . . 73 Typical current consumption vs temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals ON . . . . . 73 Typical current consumption vs temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF . . . 74 Typical current consumption vs temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals ON . . . . 74 Typical VBAT current consumption (LSE and RTC ON/backup RAM OFF) . . . . . . . . . . . . 77 Typical VBAT current consumption (LSE and RTC ON/backup RAM ON) . . . . . . . . . . . . . 78 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Doc ID 022152 Rev 2 7/167 List of figures Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. 8/167 STM32F405xx, STM32F407xx I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 114 ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 122 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 122 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 127 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 128 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 129 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 130 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 134 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 PC Card/CompactFlash controller waveforms for common memory read access . . . . . . 136 PC Card/CompactFlash controller waveforms for common memory write access . . . . . . 137 PC Card/CompactFlash controller waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 PC Card/CompactFlash controller waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 139 PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 140 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 143 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 143 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 147 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 148 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 UFBGA176+25 - ultra thin fine pitch ball grid array 10 x 10 x 0.6 mm, package outline . 150 LQFP176 24 x 24 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 151 Regulator OFF/internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Regulator OFF/internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 USB controller configured as peripheral-only and used in Full speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 156 USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 157 USB controller configured as peripheral, host, or dual-mode and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Complete audio player solution 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93. Figure 94. List of figures Complete audio player solution 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Audio player solution using PLL, PLLI2S, USB and 1 crystal . . . . . . . . . . . . . . . . . . . . . . 160 Audio PLL (PLLI2S) providing accurate I2S clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Master clock (MCK) used to drive the external audio DAC. . . . . . . . . . . . . . . . . . . . . . . . 161 Master clock (MCK) not used to drive the external audio DAC. . . . . . . . . . . . . . . . . . . . . 161 MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 RMII with a 50 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 RMII with a 25 MHz crystal and PHY with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Doc ID 022152 Rev 2 9/167 Introduction 1 STM32F405xx, STM32F407xx Introduction This datasheet provides the description of the STM32F405xx and STM32F407xx lines of microcontrollers. For more details on the whole STMicroelectronics STM32TM family, please refer to Section 2.1: Full compatibility throughout the family. The STM32F405xx and STM32F407xx datasheet should be read in conjunction with the STM32F4xx reference manual. For information on programming, erasing and protection of the internal Flash memory, please refer to the STM32F4xx Flash programming manual (PM0081). The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the CortexTM-M4 core please refer to the CortexTM-M4 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0439b/. 10/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx 2 Description Description The STM32F405xx and STM32F407xx family is based on the high-performance ARM(R) CortexTM-M4 32-bit RISC core operating at a frequency of up to 168 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all ARM singleprecision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. The Cortex-M4 core with FPU will be referred to as Cortex-M4F throughout this document. The STM32F405xx and STM32F407xx family incorporates high-speed embedded memories (Flash memory up to 1 Mbyte, up to 192 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers. a true random number generator (RNG). They also feature standard and advanced communication interfaces. Up to three I2Cs Three SPIs, two I2Ss full duplex. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization. Four USARTs plus two UARTs An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the ULPI), Two CANs An SDIO/MMC interface Ethernet and the camera interface available on STM32F407xx devices only. New advanced peripherals include an SDIO, an enhanced flexible static memory control (FSMC) interface (for devices offered in packages of 100 pins and more), a camera interface for CMOS sensors. Refer to Table 2: STM32F405xx and STM32F407xx: features and peripheral counts for the list of peripherals available on each part number. The STM32F405xx and STM32F407xx family operates in the -40 to +105 C temperature range from a 1.8 to 3.6 V power supply. The supply voltage can drop to 1.7 V when the device operates in the 0 to 70 C temperature range and PDR is disabled. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F405xx and STM32F407xx family offers devices in four packages ranging from 64 pins to 176 pins. The set of included peripherals changes with the device chosen. These features make the STM32F405xx and STM32F407xx microcontroller family suitable for a wide range of applications: Motor drive and application control Medical equipment Industrial applications: PLC, inverters, circuit breakers Printers, and scanners Alarm systems, video intercom, and HVAC Home audio appliances Doc ID 022152 Rev 2 11/167 Table 2. STM32F405xx and STM32F407xx: features and peripheral counts Peripherals STM32F405RG Flash memory in Kbytes SRAM in Kbytes STM32F405ZG STM32F407Ix 512 512 512 1024 192(112+16+64) Backup 4 No 1024 No Yes Doc ID 022152 Rev 2 General-purpose 10 Advancedcontrol 2 Basic 2 Yes 2S 3/2 (full duplex) SPI / I I2C 3 USART/UART 4/2 USB OTG FS No Yes USB OTG HS Yes Yes CAN 2 12-bit ADC Number of channels 12-bit DAC Number of channels Maximum CPU frequency No 51 82 Yes 114 82 114 140 16 24 24 3 16 16 24 Yes 2 168 MHz 1.8 to 3.6 V(1) STM32F405xx, STM32F407xx Camera interface GPIOs 1024 Yes Random number generator Operating voltage STM32F407Zx 1024 Ethernet Communication interfaces STM32F407Vx System FSMC memory controller Timers STM32F405VG Description 12/167 Figure 5 shows the general block diagram of the device family. STM32F405xx and STM32F407xx: features and peripheral counts (continued) Peripherals STM32F405RG STM32F405ZG STM32F407Vx STM32F407Zx STM32F407Ix Ambient temperatures: -40 to +85 C /-40 to +105 C Operating temperatures Package STM32F405VG Junction temperature: -40 to + 125 C LQFP64 LQFP100 LQFP144 LQFP100 1. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in the 0 to 70 C temperature range and PDR is disabled. LQFP144 UFBGA176 LQFP176 STM32F405xx, STM32F407xx Table 2. Doc ID 022152 Rev 2 Description 13/167 Description 2.1 STM32F405xx, STM32F407xx Full compatibility throughout the family The STM32F405xx and STM32F407xx are part of the STM32F4 family. They are fully pinto-pin, software and feature compatible with the STM32F2xx devices, allowing the user to try different memory densities, peripherals, and performances (FPU, higher frequency) for a greater degree of freedom during the development cycle. The STM32F405xx and STM32F407xx devices maintain a close compatibility with the whole STM32F10xxx family. All functional pins are pin-to-pin compatible. The STM32F405xx and STM32F407xx, however, are not drop-in replacements for the STM32F10xxx devices: the two families do not have the same power scheme, and so their power pins are different. Nonetheless, transition from the STM32F10xxx to the STM32F40x family remains simple as only a few pins are impacted. Figure 4, Figure 3, Figure 2, and Figure 1 give compatible board designs between the STM32F40x, STM32F2xxx, and STM32F10xxx families. Figure 1. Compatible board design between STM32F10xx/STM32F4xx for LQFP64 633 633 633 633 14/167 Doc ID 022152 Rev 2 RESISTOR OR SOLDERING BRIDGE PRESENT FOR THE 34-&XX CONFIGURATION NOT PRESENT IN THE 34-&XX CONFIGURATION AI STM32F405xx, STM32F407xx Figure 2. Description Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package 633 633 633 633 6$$ 6 33 4WO RESISTORS CONNECTED TO 6$$ 633 6 33 FOR THE 34-&XX 6 33 FOR THE 34-&XX 6 33 6 $$ OR .# FOR THE 34-&XX Figure 3. RESISTOR OR SOLDERING BRIDGE PRESENT FOR THE 34-&XXX CONFIGURATION NOT PRESENT IN THE 34-&XX CONFIGURATION 633 6 33 FOR 34-&XX 6 $$ FOR 34-&XX AIC Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package 633 633 633 0$2?/. )NVERTED RESET SIGNAL 6$$ 6 33 RESISTOR OR SOLDERING BRIDGE PRESENT FOR THE 34-&XX CONFIGURATION NOT PRESENT IN THE 34-&XX CONFIGURATION 633 4WO RESISTORS CONNECTED TO 6$$ 633 633 FOR THE 34-&XX 6 33 6 $$ OR .# FOR THE 34-&XX 6$$ OR INVERTED RESET SIGNAL FOR THE 34-&XX Doc ID 022152 Rev 2 6 33 FOR 34-&XX 6 $$ FOR 34-&XX AIC 15/167 Description STM32F405xx, STM32F407xx Figure 4. Compatible board design between STM32F2xx and STM32F4xx for LQFP176 package )NVERTED RESET SIGNAL 0$2?/. 6$$ 6 33 4WO RESISTORS CONNECTED TO 6 33 6 $$ OR .# FOR THE 34-&XX 6$$ OR INVERTED RESET SIGNAL FOR THE 34-&XX 16/167 Doc ID 022152 Rev 2 -36 STM32F405xx, STM32F407xx Description 2.2 Device overview Figure 5. STM32F40x block diagram %XTERNAL MEMORY CONTROLLER &3-# ##- DATA 2!- +" $ "53 $-! &)&/ 53" /4' (3 3TREAMS $-! 2.' 32!- +" 32!- +" !(" -(Z &)&/ !( (" -(Z 3TREAMS $-! &LASH UP TO -" 6$$ 6$$! 0!;= 0";= '0)/ 0/24 ! '0)/ 0/24 " 0#;= '0)/ 0/24 # 0$;= '0)/ 0/24 $ 0%;= '0)/ 0/24 % 53" /4' &3 2# (3 0/2 2ESET 2# ,3 )NT 0,, 3UPPLY SUPERVISION 0/20$2 "/2 06$ 633 6#!0 6#!0 6$$! 633! .234 /3#?). /3#?/54 6"!4 TO 6 ,3 0#,+X 6"!4 84!, K(Z 24# '0)/ 0/24 ) ,3 0);= '0)/ 0/24 ( 6$$ TO 6 )7$' 3TANDBY INTERFACE '0)/ 0/24 ' &#,+ 0(;= '0)/ 0/24 & (#,+X 0&;= 84!, /3# -(Z 2ESET CLOCK -!.!'4 CONTROL $0 $3#, 3$! ).4. )$ 6"53 3/& 6$$ 6$$! 0';= (39.# 639.# 0)8#,+ $;= 0OWER MANAGMT 6OLTAGE REGULATOR 6 TO 6 6$$ &)&/ #AMERA INTERFACE 0(9 ) "53 3 "53 %THERNET -!# $-! &)&/ 0(9 $0 $5,0) #+ $ $)2 340 .84 3#,3$! ).4. )$ 6"53 3/& 32!- 032!- ./2 &LASH 0# #ARD !4! .!.$ &LASH &)&/ !2- #ORTEX - -(Z &05 -)) OR 2-)) AS !& -$)/ AS !& !(" -05 .6)# %4- #,+ .% ;= !;= $;= /%. 7%. .",;= ., .2%' .7!)4)/2$9 #$ .)/2$ )/72 ).4;= ).4. .))3 AS !& &)&/ *4!' 37 !24 !##%, #!#(% 42!#%#,+ 42!#%$;= !(" BUS MATRIX 3- .*4234 *4$) *4#+37#,+ *4$/37$ *4$/ !75 "ACKUP REGISTER /3#?). /3#?/54 24#?!& 24#?!& +" "+032!- 4)- B $-! !("!0" !("!0" CHANNELS %42 AS !& 4)- B CHANNELS %42 AS !& CHANNEL AS !& CHANNEL AS !& 3$)/ --# 4)- B 4)- 07- B 4)- 4)- B 4)- B 28 48 #+ #43 243 AS !& SMCARD 53!24 IR$! 28 48 #+ #43 243 AS !& SMCARD 53!24 IR$! -/3) -)3/ 3#+ .33 AS !& 30) 4)- 4)- B B 6$$! 6$$2%&?!$# ANALOG INPUTS COMMON TO THE !$#S ANALOG INPUTS COMMON TO THE !$# ANALOG INPUTS TO !$# 53!24 -"PS 4EMPERATURE SENSOR 6$$! !$# !$# !$# $!# )& )4& CHANNEL AS !& 53!24 28 48 #+ #43 243 AS !& 53!24 SMCARD IR$! 28 48 #+ #43 243 AS !& 5!24 28 48 AS !& 5!24 28 48 AS !& 30))3 -/3)3$ -)3/3$?EXT 3#+#+ .3373 -#+ AS !& 30))3 -/3)3$ -)3/3$?EXT 3#+#+ .3373 -#+ AS !& )#3-"53 3#, 3$! 3-"! AS !& )#3-"53 3#, 3$! 3-"! AS !& BX#!. BX#!. $!#?/54 AS !& 3#, 3$! 3-"! AS !& )#3-"53 $!# $!#?/54 AS !& CHANNEL AS !& SMCARD IR$! 77$' B CHANNELS AS !& B 4)- B 4)- 07- !0"!0" -(Z-(Z MAX COMPL CHANNELS 4)-?#(;=. CHANNELS 4)-?#(;= %42 "+). AS !& COMPL CHANNELS 4)-?#(;=. CHANNELS 4)-?#(;= %42 "+). AS !& CHANNELS AS !& 4)- !0" -(Z !0" -(Z $;= #-$ #+ AS !& B %84 )4 7+50 &)&/ !& CHANNELS %42 AS !& B 4)- &)&/ $-! CHANNELS %42 AS !& B 4)- 48 28 48 28 -36 1. The timers connected to APB2 are clocked from TIMxCLK up to 168 MHz, while the timers connected to APB1 are clocked Doc ID 022152 Rev 2 17/167 Description STM32F405xx, STM32F407xx from TIMxCLK up to 84 MHz. 2. The camera interface is available only on STM32F407xxdevices. 2.2.1 ARM(R) CortexTM-M4F core with embedded Flash and SRAM The ARM Cortex-M4F processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The ARM Cortex-M4F 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. The STM32F405xx and STM32F407xx family is compatible with all ARM tools and software. Figure 5 shows the general block diagram of the STM32F40x family. Note: Cortex-M4F is binary compatible with Cortex-M3. 2.2.2 Adaptive real-time memory accelerator (ART AcceleratorTM) The ART AcceleratorTM is a memory accelerator which is optimized for STM32 industrystandard ARM(R) CortexTM-M4F processors. It balances the inherent performance advantage of the ARM Cortex-M4F over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies. To release the processor full 210 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 168 MHz. 2.2.3 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 18/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx 2.2.4 Description Embedded Flash memory The STM32F40x devices embed a Flash memory of 256 Kbytes, 512 Kbytes, 768 Kbytes or 1 Mbytes available for storing programs and data. 2.2.5 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 2.2.6 Embedded SRAM All STM32F40x products embed: Up to 192 Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory) data RAM RAM memory is accessed (read/write) at CPU clock speed with 0 wait states. 4 Kbytes of backup SRAM This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode. 2.2.7 Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB HS) and the slaves (Flash memory, RAM, FSMC, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. Doc ID 022152 Rev 2 19/167 Description Multi-AHB matrix 3 3 3 53"?(3?- -!# 53" /4' %THERNET (3 %4(%2.%4?- $-!?0 $-!?-%- $-!?-%- 3 '0 $-! 3 3 - )#/$% - $#/$% !##%, 3 $-!?0) ) BUS 3 '0 $-! 3 BUS !2#ORTEX - +BYTE ##- DATA 2!- $ BUS Figure 6. STM32F405xx, STM32F407xx &LASH MEMORY - 32! +BYTE - 32! +BYTE !(" PERIPH !(" PERIPH - - - &3-# 3TATIC -EM#TL !0" !0" "US MATRIX 3 AI 2.2.8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent. 20/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Description The DMA can be used with the main peripherals: 2.2.9 SPI and I2S I2C USART General-purpose, basic and advanced-control timers TIMx DAC SDIO Camera interface (DCMI) ADC. Flexible static memory controller (FSMC) The FSMC is embedded in the STM32F405xx and STM32F407xx family. It has four Chip Select outputs supporting the following modes: PCCard/Compact Flash, SRAM, PSRAM, NOR Flash and NAND Flash. Functionality overview: Write FIFO Maximum FSMC_CLK frequency for synchronous accesses is 60 MHz. LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 2.2.10 Nested vectored interrupt controller (NVIC) The STM32F405xx and STM32F407xx embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 87 maskable interrupt channels plus the 16 interrupt lines of the CortexTM-M4F. Closely coupled NVIC gives low-latency interrupt processing Interrupt entry vector table address passed directly to the core Allows early processing of interrupts Processing of late arriving, higher-priority interrupts Support tail chaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency. 2.2.11 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a Doc ID 022152 Rev 2 21/167 Description STM32F405xx, STM32F407xx pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs can be connected to the 16 external interrupt lines. 2.2.12 Clocks and startup On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full temperature range. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 168 MHz. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails). Several prescalers allow the configuration of the two AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB buses is 168 MHz while the maximum frequency of the high-speed APB domains is 84 MHz. The maximum allowed frequency of the low-speed APB domain is 42 MHz. The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class performance. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz. 2.2.13 Boot modes At startup, boot pins are used to select one out of three boot options: Boot from user Flash Boot from system memory Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB13), USB OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade). 2.2.14 Power supply schemes VDD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins. VSSA, VDDA = 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Refer to Figure 18: Power supply scheme for more details. Note: 22/167 VDD/VDDA minimum value of 1.7 V is obtained when the device operates in the 0 to 70 C temperature range and an inverted reset signal is applied to PDR_ON. Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx 2.2.15 Description Power supply supervisor The power supply supervisor is enabled by holding PDR_ON high. The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, BOR is always active, and ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold level is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit. The device also features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. All packages, except for the LQFP64 and LQFP100, have an internal reset controlled through the PDR_ON signal. 2.2.16 Voltage regulator The regulator has eight operating modes: Regulator ON/internal reset ON - Main regulator mode (MR) - Low power regulator (LPR) - Power-down Regulator ON/internal reset OFF - Main regulator mode (MR) - Low power regulator (LPR) - Power-down Regulator OFF/internal reset ON Regulator OFF/internal reset OFF Regulator ON Regulator ON/internal reset ON The regulator ON/internal reset ON mode is always enabled on LQFP64 and LQFP100 package. On LQFP144 package, this mode is activated by setting PDR_ON to VDD. On UFBGA176 package, the internal regulator must be activated by connecting BYPASS_REG to VSS, and PDR_ON to VDD. On LQFP176 packages, the internal reset must be activated by connecting PDR_ON to VDD. Doc ID 022152 Rev 2 23/167 Description STM32F405xx, STM32F407xx VDD minimum value is 1.8 V. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in the 0 to 70 C temperature range and PDR is disabled. There are three low-power modes: - MR is used in the nominal regulation mode (Run) - LPR is used in the Stop modes - Power-down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost). Regulator ON/internal reset OFF The regulator ON with internal reset OFF mode is not available on LQFP64 and LQFP100 packages. On LQFP144, and LQFP176 packages, the internal reset is controlled by applying an inverted reset signal to PDR_ON pin. On UFBGA176 package, the internal regulator must be activated by connecting BYPASS_REG to VSS. On LQFP176 packages, the internal reset must be activated by applying an inverted reset signal to PDR_ON pin. The NRST pin should be controlled by an external reset controller to keep the device under reset when VDD is below 1.8 V (see Figure 7). Figure 7. Regulator ON/internal reset OFF 6$$ 0$2 6 TIME 0$2?/. .234 TIME -36 24/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Description Regulator OFF This mode allows to power the device as soon as VDD reaches 1.8 V. Regulator OFF/internal reset ON This mode is available only on UFBGA package. It is activated by setting BYPASS_REG and PDR_ON pins to VDD. The regulator OFF/internal reset ON mode allows to supply externally a 1.2 V voltage source through VCAP_1 and VCAP_2 pins, in addition to VDD. The following conditions must be respected: - VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains. - If the time for VCAP_1 and VCAP_2 to reach 1.08 V is faster than the time for VDD to reach 1.8 V (VDD/VDDA minimum value of 1.7 V is obtained when the device operates in the 0 to 70 C temperature range and PDR is disabled), then PA0 should be connected to the NRST pin (see Figure 8). Otherwise, PA0 should be asserted low externally during POR until VDD reaches 1.8 V (see Figure 9). - If VCAP_1 and VCAP_2 go below 1.08 V and VDD is higher than 1.7 V, then a reset must be asserted on PA0 pin. In regulator OFF/internal reset ON mode, PA0 cannot be used as a GPIO pin since it allows to reset the part of the 1.2 V logic which is not reset by the NRST pin, when the internal voltage regulator in off. Regulator OFF/internal reset OFF This mode is available only on UFBGA package. It is activated by setting BYPASS_REG pin to VDD and by applying an inverted reset signal to PDR_ON, and allows to supply externally a 1.2 V voltage source through VCAP_1 and VCAP_2 pins, in addition to VDD. The following conditions must be respected: - VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains. - PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach 1.08 V and until VDD reaches 1.8 V (see Figure 8). - NRST should be controlled by an external reset controller to keep the device under reset when VDD is below 1.8 V (see Figure 9). Doc ID 022152 Rev 2 25/167 Description STM32F405xx, STM32F407xx Figure 8. Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization 6$$ 0$2 6 6#!0? 6 #!0? 6 6 TIME 0! TIED TO .234 .234 TIME AIC 1. This figure is valid both whatever the internal reset mode (on or off). Figure 9. Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization 6$$ 0$2 6 6#!0? 6 #!0? 6 6 TIME 0! ASSERTED EXTERNALLY .234 TIME AIB 1. This figure is valid both whatever the internal reset mode (on or off). 2.2.17 Real-time clock (RTC), backup SRAM and backup registers The backup domain of the STM32F405xx and STM32F407xx includes: The real-time clock (RTC) 4 Kbytes of backup SRAM 20 backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is also available in binary format. 26/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Description It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 s to every 36 hours. A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data which need to be retained in VBAT and standby mode. This memory area is disabled by default to minimize power consumption (see Section 2.2.18: Low-power modes). It can be enabled by software. The backup registers are 32-bit registers used to store 80 bytes of user application data when VDD power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see Section 2.2.18: Low-power modes). Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date. Like backup SRAM, the RTC and backup registers are supplied through a switch that is powered either from the VDD supply when present or from the VBAT pin. 2.2.18 Low-power modes The STM32F405xx and STM32F407xx support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. Stop mode The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup). Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.2 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Doc ID 022152 Rev 2 27/167 Description STM32F405xx, STM32F407xx Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event occurs. Note: When in Standby mode, only an RTC alarm/event or an external reset can wake up the device provided VDD is supplied by an external battery. 2.2.19 VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when no external battery and an external supercapacitor are present. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. 2.2.20 Timers and watchdogs The STM32F405xx and STM32F407xx devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. All timer counters can be frozen in debug mode. Table 3 compares the features of the advanced-control, general-purpose and basic timers. 28/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Table 3. Description Timer feature comparison Counter Counter Prescaler Timer type Timer resolution type factor Max Max DMA Capture/ Complementary interface timer request compare output clock clock generation channels (MHz) (MHz) Advanced- TIM1, control TIM8 16-bit Up, Any integer Down, between 1 Up/down and 65536 Yes 4 Yes 84 168 TIM2, TIM5 32-bit Up, Any integer Down, between 1 Up/down and 65536 Yes 4 No 42 84 TIM3, TIM4 16-bit Up, Any integer Down, between 1 Up/down and 65536 Yes 4 No 42 84 TIM9 16-bit Up Any integer between 1 and 65536 No 2 No 84 168 TIM10, TIM11 16-bit Up Any integer between 1 and 65536 No 1 No 84 168 TIM12 16-bit Up Any integer between 1 and 65536 No 2 No 42 84 TIM13, TIM14 16-bit Up Any integer between 1 and 65536 No 1 No 42 84 TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 42 84 General purpose Basic Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for: Input capture Output compare PWM generation (edge- or center-aligned modes) One-pulse mode output If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%). The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. TIM1 and TIM8 support independent DMA request generation. Doc ID 022152 Rev 2 29/167 Description STM32F405xx, STM32F407xx General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32F40x devices (see Table 3 for differences). TIM2, TIM3, TIM4, TIM5 The STM32F40x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages. The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9 and TIM12 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases. Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. TIM6 and TIM7 support independent DMA request generation. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 30/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Description SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: 2.2.21 A 24-bit downcounter Autoreload capability Maskable system interrupt generation when the counter reaches 0 Programmable clock source. Inter-integrated circuit interface (IC) Up to three IC bus interfaces can operate in multimaster and slave modes. They can support the Standard- and Fast-modes. They support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus. 2.2.22 Universal synchronous/asynchronous receiver transmitters (USART) The STM32F405xx and STM32F407xx embed four universal synchronous/asynchronous receiver transmitters (USART1, USART2, USART3 and USART6) and two universal asynchronous receiver transmitters (UART4 and UART5). These six interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to communicate at speeds of up to 10.5 Mbit/s. The other available interfaces communicate at up to 5.25 bit/s. USART1, USART2, USART3 and USART6 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller. Doc ID 022152 Rev 2 31/167 Description Table 4. STM32F405xx, STM32F407xx USART feature comparison USART Standard Modem SPI LIN irDA name features (RTS/CTS) master Smartcard (ISO 7816) Max. baud rate Max. baud rate in Mbit/s in Mbit/s (oversampling (oversampling by 16) by 8) APB mapping USART1 X X X X X X 5.25 10.5 APB2 (max. 84 MHz) USART2 X X X X X X 2.62 5.25 APB1 (max. 42 MHz) USART3 X X X X X X 2.62 5.25 APB1 (max. 42 MHz) UART4 X - X - X - 2.62 5.25 APB1 (max. 42 MHz) UART5 X - X - X - 2.62 5.25 APB1 (max. 42 MHz) USART6 X X X X X X 5.25 10.5 APB2 (max. 84 MHz) 2.2.23 Serial peripheral interface (SPI) The STM32F40x feature up to three SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1 can communicate at up to 37.5 Mbits/s, SPI2 and SPI3 can communicate at up to 21 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. The SPI interface can be configured to operate in TI mode for communications in master mode and slave mode. 2.2.24 Inter-integrated sound (I2S) Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can be operated in master or slave mode, in full duplex and simplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2Sx can be served by the DMA controller. 32/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx 2.2.25 Description Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I2S application. It allows to achieve error-free I2S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals. The PLLI2S configuration can be modified to manage an I2S sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces. The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz. In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S flow with an external PLL (or Codec output). 2.2.26 Secure digital input/output interface (SDIO) An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory Card Specification Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1. 2.2.27 Ethernet MAC interface with dedicated DMA and IEEE 1588 support Peripheral available only on the STM32F407xx devices. The STM32F407xx devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard mediumindependent interface (MII) or a reduced medium-independent interface (RMII). The STM32F407xx requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). the PHY is connected to the STM32F407xx MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) from the STM32F407xx. Doc ID 022152 Rev 2 33/167 Description STM32F405xx, STM32F407xx The STM32F407xx includes the following features: 2.2.28 Supports 10 and 100 Mbit/s rates Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors (see the STM32F46x reference manual for details) Tagged MAC frame support (VLAN support) Half-duplex (CSMA/CD) and full-duplex operation MAC control sublayer (control frames) support 32-bit CRC generation and removal Several address filtering modes for physical and multicast address (multicast and group addresses) 32-bit status code for each transmitted or received frame Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes. Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008 (PTP V2) with the time stamp comparator connected to the TIM2 input Triggers interrupt when system time becomes greater than target time Controller area network (bxCAN) The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 bytes of SRAM are allocated for each CAN. 2.2.29 Universal serial bus on-the-go full-speed (OTG_FS) The STM32F407xx embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: 2.2.30 Combined Rx and Tx FIFO size of 320 x 35 bits with dynamic FIFO sizing Supports the session request protocol (SRP) and host negotiation protocol (HNP) 4 bidirectional endpoints 8 host channels with periodic OUT support HNP/SNP/IP inside (no need for any external resistor) For OTG/Host modes, a power switch is needed in case bus-powered devices are connected Universal serial bus on-the-go high-speed (OTG_HS) The STM32F405xx and STM32F407xx devices embed a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI) for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required. 34/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Description The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: 2.2.31 Combined Rx and Tx FIFO size of 1 Kbit x 35 with dynamic FIFO sizing Supports the session request protocol (SRP) and host negotiation protocol (HNP) 6 bidirectional endpoints 12 host channels with periodic OUT support Internal FS OTG PHY support External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output. Internal USB DMA HNP/SNP/IP inside (no need for any external resistor) for OTG/Host modes, a power switch is needed in case bus-powered devices are connected Digital camera interface (DCMI) The camera interface is not available in STM32F405xx devices. STM32F407xx products embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features: 2.2.32 Programmable polarity for the input pixel clock and synchronization signals Parallel data communication can be 8-, 10-, 12- or 14-bit Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG) Supports continuous mode or snapshot (a single frame) mode Capability to automatically crop the image Random number generator (RNG) All STM32F405xx and STM32F407xx products embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 2.2.33 General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. Fast I/O handling allowing maximum I/O toggling up to 84 MHz. Doc ID 022152 Rev 2 35/167 Description 2.2.34 STM32F405xx, STM32F407xx Analog-to-digital converters (ADCs) Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: Simultaneous sample and hold Interleaved sample and hold The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4, TIM5, or TIM8 timer. 2.2.35 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.8 V and 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used. 2.2.36 Digital-to-analog converter (DAC) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. This dual digital Interface supports the following features: two DAC converters: one for each output channel 8-bit or 12-bit monotonic output left or right data alignment in 12-bit mode synchronized update capability noise-wave generation triangular-wave generation dual DAC channel independent or simultaneous conversions DMA capability for each channel external triggers for conversion input voltage reference VREF+ Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams. 2.2.37 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. 36/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Description Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 2.2.38 Embedded Trace MacrocellTM The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F40x through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools. Doc ID 022152 Rev 2 37/167 Pinouts and pin description 3 STM32F405xx, STM32F407xx Pinouts and pin description 6$$ 633 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0# 0# 0# 0! 0! Figure 10. STM32F40x LQFP64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 ,1&0 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 6$$ 6#!0? 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 0" 0" 0" 0" 0! 633 6$$ 0! 0! 0! 0! 0# 0# 0" 0" 0" 0" 0" 6#!0? 6$$ 6"!4 0# 0# 0# 0( 0( .234 0# 0# 0# 0# 633! 6$$! 0! 0! 0! AIB 38/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Pinouts and pin description 6$$ 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 11. STM32F40x LQFP100 pinout ,1&0 6$$ 633 6#!0? 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 0! 633 6$$ 0! 0! 0! 0! 0# 0# 0" 0" 0" 0% 0% 0% 0% 0% 0% 0% 0% 0% 0" 0" 6#!0? 6$$ 0% 0% 0% 0% 0% 6"!4 0# 0# 0# 633 6$$ 0( 0( .234 0# 0# 0# 0# 6$$ 633! 62%& 6$$! 0! 0! 0! AIB Doc ID 022152 Rev 2 39/167 Pinouts and pin description STM32F405xx, STM32F407xx 6$$ 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$ 633 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$ 633 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 12. STM32F40x LQFP144 pinout ,1&0 6$$ 633 6#!0? 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 6$$ 633 0' 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$ 633 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 40/167 Doc ID 022152 Rev 2 6#!0? 6$$ 0! 633 6$$ 0! 0! 0! 0! 0# 0# 0" 0" 0" 0& 0& 633 6$$ 0& 0& 0& 0' 0' 0% 0% 0% 633 6$$ 0% 0% 0% 0% 0% 0% 0" 0" 0% 0% 0% 0% 0% 6"!4 0# 0# 0# 0& 0& 0& 0& 0& 0& 633 6$$ 0& 0& 0& 0& 0& 0( 0( .234 0# 0# 0# 0# 6$$ 633! 62%& 6$$! 0! 0! 0! AIB STM32F405xx, STM32F407xx Pinouts and pin description 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$ 633 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$ 633 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! 6$$ 633 0) 0) 0) 0) 0) 0) 6 $$ Figure 13. STM32F40x LQFP176 pinout 0) 0) 0( 0( 0( 6$$ 633 6#!0? 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 6$$ 633 0' 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$ 633 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 6$$ 633 0( Doc ID 022152 Rev 2 6#!0? 6$$ 0( 0( 0( 0( 0( 0( 633 6$$ 0& 0& 0& 0' 0' 0% 0% 0% 633 6$$ 0% 0% 0% 0% 0% 0% 0" 0" ,1&0 0( 0( 0! 633 6$$ 0! 0! 0! 0! 0# 0# 0" 0" 0" 0& 0& 0% 0% 0% 0% 0% 6"!4 0) 0# 0# 0#4 0) 0) 0) 633 6$$ 0& 0& 0& 0& 0& 0& 633 6$$ 0& 0& 0& 0& 0& 0( 0( .234 0# 0# 0# 0# 6$$ 633! 62%& 6$$! 0! 0! 0! 0( 0( -36 41/167 Pinouts and pin description STM32F405xx, STM32F407xx Figure 14. STM32F40x UFBGA176 ballout ! 0% 0% 0% 0% 0" 0" 0' 0' 0" 0" 0$ 0# 0! 0! 0! " 0% 0% 0% 0" 0" 0" 0' 0' 0' 0' 0$ 0$ 0# 0# 0! # 6"!4 0) 0) 0) 6$$ 0$2?/. 6$$ 6$$ 6$$ 0' 0$ 0$ 0) 0) 0! $ 0# 0) 0) 0) 633 "//4 633 633 633 0$ 0$ 0$ 0( 0) 0! % 0# 0& 0) 0) 0( 0( 0) 0! & 0# 633 6$$ 0( 633 633 633 633 633 633 6#!0? 0# 0! ' 0( 633 6$$ 0( 633 633 633 633 633 633 6$$ 0# 0# ( 0( 0& 0& 0( 633 633 633 633 633 633 6$$ 0' 0# * .234 0& 0& 0( 633 633 633 633 633 6$$ 6$$ 0' 0' + 0& 0& 0& 6$$ 633 633 633 633 633 0( 0' 0' 0' , 0& 0& 0& "90!33? 2%' 0( 0( 0$ 0' - 633! 0# 0# 0# 0# 0" 0' 633 633 0( 0( 0( 0$ 0$ . 62%& 0! 0! 0! 0# 0& 0' 6$$ 6$$ 6$$ 0% 0( 0$ 0$ 0$ 0 62%& 0! 0! 0! 0# 0& 0& 0% 0% 0% 0% 0" 0" 0$ 0$ 2 6$$! 0! 0! 0" 0" 0& 0& 0% 0% 0% 0% 0" 0" 0" 0" 6#!0? AIB Table 5. Legend/abbreviations used in the pinout table Name Pin name Pin type Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O FTf 5 V tolerant I/O, FM+ capable TTa 3.3 V tolerant I/O directly connected to ADC TC Standard 3.3V I/O B Dedicated BOOT0 pin RST Bidirectional reset pin with embedded weak pull-up resistor I/O structure Notes 42/167 Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Table 5. Pinouts and pin description Legend/abbreviations used in the pinout table (continued) Name Abbreviation Definition Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers Doc ID 022152 Rev 2 43/167 Pinouts and pin description LQFP144 UFBGA176 LQFP176 (function after reset)(1) Pin type I / O structure - 1 1 A2 1 PE2 I/O FT TRACECLK/ FSMC_A23 / ETH_MII_TXD3 / EVENTOUT - 2 2 A1 2 PE3 I/O FT TRACED0/FSMC_A19 / EVENTOUT - 3 3 B1 3 PE4 I/O FT TRACED1/FSMC_A20 / DCMI_D4/ EVENTOUT - 4 4 B2 4 PE5 I/O FT TRACED2 / FSMC_A21 / TIM9_CH1 / DCMI_D6 / EVENTOUT - 5 5 B3 5 PE6 I/O FT TRACED3 / FSMC_A22 / TIM9_CH2 / DCMI_D7 / EVENTOUT 1 6 6 C1 6 VBAT S - - - D2 7 PI8 I/O FT (2)(3) EVENTOUT RTC_AF2 2 7 7 D1 8 PC13 I/O FT (2)(3) EVENTOUT RTC_AF1 3 8 8 E1 9 PC14-OSC32_IN I/O (PC14) FT (2)(3) EVENTOUT OSC32_IN(4) 4 9 9 F1 10 PC15OSC32_OUT (PC15) I/O FT (2)(3) EVENTOUT OSC32_OUT(4) - - - D3 11 PI9 I/O FT CAN1_RX / EVENTOUT - - - E3 12 PI10 I/O FT ETH_MII_RX_ER / EVENTOUT - - - E4 13 PI11 I/O FT OTG_HS_ULPI_DIR / EVENTOUT - - - F2 14 VSS S - - - F3 15 VDD S - - 10 E2 16 PF0 I/O FT FSMC_A0 / I2C2_SDA / EVENTOUT - - 11 H3 17 PF1 I/O FT FSMC_A1 / I2C2_SCL / EVENTOUT - - 12 H2 18 PF2 I/O FT FSMC_A2 / I2C2_SMBA / EVENTOUT - - 13 J2 19 PF3 I/O FT (4) FSMC_A3/EVENTOUT ADC3_IN9 FSMC_A4/EVENTOUT ADC3_IN14 FSMC_A5/EVENTOUT ADC3_IN15 Pin number Pin name Notes LQFP100 STM32F40x pin and ball definitions LQFP64 Table 6. STM32F405xx, STM32F407xx - - 14 J3 20 PF4 I/O FT (4) - - 15 K3 21 PF5 I/O FT (4) 44/167 Alternate functions Doc ID 022152 Rev 2 Additional functions STM32F405xx, STM32F407xx Notes STM32F40x pin and ball definitions (continued) I / O structure Table 6. Pinouts and pin description Alternate functions - - 18 K2 24 PF6 I/O FT (4) TIM10_CH1 / FSMC_NIORD/ EVENTOUT ADC3_IN4 - - 19 K1 25 PF7 I/O FT (4) TIM11_CH1/FSMC_NREG/ EVENTOUT ADC3_IN5 - - 20 L3 26 PF8 I/O FT (4) TIM13_CH1 / FSMC_NIOWR/ EVENTOUT ADC3_IN6 - - 21 L2 27 PF9 I/O FT (4) TIM14_CH1 / FSMC_CD/ EVENTOUT ADC3_IN7 - - 22 L1 28 PF10 I/O FT (4) FSMC_INTR/ EVENTOUT ADC3_IN8 5 12 23 G1 29 PH0-OSC_IN (PH0) I/O FT EVENTOUT OSC_IN(4) 6 13 24 H1 30 PH1-OSC_OUT (PH1) I/O FT EVENTOUT OSC_OUT(4) 7 14 25 J1 31 NRST 8 15 26 M2 32 PC0 I/O FT (4) OTG_HS_ULPI_STP/ EVENTOUT ADC123_IN10 9 16 27 M3 33 PC1 I/O FT (4) ETH_MDC/ EVENTOUT ADC123_IN11 FT (4) SPI2_MISO / OTG_HS_ULPI_DIR / TH_MII_TXD2 /I2S2ext_SD/ EVENTOUT ADC123_IN12 (4) SPI2_MOSI / I2S2_SD / OTG_HS_ULPI_NXT / ETH_MII_TX_CLK/ EVENTOUT ADC123_IN13 UFBGA176 LQFP176 - 10 16 G2 22 VSS S - 11 17 G3 23 VDD S LQFP100 (function after reset)(1) LQFP64 LQFP144 Pin name Pin type Pin number 10 17 28 11 18 29 M4 34 PC2 I/O RST I/O M5 35 PC3 I/O 19 30 G3 36 VDD S 12 20 31 M1 37 VSSA S N1 - VREF- S 21 32 P1 38 VREF+ S 13 22 33 R1 39 VDDA S - - - - Additional functions FT Doc ID 022152 Rev 2 45/167 Pinouts and pin description N3 (function after reset)(1) 40 PA0-WKUP (PA0) Pin type Pin name LQFP176 14 23 34 UFBGA176 LQFP144 LQFP100 LQFP64 Pin number I/O Notes STM32F40x pin and ball definitions (continued) I / O structure Table 6. STM32F405xx, STM32F407xx FT USART2_CTS/ UART4_TX/ ETH_MII_CRS / (5) TIM2_CH1_ETR/ TIM5_CH1 / TIM8_ETR/ EVENTOUT Alternate functions 15 24 35 N2 41 PA1 I/O FT (4) USART2_RTS / UART4_RX/ ETH_RMII_REF_CLK / ETH_MII_RX_CLK / TIM5_CH2 / TIMM2_CH2/ EVENTOUT 16 25 36 P2 42 PA2 I/O FT (4) USART2_TX/TIM5_CH3 / TIM9_CH1 / TIM2_CH3 / ETH_MDIO/ EVENTOUT Additional functions ADC123_IN0/WKUP(4) ADC123_IN1 ADC123_IN2 - - - F4 43 PH2 I/O FT ETH_MII_CRS/EVENTOUT - - - G4 44 PH3 I/O FT ETH_MII_COL/EVENTOUT - - - H4 45 PH4 I/O FT I2C2_SCL / OTG_HS_ULPI_NXT/ EVENTOUT - - - J4 46 PH5 I/O FT I2C2_SDA/ EVENTOUT FT (4) USART2_RX/TIM5_CH4 / TIM9_CH2 / TIM2_CH4 / OTG_HS_ULPI_D0 / ETH_MII_COL/ EVENTOUT ADC123_IN3 I/O TTa (4) SPI1_NSS / SPI3_NSS / USART2_CK / DCMI_HSYNC / OTG_HS_SOF/ I2S3_WS/ EVENTOUT ADC12_IN4 /DAC1_OUT I/O TTa (4) SPI1_SCK/ OTG_HS_ULPI_CK / TIM2_CH1_ETR/ TIM8_CHIN/ EVENTOUT ADC12_IN5/DAC2_OUT I/O SPI1_MISO / TIM8_BKIN/TIM13_CH1 / (4) DCMI_PIXCLK / TIM3_CH1 / TIM1_BKIN/ EVENTOUT 17 26 37 R2 47 PA3 I/O 18 27 38 - 48 VSS S L4 - BYPASS_REG I K4 49 VDD S 19 28 39 20 29 40 21 30 41 22 31 42 46/167 N4 P4 P3 50 51 52 PA4 PA5 PA6 FT FT Doc ID 022152 Rev 2 ADC12_IN6 STM32F405xx, STM32F407xx Notes STM32F40x pin and ball definitions (continued) I / O structure Table 6. Pinouts and pin description 23 32 43 R3 53 PA7 I/O FT SPI1_MOSI/ TIM8_CH1N / TIM14_CH1/TIM3_CH2/ ETH_MII_RX_DV / (4) TIM1_CH1N / RMII_CRS_DV/ EVENTOUT 24 33 44 N5 54 PC4 I/O FT (4) ETH_RMII_RX_D0 / ETH_MII_RX_D0/ EVENTOUT ADC12_IN14 25 34 45 P5 55 PC5 I/O FT (4) ETH_RMII_RX_D1 / ETH_MII_RX_D1/ EVENTOUT ADC12_IN15 FT (4) TIM3_CH3 / TIM8_CH2N/ OTG_HS_ULPI_D1/ ETH_MII_RXD2 / TIM1_CH2N/ EVENTOUT ADC12_IN8 (4) TIM3_CH4 / TIM8_CH3N/ OTG_HS_ULPI_D2/ ETH_MII_RXD3 / OTG_HS_INTN / TIM1_CH3N/ EVENTOUT ADC12_IN9 26 35 46 R5 56 Pin name (function after reset)(1) PB0 Pin type LQFP176 UFBGA176 LQFP144 LQFP100 LQFP64 Pin number I/O Alternate functions 27 36 47 R4 57 PB1 I/O FT 28 37 48 M6 58 PB2-BOOT1 (PB2) I/O FT EVENTOUT - - 49 R6 59 PF11 I/O FT DCMI_12/ EVENTOUT - - 50 P6 60 PF12 I/O FT FSMC_A6/ EVENTOUT - - 51 M8 61 VSS S - - 52 N8 62 VDD S - - 53 N6 63 PF13 I/O FT FSMC_A7/ EVENTOUT - - 54 R7 64 PF14 I/O FT FSMC_A8/ EVENTOUT - - 55 P7 65 PF15 I/O FT FSMC_A9/ EVENTOUT - - 56 N7 66 PG0 I/O FT FSMC_A10/ EVENTOUT - - 57 M7 67 PG1 I/O FT FSMC_A11/ EVENTOUT - 38 58 R8 68 PE7 I/O FT FSMC_D4/TIM1_ETR/ EVENTOUT - 39 59 P8 69 PE8 I/O FT FSMC_D5/ TIM1_CH1N/ EVENTOUT - 40 60 P9 70 PE9 I/O FT FSMC_D6/TIM1_CH1/ EVENTOUT M9 71 VSS S - - 61 Doc ID 022152 Rev 2 Additional functions ADC12_IN7 47/167 Pinouts and pin description LQFP64 LQFP100 LQFP144 UFBGA176 LQFP176 Pin name (function after reset)(1) - - 62 N9 72 VDD Pin type Pin number Notes STM32F40x pin and ball definitions (continued) I / O structure Table 6. STM32F405xx, STM32F407xx Alternate functions S - 41 63 R9 73 PE10 I/O FT FSMC_D7/TIM1_CH2N/ EVENTOUT - 42 64 P10 74 PE11 I/O FT FSMC_D8/TIM1_CH2/ EVENTOUT - 43 65 R10 75 PE12 I/O FT FSMC_D9/TIM1_CH3N/ EVENTOUT - 44 66 N11 76 PE13 I/O FT FSMC_D10/TIM1_CH3/ EVENTOUT - 45 67 P11 77 PE14 I/O FT FSMC_D11/TIM1_CH4/ EVENTOUT - 46 68 R11 78 PE15 I/O FT FSMC_D12/TIM1_BKIN/ EVENTOUT FT SPI2_SCK / I2S2_CK / I2C2_SCL/ USART3_TX / OTG_HS_ULPI_D3 / ETH_MII_RX_ER / TIM2_CH3/ EVENTOUT FT I2C2_SDA/USART3_RX/ OTG_HS_ULPI_D4 / ETH_RMII_TX_EN/ ETH_MII_TX_EN / TIM2_CH4/ EVENTOUT 29 47 69 R12 79 PB10 I/O 30 48 70 R13 80 PB11 I/O 31 49 71 M10 81 VCAP_1 S 32 50 72 N10 82 VDD S - - - M11 83 PH6 I/O FT I2C2_SMBA / TIM12_CH1 / ETH_MII_RXD2/ EVENTOUT - - - N12 84 PH7 I/O FT I2C3_SCL / ETH_MII_RXD3/ EVENTOUT - - - M12 85 PH8 I/O FT I2C3_SDA / DCMI_HSYNC/ EVENTOUT - - - M13 86 PH9 I/O FT I2C3_SMBA / TIM12_CH2/ DCMI_D0/ EVENTOUT - - - L13 87 PH10 I/O FT TIM5_CH1 / DCMI_D1/ EVENTOUT - - - L12 88 PH11 I/O FT TIM5_CH2 / DCMI_D2/ EVENTOUT 48/167 Doc ID 022152 Rev 2 Additional functions STM32F405xx, STM32F407xx I/O FT TIM5_CH3 / DCMI_D3/ EVENTOUT FT SPI2_NSS / I2S2_WS / I2C2_SMBA/ USART3_CK/ TIM1_BKIN / CAN2_RX / OTG_HS_ULPI_D5/ ETH_RMII_TXD0 / ETH_MII_TXD0/ OTG_HS_ID/ EVENTOUT FT SPI2_SCK / I2S2_CK / USART3_CTS/ TIM1_CH1N /CAN2_TX / OTG_HS_ULPI_D6 / ETH_RMII_TXD1 / ETH_MII_TXD1/ EVENTOUT FT SPI2_MISO/ TIM1_CH2N / TIM12_CH1 / OTG_HS_DM/ USART3_RTS / TIM8_CH2N/I2S2ext_SD/ EVENTOUT LQFP144 LQFP176 LQFP100 Pin name LQFP64 UFBGA176 Pin number - - - K12 89 PH12 - - - H12 90 VSS S - - - J12 91 VDD S 33 51 73 P12 92 34 52 74 P13 93 35 53 75 R14 94 36 54 76 R15 95 (function after reset)(1) PB12 PB13 PB14 I/O I/O I/O Notes I / O structure STM32F40x pin and ball definitions (continued) Pin type Table 6. Pinouts and pin description Alternate functions PB15 I/O FT SPI2_MOSI / I2S2_SD/ TIM1_CH3N / TIM8_CH3N / TIM12_CH2 / OTG_HS_DP/ EVENTOUT - 55 77 P15 96 PD8 I/O FT FSMC_D13 / USART3_TX/ EVENTOUT - 56 78 P14 97 PD9 I/O FT FSMC_D14 / USART3_RX/ EVENTOUT - 57 79 N15 98 PD10 I/O FT FSMC_D15 / USART3_CK/ EVENTOUT - 58 80 N14 99 PD11 I/O FT FSMC_CLE / FSMC_A16/USART3_CTS/ EVENTOUT FT FSMC_ALE/ FSMC_A17/TIM4_CH1 / USART3_RTS/ EVENTOUT - 59 81 N13 100 PD12 I/O Doc ID 022152 Rev 2 Additional functions OTG_HS_VBUS 49/167 Pinouts and pin description I/O FT FSMC_A18/TIM4_CH2/ EVENTOUT - LQFP176 UFBGA176 LQFP144 LQFP100 LQFP64 Pin number 60 82 M15 101 - Pin name (function after reset)(1) PD13 - - 83 102 VSS S - - 84 J13 103 VDD S Notes I / O structure STM32F40x pin and ball definitions (continued) Pin type Table 6. STM32F405xx, STM32F407xx Alternate functions - 61 85 M14 104 PD14 I/O FT FSMC_D0/TIM4_CH3/ EVENTOUT/ EVENTOUT - 62 86 L14 105 PD15 I/O FT FSMC_D1/TIM4_CH4/ EVENTOUT - - 87 L15 106 PG2 I/O FT FSMC_A12/ EVENTOUT - - 88 K15 107 PG3 I/O FT FSMC_A13/ EVENTOUT - - 89 K14 108 PG4 I/O FT FSMC_A14/ EVENTOUT - - 90 K13 109 PG5 I/O FT FSMC_A15/ EVENTOUT - - 91 J15 110 PG6 I/O FT FSMC_INT2/ EVENTOUT - - 92 J14 111 PG7 I/O FT FSMC_INT3 /USART6_CK/ EVENTOUT - - 93 H14 112 PG8 I/O FT USART6_RTS / ETH_PPS_OUT/ EVENTOUT - - 94 G12 113 VSS S - - 95 H13 114 VDD S FT I2S2_MCK / TIM8_CH1/SDIO_D6 / USART6_TX / DCMI_D0/TIM3_CH1/ EVENTOUT 37 63 96 H15 115 PC6 I/O 38 64 97 G15 116 PC7 I/O FT I2S3_MCK / TIM8_CH2/SDIO_D7 / USART6_RX / DCMI_D1/TIM3_CH2/ EVENTOUT 39 65 98 G14 117 PC8 I/O FT TIM8_CH3/SDIO_D0 /TIM3_CH3/ USART6_CK / DCMI_D2/ EVENTOUT FT I2S_CKIN/ MCO2 / TIM8_CH4/SDIO_D1 / /I2C3_SDA / DCMI_D3 / TIM3_CH4/ EVENTOUT 40 66 99 F14 118 50/167 PC9 I/O Doc ID 022152 Rev 2 Additional functions STM32F405xx, STM32F407xx Pin name (function after reset)(1) Pin type LQFP176 UFBGA176 LQFP144 LQFP100 LQFP64 Pin number Notes STM32F40x pin and ball definitions (continued) I / O structure Table 6. Pinouts and pin description Alternate functions 41 67 100 F15 119 PA8 I/O FT MCO1 / USART1_CK/ TIM1_CH1/ I2C3_SCL/ OTG_FS_SOF/ EVENTOUT 42 68 101 E15 120 PA9 I/O FT USART1_TX/ TIM1_CH2 / I2C3_SMBA / DCMI_D0/ EVENTOUT 43 69 102 D15 121 PA10 I/O FT USART1_RX/ TIM1_CH3/ OTG_FS_ID/DCMI_D1/ EVENTOUT 44 70 103 C15 122 PA11 I/O FT USART1_CTS / CAN1_RX / TIM1_CH4 / OTG_FS_DM/ EVENTOUT 45 71 104 B15 123 PA12 I/O FT USART1_RTS / CAN1_TX/ TIM1_ETR/ OTG_FS_DP/ EVENTOUT 46 72 105 A15 124 PA1 (JTMS-SWDIO) I/O FT JTMS-SWDIO/ EVENTOUT 47 73 106 F13 125 VCAP_2 S 74 107 F12 126 VSS S 48 75 108 G13 127 VDD S - - - - E12 128 PH13 I/O FT TIM8_CH1N / CAN1_TX/ EVENTOUT - - - E13 129 PH14 I/O FT TIM8_CH2N / DCMI_D4/ EVENTOUT - - - D13 130 PH15 I/O FT TIM8_CH3N / DCMI_D11/ EVENTOUT - - - E14 131 PI0 I/O FT TIM5_CH4 / SPI2_NSS / I2S2_WS / DCMI_D13/ EVENTOUT - - - D14 132 PI1 I/O FT SPI2_SCK / I2S2_CK / DCMI_D8/ EVENTOUT - - - C14 133 PI2 I/O FT TIM8_CH4 /SPI2_MISO / DCMI_D9 / I2S2ext_SD/ EVENTOUT - - - C13 134 PI3 I/O FT TIM8_ETR / SPI2_MOSI / I2S2_SD / DCMI_D10/ EVENTOUT - - - D9 135 VSS S - - - C9 136 VDD S Doc ID 022152 Rev 2 Additional functions OTG_FS_VBUS 51/167 Pinouts and pin description I / O structure 49 76 109 A14 137 PA14 (JTCK-SWCLK) I/O FT JTCK-SWCLK/ EVENTOUT 50 77 110 A13 138 PA15 (JTDI) I/O FT JTDI/ SPI3_NSS/ I2S3_WS/TIM2_CH1_ETR / SPI1_NSS / EVENTOUT FT SPI3_SCK / I2S3_CK/ UART4_TX/SDIO_D2 / DCMI_D8 / USART3_TX/ EVENTOUT FT UART4_RX/ SPI3_MISO / SDIO_D3 / DCMI_D4/USART3_RX / I2S3ext_SD/ EVENTOUT UFBGA176 LQFP144 LQFP100 LQFP64 Pin number 51 78 111 B14 139 52 79 112 B13 140 53 80 113 A12 141 Pin name PC10 PC11 I/O I/O Notes (function after reset)(1) Pin type STM32F40x pin and ball definitions (continued) LQFP176 Table 6. STM32F405xx, STM32F407xx Alternate functions PC12 I/O FT UART5_TX/SDIO_CK / DCMI_D9 / SPI3_MOSI /I2S3_SD / USART3_CK/ EVENTOUT - 81 114 B12 142 PD0 I/O FT FSMC_D2/CAN1_RX/ EVENTOUT - 82 115 C12 143 PD1 I/O FT FSMC_D3 / CAN1_TX/ EVENTOUT 54 83 116 D12 144 PD2 I/O FT TIM3_ETR/UART5_RX/ SDIO_CMD / DCMI_D11/ EVENTOUT - 84 117 D11 145 PD3 I/O FT FSMC_CLK/USART2_CTS / EVENTOUT - 85 118 D10 146 PD4 I/O FT FSMC_NOE/USART2_RTS / EVENTOUT - 86 119 C11 147 PD5 I/O FT FSMC_NWE/USART2_TX/ EVENTOUT - - 120 D8 148 VSS S - - 121 C8 149 VDD S - 87 122 B11 150 PD6 I/O FT FSMC_NWAIT/ USART2_RX/ EVENTOUT - 88 123 A11 151 PD7 I/O FT USART2_CK/FSMC_NE1/ FSMC_NCE2/ EVENTOUT PG9 I/O FT USART6_RX / FSMC_NE2/FSMC_NCE3/ EVENTOUT - - 52/167 124 C10 152 Doc ID 022152 Rev 2 Additional functions STM32F405xx, STM32F407xx I/O FT FSMC_NCE4_1/ FSMC_NE3/ EVENTOUT LQFP176 - UFBGA176 LQFP100 - LQFP144 LQFP64 Pin number 125 B10 153 Pin name (function after reset)(1) PG10 Notes I / O structure STM32F40x pin and ball definitions (continued) Pin type Table 6. Pinouts and pin description Alternate functions - - 126 B9 154 PG11 I/O FT FSMC_NCE4_2 / ETH_MII_TX_EN/ ETH _RMII_TX_EN/ EVENTOUT - - 127 B8 155 PG12 I/O FT FSMC_NE4 / USART6_RTS/ EVENTOUT FT FSMC_A24 / USART6_CTS /ETH_MII_TXD0/ ETH_RMII_TXD0/ EVENTOUT FT FSMC_A25 / USART6_TX /ETH_MII_TXD1/ ETH_RMII_TXD1/ EVENTOUT FT USART6_CTS / DCMI_D13/ EVENTOUT - - 128 A8 156 PG13 I/O - - 129 A7 157 PG14 I/O - - 130 D7 158 VSS S - - 131 C7 159 VDD S - - 132 B7 160 PG15 I/O 55 89 133 A10 161 PB3 (JTDO/ TRACESWO) I/O FT JTDO/ TRACESWO/ SPI3_SCK / I2S3_CK / TIM2_CH2 / SPI1_SCK/ EVENTOUT 56 90 134 A9 162 PB4 (NJTRST) I/O FT NJTRST/ SPI3_MISO / TIM3_CH1 / SPI1_MISO / I2S3ext_SD/ EVENTOUT FT I2C1_SMBA/ CAN2_RX / OTG_HS_ULPI_D7 / ETH_PPS_OUT/TIM3_CH 2 / SPI1_MOSI/ SPI3_MOSI / DCMI_D10 / I2S3_SD/ EVENTOUT FT I2C1_SCL/ TIM4_CH1 / CAN2_TX / DCMI_D5/USART1_TX/ EVENTOUT 57 91 135 A6 163 58 92 136 B6 164 PB5 PB6 I/O I/O Doc ID 022152 Rev 2 Additional functions 53/167 Pinouts and pin description Pin name (function after reset)(1) Pin type LQFP176 UFBGA176 LQFP144 LQFP100 LQFP64 Pin number 59 93 137 B5 165 PB7 I/O FT 60 94 138 D6 166 BOOT0 I B 61 95 139 A5 167 62 96 140 B4 168 PB8 I/O Notes STM32F40x pin and ball definitions (continued) I / O structure Table 6. STM32F405xx, STM32F407xx Alternate functions I2C1_SDA / FSMC_NL / DCMI_VSYNC / USART1_RX/ TIM4_CH2/ EVENTOUT VPP FT TIM4_CH3/SDIO_D4/ TIM10_CH1 / DCMI_D6 / ETH_MII_TXD3 / I2C1_SCL/ CAN1_RX/ EVENTOUT PB9 I/O FT SPI2_NSS/ I2S2_WS / TIM4_CH4/ TIM11_CH1/ SDIO_D5 / DCMI_D7 / I2C1_SDA / CAN1_TX/ EVENTOUT - 97 141 A4 169 PE0 I/O FT TIM4_ETR / FSMC_NBL0 / DCMI_D2/ EVENTOUT - 98 142 A3 170 PE1 I/O FT FSMC_NBL1 / DCMI_D3/ EVENTOUT VSS S PDR_ON I VDD S 63 99 64 - - D5 - 143 C6 171 10 144 C5 172 0 Additional functions FT - - - D4 173 PI4 I/O FT TIM8_BKIN / DCMI_D5/ EVENTOUT - - - C4 174 PI5 I/O FT TIM8_CH1 / DCMI_VSYNC/ EVENTOUT - - - C3 175 PI6 I/O FT TIM8_CH2 / DCMI_D6/ EVENTOUT - - - C2 176 PI7 I/O FT TIM8_CH3 / DCMI_D7/ EVENTOUT 1. Function availability depends on the chosen device. 2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF. - These I/Os must not be used as a current source (e.g. to drive an LED). 3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F4xx reference manual, available from the STMicroelectronics website: www.st.com. 4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1). 54/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Pinouts and pin description 5. If the device is delivered in an UFBGA176 and the BYPASS_REG pin is set to VDD (Regulator off/internal reset ON mode), then PA0 is used as an internal Reset (active low). Doc ID 022152 Rev 2 55/167 Alternate function mapping AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 USART2_CTS UART4_TX ETH_MII_CRS UART4_RX ETH_MII _RX_CLK ETH_RMII _REF_CLK EVENTOUT ETH_MDIO EVENTOUT Port SYS PA0 TIM1/2 TIM3/4/5 TIM8/9/10/11 TIM2_CH1 TIM2_ETR TIM 5_CH1 TIM8_ETR PA1 TIM2_CH2 TIM5_CH2 PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 USART2_RTS PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 AF9 CAN1/CAN2/ OTG_FS/ OTG_HS TIM12/13/14 USART2_TX USART2_RX PA4 SPI1_NSS SPI3_NSS I2S3_WS OTG_HS_ULPI_D0 AF12 AF13 ETH FSMC/SDIO/ OTG_FS DCMI TIM8_CH1N SPI1_SCK PA6 TIM1_BKIN TIM3_CH1 TIM8_BKIN SPI1_MISO TIM13_CH1 PA7 TIM1_CH1N TIM3_CH2 TIM8_CH1N SPI1_MOSI TIM14_CH1 AF014 AF15 EVENTOUT ETH _MII_COL EVENTOUT OTG_HS_SOF TIM2_CH1 TIM2_ETR MCO1 AF11 USART2_CK PA5 PA8 AF10 DCMI_HSYNC OTG_HS_ULPI_CK EVENTOUT EVENTOUT DCMI_PIXCK ETH_MII _RX_DV ETH_RMII _CRS_DV EVENTOUT EVENTOUT Doc ID 022152 Rev 2 TIM1_CH1 I2C3_SCL USART1_CK PA9 TIM1_CH2 I2C3_SMBA USART1_TX PA10 TIM1_CH3 USART1_RX PA11 TIM1_CH4 USART1_CTS CAN1_RX OTG_FS_DM EVENTOUT PA12 TIM1_ETR USART1_RTS CAN1_TX OTG_FS_DP EVENTOUT PA13 JTMS-SWDIO PA14 JTCK-SWCLK PA15 JTDI OTG_FS_SOF EVENTOUT OTG_FS_ID DCMI_D0 EVENTOUT DCMI_D1 EVENTOUT EVENTOUT EVENTOUT TIM 2_CH1 TIM 2_ETR SPI1_NSS SPI3_NSS/ I2S3S_WS EVENTOUT PB0 TIM1_CH2N TIM3_CH3 TIM8_CH2N OTG_HS_ULPI_D1 ETH _MII_RXD2 PB1 TIM1_CH3N TIM3_CH4 TIM8_CH3N OTG_HS_ULPI_D2 ETH _MII_RXD3 EVENTOUT OTG_HS_INTN EVENTOUT PB2 EVENTOUT PB3 JTDO/ TRACESWO PB4 JTRST SPI1_MISO SPI3_MISO I2C1_SMBA SPI1_MOSI SPI3_MOSI I2S3_SD I2S2_WS TIM3_CH1 TIM3_CH2 PB6 TIM4_CH1 I2C1_SCL PB7 TIM4_CH2 I2C1_SDA PB8 TIM4_CH3 TIM10_CH1 I2C1_SCL PB9 TIM4_CH4 TIM11_CH1 I2C1_SDA TIM2_CH3 I2C2_SCL PB11 TIM2_CH4 I2C2_SDA PB12 TIM1_BKIN I2C2_SMBA PB13 TIM1_CH1N PB14 TIM1_CH2N TIM8_CH2N EVENTOUT I2S3ext_SD EVENTOUT CAN2_RX USART1_TX OTG_HS_ULPI_D7 ETH _PPS_OUT CAN2_TX USART1_RX FSMC_NL CAN1_RX SPI2_NSS I2S2_WS SPI2_SCK I2S2_CK USART3_TX OTG_HS_ULPI_D3 USART3_RX SPI2_MISO ETH _MII_TXD3 CAN1_TX SPI2_NSS I2S2_WS SPI2_SCK I2S2_CK I2S2ext_SD DCMI_D10 OTG_HS_ULPI_D4 USART3_CK CAN2_RX OTG_HS_ULPI_D5 USART3_CTS CAN2_TX OTG_HS_ULPI_D6 USART3_RTS TIM12_CH1 DCMI_D5 EVENTOUT DCMI_VSYNC EVENTOUT SDIO_D4 DCMI_D6 EVENTOUT SDIO_D5 DCMI_D7 EVENTOUT ETH_ MII_RX_ER ETH _MII_TX_EN ETH _RMII_TX_EN ETH _MII_TXD0 ETH _RMII_TXD0 ETH _MII_TXD1 ETH _RMII_TXD1 EVENTOUT EVENTOUT EVENTOUT OTG_HS_ID EVENTOUT EVENTOUT OTG_HS_DM EVENTOUT STM32F405xx, STM32F407xx SPI1_SCK SPI3_SCK I2S3_CK TIM2_CH2 PB5 PB10 Pinouts and pin description 56/167 Table 7. Alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 Port PB15 SYS TIM1/2 RTC_50Hz TIM1_CH3N TIM3/4/5 TIM8/9/10/11 SPI2_MOSI I2S2_SD TIM8_CH3N AF9 AF10 CAN1/CAN2/ OTG_FS/ OTG_HS TIM12/13/14 AF12 AF13 ETH FSMC/SDIO/ OTG_FS DCMI TIM12_CH2 PC0 AF014 OTG_HS_DP EVENTOUT ETH_MDC PC2 SPI2_MISO PC3 SPI2_MOSI I2S2_SD I2S2ext_SD OTG_HS_ULPI_DIR OTG_HS_ULPI_NXT PC4 PC5 PC6 TIM3_CH1 TIM8_CH1 PC7 TIM3_CH2 TIM8_CH2 PC8 MCO2 TIM3_CH3 TIM8_CH3 TIM3_CH4 TIM8_CH4 I2S2_MCK I2S3_MCK I2C3_SDA Doc ID 022152 Rev 2 PC10 PC11 PC12 EVENTOUT ETH _MII_TXD2 EVENTOUT ETH _MII_TX_CLK ETH _RMII_TX_CLK ETH_MII_RXD0 ETH_RMII_RXD0 ETH _MII_RXD1 ETH _RMII_RXD1 EVENTOUT EVENTOUT EVENTOUT USART6_TX SDIO_D6 DCMI_D0 EVENTOUT USART6_RX SDIO_D7 DCMI_D1 EVENTOUT USART6_CK SDIO_D0 DCMI_D2 EVENTOUT SDIO_D1 DCMI_D3 EVENTOUT I2S_CKIN SPI3_SCK/ I2S3S_CK SPI3_MISO I2S3ext_SD/ SPI3_MOSI I2S3_SD AF15 EVENTOUT OTG_HS_ULPI_STP PC1 PC9 AF11 USART3_TX/ UART4_TX SDIO_D2 DCMI_D8 EVENTOUT USART3_RX UART4_RX SDIO_D3 DCMI_D4 EVENTOUT USART3_CK UART5_TX SDIO_CK DCMI_D9 EVENTOUT STM32F405xx, STM32F407xx Table 7. PC13 PC14 PC15 PD0 CAN1_RX FSMC_D2 EVENTOUT PD1 CAN1_TX FSMC_D3 EVENTOUT PD2 TIM3_ETR UART5_RX SDIO_CMD FSMC_CLK DCMI_D11 EVENTOUT USART2_CTS EVENTOUT PD4 USART2_RTS FSMC_NOE EVENTOUT PD5 USART2_TX FSMC_NWE EVENTOUT PD6 USART2_RX FSMC_NWAIT EVENTOUT EVENTOUT PD7 USART2_CK FSMC_NE1/ FSMC_NCE2 PD8 USART3_TX FSMC_D13 EVENTOUT PD9 USART3_RX FSMC_D14 EVENTOUT PD10 USART3_CK FSMC_D15 EVENTOUT USART3_CTS FSMC_A16 EVENTOUT USART3_RTS FSMC_A17 EVENTOUT PD11 57/167 PD12 TIM4_CH1 PD13 TIM4_CH2 FSMC_A18 EVENTOUT PD14 TIM4_CH3 FSMC_D0 EVENTOUT Pinouts and pin description PD3 Alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 AF9 AF10 CAN1/CAN2/ OTG_FS/ OTG_HS TIM12/13/14 AF11 AF12 AF13 ETH FSMC/SDIO/ OTG_FS DCMI AF014 AF15 PD15 TIM4_CH4 FSMC_D1 PE0 TIM4_ETR FSMC_NBL0 DCMI_D2 EVENTOUT FSMC_BLN1 DCMI_D3 EVENTOUT PE1 ETH _MII_TXD3 EVENTOUT PE2 TRACECLK FSMC_A23 PE3 TRACED0 EVENTOUT FSMC_A19 EVENTOUT PE4 TRACED1 FSMC_A20 DCMI_D4 EVENTOUT PE5 TRACED2 TIM9_CH1 FSMC_A21 DCMI_D6 EVENTOUT PE6 TRACED3 TIM9_CH2 FSMC_A22 DCMI_D7 EVENTOUT PE7 TIM1_ETR FSMC_D4 EVENTOUT PE8 TIM1_CH1N FSMC_D5 EVENTOUT Doc ID 022152 Rev 2 PE9 TIM1_CH1 FSMC_D6 EVENTOUT PE10 TIM1_CH2N FSMC_D7 EVENTOUT PE11 TIM1_CH2 FSMC_D8 EVENTOUT PE12 TIM1_CH3N FSMC_D9 EVENTOUT PE13 TIM1_CH3 FSMC_D10 EVENTOUT PE14 TIM1_CH4 FSMC_D11 EVENTOUT PE15 TIM1_BKIN EVENTOUT FSMC_A0 EVENTOUT PF1 I2C2_SCL FSMC_A1 EVENTOUT PF2 I2C2_SMBA FSMC_A2 EVENTOUT PF3 FSMC_A3 EVENTOUT PF4 FSMC_A4 EVENTOUT PF5 FSMC_A5 EVENTOUT PF6 TIM10_CH1 FSMC_NIORD EVENTOUT PF7 TIM11_CH1 FSMC_NREG EVENTOUT PF8 TIM13_CH1 FSMC_NIOWR EVENTOUT PF9 TIM14_CH1 FSMC_CD EVENTOUT PF10 FSMC_INTR PF11 EVENTOUT DCMI_D12 EVENTOUT PF12 FSMC_A6 EVENTOUT PF13 FSMC_A7 EVENTOUT PF14 FSMC_A8 EVENTOUT PF15 FSMC_A9 EVENTOUT STM32F405xx, STM32F407xx FSMC_D12 I2C2_SDA PF0 Pinouts and pin description 58/167 Table 7. Alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 AF9 AF10 CAN1/CAN2/ OTG_FS/ OTG_HS TIM12/13/14 AF11 AF12 AF13 ETH FSMC/SDIO/ OTG_FS DCMI AF014 AF15 PG0 FSMC_A10 EVENTOUT PG1 FSMC_A11 EVENTOUT PG2 FSMC_A12 EVENTOUT PG3 FSMC_A13 EVENTOUT PG4 FSMC_A14 EVENTOUT PG5 FSMC_A15 EVENTOUT PG6 FSMC_INT2 EVENTOUT FSMC_INT3 EVENTOUT PG7 USART6_CK PG8 USART6_RTS PG9 USART6_RX ETH _PPS_OUT Doc ID 022152 Rev 2 ETH _MII_TX_EN ETH _RMII_TX_EN PG11 PG12 USART6_RTS PG13 UART6_CTS PG14 USART6_TX PG15 USART6_CTS EVENTOUT FSMC_NE2/ FSMC_NCE3 FSMC_NCE4_1/ FSMC_NE3 PG10 ETH _MII_TXD0 ETH _RMII_TXD0 ETH _MII_TXD1 ETH _RMII_TXD1 STM32F405xx, STM32F407xx Table 7. EVENTOUT EVENTOUT FSMC_NCE4_2 EVENTOUT FSMC_NE4 EVENTOUT FSMC_A24 EVENTOUT FSMC_A25 EVENTOUT DCMI_D13 EVENTOUT PH0 PH1 PH2 ETH _MII_CRS EVENTOUT PH3 ETH _MII_COL EVENTOUT I2C2_SCL PH5 I2C2_SDA PH6 I2C2_SMBA PH7 I2C3_SCL PH8 I2C3_SDA PH9 I2C3_SMBA OTG_HS_ULPI_NXT EVENTOUT EVENTOUT TIM12_CH1 ETH _MII_RXD2 EVENTOUT ETH _MII_RXD3 EVENTOUT DCMI_HSYNC DCMI_D0 EVENTOUT PH10 TIM5_CH1 DCMI_D1 EVENTOUT PH11 TIM5_CH2 DCMI_D2 EVENTOUT PH12 TIM5_CH3 DCMI_D3 59/167 PH13 TIM8_CH1N PH14 TIM8_CH2N TIM12_CH2 EVENTOUT CAN1_TX EVENTOUT EVENTOUT DCMI_D4 EVENTOUT Pinouts and pin description PH4 Alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 Port SYS TIM1/2 TIM3/4/5 PH15 PI0 TIM8/9/10/11 AF9 AF10 CAN1/CAN2/ OTG_FS/ OTG_HS TIM12/13/14 AF11 AF12 AF13 ETH FSMC/SDIO/ OTG_FS DCMI TIM8_CH3N SPI2_NSS I2S2_WS SPI2_SCK I2S2_CK TIM5_CH4 PI1 I2S2ext_SD AF014 AF15 DCMI_D11 EVENTOUT DCMI_D13 EVENTOUT DCMI_D8 EVENTOUT PI2 TIM8_CH4 SPI2_MISO PI3 TIM8_ETR SPI2_MOSI I2S2_SD DCMI_D9 EVENTOUT DCMI_D10 EVENTOUT PI4 TIM8_BKIN DCMI_D5 EVENTOUT PI5 TIM8_CH1 DCMI_VSYNC EVENTOUT PI6 TIM8_CH2 DCMI_D6 EVENTOUT PI7 TIM8_CH3 DCMI_D7 EVENTOUT Pinouts and pin description 60/167 Table 7. PI8 PI9 CAN1_RX EVENTOUT Doc ID 022152 Rev 2 PI10 PI11 ETH _MII_RX_ER OTG_HS_ULPI_DIR EVENTOUT EVENTOUT STM32F405xx, STM32F407xx STM32F405xx, STM32F407xx 4 Memory map Memory map The memory map is shown in Figure 15. Figure 15. Memory map 2ESERVED !(" 2ESERVED !(" 2ESERVED !(" X&&&& &&&& X% X$&&& &&&& 2ESERVED -BYTE BLOCK #ORTEX -gS INTERNAL PERIPHERALS !(" 2ESERVED -BYTE BLOCK .OT USED -BYTE BLOCK &3-# REGISTERS X X&&& &&&& X X&&& &&&& X X # X&&& &&&& X X &&& X && X X && X X X &&&& X &&&& X X X&&& &&&& X X &&&& !(" X# X"&&& &&&& X! X&&& &&&& X! X"&&& &&&& X! &&& 2ESET CLOCK CONTROLLER 2## 2ESERVED #2# 2ESERVED -BYTE BLOCK &3-# BANK BANK !(" 2ESERVED X # X X X X X && X "&& X && X && X &&& X X # X &&&& X "&& !0" -BYTE BLOCK &3-# BANK BANK %84) 393#&' 2ESERVED X X # X &&& X X "&& X X && X && -BYTE BLOCK 0ERIPHERALS !0" X X&&& &&&& -BYTE BLOCK 32!X X&&& &&&& -BYTE BLOCK #ODE X 2ESERVED 32!- +" ALIASED BY BIT BANDING 32!- +" ALIASED BY BIT BANDING 2ESERVED /PTION "YTES 2ESERVED 3YSTEM MEMORY 2ESERVED ##- DATA 2! +" DATA 32!2ESERVED &LASH 2ESERVED !LIASED TO &LASH SYSTEM MEMORY OR 32!- DEPENDING ON THE "//4 PINS X X&&& &&&& X # X &&&& 2ESERVED X X X &&&& X && X X "&&& X&&& # X&&& # X&&& ! X&&& X X&&& &&&& X&&& # X&&& &&& X&&& !& X&&% &&&& !0" X X &&&& X X&&& &&&& X X& &&&& X X&& &&&& X X& &&&& 2ESERVED X X X && X && !0" X -36 Doc ID 022152 Rev 2 61/167 Electrical characteristics STM32F405xx, STM32F407xx 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.3 V (for the 1.8 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 16. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 17. Figure 16. Pin loading conditions Figure 17. Pin input voltage 34-& PIN # P& 34-& PIN /3#?/54 (I : WHEN USING (3% OR ,3% -36 62/167 Doc ID 022152 Rev 2 6). /3#?/54 (I : WHEN USING (3% OR ,3% -36 STM32F405xx, STM32F407xx 5.1.6 Electrical characteristics Power supply scheme Figure 18. Power supply scheme 6"!4 /54 '0 )/S ). & )/ ,OGIC +ERNEL LOGIC #05 DIGITAL 2!- 6#!0? 6#!0? 6$$ N& & ,EVEL SHIFTER 6"!4 TO 6 6$$ "ACKUP CIRCUITRY /3#+ 24# 7AKEUP LOGIC "ACKUP REGISTERS BACKUP 2!- 0O WER SWI TCH 6OLTAGE REGULATOR 633 &LASH MEMORY "90!33?2%' 0$2?/. 6$$ 6$$! 62%& N& & 2ESET CONTROLLER N& & 62%& 62%& !$# !NALOG 2#S 0,, 633! -36 1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device. 2. To connect BYPASS_REG and PDR_ON pins, refer to Section 2.2.17: Real-time clock (RTC), backup SRAM and backup registers. 3. The two 2.2 F ceramic capacitors should not be connected when the voltage regulator is OFF. 4. The 4.7 F ceramic capacitor must be connected to one of the VDD pin. 5. VDDA=VDD and VSSA=VSS. Doc ID 022152 Rev 2 63/167 Electrical characteristics 5.1.7 STM32F405xx, STM32F407xx Current consumption measurement Figure 19. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 8: Voltage characteristics, Table 9: Current characteristics, and Table 10: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 8. Voltage characteristics Symbol Ratings Min Max VDD-VSS External main supply voltage (including VDDA, VDD)(1) -0.3 4.0 VSS-0.3 VDD+4 VSS-0.3 4.0 Variations between different VDD power pins - 50 Variations between all the different ground pins - 50 Input voltage on five-volt tolerant VIN |VDDx| |VSSX - VSS| VESD(HBM) pin(2) Input voltage on any other pin Electrostatic discharge voltage (human body model) Unit V mV see Section 5.3.14: Absolute maximum ratings (electrical sensitivity) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum value must always be respected. Refer to Table 9 for the values of the maximum allowed injected current. 64/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Table 9. Electrical characteristics Current characteristics Symbol Ratings Max. IVDD Total current into VDD power lines (source)(1) 150 IVSS (1) 150 Total current out of VSS ground lines (sink) IIO Output current sunk by any I/O and control pin 25 Output current source by any I/Os and control pin 25 (3) Injected current on five-volt tolerant I/O IINJ(PIN) (2) IINJ(PIN) Injected current on any other pin (4) mA -5/+0 (4) Total injected current (sum of all I/O and control pins) Unit 5 (5) 25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. Negative injection disturbs the analog performance of the device. See note in Section 5.3.20: 12-bit ADC characteristics. 3. Positive injection is not possible on these I/Os. A negative injection is induced by VINVDD while a negative injection is induced by VIN 25 MHz. Doc ID 022152 Rev 2 71/167 Electrical characteristics STM32F405xx, STM32F407xx 3. When analog peripheral blocks such as (ADCs, DACs, HSE, LSE, HSI,LSI) are on, an additional power consumption should be considered. Table 18. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM (1) Max(2) Typ Symbol Parameter Conditions External clock(3), all peripherals enabled(4) fHCLK TA = 25 C TA = 85 C TA = 105 C 168 MHz 87 102 109 144 MHz 67 80 86 120 MHz 56 69 75 90 MHz 44 56 62 60 MHz 30 42 49 30 MHz 16 28 35 25 MHz 12 24 31 9 20 28 8 MHz 5 17 24 4 MHz 3 15 22 2 MHz 2 14 21 168 MHz 40 54 61 144 MHz 31 43 50 120 MHz 26 38 45 90 MHz 20 32 39 60 MHz 14 26 33 30 MHz 8 20 27 25 MHz 6 18 25 5 16 24 8 MHz 3 15 22 4 MHz 2 14 21 2 MHz 2 14 21 16 IDD Supply current in Run mode External clock(3), all peripherals disabled 16 MHz(5) MHz(5) Unit mA 1. Code and data processing running from SRAM1 using boot pins. 2. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled. 3. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz. 4. When the ADC is on (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part. 5. In this case HCLK = system clock/2. 72/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Electrical characteristics Figure 21. Typical current consumption vs temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF )$$ 25.M! # # # # # # #05 &REQUENCY -(Z -36 Figure 22. Typical current consumption vs temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals ON )$$ 25.M! # # # # # # #05 &REQUENCY -(Z -36 Doc ID 022152 Rev 2 73/167 Electrical characteristics STM32F405xx, STM32F407xx Figure 23. Typical current consumption vs temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF )$$ 25.M! # # # # # # #05 &REQUENCY -(Z -36 Figure 24. Typical current consumption vs temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals ON )$$ 25.M! # # # # # # #05 &REQUENCY -(Z -36 74/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Table 19. Electrical characteristics Typical and maximum current consumption in Sleep mode Max(1) Typ Symbol Parameter Conditions External clock(2), all peripherals enabled(3) IDD Supply current in Sleep mode External clock(2), all peripherals disabled fHCLK TA = 25 C TA = 85 C TA = 105 C 168 MHz 59 77 84 144 MHz 46 61 67 120 MHz 38 53 60 90 MHz 30 44 51 60 MHz 20 34 41 30 MHz 11 24 31 25 MHz 8 21 28 16 MHz 6 18 25 8 MHz 3 16 23 4 MHz 2 15 22 2 MHz 2 14 21 168 MHz 12 27 35 144 MHz 9 22 29 120 MHz 8 20 28 90 MHz 7 19 26 60 MHz 5 17 24 30 MHz 3 16 23 25 MHz 2 15 22 16 MHz 2 14 21 8 MHz 1 14 21 4 MHz 1 13 21 2 MHz 1 13 21 Unit mA 1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled. 2. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz. 3. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). Doc ID 022152 Rev 2 75/167 Electrical characteristics Table 20. STM32F405xx, STM32F407xx Typical and maximum current consumptions in Stop mode Typ Symbol Parameter Supply current in Stop mode with main regulator in Run mode IDD_STOP TA = 25 C TA = 25 C TA = 85 C TA = 105 C Flash in Stop mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.60 1.20 11.00 20.00 Flash in Deep power down mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.55 1.20 11.00 20.00 Flash in Stop mode, low-speed and high-speed Supply current internal RC oscillators and high-speed in Stop mode oscillator OFF (no independent watchdog) with main Flash in Deep power down mode, low-speed regulator in and high-speed internal RC oscillators and Low Power high-speed oscillator OFF (no independent mode watchdog) Table 21. Symbol Conditions Unit mA 0.40 1.10 8.00 15.00 0.35 1.1 8.00 15.00 Typical and maximum current consumptions in Standby mode(1) Parameter Conditions Backup SRAM ON, low-speed oscillator and RTC ON Supply current Backup SRAM OFF, lowIDD_STBY in Standby speed oscillator and RTC ON mode Backup SRAM ON, RTC OFF Backup SRAM OFF, RTC OFF Typ Max TA = 25 C TA = 85 C TA = 105 C VDD = 1.8 V VDD= 2.4 V VDD = 3.3 V 3.0 3.4 4.0 TBD(2) TBD(2) 2.4 2.7 3.3 TBD(2) TBD(2) 2.4 2.6 3.0 12.5(2) 24.8(2) 1.7 1.9 2.2 9.8(2) 19.2(2) 1. TBD stands for "to be defined". 2. Based on characterization, not tested in production. 76/167 Max Doc ID 022152 Rev 2 Unit VDD = 3.6 V A STM32F405xx, STM32F407xx Electrical characteristics Typical and maximum current consumptions in VBAT mode(1) Table 22. Typ Symbol Parameter Max TA = 25 C Conditions TA = 85 C VBAT = VBAT= VBAT = 1.8 V 2.4 V 3.3 V Backup SRAM ON, low-speed oscillator and RTC ON Backup Backup SRAM OFF, low-speed IDD_VBAT domain supply oscillator and RTC ON current Backup SRAM ON, RTC OFF Backup SRAM OFF, RTC OFF TA = 105 C VBAT = 3.6 V 1.29 1.42 1.68 TBD(2) TBD(2) 0.62 0.73 0.96 TBD(2) TBD(2) 0.79 0.10 0.81 0.10 Unit (2) 0.86 9 0.10 5(2) A (2) 16 7(2) 1. TBD stands for "to be defined". 2. Based on characterization, not tested in production. Figure 25. Typical VBAT current consumption (LSE and RTC ON/backup RAM OFF) 3.5 3 IVBAT in (A) 2.5 1.65V 1.8V 2 2V 2.4V 1.5 2.7V 3V 3.3V 1 3.6V 0.5 0 0 10 20 30 40 50 60 70 80 90 100 Temperature in (C) -36 Doc ID 022152 Rev 2 77/167 Electrical characteristics STM32F405xx, STM32F407xx Figure 26. Typical VBAT current consumption (LSE and RTC ON/backup RAM ON) 6 5 IVBAT in (A) 4 1.65V 1.8V 2V 3 2.4V 2.7V 3V 2 3.3V 3.6V 1 0 0 10 20 30 40 50 60 70 80 90 100 Temperature in (C) -36 I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 44: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption measured previously (see Table 24: Peripheral current consumption), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the MCU supply 78/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Electrical characteristics voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DD x f SW x C where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDD is the MCU supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. Doc ID 022152 Rev 2 79/167 Electrical characteristics Table 23. Symbol STM32F405xx, STM32F407xx Switching output I/O current consumption Parameter Conditions(1) I/O toggling frequency (fSW) Typ 2 MHz 0.02 8 MHz 0.14 25 MHz 0.51 50 MHz 0.86 60 MHz 1.30 2 MHz 0.10 8 MHz 0.38 25 MHz 1.18 50 MHz 2.47 60 MHz 2.86 2 MHz 0.17 8 MHz 0.66 25 MHz 1.70 50 MHz 2.65 60 MHz 3.48 2 MHz 0.23 8 MHz 0.95 25 MHz 3.20 50 MHz 4.69 60 MHz 8.06 2 MHz 0.30 8 MHz 1.22 25 MHz 3.90 50 MHz 8.82 60 MHz -(3) VDD = 3.3 V(2) C = CINT VDD = 3.3 V CEXT = 0 pF C = CINT + CEXT+ CS IDDIO I/O switching current VDD = 3.3 V CEXT = 10 pF C = CINT + CEXT+ CS VDD = 3.3 V CEXT = 22 pF C = CINT + CEXT+ CS VDD = 3.3 V CEXT = 33 pF C = CINT + CEXT+ CS 1. CS is the PCB board capacitance including the pad pin. CS = 7 pF (estinated value). 2. This test is performed by cutting the LQFP package pin (pad removal). 3. At 60 MHz, C maximum load is specified 30 pF. 80/167 Doc ID 022152 Rev 2 Unit mA STM32F405xx, STM32F407xx Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 24. The MCU is placed under the following conditions: At startup, all I/O pins are configured as analog pins by firmware. All peripherals are disabled unless otherwise mentioned The code is running from Flash memory and the Flash memory access time is equal to 5 wait states at 168 MHz. The code is running from Flash memory and the Flash memory access time is equal to 4 wait states at 144 MHz, and the power scale mode is set to 2. ART accelerator and Cache off. The given value is calculated by measuring the difference of current consumption - with all peripherals clocked off - with one peripheral clocked on (with only the clock applied) When the peripherals are enabled: HCLK is the system clock, fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2. The typical values are obtained for VDD = 3.3 V and TA= 25 C, unless otherwise specified. Table 24. Peripheral current consumption Peripheral(1) AHB1 168 MHz 144 MHz GPIO A 0.49 0.36 GPIO B 0.45 0.33 GPIO C 0.45 0.34 GPIO D 0.45 0.34 GPIO E 0.47 0.35 GPIO F 0.45 0.33 GPIO G 0.44 0.33 GPIO H 0.45 0.34 GPIO I 0.44 0.33 OTG_HS + ULPI 4.57 3.55 CRC 0.07 0.06 BKPSRAM 0.11 0.08 DMA1 6.15 4.75 DMA2 6.24 4.8 ETH_MAC + ETH_MAC_TX ETH_MAC_RX ETH_MAC_PTP 3.28 2.54 OTG_FS 4.59 3.69 DCMI 1.04 0.80 AHB2 Unit mA mA Doc ID 022152 Rev 2 81/167 Electrical characteristics Table 24. STM32F405xx, STM32F407xx Peripheral current consumption (continued) Peripheral(1) AHB3 168 MHz 144 MHz FSMC 2.18 1.67 TIM2 0.80 0.61 TIM3 0.58 0.44 TIM4 0.62 0.48 TIM5 0.79 0.61 TIM6 0.15 0.11 TIM7 0.16 0.12 TIM12 0.33 0.26 TIM13 0.27 0.21 TIM14 0.27 0.21 PWR 0.04 0.03 USART2 0.17 0.13 USART3 0.17 0.13 UART4 0.17 0.13 UART5 0.17 0.13 I2C1 0.17 0.13 I2C2 0.18 0.13 APB1 I2C3 0.18 0.13 SPI2/I2S2 (2) 0.17/0.16 0.13/0.12 SPI3/I2S3 (2) 0.16/0.14 0.12/0.12 CAN1 0.27 0.21 CAN2 0.26 0.20 DAC 0.14 0.10 (3) 0.91 0.89 2(4) 0.91 0.89 DAC channel 1 and 2(3)(4) 1.69 1.68 WWDG 0.04 0.04 DAC channel 1 DAC channel 82/167 Doc ID 022152 Rev 2 Unit mA STM32F405xx, STM32F407xx Table 24. Electrical characteristics Peripheral current consumption (continued) Peripheral(1) 168 MHz 144 MHz SDIO 0.64 0.54 TIM1 1.47 1.14 TIM8 1.58 1.22 TIM9 0.68 0.54 TIM10 0.45 0.36 TIM11 0.47 0.38 (5) 2.20 2.10 ADC2(5) 2.04 1.93 (5) 2.10 2.00 SPI1 0.14 0.12 USART1 0.34 0.27 USART6 0.34 0.28 APB2 ADC1 ADC3 Unit mA 1. HSE oscillator with 4 MHz crysta) and PLL are on. 2. I2SMOD bit set in SPI_I2SCFGR register, and then the I2SE bit set to enable I2S peripheral. 3. EN1 bit is set in DAC_CR register. 4. EN2 bit is set in DAC_CR register. 5. ADON bit set in ADC_CR2 register. 5.3.7 Wakeup time from low-power mode The wakeup times given in Table 25 is measured on a wakeup phase with a 16 MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: Stop or Standby mode: the clock source is the RC oscillator Sleep mode: the clock source is the clock that was set before entering Sleep mode. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 11. Table 25. Low-power mode wakeup timings Symbol tWUSLEEP(2) tWUSTOP(2) tWUSTDBY(2)(3) Min(1) Typ(1) Max(1) Unit Wakeup from Sleep mode - 1 - s Wakeup from Stop mode (regulator in Run mode) - 13 - Wakeup from Stop mode (regulator in low power mode) - 17 40 Wakeup from Stop mode (regulator in low power mode and Flash memory in Deep power down mode) - 110 - 260 375 480 Parameter Wakeup from Standby mode s s 1. Based on characterization, not tested in production. 2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction. 3. tWUSTDBY minimum and maximum values are given at 105 C and -45 C, respectively. Doc ID 022152 Rev 2 83/167 Electrical characteristics 5.3.8 STM32F405xx, STM32F407xx External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 26 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 11. Table 26. High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit 1 8 50 MHz fHSE_ext External user clock source frequency(1) VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD tw(HSE) tw(HSE) OSC_IN high or low time(1) 5 - - tr(HSE) tf(HSE) OSC_IN rise or fall time(1) - - 10 OSC_IN input capacitance(1) - 5 - pF 45 - 55 % - - 1 A Cin(HSE) ns DuCy(HSE) Duty cycle IL V VSS VIN VDD OSC_IN Input leakage current 1. Guaranteed by design, not tested in production. Low-speed external user clock generated from an external source The characteristics given in Table 27 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 11. Table 27. Low-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit - 32.768 1000 kHz fLSE_ext User External clock source frequency(1) VLSEH OSC32_IN input pin high level voltage 0.7VDD - VDD VLSEL OSC32_IN input pin low level voltage VSS - 0.3VDD tw(LSE) tf(LSE) OSC32_IN high or low time(1) 450 - - tr(LSE) tf(LSE) OSC32_IN rise or fall time(1) - - 50 OSC32_IN input capacitance(1) - 5 - pF 30 - 70 % - - 1 A Cin(LSE) DuCy(LSE) IL ns Duty cycle OSC32_IN Input leakage current VSS VIN VDD 1. Guaranteed by design, not tested in production. 84/167 V Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Electrical characteristics Figure 27. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) t tW(HSE) tW(HSE) THSE External clock source fHSE_ext OSC _IN IL STM32F ai17528 Figure 28. Low-speed external clock source AC timing diagram VLSEH 90% VLSEL 10% tr(LSE) tf(LSE) tW(LSE) OSC32_IN IL tW(LSE) t TLSE External clock source fLSE_ext STM32F ai17529 High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 28. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Doc ID 022152 Rev 2 85/167 Electrical characteristics Table 28. Symbol STM32F405xx, STM32F407xx HSE 4-26 MHz oscillator characteristics(1) (2) Min Typ Max Unit Oscillator frequency 4 - 26 MHz RF Feedback resistor - 200 - k C Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) RS = 30 - 15 - pF i2 HSE driving current VDD = 3.3 V, VIN = VSS with 30 pF load - - 1 mA gm Oscillator transconductance Startup 5 - - mA/V VDD is stabilized - 2 - ms fOSC_IN tSU(HSE(4) Parameter Conditions Startup time 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization, not tested in production. 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 29). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. Figure 29. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 fHSE OSC_IN 8 MH z resonator CL2 REXT(1) RF OSC_OU T Bias controlled gain STM32F ai17530 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 29. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). 86/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Table 29. Electrical characteristics LSE oscillator characteristics (fLSE = 32.768 kHz) (1)(2) Symbol Parameter Conditions RF Feedback resistor C(3) Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(4) I2 LSE driving current gm Oscillator Transconductance tSU(LSE)(5) Min Typ Max Unit - TBD - M RS = 30 k - - TBD pF VDD = 3.3 V, VIN = VSS - - TBD A TBD - - A/V - TBD - s startup time VDD is stabilized 1. Based on characterization, not tested in production. 2. TBD stands for "to be defined". 3. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for ST microcontrollers". 4. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details 5. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Note: For CL1 and CL2 it is recommended to use high-quality external ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator (see Figure 30). CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF, then CL1 = CL2 = 8 pF. Figure 30. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 fLSE OSC32_IN 32.768 kH z resonator CL2 RF Bias controlled gain OSC32_OU T STM32F ai17531 Doc ID 022152 Rev 2 87/167 Electrical characteristics 5.3.9 STM32F405xx, STM32F407xx Internal clock source characteristics The parameters given in Table 30 and Table 31 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 11. High-speed internal (HSI) RC oscillator Low-speed internal (LSI) RC oscillator Table 30. Symbol HSI oscillator characteristics (1) Parameter Conditions Min Typ Max Unit - 16 - MHz - - 1 % TA = -40 to 105 C -8 - 4.5 % TA = -10 to 85 C -4 - 4 % TA = 25 C -1 - 1 % HSI oscillator startup time - 2.2 4 s HSI oscillator power consumption - 60 80 A Frequency fHSI User-trimmed with the RCC_CR register(2) Accuracy of the HSI oscillator Factorycalibrated ACCHSI tsu(HSI)(3) IDD(HSI) 1. VDD = 3.3 V, TA = -40 to 105 C unless otherwise specified. 2. Refer to application note AN2868 "STM32F10xxx internal RC oscillator (HSI) calibration" available from the ST website www.st.com. 3. Guaranteed by design, not tested in production. Table 31. LSI oscillator characteristics (1) Symbol fLSI(2) tsu(LSI) (3) IDD(LSI)(3) Parameter Min Typ Max Unit 17 32 47 kHz LSI oscillator startup time - 15 40 s LSI oscillator power consumption - 0.4 0.6 A Frequency 1. VDD = 3 V, TA = -40 to 105 C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production. 88/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Electrical characteristics Figure 31. ACCLSI versus temperature MAX AVG MIN .ORMALIZED DEVIATI ON 4EMPERAT URE # -36 5.3.10 PLL characteristics The parameters given in Table 32 and Table 33 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 11. Table 32. Symbol Main PLL characteristics Parameter fPLL_IN PLL input clock(1) fPLL_OUT PLL multiplier output clock fPLL48_OUT 48 MHz PLL multiplier output clock fVCO_OUT PLL VCO output tLOCK PLL lock time Conditions Min Typ Max Unit 0.95(2) 1 2.10 MHz 24 - 168 MHz - 48 - MHz 192 - 432 MHz VCO freq = 192 MHz 75 - 200 VCO freq = 432 MHz 100 - 300 s Doc ID 022152 Rev 2 89/167 Electrical characteristics Table 32. Symbol STM32F405xx, STM32F407xx Main PLL characteristics (continued) Parameter Conditions Min Typ Max RMS - 25 - peak to peak - 150 - RMS - 15 - peak to peak - 200 - Main clock output (MCO) for RMII Ethernet Cycle to cycle at 50 MHz on 1000 samples - 32 - Main clock output (MCO) for MII Ethernet Cycle to cycle at 25 MHz on 1000 samples - 40 - Bit Time CAN jitter Cycle to cycle at 1 MHz on 1000 samples - 330 - IDD(PLL)(4) PLL power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLL)(4) PLL power consumption on VDDA VCO freq = 192 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA Cycle-to-cycle jitter System clock 120 MHz Period Jitter (3) Jitter Unit ps 1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S. 2. Guaranteed by design, not tested in production. 3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%. 4. Based on characterization, not tested in production. Table 33. Symbol PLLI2S (audio PLL) characteristics(1) Parameter fPLLI2S_IN PLLI2S input clock(2) fPLLI2S_OUT PLLI2S multiplier output clock fVCO_OUT PLLI2S VCO output tLOCK PLLI2S lock time Conditions Min Typ Max Unit 0.95(3) 1 2.10 MHz - - 216 MHz 192 - 432 MHz VCO freq = 192 MHz 75 - 200 VCO freq = 432 MHz 100 - 300 RMS - 90 - peak to peak - 280 - ps TBD - TBD ps - 400 - ps s Cycle to cycle at 12,343 MHz on 48KHz period, N=432, P=4, R=5 Master I2S clock jitter Average frequency of 12,343 MHz N = 432, P = 4, R = 5 on 256 samples (4) Jitter WS I2S clock jitter 90/167 Cycle to cycle at 48 KHz on 1000 samples Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Table 33. Electrical characteristics PLLI2S (audio PLL) characteristics(1) (continued) Symbol Parameter Conditions IDD(PLLI2S)(5) PLLI2S power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz IDDA(PLLI2S)(5) PLLI2S power consumption on VDDA VCO freq = 192 MHz VCO freq = 432 MHz Min Typ Max Unit 0.15 0.45 - 0.40 0.75 mA - 0.40 0.85 mA 0.30 0.55 1. TBD stands for "to be defined". 2. Take care of using the appropriate division factor M to have the specified PLL input clock values. 3. Guaranteed by design, not tested in production. 4. Value given with main PLL running. 5. Based on characterization, not tested in production. Doc ID 022152 Rev 2 91/167 Electrical characteristics 5.3.11 STM32F405xx, STM32F407xx PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 40: EMI characteristics). It is available only on the main PLL. Table 34. SSCG parameters constraint Symbol Parameter Min Typ Max(1) Unit fMod Modulation frequency - - 10 KHz md Peak modulation depth 0.25 - 2 % - 215 - MODEPER * INCSTEP - -1 1. Guaranteed by design, not tested in production. Equation 1 The frequency modulation period (MODEPER) is given by the equation below: MODEPER = round [ f PLL_IN ( 4 x fMod ) ] fPLL_IN and fMod must be expressed in Hz. As an example: If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by equation 1: 6 3 MODEPER = round [ 10 ( 4 x 10 ) ] = 25 Equation 2 Equation 2 allows to calculate the increment step (INCSTEP): INCSTEP = round [ ( ( 2 15 - 1 ) x md x f VCO_OUT ) ( 100 x 5 x MODEPER ) ] fVCO_OUT must be expressed in MHz. With a modulation depth (md) = 2 % (4 % peak to peak), and fVCO_OUT = 240 (in MHz): INCSTEP = round [ ( ( 2 15 - 1 ) x 2 x 240 ) ( 100 x 5 x 25 ) ] = 1258md(quantitazed)% An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of MODPER and INCSTEP. As a result, the achieved modulation depth is quantized. The percentage quantized modulation depth is given by the following formula: md quantized % = ( MODEPER x INCSTEP x 100 x 5 ) ( ( 2 15 - 1 ) x f VCO_OUT ) As a result: md quantized % = ( 25 x 1258 x 100 x 5 ) ( ( 2 15 - 1 ) x 240 ) = 1.99954%(peak) The error in modulation depth is consequently: 2.0 - 1.99954 = 0.00046%. 92/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Electrical characteristics Figure 32 and Figure 33 show the main PLL output clock waveforms in center spread and down spread modes, where: F0 is fPLL_OUT nominal. Tmode is the modulation period. md is the modulation depth. Figure 32. PLL output clock waveforms in center spread mode &REQUENCY 0,,?/54 MD & MD TMODE 4IME TMODE AI Figure 33. PLL output clock waveforms in down spread mode &REQUENCY 0,,?/54 & MD TMODE 4IME TMODE AI 5.3.12 Memory characteristics Flash memory The characteristics are given at TA = -40 to 105 C unless otherwise specified. The devices are shipped to customers with the Flash memory erased. Table 35. Symbol IDD Flash memory characteristics(1) Parameter Supply current Conditions Min Max Unit Read mode fHCLK = 168 MHz with 5 wait states, VDD = 3.3 V - 100 mA Write / Erase modes fHCLK = 168 MHz, VDD = 3.3 V - TBD mA Doc ID 022152 Rev 2 93/167 Electrical characteristics STM32F405xx, STM32F407xx 1. TBD stands for "to be defined". Table 36. Symbol tprog Flash memory programming Word programming time tERASE16KB Sector (16 KB) erase time tERASE64KB Sector (64 KB) erase time tERASE128KB Sector (128 KB) erase time tME Vprog Conditions Min(1) Typ Max(1) Unit Program/erase parallelism (PSIZE) = x 8/16/32 - 16 100(2) Program/erase parallelism (PSIZE) = x 8 - 400 800 Program/erase parallelism (PSIZE) = x 16 - 300 600 Program/erase parallelism (PSIZE) = x 32 - 250 500 Program/erase parallelism (PSIZE) = x 8 - 1200 2400 Program/erase parallelism (PSIZE) = x 16 - 700 1400 Program/erase parallelism (PSIZE) = x 32 - 550 1100 Program/erase parallelism (PSIZE) = x 8 - 2 4 Program/erase parallelism (PSIZE) = x 16 - 1.3 2.6 Program/erase parallelism (PSIZE) = x 32 - 1 2 Program/erase parallelism (PSIZE) = x 8 - 16 32 Program/erase parallelism (PSIZE) = x 16 - 11 21 Program/erase parallelism (PSIZE) = x 32 - 8 16 32-bit program operation 2.7 - 3.6 V 16-bit program operation 2.1 - 3.6 V 8-bit program operation 1.8 - 3.6 V Parameter Mass erase time Programming voltage 1. Based on characterization, not tested in production. 2. The maximum programming time is measured after 100K erase operations. 94/167 Doc ID 022152 Rev 2 s ms ms s s STM32F405xx, STM32F407xx Electrical characteristics Flash memory programming with VPP(1) Table 37. Min(1) Typ Max(2) Double word programming - 16 100(3) tERASE16KB Sector (16 KB) erase time - TBD - tERASE64KB Sector (64 KB) erase time - TBD - - TBD - - 6.8 - 2.7 - 3.6 V Symbol Parameter tprog Conditions tERASE128KB Sector (128 KB) erase time tME Mass erase time TA = 0 to +40 C Unit s Vprog Programming voltage VPP VPP voltage range 7 - 9 V IPP Minimum current sunk on the VPP pin 10 - - mA - - 1 hour tVPP(4) Cumulative time during which VPP is applied 1. TBD stands for "to be defined". 2. Guaranteed by design, not tested in production. 3. The maximum programming time is measured after 100K erase operations. 4. VPP should only be connected during programming/erasing. Table 38. Flash memory endurance and data retention Value Symbol NEND tRET Parameter Endurance Data retention Conditions Min(1) TA = -40 to +85 C (6 suffix versions) TA = -40 to +105 C (7 suffix versions) 10 1 kcycle(2) at TA = 85 C 30 1 kcycle(2) at TA = 105 C 10 10 kcycles (2) at TA = 55 C Unit kcycles Years 20 1. Based on characterization, not tested in production. 2. Cycling performed over the whole temperature range. 5.3.13 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. Doc ID 022152 Rev 2 95/167 Electrical characteristics STM32F405xx, STM32F407xx A device reset allows normal operations to be resumed. The test results are given in Table 39. They are based on the EMS levels and classes defined in application note AN1709. Table 39. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD VDD = 3.3 V, LQFP176, TA = +25 C, Voltage limits to be applied on any I/O pin to fHCLK = 168 MHz, conforms to induce a functional disturbance IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, LQFP176, TA = +25 C, fHCLK = 168 MHz, conforms to IEC 61000-4-2 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: Corrupted program counter Unexpected reset Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). 96/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Electrical characteristics Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC(R) code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. Table 40. Symbol EMI characteristics Parameter Max vs. [fHSE/fCPU] Monitored frequency band Conditions Unit 25/168 MHz VDD = 3.3 V, TA = 25 C, LQFP176 package, conforming to SAE J1752/3 EEMBC, code running from Flash with ART accelerator enabled SEMI 5.3.14 0.1 to 30 MHz 32 30 to 130 MHz 25 130 MHz to 1GHz 29 SAE EMI Level 4 0.1 to 30 MHz 19 30 to 130 MHz 16 130 MHz to 1GHz 18 SAE EMI level 3.5 dBV - Peak level VDD = 3.3 V, TA = 25 C, LQFP176 package, conforming to SAE J1752/3 EEMBC, code running from Flash with ART accelerator and clock dithering enabled dBV - Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 41. Symbol ESD absolute maximum ratings Conditions Class Maximum value(1) TA = +25 C conforming to JESD22-A114 2 2000(2) Ratings VESD(HBM) Electrostatic discharge voltage (human body model) VESD(CDM) Electrostatic discharge voltage (charge device model) Unit V TA = +25 C conforming to JESD22-C101 II 500 1. Based on characterization results, not tested in production. 2. On VBAT pin, VESD(HBM) is limited to 1000 V. Doc ID 022152 Rev 2 97/167 Electrical characteristics STM32F405xx, STM32F407xx Static latchup Two complementary static tests are required on six parts to assess the latchup performance: A supply overvoltage is applied to each power supply pin A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latchup standard. Table 42. Electrical sensitivities Symbol LU 5.3.15 Parameter Static latch-up class Conditions Class TA = +105 C conforming to JESD78A II level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibilty to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation). The test results are given in Table 43. Table 43. I/O current injection susceptibility Functional susceptibility Symbol IINJ 98/167 Description Negative injection Positive injection Injected current on all FT pins -5 +0 Injected current on any other pin -5 +5 Unit mA Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx 5.3.16 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 44 are derived from tests performed under the conditions summarized in Table 11. All I/Os are CMOS and TTL compliant. Table 44. I/O static characteristics Symbol VIL VIH(1) VIL Parameter Conditions Typ Max VSS-0.3 - 0.8 2.0 - VDD+0.3 2.0 - 5.5 VSS-0.3 - 0.3VDD - 3.6(4) - 5.2(4) - 5.5(4) - 200 - 5% VDD(4) - - VSS VIN VDD - - 1 VIN = 5 V - - 3 30 40 50 8 11 15 Input low level voltage TTa/TC(2) I/O input high level voltage (3) FT TTL ports 2.7 V VDD 3.6 V I/O input high level voltage Input low level voltage CMOS ports 1.8 V VDD 3.6 V TTa/TC I/O input high level voltage VIH(1) Min 0.7VDD FT I/O input high level voltage CMOS ports 2.0 V VDD 3.6 V I/O Schmitt trigger voltage hysteresis(5) Vhys IO FT Schmitt trigger voltage hysteresis(5) I/O input leakage current (6) Ilkg RPU I/O FT input leakage current Weak pull-up equivalent resistor(7) (6) All pins except for PA10 and PB12 Unit V mV A VIN = VSS PA10 and PB12 k RPD Weak pull-down equivalent resistor All pins except for PA10 and PB12 PA10 and PB12 CIO(8) 30 40 50 8 11 15 VIN = VDD I/O pin capacitance 5 pF 1. If VIH maximum value cannot be respected, the injection current must be limited externally to IINJ(PIN) maximum value. 2. TTa = 3.3 V tolerant I/O directly connected to ADC; TC = standard 3.3 V I/O. 3. FT = 5 V tolerant. 4. With a minimum of 100 mV. 5. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production. 6. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins. 7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order). 8. Guaranteed by design, not tested in production. Doc ID 022152 Rev 2 99/167 Electrical characteristics STM32F405xx, STM32F407xx All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. Output driving current The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or source 20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2. In particular: The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 9). The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 9). Output voltage levels Unless otherwise specified, the parameters given in Table 45 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 11. All I/Os are CMOS and TTL compliant. Table 45. Symbol VOL(2) VOH (3) VOL (2) VOH (3) Output voltage characteristics(1) Parameter Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 8 pins are sourced at same time Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL(2)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL(2)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time Conditions Min Max TTL port IIO = +8 mA 2.7 V < VDD < 3.6 V - 0.4 CMOS port IIO =+ 8mA 2.7 V < VDD < 3.6 V IIO = +20 mA 2.7 V < VDD < 3.6 V IIO = +6 mA 2 V < VDD < 2.7 V Unit V VDD-0.4 - - 0.4 V 2.4 - - 1.3 V VDD-1.3 - - 0.4 V VDD-0.4 - 1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED). 2. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 9 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 9 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 4. Based on characterization data, not tested in production. 100/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 34 and Table 46, respectively. Unless otherwise specified, the parameters given in Table 46 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 11. Table 46. OSPEEDRy [1:0] bit value(1) I/O AC characteristics(1)(2)(3) Symbol Parameter Conditions fmax(IO)out Maximum frequency(4) 00 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time fmax(IO)out Maximum frequency(4) 01 Min Typ Max Unit CL = 50 pF, VDD > 2.70 V - - 2 CL = 50 pF, VDD > 1.8 V - - 2 CL = 10 pF, VDD > 2.70 V - - TBD CL = 10 pF, VDD > 1.8 V - - TBD - - TBD MHz CL = 50 pF, VDD = 1.8 V to 3.6 V ns - - TBD CL = 50 pF, VDD > 2.70 V - - 25 CL = 50 pF, VDD > 1.8 V - - 12.5(5) CL = 10 pF, VDD > 2.70 V - - 50(5) CL = 10 pF, VDD > 1.8 V - - TBD Output high to low level fall time CL = 50 pF, VDD < 2.7 V - - TBD tf(IO)out CL = 10 pF, VDD > 2.7 V - - TBD CL = 50 pF, VDD < 2.7 V - - TBD tr(IO)out Output low to high level rise time CL = 10 pF, VDD > 2.7 V - - TBD CL = 40 pF, VDD > 2.70 V - - 50(5) CL = 40 pF, VDD > 1.8 V - - 25 CL = 10 pF, VDD > 2.70 V - - 100(5) CL = 10 pF, VDD > 1.8 V - - TBD CL = 50 pF, 2.4 < VDD < 2.7 V - - TBD CL = 10 pF, VDD > 2.7 V - - TBD CL = 50 pF, 2.4 < VDD < 2.7 V - - TBD CL = 10 pF, VDD > 2.7 V - - TBD fmax(IO)out Maximum frequency(4) 10 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time Doc ID 022152 Rev 2 MHz ns MHz ns 101/167 Electrical characteristics Table 46. OSPEEDRy [1:0] bit value(1) STM32F405xx, STM32F407xx I/O AC characteristics(1)(2)(3) (continued) Symbol Parameter Conditions Fmax(IO)out Maximum frequency(4) 11 - tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time tEXTIpw Pulse width of external signals detected by the EXTI controller Min Typ Max CL = 30 pF, VDD > 2.70 V - - 100(5) CL = 30 pF, VDD > 1.8 V - - 50(5) CL = 10 pF, VDD > 2.70 V - - 200(5) CL = 10 pF, VDD > 1.8 V - - TBD CL = 20 pF, 2.4 < VDD < 2.7 V - - TBD CL = 10 pF, VDD > 2.7 V - - TBD CL = 20 pF, 2.4 < VDD < 2.7 V - - TBD CL = 10 pF, VDD > 2.7 V - - TBD 10 - - 2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F20/21xxx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register. 3. TBD stands for "to be defined". 4. The maximum frequency is defined in Figure 34. 5. For maximum frequencies above 50 MHz, the compensation cell should be used. Figure 34. I/O AC characteristics definition 90% 10% 50% 90% 10% EXT ERNAL OUTPUT ON 50pF tr(I O)out tr(I O)out T Maximum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131 102/167 Doc ID 022152 Rev 2 MHz ns 1. Based on characterization data, not tested in production. 50% Unit ns STM32F405xx, STM32F407xx 5.3.17 Electrical characteristics NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 44). Unless otherwise specified, the parameters given in Table 47 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 11. Table 47. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit VIL(NRST)(1) NRST Input low level voltage -0.5 - 0.8 VIH(NRST)(1) NRST Input high level voltage 2 - VDD+0.5 Vhys(NRST) NRST Schmitt trigger voltage hysteresis - 200 - mV 30 40 50 k - - 100 ns Weak pull-up equivalent resistor(2) RPU VF(NRST) V (1) VIN = VSS NRST Input filtered pulse VNF(NRST)(1) NRST Input not filtered pulse VDD > 2.7 V 300 - - ns TNRST_OUT Generated reset pulse duration Internal Reset source 20 - - s 1. Guaranteed by design, not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). Figure 35. Recommended NRST pin protection 6$$ %XTERNAL RESET CIRCUIT .234 205 )NTERNAL 2ESET &ILTER & 34-&XXX AIC 2. The reset network protects the device against parasitic resets. 3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 47. Otherwise the reset is not taken into account by the device. Doc ID 022152 Rev 2 103/167 Electrical characteristics 5.3.18 STM32F405xx, STM32F407xx TIM timer characteristics The parameters given in Table 48 and Table 49 are guaranteed by design. Refer to Section 5.3.16: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 48. Symbol tres(TIM) Characteristics of TIMx connected to the APB1 domain(1) Parameter Timer resolution time Conditions AHB/APB1 prescaler distinct from 1, fTIMxCLK = 84 MHz AHB/APB1 prescaler = 1, fTIMxCLK = 42 MHz fEXT ResTIM tCOUNTER Min Max Unit 1 - tTIMxCLK 11.9 - ns 1 - tTIMxCLK 23.8 - ns Timer external clock frequency on CH1 to CH4 0 fTIMxCLK/2 MHz 0 42 MHz Timer resolution - 16/32 bit 65536 tTIMxCLK 780 s - tTIMxCLK 51130563 s - 65536 x 65536 tTIMxCLK - 51.1 s 16-bit counter clock period 1 when internal clock is fTIMxCLK = 84 MHz 0.0119 selected APB1= 42 MHz 32-bit counter clock period 1 when internal clock is 0.0119 selected tMAX_COUNT Maximum possible count 1. TIMx is used as a general term to refer to the TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, and TIM12 timers. 104/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Table 49. Symbol tres(TIM) Electrical characteristics Characteristics of TIMx connected to the APB2 domain(1) Parameter Timer resolution time Conditions AHB/APB2 prescaler distinct from 1, fTIMxCLK = 168 MHz AHB/APB2 prescaler = 1, fTIMxCLK = 84 MHz fEXT ResTIM tCOUNTER Timer external clock frequency on CH1 to CH4 Timer resolution fTIMxCLK = 168 MHz 16-bit counter clock APB2 = 84 MHz period when internal clock is selected tMAX_COUNT Maximum possible count Min Max Unit 1 - tTIMxCLK 5.95 - ns 1 - tTIMxCLK 11.9 - ns 0 fTIMxCLK/2 MHz 0 84 MHz - 16 bit 1 65536 tTIMxCLK - 32768 tTIMxCLK 1. TIMx is used as a general term to refer to the TIM1, TIM8, TIM9, TIM10, and TIM11 timers. 5.3.19 Communications interfaces I2C interface characteristics Unless otherwise specified, the parameters given in Table 50 are derived from tests performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 11. The STM32F405xx and STM32F407xx I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 50. Refer also to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Doc ID 022152 Rev 2 105/167 Electrical characteristics Table 50. STM32F405xx, STM32F407xx I2C characteristics Standard mode I2C(1) Symbol Fast mode I2C(1)(2) Parameter Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - - (4) s (3) 900(3) th(SDA) SDA data hold time tr(SDA) tr(SCL) SDA and SCL rise time - 1000 20 + 0.1Cb 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 th(STA) Start condition hold time 4.0 - 0.6 - tsu(STA) Repeated Start condition setup time 4.7 - 0.6 - tsu(STO) Stop condition setup time 4.0 - 0.6 - s tw(STO:STA) Stop to Start condition time (bus free) 4.7 - 1.3 - s Cb Capacitive load for each bus line - 400 - 400 pF 0 0 ns s 1. Guaranteed by design, not tested in production. 2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to achieve fast mode I2C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode clock. 3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. 4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 106/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Electrical characteristics Figure 36. I2C bus AC waveforms and measurement circuit 6$$ K 6$$ K )# BUS 34-&XX 3$! 3#, 3 4!24 2%0%!4%$ 3 4!24 3 4!24 TSU34! 3$! TF3$! TR3$! TH34! TSU3$! TW3#,, 3#, TW3#,( TR3#, TW34/34! 3 4/0 TH3$! TSU34/ TF3#, AIB 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 51. SCL frequency (fPCLK1= 42 MHz.,VDD = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.7 k 400 0x8019 300 0x8021 200 0x8032 100 0x0096 50 0x012C 20 0x02EE 2 1. RP = External pull-up resistance, fSCL = I C speed, 2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the tolerance on the achieved speed 2%. These variations depend on the accuracy of the external components used to design the application. Doc ID 022152 Rev 2 107/167 Electrical characteristics STM32F405xx, STM32F407xx I2S - SPI interface characteristics Unless otherwise specified, the parameters given in Table 52 for SPI or in Table 53 for I2S are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 11. Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 52. Symbol fSCK 1/tc(SCK) SPI characteristics(1)(2) Parameter Conditions Min Max Master mode - 37.5 Slave mode - 37.5 - 8 ns % SPI clock frequency Unit MHz tr(SCL) tf(SCL) SPI clock rise and fall time Capacitive load: C = 30 pF DuCy(SCK) SPI slave input clock duty cycle Slave mode 30 70 tsu(NSS)(3) NSS setup time Slave mode 4tPCLK - th(NSS)(3) NSS hold time Slave mode 2tPCLK - TBD TBD Master mode 5 - Slave mode 5 - Master mode 5 - Slave mode 4 - (3) tw(SCLH) tw(SCLL)(3) SCK high and low time Master mode, fPCLK = TBD MHz tsu(MI) (3) tsu(SI)(3) Data input setup time th(MI) (3) th(SI)(3) Data input hold time ta(SO)(3)(4) Data output access time Slave mode, fPCLK = 20 MHz 0 3 tPCLK tdis(SO)(3)(5) Data output disable time Slave mode 2 10 tv(SO) (3)(1) Data output valid time Slave mode (after enable edge) - 25 (3)(1) Data output valid time Master mode (after enable edge) - 5 Slave mode (after enable edge) 15 - Master mode (after enable edge) 2 - tv(MO) th(SO)(3) th(MO)(3) ns Data output hold time 1. Remapped SPI1 characteristics to be determined. 2. TBD stands for "to be defined". 3. Based on characterization, not tested in production. 4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z 108/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Electrical characteristics Figure 37. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) th(NSS) SCK Input tSU(NSS) CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 38. SPI timing diagram - slave mode and CPHA = 1(1) NSS input SCK Input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tc(SCK) tw(SCKH) tw(SCKL) tv(SO) ta(SO) MISO OUT P UT MS B O UT tsu(SI) MOSI I NPUT th(NSS) th(SO) BI T6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) B I T1 IN M SB IN LSB IN ai14135 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Doc ID 022152 Rev 2 109/167 Electrical characteristics STM32F405xx, STM32F407xx Figure 39. SPI timing diagram - master mode(1) High NSS input SCK Input SCK Input tc(SCK) CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTUT M SB OUT B I T1 OUT tv(MO) LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 110/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Table 53. Electrical characteristics I2S characteristics(1) Symbol Parameter Conditions Min Max TBD TBD Slave 0 TBD - TBD Master fCK 1/tc(CK) I2S clock frequency tr(CK) tf(CK) I2S clock rise and fall time capacitive load CL = 50 pF tv(WS) (2) WS valid time Master TBD - th(WS) (2) WS hold time Master TBD - WS setup time Slave TBD - WS hold time Slave TBD - tw(CKH) tw(CKL) (2) CK high and low time Master fPCLK= TBD, presc = TBD TBD - tsu(SD_MR) (2) tsu(SD_SR) (2) Data input setup time Master receiver Slave receiver TBD TBD - th(SD_MR)(2)(3) th(SD_SR) (2)(3) Data input hold time Master receiver Slave receiver TBD TBD - Data input hold time Master fPCLK = TBD Slave fPCLK = TBD TBD TBD - Slave transmitter (after enable edge) - TBD fPCLK = TBD - TBD Slave transmitter (after enable edge) TBD - Master transmitter (after enable edge) - TBD fPCLK = TBD TBD TBD Master transmitter (after enable edge) TBD - tsu(WS) th(WS) (2) (2) (2) th(SD_MR) (2) th(SD_SR) (2) tv(SD_ST) (2)(3) Data output valid time th(SD_ST) (2) Data output hold time tv(SD_MT) (2)(3) Data output valid time th(SD_MT) (2) Data output hold time Unit MHz ns 1. TBD stands for "to be defined". 2. Based on design simulation and/or characterization results, not tested in production. 3. Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns. Doc ID 022152 Rev 2 111/167 Electrical characteristics STM32F405xx, STM32F407xx Figure 40. I2S slave timing diagram (Philips protocol)(1) CK Input tc(CK) CPOL = 0 CPOL = 1 tw(CKH) th(WS) tw(CKL) WS input tv(SD_ST) tsu(WS) SDtransmit LSB transmit(2) MSB transmit Bitn transmit tsu(SD_SR) LSB receive(2) SDreceive th(SD_ST) LSB transmit th(SD_SR) MSB receive Bitn receive LSB receive ai14881b 1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 41. I2S master timing diagram (Philips protocol)(1) tf(CK) tr(CK) CK output tc(CK) CPOL = 0 tw(CKH) CPOL = 1 tv(WS) th(WS) tw(CKL) WS output tv(SD_MT) SDtransmit LSB transmit(2) MSB transmit LSB receive(2) LSB transmit th(SD_MR) tsu(SD_MR) SDreceive Bitn transmit th(SD_MT) MSB receive Bitn receive LSB receive ai14884b 1. Based on characterization, not tested in production. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 112/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Electrical characteristics USB OTG FS characteristics This interface is present in both the USB OTG HS and USB OTG FS controllers. Table 54. USB OTG FS startup time Symbol tSTARTUP(1) Parameter USB OTG FS transceiver startup time Max Unit 1 s 1. Guaranteed by design, not tested in production. Table 55. USB OTG FS DC electrical characteristics Symbol VDD Input levels Parameter Conditions USB OTG FS operating voltage Min.(1) Typ. Max.(1) Unit 3.0(2) - 3.6 VDI(3) Differential input sensitivity I(USB_FS_DP/DM, USB_HS_DP/DM) 0.2 - - VCM(3) Differential common mode range Includes VDI range 0.8 - 2.5 VSE(3) Single ended receiver threshold 1.3 - 2.0 VOL Static output level low - - 0.3 2.8 - 3.6 17 21 24 0.65 1.1 2.0 Output levels VOH Static output level high RL of 1.5 k to 3.6 V(4) RL of 15 k to VSS(4) PA11, PA12, PB14, PB15 (USB_FS_DP/DM, USB_HS_DP/DM) RPD RPU PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) V V V VIN = VDD k PA12, PB15 (USB_FS_DP, USB_HS_DP) VIN = VSS 1.5 1.8 2.1 PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) VIN = VSS 0.25 0.37 0.55 1. All the voltages are measured from the local ground potential. 2. The STM32F405xx and STM32F407xx USB OTG FS functionality is ensured down to 2.7 V but not the full USB OTG FS electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 3. Guaranteed by design, not tested in production. 4. RL is the load connected on the USB OTG FS drivers Doc ID 022152 Rev 2 113/167 Electrical characteristics STM32F405xx, STM32F407xx Figure 42. USB OTG FS timings: definition of data signal rise and fall time Crossover points Differen tial data lines VCRS VS S Table 56. tr tf ai14137 USB OTG FS electrical characteristics(1) Driver characteristics Symbol tr tf trfm VCRS Parameter Rise time(2) Fall time(2) Conditions Min Max Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr/tf 90 110 % 1.3 2.0 V Rise/ fall time matching Output signal crossover voltage 1. Guaranteed by design, not tested in production. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). Table 57. USB FS clock timing parameters(1)(2) Parameter Symbol Min fHCLK value to guarantee proper operation of USB FS interface - 14.2 Max Unit MHz FSTART_8BIT TBD TBD TBD MHz Frequency (steady state) 500 ppm FSTEADY TBD TBD TBD MHz Duty cycle (first transition) DSTART_8BIT TBD TBD TBD % DSTEADY TBD TBD TBD % - - TBD ms Frequency (first transition) 8-bit 10% 8-bit 10% Duty cycle (steady state) 500 ppm Time to reach the steady state frequency and TSTEADY duty cycle after the first transition Clock startup time after the de-assertion of SuspendM Peripheral TSTART_DEV - - TBD Host TSTART_HOST - - - - - - PHY preparation time after the first transition TPREP of the input clock 1. Guaranteed by design, not tested in production. 2. TBD stands for "to be defined". 114/167 Nominal Doc ID 022152 Rev 2 ms s STM32F405xx, STM32F407xx Electrical characteristics USB HS characteristics Table 58 shows the USB HS operating voltage. Table 58. USB HS DC electrical characteristics Symbol Input level Parameter VDD Ethernet operating voltage Min.(1) Max.(1) Unit 2.7 3.6 V Nominal Max 1. All the voltages are measured from the local ground potential. Table 59. USB HS clock timing parameters(1) Parameter Symbol Min fHCLK value to guarantee proper operation of USB HS interface Frequency (first transition) 8-bit 10% 30 FSTEADY Duty cycle (first transition) DSTART_8BIT 8-bit 10% Duty cycle (steady state) 500 ppm DSTEADY 60 66 MHz 59.97 60 60.03 MHz 40 50 60 % 49.975 50 50.025 % - - 1.4 ms Time to reach the steady state frequency and TSTEADY duty cycle after the first transition Clock startup time after the de-assertion of SuspendM MHz 54 FSTART_8BIT Frequency (steady state) 500 ppm Unit Peripheral TSTART_DEV - - 5.6 Host TSTART_HOST - - - - - - ms PHY preparation time after the first transition TPREP of the input clock s 1. Guaranteed by design, not tested in production. Figure 43. ULPI timing diagram #LOCK #ONTROL )N 5,0)?$)2 5,0)?.84 T3# T(# T3$ T($ DATA )N BIT T$# #ONTROL OUT 5,0)?340 DATA OUT BIT T$# T$$ AIC Doc ID 022152 Rev 2 115/167 Electrical characteristics Table 60. STM32F405xx, STM32F407xx ULPI timing Value(1) Parameter Symbol Control in (ULPI_DIR) setup time tSC Control in (ULPI_NXT) setup time Unit Min. Max. - 2.0 - 1.5 - Control in (ULPI_DIR, ULPI_NXT) hold time tHC Data in setup time tSD - 2.0 Data in hold time tHD 0 - Control out (ULPI_STP) setup time and hold time tDC - 9.2 Data out available from clock rising edge tDD - 10.7 Min.(1) Max.(1) Unit 2.7 3.6 V ns 1. VDD = 2.7 V to 3.6 V and TA = -40 to 85 C. Ethernet characteristics Table 61 shows the Ethernet operating voltage. Table 61. Ethernet DC electrical characteristics Symbol Input level Parameter VDD Ethernet operating voltage 1. All the voltages are measured from the local ground potential. Table 62 gives the list of Ethernet MAC signals for the SMI (station management interface) and Figure 44 shows the corresponding timing diagram. Figure 44. Ethernet SMI timing diagram tMDC ETH_MDC td(MDIO) ETH_MDIO(O) tsu(MDIO) th(MDIO) ETH_MDIO(I) ai15666c Table 62. Symbol Dynamics characteristics: Ethernet MAC signals for SMI(1) Rating Min Typ Max Unit tMDC MDC cycle time (1.71 MHz, AHB = 72 MHz) TBD TBD TBD ns td(MDIO) MDIO write data valid time TBD TBD TBD ns TBD TBD TBD ns TBD TBD TBD ns tsu(MDIO) Read data setup time th(MDIO) Read data hold time 1. TBD stands for "to be defined". 116/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Electrical characteristics Table 63 gives the list of Ethernet MAC signals for the RMII and Figure 45 shows the corresponding timing diagram. Figure 45. Ethernet RMII timing diagram RMII_REF_CLK td(TXEN) td(TXD) RMII_TX_EN RMII_TXD[1:0] tsu(RXD) tsu(CRS) tih(RXD) tih(CRS) RMII_RXD[1:0] RMII_CRS_DV ai15667 Table 63. Dynamics characteristics: Ethernet MAC signals for RMII Symbol Rating Min Typ Max Unit tsu(RXD) Receive data setup time 2 - - ns tih(RXD) Receive data hold time 1 - - ns tsu(CRS) Carrier sense set-up time 0.5 - - ns tih(CRS) Carrier sense hold time 2 - - ns td(TXEN) Transmit enable valid delay time 8 9.5 11 ns td(TXD) Transmit data valid delay time 8.5 10 11.5 ns Table 64 gives the list of Ethernet MAC signals for MII and Figure 45 shows the corresponding timing diagram. Figure 46. Ethernet MII timing diagram MII_RX_CLK MII_RXD[3:0] MII_RX_DV MII_RX_ER tsu(RXD) tsu(ER) tsu(DV) tih(RXD) tih(ER) tih(DV) MII_TX_CLK td(TXEN) td(TXD) MII_TX_EN MII_TXD[3:0] ai15668 Doc ID 022152 Rev 2 117/167 Electrical characteristics Table 64. STM32F405xx, STM32F407xx Dynamics characteristics: Ethernet MAC signals for MII(1) Symbol Rating Min Typ Max Unit tsu(RXD) Receive data setup time TBD TBD TBD ns tih(RXD) Receive data hold time TBD TBD TBD ns tsu(DV) Data valid setup time TBD TBD TBD ns tih(DV) Data valid hold time TBD TBD TBD ns tsu(ER) Error setup time TBD TBD TBD ns tih(ER) Error hold time TBD TBD TBD ns td(TXEN) Transmit enable valid delay time 13.4 15.5 17.7 ns td(TXD) Transmit data valid delay time 12.9 16.1 19.4 ns 1. TBD stands for "to be defined". CAN (controller area network) interface Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CANTX and CANRX). 5.3.20 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 65 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 11. Table 65. ADC characteristics(1) Symbol Parameter VDDA Power supply VREF+ Positive reference voltage fADC fTRIG(5) VAIN RAIN(5) ADC clock frequency External trigger frequency Conditions VDDA = 1.8(2)(4) to 2.4 V VDDA = 2.4 to 3.6 V(4) fADC = 30 MHz Conversion voltage range(6) External input impedance See Equation 1 for details RADC(5)(7) Sampling switch resistance CADC(5) Internal sample and hold capacitor tlat(5) Injection trigger conversion latency fADC = 30 MHz tlatr(5) Regular trigger conversion latency fADC = 30 MHz 118/167 Min Typ Max Unit 1.8(2) - 3.6 V 1.8(2)(3)(4) - VDDA V 0.6 15 18 MHz 0.6 30 36 MHz - - TBD kHz - - 17 1/fADC 0 (VSSA or VREFtied to ground) - VREF+ V - - 50 k - - 6 k - 4 - pF - - 0.100 s - - 3(8) 1/fADC - - 0.067 s - 2(8) 1/fADC - Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Table 65. Symbol ADC characteristics(1) (continued) Parameter tS(5) Sampling time tSTAB(5) Power-up time tCONV(5) Electrical characteristics Conditions Min Typ Max Unit fADC = 30 MHz 0.100 - 16 s 3 - 416 1/fADC - 2 3 s fADC = 30 MHz 12-bit resolution 0.416 - 12.95 s fADC = 30 MHz 10-bit resolution 0.360 - 12.89 s fADC = 30 MHz 8-bit resolution 0.305 - 12.84 s fADC = 30 MHz 6-bit resolution 0.250 - 12.79 s Total conversion time (including sampling time) 9 to 492 (tS for sampling +n-bit resolution for successive approximation) Sampling rate fS(5) IVREF+(5) IDDA(5) (fADC = 30 MHz, and tS = 3 ADC cycles) ADC VREF DC current consumption in conversion mode ADC VDDA DC current consumption in conversion mode 1/fADC 12-bit resolution Single ADC - - 2 Msps 12-bit resolution Interleave Dual ADC mode - - 3.75 Msps 12-bit resolution Interleave Triple ADC mode - - 6 Msps fADC = 30 MHz 3 sampling time 12-bit resolution - 300 500 A fADC = 30 MHz 480 sampling time 12-bit resolution - - TBD A fADC = 30 MHz 3 sampling time 12-bit resolution - 1.6 1.8 fADC = 30 MHz 480 sampling time 12-bit resolution - mA - TBD 1. TBD stands for "to be defined". 2. If an inverted reset signal is applied to PDR_ON, this value can be lowered to 1.7 V when the device operates in a reduced temperature range (0 to 70 C). 3. It is recommended to maintain the voltage difference between VREF+ and VDDA below 1.8 V. 4. VDDA -VREF+ < 1.2 V. 5. Based on characterization, not tested in production. 6. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 7. RADC maximum value is given for VDD=1.8 V, and minimum value for VDD=3.3 V. 8. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 65. Doc ID 022152 Rev 2 119/167 Electrical characteristics STM32F405xx, STM32F407xx Equation 1: RAIN max formula R AIN ( k - 0.5 ) - - R ADC = ------------------------------------------------------------N+2 f ADC x C ADC x ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. a Table 66. Symbol ADC accuracy at fADC = 30 MHz(1) Parameter Test conditions ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 60 MHz, fADC = 30 MHz, RAIN < 10 k, VDDA = 1.8(3) to 3.6 V Typ Max(2) 2 5 1.5 2.5 1.5 3 1 2 1.5 3 Unit LSB 1. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 2. Based on characterization, not tested in production. 3. If an inverted reset signal is applied to PDR_ON, this value can be lowered to 1.7 V when the device operates in a reduced temperature range (0 to 70 C). Note: 120/167 ADC accuracy vs. negative injection current: Injecting a negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.16 does not affect the ADC accuracy. Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Electrical characteristics Figure 47. ADC accuracy characteristics 6 6 ;,3")$%!, 2%& OR $$! DEPENDING ON PACKAGE = %' %4 %/ %, %$ , 3")$%!, 633! 6$$! AIC 1. See also Table 66. 2. Example of an actual transfer curve. 3. Ideal transfer curve. 4. End point correlation line. 5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. Figure 48. Typical connection diagram using the ADC STM32F VDD RAIN(1) Sample and hold ADC converter VT 0.6 V RADC(1) AINx VAIN Cparasitic VT 0.6 V IL1 A 12-bit converter CADC(1) ai17534 1. Refer to Table 65 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. Doc ID 022152 Rev 2 121/167 Electrical characteristics STM32F405xx, STM32F407xx General PCB design guidelines Power supply decoupling should be performed as shown in Figure 49 or Figure 50, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 49. Power supply and reference decoupling (VREF+ not connected to VDDA) STM32F V REF+ (See note 1) 1 F // 10 nF V DDA 1 F // 10 nF V SSA/V REF(See note 1) ai17535 1. VREF+ and VREF- inputs are both available on UFBGA176. VREF+ is also available on LQFP100, LQFP144, and LQFP176. When VREF+ and VREF- are not available, they are internally connected to VDDA and VSSA. Figure 50. Power supply and reference decoupling (VREF+ connected to VDDA) STM32F VREF+/VDDA (See note 1) 1 F // 10 nF VREF-/VSSA (See note 1) ai17536 1. VREF+ and VREF- inputs are both available on UFBGA176. VREF+ is also available on LQFP100, LQFP144, and LQFP176. When VREF+ and VREF- are not available, they are internally connected to VDDA and VSSA. 122/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Electrical characteristics 5.3.21 Temperature sensor characteristics Table 67. TS characteristics Symbol Parameter TL(1) Avg_Slope (1) V25(1) tSTART(2) TS_temp (3)(2) Min Typ Max Unit VSENSE linearity with temperature - 1 2 C Average slope - 2.5 mV/C Voltage at 25 C - 0.76 V Startup time - 6 10 s 10 - - s ADC sampling time when reading the temperature (1 C accuracy) 1. Based on characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. Shortest sampling time can be determined in the application by multiple iterations. 5.3.22 VBAT monitoring characteristics Table 68. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit K R Resistor bridge for VBAT - 50 - Q Ratio on VBAT measurement - 2 - Error on Q -1 - +1 % ADC sampling time when reading the VBAT 1 mV accuracy 5 - - s (1) Er TS_vbat(2)(2) 1. Guaranteed by design, not tested in production. 2. Shortest sampling time can be determined in the application by multiple iterations. 5.3.23 Embedded reference voltage The parameters given in Table 69 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 11. Table 69. Embedded internal reference voltage Symbol VREFINT TS_vrefint(1) VRERINT_s(2) Parameter Internal reference voltage Conditions Min Typ Max Unit -40 C < TA < +105 C 1.18 1.21 1.24 V 10 - - s - 3 5 mV ADC sampling time when reading the internal reference voltage Internal reference voltage spread over the temperature range VDD = 3 V TCoeff(2) Temperature coefficient - 30 50 ppm/C tSTART(2) Startup time - 6 10 s 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production. Doc ID 022152 Rev 2 123/167 Electrical characteristics STM32F405xx, STM32F407xx 5.3.24 DAC electrical characteristics Table 70. DAC characteristics Symbol Parameter Min Typ Max Unit Comments VDDA Analog supply voltage 1.8(1) - 3.6 V VREF+ Reference supply voltage 1.8(1) - 3.6 V VSSA Ground 0 - 0 V RLOAD(2) Resistive load with buffer ON 5 - - k RO(2) Impedance output with buffer OFF - - 15 k When the buffer is OFF, the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 M CLOAD(2) Capacitive load - - 50 pF Maximum capacitive load at DAC_OUT pin (when the buffer is ON). DAC_OUT Lower DAC_OUT voltage min(2) with buffer ON 0.2 - - V DAC_OUT Higher DAC_OUT voltage with buffer ON max(2) - - VDDA - 0.2 V DAC_OUT Lower DAC_OUT voltage min(2) with buffer OFF - 0.5 - mV DAC_OUT Higher DAC_OUT voltage with buffer OFF max(2) - - VREF+ - 1LSB - 170 240 IVREF+(3) IDDA(3) DNL(3) 124/167 Differential non linearity Difference between two consecutive code-1LSB) It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x1C7) to (0xE38) at VREF+ = 1.8 V It gives the maximum output excursion of the DAC. DAC DC VREF current consumption in quiescent mode (Standby mode) DAC DC VDDA current consumption in quiescent mode (Standby mode) VREF+ VDDA V With no load, worst code (0x800) at VREF+ = 3.6 V in terms of DC consumption on the inputs A With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs - 50 75 - 280 380 A With no load, middle code (0x800) on the inputs - 475 625 A With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs - - 0.5 LSB Given for the DAC in 10-bit configuration. - - 2 LSB Given for the DAC in 12-bit configuration. Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Table 70. Symbol INL(3) Offset(3) Gain error(3) Electrical characteristics DAC characteristics (continued) Parameter Min Typ Max Unit - - 1 LSB Given for the DAC in 10-bit configuration. - - 4 LSB Given for the DAC in 12-bit configuration. - - 10 mV Given for the DAC in 12-bit configuration - - 3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V - - 12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V - - 0.5 % Given for the DAC in 12-bit configuration - 3 6 s CLOAD 50 pF, RLOAD 5 k Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) Gain error Settling time (full scale: for a 10-bit input code transition (3) between the lowest and the tSETTLING highest input codes when DAC_OUT reaches final value 4LSB Comments THD(3) Total Harmonic Distortion Buffer ON - - - dB CLOAD 50 pF, RLOAD 5 k Update rate(2) Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) - - 1 MS/s CLOAD 50 pF, RLOAD 5 k - 6.5 10 s CLOAD 50 pF, RLOAD 5 k input code between lowest and highest possible ones. - -67 -40 dB No RLOAD, CLOAD = 50 pF Wakeup time from off state tWAKEUP(3) (Setting the ENx bit in the DAC Control register) PSRR+ (2) Power supply rejection ratio (to VDDA) (static DC measurement) 1. If an inverted reset signal is applied to PDR_ON, this value can be lowered to 1.7 V when the device operates in a reduced temperature range (0 to 70 C). 2. Guaranteed by design, not tested in production. 3. Guaranteed by characterization, not tested in production. Doc ID 022152 Rev 2 125/167 Electrical characteristics STM32F405xx, STM32F407xx Figure 51. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer(1) R LOAD DACx_OUT 12-bit digital to analog converter C LOAD ai17157 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 5.3.25 FSMC characteristics Asynchronous waveforms and timings Figure 52 through Figure 55 represent asynchronous waveforms and Table 71 through Table 74 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: AddressSetupTime = 1 AddressHoldTime = 0x1 DataSetupTime = 0x1 BusTurnAroundDuration = 0x0 In all timing tables, the THCLK is the HCLK clock period. 126/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Electrical characteristics Figure 52. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms TW.% &3-#?.% TV./%?.% T W./% T H.%?./% &3-#?./% &3-#?.7% TV!?.% &3-#?!;= T H!?./% !DDRESS TV",?.% T H",?./% &3-#?.",;= T H$ATA?.% T SU$ATA?./% TH$ATA?./% T SU$ATA?.% $ATA &3-#?$;= T V.!$6?.% TW.!$6 &3-#?.!$6 AIC 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 71. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) Symbol tw(NE) tv(NOE_NE) Parameter FSMC_NE low time Max 2THCLK-0.5 2 THCLK+1 Unit ns 0.5 3 ns 2THCLK-2 2THCLK+ 2 ns FSMC_NOE high to FSMC_NE high hold time 0 - ns FSMC_NEx low to FSMC_A valid - 4.5 ns th(A_NOE) Address hold time after FSMC_NOE high 4 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 1.5 ns th(BL_NOE) FSMC_BL hold time after FSMC_NOE high 0 - ns tsu(Data_NE) Data to FSMC_NEx high setup time THCLK+4 - ns tsu(Data_NOE) Data to FSMC_NOEx high setup time THCLK+4 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns th(Data_NE) Data hold time after FSMC_NEx high 0 - ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 2 ns FSMC_NADV low time - THCLK ns tw(NOE) th(NE_NOE) tv(A_NE) tw(NADV) FSMC_NEx low to FSMC_NOE low Min FSMC_NOE low time 1. CL = 30 pF. 2. Based on characterization, not tested in production. Doc ID 022152 Rev 2 127/167 Electrical characteristics STM32F405xx, STM32F407xx Figure 53. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms tw(NE) FSMC_NEx FSMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FSMC_NWE tv(A_NE) FSMC_A[25:0] th(A_NWE) Address tv(BL_NE) FSMC_NBL[1:0] th(BL_NWE) NBL tv(Data_NE) th(Data_NWE) Data FSMC_D[15:0] t v(NADV_NE) tw(NADV) FSMC_NADV(1) ai14990 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 72. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Symbol tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) Parameter Min Max Unit 3THCLK 3THCLK+ 4 ns THCLK-0.5 THCLK+0.5 ns FSMC_NWE low time THCLK-1 THCLK+2 ns FSMC_NWE high to FSMC_NE high hold time THCLK-1 - ns - 0 ns THCLK- 2 - ns - 1.5 ns THCLK- 1 - ns FSMC_NE low time FSMC_NEx low to FSMC_NWE low FSMC_NEx low to FSMC_A valid th(A_NWE) Address hold time after FSMC_NWE high tv(BL_NE) FSMC_NEx low to FSMC_BL valid th(BL_NWE) FSMC_BL hold time after FSMC_NWE high tv(Data_NE) Data to FSMC_NEx low to Data valid - THCLK+3 ns th(Data_NWE) Data hold time after FSMC_NWE high THCLK-1 - ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 2 ns FSMC_NADV low time - THCLK+0.5 ns tw(NADV) 1. CL = 30 pF. 2. Based on characterization, not tested in production. 128/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Electrical characteristics Figure 54. Asynchronous multiplexed PSRAM/NOR read waveforms tw(NE) FSMC_NE tv(NOE_NE) t h(NE_NOE) FSMC_NOE t w(NOE) FSMC_NWE tv(A_NE) FSMC_A[25:16] t h(A_NOE) Address tv(BL_NE) th(BL_NOE) FSMC_NBL[1:0] NBL th(Data_NE) tsu(Data_NE) t v(A_NE) tsu(Data_NOE) Address FSMC_AD[15:0] t v(NADV_NE) th(Data_NOE) Data th(AD_NADV) tw(NADV) FSMC_NADV ai14892b Table 73. Symbol tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV) Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Parameter Min Max Unit 3THCLK-1 3THCLK+1 ns 2THCLK-0.5 2THCLK+0.5 ns THCLK-1 THCLK+1 ns FSMC_NOE high to FSMC_NE high hold time 0 - ns FSMC_NEx low to FSMC_A valid - 3 ns FSMC_NEx low to FSMC_NADV low 1 2 ns THCLK- 2 THCLK+1 ns THCLK - ns THCLK-1 - ns FSMC_NE low time FSMC_NEx low to FSMC_NOE low FSMC_NOE low time FSMC_NADV low time FSMC_AD(adress) valid hold time after FSMC_NADV high) th(A_NOE) Address hold time after FSMC_NOE high th(BL_NOE) FSMC_BL time after FSMC_NOE high 0 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 2 ns tsu(Data_NE) Data to FSMC_NEx high setup time THCLK+4 - ns tsu(Data_NOE) Data to FSMC_NOE high setup time THCLK+4 - ns th(Data_NE) Data hold time after FSMC_NEx high 0 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Doc ID 022152 Rev 2 129/167 Electrical characteristics STM32F405xx, STM32F407xx Figure 55. Asynchronous multiplexed PSRAM/NOR write waveforms tw(NE) FSMC_NEx FSMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FSMC_NWE tv(A_NE) FSMC_A[25:16] th(A_NWE) Address tv(BL_NE) th(BL_NWE) FSMC_NBL[1:0] NBL t v(A_NE) t v(Data_NADV) Address FSMC_AD[15:0] t v(NADV_NE) th(Data_NWE) Data th(AD_NADV) tw(NADV) FSMC_NADV ai14891B Table 74. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Symbol Min Max Unit FSMC_NE low time 4THCLK-0.5 4THCLK+3 ns FSMC_NEx low to FSMC_NWE low THCLK-0.5 THCLK -0.5 ns FSMC_NWE low tim e 2THCLK-0.5 2THCLK+3 ns THCLK - ns FSMC_NEx low to FSMC_A valid - 0 ns FSMC_NEx low to FSMC_NADV low 1 2 ns FSMC_NADV low time THCLK- 2 THCLK+ 1 ns FSMC_AD(adress) valid hold time after FSMC_NADV high) THCLK-2 - ns THCLK - ns THCLK-2 - ns FSMC_NEx low to FSMC_BL valid - 1.5 ns tv(Data_NADV) FSMC_NADV high to Data valid - THCLK-0.5 ns th(Data_NWE) Data hold time after FSMC_NWE high THCLK - ns tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV) Parameter FSMC_NWE high to FSMC_NE high hold time th(A_NWE) Address hold time after FSMC_NWE high th(BL_NWE) FSMC_BL hold time after FSMC_NWE high tv(BL_NE) 1. CL = 30 pF. 2. Based on characterization, not tested in production. 130/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Electrical characteristics Synchronous waveforms and timings Figure 56 through Figure 59 represent synchronous waveforms and Table 76 through Table 78 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: BurstAccessMode = FSMC_BurstAccessMode_Enable; MemoryType = FSMC_MemoryType_CRAM; WriteBurst = FSMC_WriteBurst_Enable; CLKDivision = 1; (0 is not supported, see the STM32F40xxx/41xxx reference manual) DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM In all timing tables, the THCLK is the HCLK clock period (with maximum FSMC_CLK = 60 MHz). Figure 56. Synchronous multiplexed NOR/PSRAM read timings "53452. TW#,+ TW#,+ &3-#?#,+ $ATA LATENCY TD#,+, .%X, T D#,+, .%X( &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !)6 TD#,+, !6 &3-#?!;= TD#,+, ./%( TD#,+, ./%, &3-#?./% TD#,+, !$)6 TSU!$6 #,+( TD#,+, !$6 &3-#?!$;= !$;= TH#,+( !$6 TSU!$6 #,+( $ TSU.7!)46 #,+( TH#,+( !$6 $ TH#,+( .7!)46 &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( TH#,+( .7!)46 &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( TH#,+( .7!)46 AIG Doc ID 022152 Rev 2 131/167 Electrical characteristics Table 75. STM32F405xx, STM32F407xx Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol tw(CLK) Parameter FSMC_CLK period Max Unit 2THCLK - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 0 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0...2) 2 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 2 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 2 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16...25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16...25) 0 - ns td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low - 0 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 2 - ns td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid - 4.5 ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns tsu(ADV-CLKH) FSMC_A/D[15:0] valid data before FSMC_CLK high 6 - ns th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high 0 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. 132/167 Min Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Electrical characteristics Figure 57. Synchronous multiplexed PSRAM write timings "53452. TW#,+ TW#,+ &3-#?#,+ $ATA LATENCY TD#,+, .%X, TD#,+, .%X( &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !6 TD#,+, !)6 &3-#?!;= TD#,+, .7%, TD#,+, .7%( &3-#?.7% TD#,+, !$)6 TD#,+, $ATA TD#,+, $ATA TD#,+, !$6 !$;= &3-#?!$;= $ $ &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( TH#,+( .7!)46 TD#,+, .",( &3-#?.", AIG Table 76. Synchronous multiplexed PSRAM write timings(1)(2) Symbol tw(CLK) Parameter FSMC_CLK period Min Max Unit 2THCLK - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 1 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0...2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 0 ns 0 - ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16...25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16...25) 8 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 0.5 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 0 - ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns td(CLKL-DATA) FSMC_A/D[15:0] valid data after FSMC_CLK low - 3 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 0 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Doc ID 022152 Rev 2 133/167 Electrical characteristics STM32F405xx, STM32F407xx Figure 58. Synchronous non-multiplexed NOR/PSRAM read timings "53452. TW#,+ TW#,+ &3-#?#,+ TD#,+, .%X, TD#,+, .%X( $ATA LATENCY &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !)6 TD#,+, !6 &3-#?!;= TD#,+, ./%, TD#,+, ./%( &3-#?./% TSU$6 #,+( TH#,+( $6 TSU$6 #,+( &3-#?$;= $ TSU.7!)46 #,+( TH#,+( $6 $ TH#,+( .7!)46 &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( T H#,+( .7!)46 &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( TH#,+( .7!)46 AIF Table 77. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Max Unit 2THCLK -0.5 - ns tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 0.5 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0...2) 0 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 2 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 3 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16...25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16...25) 2 - ns td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low - 0.5 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 1.5 - ns tsu(DV-CLKH) FSMC_D[15:0] valid data before FSMC_CLK high 6 - ns th(CLKH-DV) FSMC_D[15:0] valid data after FSMC_CLK high 3 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. 134/167 Min Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Electrical characteristics Figure 59. Synchronous non-multiplexed PSRAM write timings TW#,+ "53452. TW#,+ &3-#?#,+ TD#,+, .%X, TD#,+, .%X( $ATA LATENCY &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !6 TD#,+, !)6 &3-#?!;= TD#,+, .7%, TD#,+, .7%( &3-#?.7% TD#,+, $ATA &3-#?$;= TD#,+, $ATA $ $ &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( TD#,+, .",( TH#,+( .7!)46 &3-#?.", AIG Table 78. Synchronous non-multiplexed PSRAM write timings(1)(2) Symbol tw(CLK) Parameter Max Unit 2THCLK - ns FSMC_CLK low to FSMC_NEx low (x=0..2) - 1 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0...2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 7 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 6 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16...25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16...25) 6 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 1 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 2 - ns td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low - 3 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 3 - ns t d(CLKL-NExL) FSMC_CLK period Min 1. CL = 30 pF. 2. Based on characterization, not tested in production. Doc ID 022152 Rev 2 135/167 Electrical characteristics STM32F405xx, STM32F407xx PC Card/CompactFlash controller waveforms and timings Figure 60 through Figure 65 represent synchronous waveforms, and Table 79 and Table 80 provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: COM.FSMC_SetupTime = 0x04; COM.FSMC_WaitSetupTime = 0x07; COM.FSMC_HoldSetupTime = 0x04; COM.FSMC_HiZSetupTime = 0x00; ATT.FSMC_SetupTime = 0x04; ATT.FSMC_WaitSetupTime = 0x07; ATT.FSMC_HoldSetupTime = 0x04; ATT.FSMC_HiZSetupTime = 0x00; IO.FSMC_SetupTime = 0x04; IO.FSMC_WaitSetupTime = 0x07; IO.FSMC_HoldSetupTime = 0x04; IO.FSMC_HiZSetupTime = 0x00; TCLRSetupTime = 0; TARSetupTime = 0. In all timing tables, the THCLK is the HCLK clock period. Figure 60. PC Card/CompactFlash controller waveforms for common memory read access FSMC_NCE4_2(1) FSMC_NCE4_1 th(NCEx-AI) tv(NCEx-A) FSMC_A[10:0] th(NCEx-NREG) th(NCEx-NIORD) th(NCEx-NIOWR) td(NREG-NCEx) td(NIORD-NCEx) FSMC_NREG FSMC_NIOWR FSMC_NIORD FSMC_NWE td(NCE4_1-NOE) FSMC_NOE tw(NOE) tsu(D-NOE) th(NOE-D) FSMC_D[15:0] ai14895b 1. FSMC_NCE4_2 remains high (inactive during 8-bit access. 136/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Electrical characteristics Figure 61. PC Card/CompactFlash controller waveforms for common memory write access FSMC_NCE4_1 FSMC_NCE4_2 High tv(NCE4_1-A) th(NCE4_1-AI) FSMC_A[10:0] th(NCE4_1-NREG) th(NCE4_1-NIORD) th(NCE4_1-NIOWR) td(NREG-NCE4_1) td(NIORD-NCE4_1) FSMC_NREG FSMC_NIOWR FSMC_NIORD td(NCE4_1-NWE) tw(NWE) td(NWE-NCE4_1) FSMC_NWE FSMC_NOE MEMxHIZ =1 td(D-NWE) tv(NWE-D) th(NWE-D) FSMC_D[15:0] ai14896b Doc ID 022152 Rev 2 137/167 Electrical characteristics STM32F405xx, STM32F407xx Figure 62. PC Card/CompactFlash controller waveforms for attribute memory read access FSMC_NCE4_1 tv(NCE4_1-A) FSMC_NCE4_2 th(NCE4_1-AI) High FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD td(NREG-NCE4_1) th(NCE4_1-NREG) FSMC_NREG FSMC_NWE td(NCE4_1-NOE) tw(NOE) td(NOE-NCE4_1) FSMC_NOE tsu(D-NOE) th(NOE-D) FSMC_D[15:0](1) ai14897b 1. Only data bits 0...7 are read (bits 8...15 are disregarded). 138/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Electrical characteristics Figure 63. PC Card/CompactFlash controller waveforms for attribute memory write access FSMC_NCE4_1 FSMC_NCE4_2 High tv(NCE4_1-A) th(NCE4_1-AI) FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD td(NREG-NCE4_1) th(NCE4_1-NREG) FSMC_NREG td(NCE4_1-NWE) tw(NWE) FSMC_NWE td(NWE-NCE4_1) FSMC_NOE tv(NWE-D) FSMC_D[7:0](1) ai14898b 1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z). Figure 64. PC Card/CompactFlash controller waveforms for I/O space read access FSMC_NCE4_1 FSMC_NCE4_2 th(NCE4_1-AI) tv(NCEx-A) FSMC_A[10:0] FSMC_NREG FSMC_NWE FSMC_NOE FSMC_NIOWR tw(NIORD) td(NIORD-NCE4_1) FSMC_NIORD tsu(D-NIORD) td(NIORD-D) FSMC_D[15:0] ai14899B Doc ID 022152 Rev 2 139/167 Electrical characteristics STM32F405xx, STM32F407xx Figure 65. PC Card/CompactFlash controller waveforms for I/O space write access &3-#?.#%? &3-#?.#%? TV.#%X ! TH.#%? !) &3-#?!;= &3-#?.2%' &3-#?.7% &3-#?./% &3-#?.)/2$ TD.#%? .)/72 TW.)/72 &3-#?.)/72 !44X(): TV.)/72 $ TH.)/72 $ &3-#?$;= AIC Table 79. Switching characteristics for PC Card/CF read and write cycles in attribute/common space(1)(2) Symbol Parameter Min Max Unit tv(NCEx-A) FSMC_Ncex low to FSMC_Ay valid - 0 ns th(NCEx_AI) FSMC_NCEx high to FSMC_Ax invalid 4 - ns td(NREG-NCEx) FSMC_NCEx low to FSMC_NREG valid - 3.5 ns th(NCEx-NREG) FSMC_NCEx high to FSMC_NREG invalid THCLK+4 - ns td(NCEx-NWE) FSMC_NCEx low to FSMC_NWE low - 5THCLK+0.5 ns td(NCEx-NOE) FSMC_NCEx low to FSMC_NOE low - 5THCLK +0.5 ns 8THCLK-1 8THCLK+1 ns 5THCLK+2.5 - ns 4.5 - ns 3 - ns 8THCLK-0.5 8THCLK+ 3 ns 5THCLK-1 - ns tw(NOE) td(NOE_NCEx) tsu (D-NOE) FSMC_NOE low width FSMC_NOE high to FSMC_NCEx high FSMC_D[15:0] valid data before FSMC_NOE high th(N0E-D) FSMC_N0E high to FSMC_D[15:0] invalid tw(NWE) FSMC_NWE low width td(NWE_NCEx) FSMC_NWE high to FSMC_NCEx high td(NCEx-NWE) FSMC_NCEx low to FSMC_NWE low - 5THCLK+ 1 ns tv(NWE-D) FSMC_NWE low to FSMC_D[15:0] valid - 0 ns th (NWE-D) FSMC_NWE high to FSMC_D[15:0] invalid 8THCLK -1 - ns td (D-NWE) FSMC_D[15:0] valid before FSMC_NWE high 13THCLK -1 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. 140/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Table 80. Electrical characteristics Switching characteristics for PC Card/CF read and write cycles in I/O space(1)(2) Symbol Parameter tw(NIOWR) FSMC_NIOWR low width tv(NIOWR-D) FSMC_NIOWR low to FSMC_D[15:0] valid th(NIOWR-D) FSMC_NIOWR high to FSMC_D[15:0] invalid Min Max Unit 8THCLK -1 - ns - 5THCLK- 1 ns 8THCLK- 2 - ns - 5THCLK+ 2.5 ns 5THCLK-1.5 - ns - 5THCLK+ 2 ns td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid th(NCEx-NIOWR) FSMC_NCEx high to FSMC_NIOWR invalid td(NIORD-NCEx) FSMC_NCEx low to FSMC_NIORD valid th(NCEx-NIORD) FSMC_NCEx high to FSMC_NIORD) valid 5THCLK- 1.5 - ns FSMC_NIORD low width 8THCLK-0.5 - ns tw(NIORD) tsu(D-NIORD) FSMC_D[15:0] valid before FSMC_NIORD high 9 - ns td(NIORD-D) FSMC_D[15:0] valid after FSMC_NIORD high 0 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. NAND controller waveforms and timings Figure 66 through Figure 69 represent synchronous waveforms, and Table 81 and Table 82 provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: COM.FSMC_SetupTime = 0x01; COM.FSMC_WaitSetupTime = 0x03; COM.FSMC_HoldSetupTime = 0x02; COM.FSMC_HiZSetupTime = 0x01; ATT.FSMC_SetupTime = 0x01; ATT.FSMC_WaitSetupTime = 0x03; ATT.FSMC_HoldSetupTime = 0x02; ATT.FSMC_HiZSetupTime = 0x01; Bank = FSMC_Bank_NAND; MemoryDataWidth = FSMC_MemoryDataWidth_16b; ECC = FSMC_ECC_Enable; ECCPageSize = FSMC_ECCPageSize_512Bytes; TCLRSetupTime = 0; TARSetupTime = 0. In all timing tables, the THCLK is the HCLK clock period. Doc ID 022152 Rev 2 141/167 Electrical characteristics STM32F405xx, STM32F407xx Figure 66. NAND controller waveforms for read access &3-#?.#%X !,% &3-#?! #,% &3-#?! &3-#?.7% TD!,% ./% TH./% !,% &3-#?./% .2% TSU$ ./% TH./% $ &3-#?$;= AIC Figure 67. NAND controller waveforms for write access &3-#?.#%X !,% &3-#?! #,% &3-#?! TD!,% .7% TH.7% !,% &3-#?.7% &3-#?./% .2% TV.7% $ TH.7% $ &3-#?$;= AIC 142/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Electrical characteristics Figure 68. NAND controller waveforms for common memory read access &3-#?.#%X !,% &3-#?! #,% &3-#?! TD!,% ./% TH./% !,% &3-#?.7% TW./% &3-#?./% TSU$ ./% TH./% $ &3-#?$;= AIC Figure 69. NAND controller waveforms for common memory write access &3-#?.#%X !,% &3-#?! #,% &3-#?! TD!,% ./% TW.7% TH./% !,% &3-#?.7% &3-#?./% TD$ .7% TV.7% $ TH.7% $ &3-#?$;= AIC Table 81. Symbol tw(N0E) Switching characteristics for NAND Flash read cycles(1) Parameter FSMC_NOE low width Min Max Unit 4THCLK- 0.5 4THCLK+ 3 ns tsu(D-NOE) FSMC_D[15-0] valid data before FSMC_NOE high 10 - ns th(NOE-D) FSMC_D[15-0] valid data after FSMC_NOE high 0 - ns td(ALE-NOE) FSMC_ALE valid before FSMC_NOE low - 3THCLK ns th(NOE-ALE) FSMC_NWE high to FSMC_ALE invalid 3THCLK- 2 - ns 1. CL = 30 pF. Doc ID 022152 Rev 2 143/167 Electrical characteristics STM32F405xx, STM32F407xx Switching characteristics for NAND Flash write cycles(1) Table 82. Symbol Parameter tw(NWE) FSMC_NWE low width Min Max Unit 4THCLK-1 4THCLK+ 3 ns - 0 ns tv(NWE-D) FSMC_NWE low to FSMC_D[15-0] valid th(NWE-D) FSMC_NWE high to FSMC_D[15-0] invalid 3THCLK -2 - ns td(D-NWE) FSMC_D[15-0] valid before FSMC_NWE high 5THCLK-3 - ns - 3THCLK ns 3THCLK-2 - ns Max Unit td(ALE-NWE) FSMC_ALE valid before FSMC_NWE low th(NWE-ALE) FSMC_NWE high to FSMC_ALE invalid 1. CL = 30 pF. 5.3.26 Camera interface (DCMI) timing specifications Table 83. DCMI characteristics Symbol Parameter Conditions Min (1) Frequency ratio DCMI_PIXCLK/fHCLK 0.4 1. Maximum value of DCMI_PIXCLK = 54 MHz. 5.3.27 SD/SDIO MMC card host interface (SDIO) characteristics Unless otherwise specified, the parameters given in Table 84 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 11. Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (D[7:0], CMD, CK). Figure 70. SDIO high-speed mode tf tr tC tW(CKH) tW(CKL) CK tOV tOH D, CMD (output) tISU tIH D, CMD (input) ai14887 144/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Electrical characteristics Figure 71. SD default mode CK tOVD tOHD D, CMD (output) ai14888 Table 84. Symbol SD / MMC characteristics(1) Parameter Conditions Min Max Unit TBD TBD MHz - TBD - fPP Clock frequency in data transfer mode CL 30 pF - SDIO_CK/fPCLK2 frequency ratio - tW(CKL) Clock low time, fPP = 16 MHz CL 30 pF TBD - tW(CKH) Clock high time, fPP = 16 MHz CL 30 pF TBD - tr Clock rise time CL 30 pF - TBD tf Clock fall time CL 30 pF - TBD ns CMD, D inputs (referenced to CK) tISU Input setup time CL 30 pF TBD - tIH Input hold time CL 30 pF TBD - ns CMD, D outputs (referenced to CK) in MMC and SD HS mode tOV Output valid time CL 30 pF - TBD tOH Output hold time CL 30 pF TBD - ns CMD, D outputs (referenced to CK) in SD default mode(2) tOVD Output valid default time CL 30 pF - TBD tOHD Output hold default time CL 30 pF TBD - ns 1. TBD stands for "to be defined". 2. Refer to SDIO_CLKCR, the SDI clock control register to control the CK output. 5.3.28 RTC characteristics Table 85. Symbol - RTC characteristics Parameter fPCLK1/RTCCLK frequency ratio Conditions Any read/write operation from/to an RTC register Doc ID 022152 Rev 2 Min Max Unit 4 - - 145/167 Package characteristics STM32F405xx, STM32F407xx 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 146/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Package characteristics Figure 73. Recommended footprint(1)(2) Figure 72. LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package outline(1) A 48 33 A2 0.3 A1 E 49 b E1 12.7 32 0.5 10.3 e 10.3 64 17 1.2 1 D1 c 7.8 L1 D 16 12.7 L ai14398b ai14909 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 86. LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.600 A1 0.050 A2 1.350 b 0.170 c 0.090 Max 0.0630 0.150 0.0020 0.0059 1.400 1.450 0.0531 0.0551 0.0571 0.220 0.270 0.0067 0.0087 0.0106 0.200 0.0035 0.0079 D 12.000 0.4724 D1 10.000 0.3937 E 12.000 0.4724 E1 10.000 0.3937 e 0.500 0.0197 0 3.5 7 0 3.5 7 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 1.000 0.0394 Number of pins N 64 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 022152 Rev 2 147/167 Package characteristics STM32F405xx, STM32F407xx Figure 74. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline(1) Figure 75. Recommended footprint(1)(2) 0.25 mm 0.10 inch GAGE PLANE k D L D1 75 51 L1 D3 51 75 76 C 76 50 0.5 50 0.3 16.7 b 14.3 E3 E1 E 100 100 26 1.2 26 Pin 1 1 identification 25 1 C ccc 25 12.3 e A1 16.7 A2 ai14906 A SEATING PLANE C 1L_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 87. LQPF100 - 14 x 14 mm 100-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.600 Max 0.0630 A1 0.050 0.150 0.0020 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 12.000 0.0059 0.0079 0.4724 E 15.80v 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 12.000 0.4724 e 0.500 0.0197 L 0.450 L1 k ccc 0.600 0.750 1.000 0 3.5 0.0236 0.0295 0.0394 7 0.080 0 3.5 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 148/167 0.0177 Doc ID 022152 Rev 2 7 STM32F405xx, STM32F407xx Package characteristics Figure 76. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline(1) Figure 77. Recommended footprint(1)(2) Seating plane C A A2 A1 c b ccc 0.25 mm gage plane C D k 108 109 73 1.35 72 0.35 D1 A1 D3 108 L 73 0.5 L1 72 109 17.85 19.9 E1 E 144 22.6 37 E3 1 36 19.9 22.6 a 144 Pin 1 identification 37 36 1 e ME_1A 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 88. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.600 A1 0.050 A2 1.350 b 0.170 c 0.090 D 21.800 D1 Max 0.0630 0.150 0.0020 1.400 1.450 0.0531 0.0551 0.0571 0.220 0.270 0.0067 0.0087 0.0106 0.200 0.0035 22.000 22.200 0.8583 0.8661 0.874 19.800 20.000 20.200 0.7795 0.7874 0.7953 E 21.800 22.000 22.200 0.8583 0.8661 0.8740 E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 17.500 0.0059 0.0079 0.689 E3 17.500 0.6890 e 0.500 0.0197 L 0.450 L1 k ccc 0.600 0.750 0.0177 1.000 0 3.5 0.0236 0.0295 0.0394 7 0.080 0 3.5 7 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 022152 Rev 2 149/167 Package characteristics STM32F405xx, STM32F407xx Figure 78. UFBGA176+25 - ultra thin fine pitch ball grid array 10 x 10 x 0.6 mm, package outline C Seating plane A2 ddd A4 C A A3 A1 A D B Ball A1 e F A F E e R 15 Ob 1 (176 balls) O eee M C A O fff M B A0E7_ME C 1. Drawing is not to scale. Table 89. UFBGA176+25 - ultra thin fine pitch ball grid array 10 x 10 x 0.6 mm mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.002 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 A3 0.130 0.0051 A4 0.270 0.320 0.370 0.0106 0.0126 0.0146 b 0.230 0.280 0.330 0.0091 0.0110 0.0130 D 9.950 10.000 10.050 0.3740 0.3937 0.3957 E 9.950 10.000 10.050 0.3740 0.3937 0.3957 e 0.600 0.650 0.700 0.0236 0.0256 0.0276 F 0.400 0.450 0.500 0.0157 0.0177 0.0197 ddd 0.080 0.0031 eee 0.150 0.0059 fff 0.080 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 150/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Package characteristics Figure 79. LQFP176 24 x 24 mm, 144-pin low-profile quad flat package outline C Seating plane 0.25 mm gauge plane A A2 k c A1 ccc C A1 HD L D L1 ZD ZE 89 132 88 133 b E 176 Pin 1 identification HE 45 44 1 e 1T_ME 1. Drawing is not to scale. Table 90. LQFP176, 24 x 24 mm, 144-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.600 Max 0.0630 A1 0.050 0.150 0.0020 A2 1.350 1.450 0.0531 0.0060 b 0.170 0.270 0.0067 0.0106 C 0.090 0.200 0.0035 0.0079 D 23.900 24.100 0.9409 0.9488 E 23.900 24.100 0.9409 0.9488 e 0.500 0.0197 HD 25.900 26.100 1.0200 1.0276 HE 25.900 26.100 1.0200 1.0276 L 0.450 0.750 0.0177 0.0295 L1 1.000 0.0394 ZD 1.250 0.0492 ZE 1.250 0.0492 ccc k 0.080 0 7 0.0031 0 7 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 022152 Rev 2 151/167 Package characteristics 6.2 STM32F405xx, STM32F407xx Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where: TA max is the maximum ambient temperature in C, JA is the package junction-to-ambient thermal resistance, in C/W, PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 91. Package thermal characteristics Symbol JA Parameter Value Thermal resistance junction-ambient LQFP64 - 10 x 10 mm / 0.5 mm pitch 46 Thermal resistance junction-ambient LQFP100 - 14 x 14 mm / 0.5 mm pitch 43 Thermal resistance junction-ambient LQFP144 - 20 x 20 mm / 0.5 mm pitch 40 Thermal resistance junction-ambient LQFP176 - 24 x 24 mm / 0.5 mm pitch 38 Thermal resistance junction-ambient UFBGA176 - 10x 10 mm / 0.65 mm pitch 39 Unit C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. 152/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Part numbering 7 Part numbering Table 92. Ordering information scheme Example: STM32 F 405 R E T 6 xxx Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 405 = STM32F40x, connectivity, USB OTG FS/HS, 407= STM32F40x, connectivity, USB OTG FS/HS, camera interface, Ethernet Pin count R = 64 pins or 66 pins V = 100 pins Z = 144 pins I = 176 pins Flash memory size C = 256 Kbytes of Flash memory E = 512 Kbytes of Flash memory F = 768 Kbytes of Flash memory G = 1024 Kbytes of Flash memory Package T = LQFP H = UFBGA Temperature range 6 = Industrial temperature range, -40 to 85 C. 7 = Industrial temperature range, -40 to 105 C. Options xxx = programmed parts TR = tape and reel For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. Doc ID 022152 Rev 2 153/167 Application block diagrams Appendix A A.1 STM32F405xx, STM32F407xx Application block diagrams Main applications versus package Table 93 gives examples of configurations for each package. Table 93. Main applications versus package for STM32F407xx microcontrollers(1) 64 pins 100 pins 144 pins 176 pins Config Config Config Config Config Config Config Config Config Config Config Config Config 1 2 3 1 2 3 4 1 2 3 4 1 2 USB 1 USB 2 OTG FS X X X X X X - X FS X X X X X X X X X HS ULPI - - - X - - - X X X X OTGFS - - - X X X X X FS - - - X X X X X X MII - - - - - X X RMII - - - - X X X X - X - - X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Ethernet SPI/I2S2 SPI/I2S3 SDIO SDIO 8bits Data 10bits Data - SDIO or DCMI SDIO or DCMI - X SDIO or DCMI SDIO or DCMI SDIO or DCMI X X X SDIO or DCMI X X SDIO or DCMI DCMI 12bits Data FSMC CAN - X X X X X X X X X 14bits Data - - - - - - - NOR/ RAM Muxed - - - X X X X NOR/ RAM - - - NAND - - - X X X*22 CF - - - - - - X X - X X X X X X X X X X X X X X*19 X X*19 X*22 X*19 X*22 X*22 - - X X X X X X X X - - X X - X 1. X*y: FSMC address limited to "y". 154/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx A.2 Application block diagrams Application example with regulator OFF Figure 80. Regulator OFF/internal reset ON 0OWER DOWN RESET RISEN AFTER 6#!0?6#!0? STABILIZATION 0OWER DOWN RESET RISEN BEFORE 6#!0?6#!0? STABILIZATION 6#!0? MONITORING %XT RESET CONTROLLER ACTIVE WHEN 6 #!0? 6 !PPLICATION RESET SIGNAL OPTIONAL 6$$ 0! 6$$ 6$$ .234 !PPLICATION RESET SIGNAL OPTIONAL 0! 6$$ .234 0$2?/. 0$2?/. "90!33?2%' "90!33?2%' 6 6 6#!0? 6#!0? 6#!0? 6#!0? AI 1. This mode is available only on UFBGA176 package. Figure 81. Regulator OFF/internal reset OFF 6$$ 6$$ MONITORING %XT RESET CONTROLLER ACTIVE WHEN 6 $$ 6 OR 6 #!0?6#!0? 6 6$$ 6$$ .234 0! "90!33?2%' 0$2?/. 6$$ 6 6#!0? 6#!0? AI 1. This mode is available only on UFBGA176 package. Doc ID 022152 Rev 2 155/167 Application block diagrams A.3 STM32F405xx, STM32F407xx USB OTG full speed (FS) interface solutions Figure 82. USB controller configured as peripheral-only and used in Full speed mode 6$$ 6 TO 6$$ 6OLATGE REGULATOR 6"53 0!0" $- /3#?). 0!0" $0 0!0" 633 /3#?/54 53" 3TD " CONNECTOR 34-&XX -36 1. External voltage regulator only needed when building a VBUS powered device. 2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller. Figure 83. USB controller configured as host-only and used in full speed mode 6$$ %. '0)/ '0)/ )21 /VERCURRENT #URRENT LIMITER POWER SWITCH 6 0WR 0!0" /3#?). 0!0" 0!0" 6"53 $$0 633 /3#?/54 53" 3TD ! CONNECTOR 34-&XX -36 1. The current limiter is required only if the application has to support a VBUS powered device. A basic power switch can be used if 5 V are available on the application board. 2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller. 156/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Application block diagrams Figure 84. USB controller configured in dual mode and used in full speed mode 6$$ 6 TO 6$$ VOLTAGE REGULATOR 6$$ '0)/ )21 /VERCURRENT #URRENT LIMITER POWER SWITCH 6 0WR 34-&XX 0!0" 0!0" /3#?). /3#?/54 0!0" 0!0" 6"53 $$0 )$ 633 53"MICRO !" CONNECTOR '0)/ %. -36 1. External voltage regulator only needed when building a VBUS powered device. 2. The current limiter is required only if the application has to support a VBUS powered device. A basic power switch can be used if 5 V are available on the application board. 3. The ID pin is required in dual role only. 4. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller. Doc ID 022152 Rev 2 157/167 Application block diagrams A.4 STM32F405xx, STM32F407xx USB OTG high speed (HS) interface solutions Figure 85. USB controller configured as peripheral, host, or dual-mode and used in high speed mode 34-&XX &3 0(9 53" (3 /4' #TRL $0 $- NOT CONNECTED $0 5,0)?#,+ $- 5,0)?$;= 5,0) )$ 5,0)?$)2 6"53 5,0)?340 53" CONNECTOR 633 5,0)?.84 (IGH SPEED /4' 0(9 0,, 84 OR -(Z 84 -#/ OR -#/ 8) -36 1. It is possible to use MCO1 or MCO2 to save a crystal. It is however not mandatory to clock the STM32F40x with a 24 or 26 MHz crystal when using USB HS. The above figure only shows an example of a possible connection. 2. The ID pin is required in dual role only. 158/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx A.5 Application block diagrams Complete audio player solutions Two solutions are offered, illustrated in Figure 86 and Figure 87. Figure 86 shows storage media to audio DAC/amplifier streaming using a software Codec. This solution implements an audio crystal to provide audio class I2S accuracy on the master clock (0.5% error maximum, see the Serial peripheral interface section in the reference manual for details). Figure 86. Complete audio player solution 1 34-&XX 84!, -(Z OR -(Z #ORTEX -& CORE UP TO -(Z 0ROGRAM MEMORY /4' HOST MODE 0(9 53" -ASS STORAGE DEVICE &ILE 3YSTEM 30) ,#$ TOUCH SCREEN '0)/ #ONTROL BUTTONS $!# !UDIO AMPLI )3 !UDIO #/$%# 5SER APPLICATION --# 3$#ARD 30) -36 Figure 87 shows storage media to audio Codec/amplifier streaming with SOF synchronization of input/output audio streaming using a hardware Codec. Figure 87. Complete audio player solution 2 34-&XX 84!, -(Z OR -(Z #ORTEX -& CORE UP TO -(Z 0ROGRAM MEMORY 53" -ASS STORAGE DEVICE /4' 3/& --# 3$#ARD &ILE 3YSTEM 30) ,#$ TOUCH SCREEN '0)/ #ONTROL BUTTONS )3 0(9 5SER APPLICATION 30) !UDIO #/$%# !UDIO AMPLI 3/& SYNCHRONIZATION OF INPUTOUTPUT AUDIO STREAMING -36 Doc ID 022152 Rev 2 159/167 Application block diagrams STM32F405xx, STM32F407xx Figure 88. Audio player solution using PLL, PLLI2S, USB and 1 crystal 34-&XX $IV BY - /3# 84!, -(Z OR -(Z 0,, X . $IV BY 0 #ORTEX -& CORE UP TO -(Z $IV BY 1 /4' -(Z 0,,)3 X . $IV BY 2 0(9 -#/02% -#/02% -#/ -#/ )3 ACCURACY -#,+ IN -#,+ OUT 3#,+ $!# !UDIO AMPLI -36 Figure 89. Audio PLL (PLLI2S) providing accurate I2S clock PLLI2S Phase lock detector CLKIN /M M=1,2,3,..,64 1 MHz PhaseC VCO 192 to 432 MHz I2S_MCK = 256 x FSAUDIO 11.2896 MHz for 44.1 kHz 12.2880 MHz for 48.0 kHz /N N=192,194,..,432 /R I2SCOM_CK I2S CTL I2S_MCK R=2,3,4,5,6,7 I2SD=2,3,4.. 129 ai16041b 160/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Application block diagrams Figure 90. Master clock (MCK) used to drive the external audio DAC I2S controller I2S_CK I2S_MCK = 256 x FSAUDIO = 11.2896 MHz for FSAUDIO = 44.1 kHz = 12.2880 MHz for FSAUDIO = 48.0 kHz /I2SD 2,3,4,..,129 I2S_SCK(1) = I2S_MCK/8 for 16-bit stereo = I2S_MCK/4 for 32-bit stereo /8 /(2 x 16) FSAUDIO for 16-bit stereo /4 /(2 x 32) FSAUDIO for 32-bit stereo ai16042 1. I2S_SCK is the I2S serial clock to the external audio DAC (not to be confused with I2S_CK). Figure 91. Master clock (MCK) not used to drive the external audio DAC I2S controller I2S_SCK(1) I2SCOM_CK /I2SD /(2 x 16) FSAUDIO for 16-bit stereo /(2 x 32) FSAUDIO for 32-bit stereo ai16042 1. I2S_SCK is the I2S serial clock to the external audio DAC (not to be confused with I2S_CK). Doc ID 022152 Rev 2 161/167 Application block diagrams A.6 STM32F405xx, STM32F407xx Ethernet interface solutions Figure 92. MII mode using a 25 MHz crystal 34- -#5 -))?48?#,+ -))?48?%. -))?48$;= -))?#23 -))?#/, %THERNET -!# (#,+ )%%% 040 4IMER INPUT TRIGGER 4IMESTAMP 4)- COMPARATOR %THERNET 0(9 -)) PINS -))?28?#,+ -))?28$;= -))?28?$6 -))?28?%2 -)) -$# PINS -$)/ -$# 003?/54 84!, -(Z /3# (#,+ 0,, -#/-#/ 0(9?#,+ -(Z 84 -36 1. fHCLK must be greater than 25 MHz. 2. Pulse per second when using IEEE1588 PTP optional signal. Figure 93. RMII with a 50 MHz oscillator 34- -#5 %THERNET 0(9 2-))?48?%. %THERNET -!# 2-))?48$;= 2-))?28$;= (#,+ 2-))?#28?$6 2-))?2%&?#,+ )%%% 040 2-)) PINS 2-)) -$# PINS -$)/ 4IMER INPUT TRIGGER 4IMESTAMP 4)- COMPARATOR -$# OR OR -(Z SYNCHRONOUS -(Z /3# -(Z 0,, (#,+ 0(9?#,+ -(Z 84 -(Z -36 1. fHCLK must be greater than 25 MHz. 162/167 Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Application block diagrams Figure 94. RMII with a 25 MHz crystal and PHY with PLL 34-& -#5 %THERNET 0(9 2-))?48?%. %THERNET -!# 2-))?48$;= 2-))?28$;= (#,+ )%%% 040 2-))?#28?$6 2-))?2%&?#,+ 2-)) PINS 2%&?#,+ -$)/ 4IMER INPUT TRIGGER 4IMESTAMP 4)- COMPARATOR 2-)) -$# PINS -$# OR OR -(Z SYNCHRONOUS -(Z 84!, -(Z /3# 0,, (#,+ 0,, -#/-#/ 0(9?#,+ -(Z 84 -36 1. fHCLK must be greater than 25 MHz. 2. The 25 MHz (PHY_CLK) must be derived directly from the HSE oscillator, before the PLL block. Doc ID 022152 Rev 2 163/167 Revision history 8 STM32F405xx, STM32F407xx Revision history Table 94. Document revision history Date Revision 15-Sep-2011 1 Initial release. 2 Added WLCSP90 package on cover page. Renamed USART4 and USART5 into UART4 and UART5, respectively. Updated number of USB OTG HS and FS in Table 2: STM32F405xx and STM32F407xx: features and peripheral counts. Updated Figure 3: Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package and Figure 4: Compatible board design between STM32F2xx and STM32F4xx for LQFP176 package, and removed note 1 and 2. Updated Section 2.2.9: Flexible static memory controller (FSMC). Modified I/Os used to reprogram the Flash memory for CAN2 and USB OTG FS in Section 2.2.13: Boot modes. Updated note in Section 2.2.14: Power supply schemes. PDR_ON no more available on LQFP100 package. Updated Section 2.2.16: Voltage regulator. Updated condition to obtain a minimum supply voltage of 1.7 V in the whole document. Renamed USART4/5 to UART4/5 and added LIN and IrDA feature for UART4 and UART5 in Table 4: USART feature comparison. Removed support of I2C for OTG PHY in Section 2.2.29: Universal serial bus on-the-go full-speed (OTG_FS). Added Table 5: Legend/abbreviations used in the pinout table. Table 6: STM32F40x pin and ball definitions: replaced VSS_3, VSS_4, and VSS_8 by VSS; reformatted Table 6: STM32F40x pin and ball definitions to better highlight I/O structure, and alternate functions versus additional functions; signal corresponding to LQFP100 pin 99 changed from PDR_ON to VSS; EVENTOUT added in the list of alternate functions for all I/Os; ADC3_IN8 added as alternate function for PF10; FSMC_CLE and FSMC_ALE added as alternate functions for PD11 and PD12, respectively; PH10 alternate function TIM15_CH1_ETR renamed TIM5_CH1; updated PA4 and PAA5 pin type. Removed OTG_HS_SCL, OTG_HS_SDA, OTG_FS_INTN, OTG_FS_SDA, OTG_FS_SCL alternate functions in Table 6: STM32F40x pin and ball definitions and Table 7: Alternate function mapping. Changed TCM data RAM to CCM data RAM in Figure 15: Memory map. Added IVDD and IVSS maximum values in Table 9: Current characteristics. Added Note 1 related to fHCLK, updated Note 2 in Table 11: General operating conditions, and added maximum power dissipation values. Updated Table 12: Limitations depending on the operating power supply range. 24-Jan-2012 164/167 Changes Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Table 94. Revision history Document revision history (continued) Date 24-Jan-2012 Revision Changes Added V12 in Table 16: Embedded reset and power control block characteristics. Updated Table 17: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) and Table 18: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM. Added Figure , Figure 22, Figure 23, anhd Figure 24. Updated Table 19: Typical and maximum current consumption in Sleep mode and removed Note 1. Updated Table 20: Typical and maximum current consumptions in Stop mode and Table 21: Typical and maximum current consumptions in Standby mode, Table 22: Typical and maximum current consumptions in VBAT mode, and Table 23: Switching output I/O current consumption. Section : On-chip peripheral current consumption: modified conditions, and updated Table 24: Peripheral current consumption and Note 2. Changed fHSE_ext to 50 MHz and tr(HSE)/tf(HSE) maximum value in Table 26: High-speed external user clock characteristics. Added Cin(LSE) in Table 27: Low-speed external user clock 2 characteristics. (continued) Updated maximum PLL input clock frequency, removed related note, and deleted jitter for MCO for RMII Ethernet typical value in Table 32: Main PLL characteristics. Updated maximum PLLI2S input clock frequency and removed related note in Table 33: PLLI2S (audio PLL) characteristics. Updated Section : Flash memory to specify that the devices are shipped to customers with the Flash memory erased. Updated Table 35: Flash memory characteristics, and added tME in Table 36: Flash memory programming. Updated Table 39: EMS characteristics, and Table 40: EMI characteristics. Updated Table 53: I2S characteristics Updated Figure 43: ULPI timing diagram and Table 60: ULPI timing. Added tCOUNTER and tMAX_COUNT in Table 48: Characteristics of TIMx connected to the APB1 domain and Table 49: Characteristics of TIMx connected to the APB2 domain. Updated Table 63: Dynamics characteristics: Ethernet MAC signals for RMII. Removed USB-IF certification in Section : USB OTG FS characteristics. Doc ID 022152 Rev 2 165/167 Revision history STM32F405xx, STM32F407xx Table 94. Document revision history (continued) Date 24-Jan-2012 166/167 Revision Changes Updated Table 57: USB FS clock timing parameters and Table 59: USB HS clock timing parameters Updated Table 65: ADC characteristics. Updated Table 66: ADC accuracy at fADC = 30 MHz. Updated Note 1 in Table 70: DAC characteristics. Section 5.3.25: FSMC characteristics: updated Table 71 toTable 82, changed CL value to 30 pF, and modified FSMC configuration for asynchronous timings and waveforms. Updated Figure 57: Synchronous multiplexed PSRAM write timings. Updated Table 91: Package thermal characteristics. 2 Appendix A.3: USB OTG full speed (FS) interface solutions: modified (continued) Figure 82: USB controller configured as peripheral-only and used in Full speed mode added Note 2, updated Figure 83: USB controller configured as host-only and used in full speed mode and added Note 2, changed Figure 84: USB controller configured in dual mode and used in full speed mode and added Note 3. Appendix A.4: USB OTG high speed (HS) interface solutions: removed figures USB OTG HS device-only connection in FS mode and USB OTG HS host-only connection in FS mode, and updated Figure 85: USB controller configured as peripheral, host, or dual-mode and used in high speed mode and added Note 2. Added Appendix A.6: Ethernet interface solutions. Doc ID 022152 Rev 2 STM32F405xx, STM32F407xx Please Read Carefully: Information in this document is provided solely in connection with ST products. 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