1
Semiconductor
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Copyright © Harris Corporation 1998
CA3160, CA3160A
4MHz, BiMOS Operational Amplifier with
MOSFET Input/CMOS Output
The CA3160A and CA3160 are integrated circuit oper ational
amplifiers that combine the advantage of both CMOS and
bipolar transistors on a monolithic chip. The CA3160 series are
frequency compensated versions of the popular CA3130
series.
Gate protected P-Channel MOSFET (PMOS) transistors are
used in the input circuit to provide very high input
impedance, very low input current, and exceptional speed
performance. The use of PMOS field effect transistors in the
input stage results in common-mode input voltage capability
down to 0.5V below the negative supply terminal, an
important attribute in single supply applications.
A complementary symmetry MOS (CMOS) transistor-pair,
capable of swinging the output voltage to within 10mV of
either supply voltage terminal (at very high values of load
impedance), is employed as the output circuit.
The CA3160 Series circuits operate at supply voltages
ranging from 5V to 16V, or ±2.5V to ±8V when using split
supplies, and have terminals for adjustment of offset voltage
for applications requiring offset null capability. Terminal
provisions are also made to permit strobing of the output
stage.
The CA3160A offers superior input characteristics over
those of the CA3160.
Features
• MOSFET Input Stage Provides:
- Very High ZI = 1.5TΩ (1.5 x 1012Ω) (Typ)
- Very Low II. . . . . . . . . . . . . 5pA (Typ) at 15V Operation
. . . . . . . . . . . . . . . . . . . . . . . 2pA (Typ) at 5V Operation
• Common-Mode Input Voltage Range Includes
Negative Supply Rail; Input Terminals Can Be Swung
0.5V Below Negative Supply Rail
• CMOS Output Stage Permits Signal Swing to Either (or
Both) Supply Rails
Applications
• Ground Referenced Single Supply Amplifiers
• Fast Sample Hold Amplifiers
• Long Duration Timers/Monostables
• High Input Impedance Wideband Amplifiers
• Voltage Followers (e.g., Follower for Single Supply
D/A Converter)
• Wien-Bridge Oscillators
• Voltage Controlled Oscillators
• Photo Diode Sensor Amplifiers
Pinouts
CA3160
(METAL CAN)
TOP VIEW
CA3160
(PDIP)
TOP VIEW
NO TE: CA3160 Series devices ha ve an on-chip frequency
compensation network. Supplementary phase compensation or
frequency roll-off (if desired) can be connected externally between
Terminals 1 and 8.
Ordering Information
PART NUMBER TEMP.
RANGE (oC) PACKAGE PKG.
NO.
CA3160AE -55 to 125 8 Ld PDIP E8.3
CA3160E -55 to 125 8 Ld PDIP E8.3
CA3160T -55 to 125 8 Pin Metal Can T8.C
TAB
OUTPUT
INV.
V- AND CASE
OFFSET
NON-INV.
V+
OFFSET
2
4
6
1
3
7
5
8
-
+
NULL
INPUT
INPUT NULL
STROBESUPPLEMENTARY
COMPENSATION
OFFSET NULL
INV.
NON-INV.
V-
1
2
3
4
8
7
6
5
STROBE
V+
OUTPUT
OFFSET NULL
-
+
INPUT
INPUT
September 1998 File Number 976.3
2
Absolute Maximum Ratings Thermal Information
Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . . . +16V
Differential Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . .8V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V)
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Output Short Circuit Duration (Note 2). . . . . . . . . . . . . . . . Indefinite
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . 110 N/A
Metal Can Package . . . . . . . . . . . . . . . 170 85
Maximum Junction Temperature (Metal Can). . . . . . . . . . . . . . .175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
2. Short Circuit may be applied to ground or to either supply.
Electrical Specifications TA = 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS
CA3160 CA3160A
UNITSMIN TYP MAX MIN TYP MAX
Input Offset Voltage |VIO|V
S = ±7.5V - 6 15 - 2 5 mV
Input Offset Current |IIO|V
S = ±7.5V - 0.5 30 - 0.5 20 pA
Input Current IIVS = ±7.5V - 5 50 - 5 30 pA
Large-Signal Voltage Gain AOL VO = 10VP-P, RL = 2kΩ50 320 - 50 320 - kV/V
94 110 - 94 110 - dB
Common-Mode Rejection Ratio CMRR 70 90 - 80 95 - dB
Common-Mode Input-Voltage Range VlCR 0 -0.5 to 12 10 0 -0.5 to 12 10 V
Power-Supply Rejection Ratio PSRR ∆VIO/∆VS, VS = ±7.5V - 32 320 - 32 150 µV/V
Maximum Output Voltage VOM+R
L = 2kΩ12 13.3 - 12 13.3 - V
VOM- - 0.002 0.01 - 0.002 0.01 V
VOM+R
L = ∞ 14.99 15 - 14.99 15 - V
VOM- - 0 0.01 - 0 0.01 V
Maximum Output Current IOM+V
O = 0V (Source) 12 22 45 12 22 45 mA
IOM-V
O = 15V (Sink) 12 20 45 12 20 45 mA
Supply Current (Note 3) I+ VO = 7.5V, R L = ∞- 10 15 - 10 15 mA
VO = 0V, R L = ∞-23-23mA
Input Offset Voltage Temperature Drift ∆VIO/∆T-8--6-µV/oC
Electrical Specifications For Design Guidance, VSUPPLY = ±7.5V, TA = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS
CA3160 CA3160A
UNITSTYP TYP
Input Offset Voltage Adjustment Range 10kΩ Across Terminals 4 and 5 or
Terminals 4 and 1 ±22 ±22 mV
Input Resistance RI1.5 1.5 TΩ
Input Capacitance CIf = 1MHz 4.3 4.3 pF
Equivalent Input Noise Voltage eNBW = 0.2MHz RS = 1MΩ40 40 µV
RS = 10MΩ50 50 µV
Equivalent Input Noise Voltage eNRS = 100Ω1kHz 72 72 nV/√Hz
10kHz 30 30 nV/√Hz
CA3160, CA3160A
3
Block Diagram
Unity Gain Crossover Frequency fT4 4 MHz
Slew Rate SR 10 10 V/µs
Transient Response Rise and Fall Time trCL = 25pF, RL = 2kΩ, (Voltage Follower) 0.09 0.09 µs
Overshoot OS 10 10 %
Settling Time tSCL= 25pF, RL=2kΩ, (Voltage Follower)
To <0.1%, VIN = 4VP-P 1.8 1.8 µs
Electrical Specifications For Design Guidance, VSUPPLY = ±7.5V, TA = 25oC, Unless Otherwise Specified (Continued)
PARAMETER SYMBOL TEST CONDITIONS
CA3160 CA3160A
UNITSTYP TYP
Electrical Specifications For Design Guidance, V+ = +5V, V- = 0V, TA = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS
CA3160 CA3160A
UNITSTYP TYP
Input Offset Voltage VIO 62mV
Input Offset Current IIO 0.1 0.1 pA
Input Current Il22pA
Common-Mode Rejection Ratio CMRR 80 90 dB
Large Signal Voltage Gain AOL VO = 4VP-P, RL = 5kΩ100 100 kV/V
100 100 dB
Common-Mode Input Voltage Range VlCR 0 to 2.8 0 to 2.8 V
Supply Current I+ VO = 5V, RL = ∞300 300 µA
VO = 2.5V, RL = ∞ 500 500 µA
Power Supply Rejection Ratio PSRR ∆VIO/∆V+ 200 200 µV/V
NOTE:
3. ICC typically increases by 1.5mA/MHz during operation.
6
BIAS CKT.
200µA 1.35mA 200µA
7
8mA
(NOTE 4)
OUTPUT
AV≈30X
AV≈
6000X
STROBE
V-
V+
OFFSET
NULL
COMPENSATION
(WHEN DESIRED)
+
-
INPUT AV≈5X
CC
NOTES:
4. Total supply voltage (for indicated voltage
gains) = 15V with input terminals biased so
that Terminal 6 potential is +7.5V above
Terminal 4.
5. Total supply voltage (for indicated voltage
gains) = 15V with output terminal driven to
either supply rail.
0mA
(NOTE 5)
4
815
2
3
CA3160, CA3160A
4
Schematic Diagram
Application Information
Circuit Description
Ref er to the Block Diagram of the CA3160 series CMOS
Operational Amplifiers. The input terminals ma y be oper ated
down to 0.5V belo w the negative supply rail, and the output
can be s wung very close to either supply rail in many
applications. Consequently, the CA3160 series circuits are
ideal f or single supply oper ation. Three class A amplifier
stages, ha ving the individual gain capability and current
consumption shown in the Bloc k Diag r am provide the total
gain of the CA3160. A biasing circuit provides two potentials
f or common use in the first and second stages . Terminals 8
and 1 can be used to supplement the internal phase
compensation network if additional phase compensation or
frequency roll-off is desired. Terminals 8 and 4 can also be
used to strobe the output stage into a low quiescent current
state. When Terminal 8 is tied to the negative supply rail
(Terminal 4) by mechanical or electrical means, the output
potential at Terminal 6 essentially rises to the positive supply-
rail potential at Terminal 7. This condition of essentially zero
current drain in the output stage under the strobed “OFF”
condition can only be achie ved when the ohmic load
resistance presented to the amplifier is very high (e.g., when
the amplifier output is used to drive MOS digital circuits in
comparator applications).
Input Stage - The circuit of the CA3160 is shown in the
Schematic Diagram. It consists of a differential-input stage
using PMOS field-eff ect tr ansistors (Q6, Q7) working into a
mirror-pair of bipolar transistors (Q9,Q
10) functioning as load
resistors together with resistors R3 through R6. The mirror-
pair transistors also function as a differential-to-single-ended
converter to provide base drive to the second-stage bipolar
transistor (Q11). Offset nulling, when desired, can be effected
by connecting a 100,000Ω potentiometer across Terminals 1
and 5 and the potentiometer slider arm to Terminal 4.
Cascode-connected PMOS transistors Q2, Q4, are the
constant-current source for the input stage. The biasing circuit
f or the constant-current source is subsequently described.
The small diodes D5through D7provide gate-oxide protection
against high-voltage tr ansients, including static electricity
during handling for Q6 and Q7.
Second-Stage - Most of the voltage gain in the CA3160 is
provided b y the second amplifier stage, consisting of bipolar
7
4815
2
3
BIAS CURRENT “CURRENT SOURCE
LOAD” FOR Q11
Q2
D1
D2
D3
D4
Z1
8.3V
Q1
R1
40kΩ
Q4
R2
5kΩ
INPUT STAGE
D5
NON-INV.
INPUT
INV. INPUT
+
-
Q6
R3
1kΩ
Q9Q10
R5
1kΩR6
1kΩ
R4
1kΩ
Q7
D6D7
Q3
OFFSET NULL
Q11
SUPPLEMENTARY
COMP IF DESIRED STROBING
SECOND
OUTPUT Q8
Q12
STAGE
STAGE
Q5
V+
2kΩ
30
pF 6
OUTPUT
NOTE: Diodes D5 Through D7 Provide Gate Oxide Protection For MOSFET Input Stage.
CURRENT SOURCE
FOR Q6 AND Q7
CA3160, CA3160A
5
transistor Q11 and its cascode-connected load resistance
provided by PMOS transistors Q3and Q5. The source of bias
potentials for these PMOS transistors is described later. Miller
Effect compensation (roll off) is accomplished by means of the
30pF capacitor and 2kΩresistor connected between the base
and collector of transistor Q11. These internal components
provide sufficient compensation for unity gain operation in
most applications. Ho w ev er, additional compensation, if
desired, ma y be used betw een Terminals 1 and 8.
Bias-Source Cir cuit - At total supply v oltages , some what
above 8.3V, resistor R2and zener diode Z1serve to establish a
voltage of 8.3V across the series-connected circuit, consisting
of resistor R1, diodes D1through D4, and PMOS transistor Q1.
A tap at the junction of resistor R1 and diode D4 provides a
gate-bias potential of about 4.5V f or PMOS transistors Q4 and
Q5 with respect to Terminal 7. A potential of about 2.2V is
de v eloped across diode-connected PMOS transistor Q1 with
respect to Terminal 7 to provide gate bias for PMOS transistors
Q2 and Q3. It should be noted that Q1 is “mirror-connected” to
both Q2 and Q3. Since transistors Q1, Q2, Q3 are designed to
be identical, the approximately 200µA current in Q1establishes
a similar current in Q2 and Q3 as constant-current sources for
both the first and second amplifier stages, respectiv ely.
At total supply voltages somewhat less than 8.3V, zener diode
Z1 becomes nonconductive and the potential, de veloped
across series-connected R1, D1 - D4, and Q1, varies directly
with variations in supply v oltage. Consequently, the gate bias
f or Q4, Q5 and Q2, Q3 varies in accordance with supply-
voltage variations. This variation results in deterioration of the
power-supply-rejection r atio (PSRR) at total supply voltages
below 8.3V. Operation at total supply voltages below about
4.5V results in seriously degraded perf ormance.
Output Stage - The output stage consists of a drain-loaded
inv erting amplifier using CMOS transistors operating in the
Class A mode. When operating into very high resistance loads,
the output can be s wung within milliv olts of either supply rail.
Because the output stage is a drain-loaded amplifier, its gain is
dependent upon the load impedance. The transfer
characteristics of the output stage for a load returned to the
negative supply r ail are sho wn in Figure 17. Typical op amp
loads are readily driven b y the output stage. Because large-
signal e xcursions are non-linear, requiring feedbac k f or good
wa v eform reproduction, transient delays may be encountered.
As a voltage follower, the amplifier can achieve 0.01% accuracy
le v els , including the negativ e supply rail.
Offset Nulling
Offset-voltage nulling is usually accomplished with a
100,000Ω potentiometer connected across Terminals 1 and
5 and with the potentiometer slider arm connected to
Terminal 4. A fine offset-null adjustment usually can be
effected with the slider arm positioned in the mid-point of the
potentiometer's total range.
Input Current Variation with Common Mode Input
Voltage
As shown in the Electrical Specifications, the input current f or
the CA3160 Series Op Amps is typically 5pA at TA = 25oC
when Terminals 2 and 3 are at a common-mode potential of
+7.5V with respect to negative supply Terminal 4. Figure 23
contains data showing the v ariation of input current as a
function of common-mode input voltage at TA=25
oC. These
data show that circuit designers can adv antageously exploit
these characteristics to design circuits which typically require
an input current of less than 1pA, provided the common-mode
input voltage does not exceed 2V. As pre viously noted, the
input current is essentially the result of the leakage current
through the gate-protection diodes in the input circuit and,
theref ore, a function of the applied voltage. Although the finite
resistance of the glass terminal-to-case insulator of the metal
can package also contributes an increment of leakage current,
there are useful compensating f actors. Because the gate-
protection network functions as if it is connected to Terminal 4
potential, and the metal can case of the CA3160 is also
internally tied to Terminal 4, input Terminal 3 is essentially
“guarded” from spurious leakage currents.
Input-Current Variation with Temperature
The input current of the CA3160 Series circuits is typically 5pA
at 25oC . The major portion of this input current is due to
leakage current through the gate-protective diodes in the input
circuit. As with any semiconductor junction device, including op
amps with a junction-FET input stage, the leakage current
approximately doubles for every 10oC increase in temperature.
Figure 24 provides data on the typical v ariation of input bias
current as a function of temperature in the CA3160.
In applications requiring the lowest practical input current and
incremental increases in current because of “warm-up” effects ,
it is suggested that an appropriate heat sink be used with the
CA3160. In addition, when “sinking” or “sourcing” significant
output current the chip temperature increases, causing an
increase in the input current. In such cases, heat-sinking can
also very markedly reduce and stabilize input current variations.
Input Offset Voltage (V
IO
) Variation with DC Bias
vs Device Operating Life
It is well known that the char acteristics of a MOSFET device
can change slightly when a DC gate-source bias potential is
applied to the device for extended time periods. The magnitude
of the change is increased at high temperatures. Users of the
CA3160 should be alert to the possible impacts of this eff ect if
the application of the de vice in v olv es extended operation at
high temperatures with a significant differential DC bias voltage
applied across Terminals 2 and 3. Figure 25 shows typical data
pertinent to shifts in offset voltage encountered with CA3160
de vices in metal can pac kages during life testing. At lo w er
temperatures (metal can and plastic) f or example at 85oC, this
change in voltage is consider ab ly less . In typical linear
applications where the diff erential v oltage is small and
symmetrical, these incremental changes are of about the same
CA3160, CA3160A
6
magnitude as those encountered in an operational amplifier
emplo ying a bipolar transistor input stage . The 2V diff erential
voltage example represents conditions when the amplifier
output state is “toggled”, e.g., as in comparator applications .
Power Supply Considerations
Because the CA3160 is very useful in single supply
applications, it is pertinent to review some consider ations
relating to power supply current consumption under both
single and dual supply service. Figures 1A and 1B sho w the
CA3160 connected f or both dual and single supply oper ation.
Dual-supply operation: When the output voltage at Terminal
6 is 0V, the currents supplied by the two power supplies are
equal. When the gate terminals of Q8 and Q12 are driven
increasingly positive with respect to ground, current flow
through Q12 (from the negative supply) to the load is
increased and current flow through Q8 (from the positive
supply) decreases correspondingly. When the gate terminals
of Q8 and Q12 are driven increasingly negative with respect
to ground, current flow through Q8 is increased and current
flow through Q12 is decreased accordingly.
Single supply operation: Initially, let it be assumed that the
value of RLis very high (or disconnected), and that the input-
terminal bias (Terminals 2 and 3) is such that the output
terminal (No. 6) voltage is at V+/2, i.e., the voltage-drops
across Q8and Q12 are of equal magnitude. Figure 18 shows
typical quiescent supply-current vs supply voltage for the
CA3160 operated under these conditions.
Since the output stage is operating as a Class A amplifier, the
supply current will remain constant under dynamic operating
conditions as long as the transistors are operated in the linear
portion of their voltage-transfer characteristics (see Figure 17).
If either Q8 or Q12 are swung out of their linear regions tow ard
cutoff (a non-linear region), there will be a corresponding
reduction in supply-current. In the e xtreme case, e .g., with
Terminal 8 swung do wn to ground potential (or tied to g round),
NMOS transistor Q12 is completely cut off and the supply
current to series connected transistors Q8, Q12 goes
essentially to zero. The two preceding stages in the CA3160,
howev er, continue to draw modest supply-current (see the
lower curve in Figure 18) ev en though the output stage is
strobed off. Figure 1A shows a dual-supply arrangement for the
output stage that can also be strobed off , assuming RL=∞, by
pulling the potential of Terminal 8 down to that of Terminal 4.
Let it now-be assumed that a load resistance of nominal v alue
(e.g., 2kΩ) is connected between Terminal 6 and ground in the
circuit of Figure 1B. Let it further be assumed again that the
input-terminal bias (Terminals 2 and 3) is such that the output
terminal (No. 6) v oltage is at V+/2. Since PMOS tr ansistor Q8
must now supply quiescent current to both RL and transistor
Q12, it should be apparent that under these conditions the
supply current must increase as an in v erse function of the RL
magnitude. Figure 20 sho ws the v oltage-drop across PMOS
transistor Q8 as a function of load current at sev er al supply
voltages. Figure 17 shows the voltage transfer characteristics of
the output stage f or se v er al v alues of load resistance .
Wideband Noise
From the standpoint of low-noise performance considerations,
the use of the CA3160 is most advantageous in applications
where in the source resistance of the input signal is on the
order of 1MΩ or more. In this case, the total input-ref erred
noise voltage is typically only 40µV when the test circuit
amplifier of Figure 2 is operated at a total supply v oltage of
15V. This value of total input-referred noise remains
essentially constant, e ven though the v alue of source
resistance is raised b y an order of magnitude . This
characteristic is due to the fact that reactance of the input
capacitance becomes a significant f actor in shunting the
source resistance. It should be noted, however, that for values
of source resistance very much greater than 1MΩ, the total
noise voltage gener ated can be dominated by the thermal
noise contributions of both the f eedback and source resistors.
7
3
2
8
4
6
V+
-
+
CA3160
NEGATIVE
SUPPLY
OUTPUT
RL
STAGE
Q12
Q8
V-
FIGURE 1A. DUAL POWER SUPPLY OPERATION
7
3
2
8
4
6
-
+
CA3160 OUTPUT
RL
STAGE
Q12
Q8
V+
FIGURE 1B. SINGLE POWER SUPPLY OPERATION
FIGURE 1. CA3160 OUTPUT STAGE IN DUAL AND SINGLE
POWER SUPPLY OPERATION
CA3160, CA3160A
7
CA3160 6
7
3
4
2
+7.5V
0.01µF
NOISE
VOLTAGE
OUTPUT
30.1kΩ
0.01
µF
1kΩ
-7.5V
RS
1MΩ+
-
BW (3dB) = 200kHz
TOTAL NOISE VOLTAGE
(INPUT REFERRED = 40µV (TYP)
FIGURE 2. TEST CIRCUIT AMPLIFIER (30dB GAIN) USED FOR
WIDEBAND NOISE MEASUREMENTS
Typical Performance Curves
FIGURE 3A.
FIGURE 3B. SMALL SIGNAL RESPONSE FIGURE 3C. INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING
SETTLING TIME
FIGURE 3. DUAL SUPPLY VOLTAGE FOLLOWER WITH ASSOCIATED WAVEFORMS
CA3160 6
7
3
4
2
+7.5V
0.01µF
0.01
µF
-7.5V
10kΩ+
-2kΩ
25pF
SIMULATED
LOAD
CAPACITANCE
0.1µF
BW (-3dB) = 4MHz
SR = 10V/µs
2kΩ
Top Trace: Output
Bottom Trace: Input
Top Trace: Output Signal
Center Trace: Difference Signal 5mV/Div.
Bottom Trace: Input Signal
CA3160, CA3160A
8
Typical Applications
Voltage Follo wers
Operational amplifiers with v ery high input resistances, lik e
the CA3160, are particularly suited to service as voltage
f ollo w ers. Figure 3 shows the circuit of a classical voltage
follower, together with pertinent waveforms using the CA3160
in a split-supply configuration.
A voltage follo w er, operated from a single supply, is shown in
Figure 4 together with related waveforms. This follower circuit
is linear over a wide dynamic range, as illustr ated by the
reproduction of the output wa veform in Figure 4B with input-
signal ramping. The wav eforms in Figure 4C show that the
f ollo w er does not lose its input-to-output phase-sense, e ven
though the input is being s wung 7.5V belo w g round potential.
This unique characteristic is an important attribute in both
operational amplifier and comparator applications . Figure 4C
also shows the manner in which the COS/MOS output stage
permits the output signal to swing down to the negative
supply-rail potential (i.e., g round in the case shown). The
digital-to-analog converter (D AC) circuit, described in the
following section, illustrates the practical use of the CA3160 in
a single supply voltage follo w er application.
9-Bit CMOS D A C
A typical circuit of a 9-bit Digital-to-Analog Conv erter (DA C) (see
Note6) isshownin Figure5. This systemcombines the concepts
of multiple-s witch CMOS lCs, a lo w-cost ladder network of
discrete metal-oxide-film resistors, a CA3160 op amp connected
as a follower, and an inexpensive monolithic regulator in a simple
single power-supply arr angement. An additional f eature of the
D A C is that it is readily interf aced with CMOS input logic, e .g.,
10V logic le vels are used in the circuit of Figure 5.
The circuit uses an R/2R voltage-ladder network, with the output-
potential obtained directly by terminating the ladder arms at
either the positive or the negativ e po wer supply terminal. Each
CD4007A contains three inverters, each inverter functioning as a
single-pole double-thro w s witch to terminate an arm of the R/2R
network at either the positive or negativ e po wer-supply terminal.
The resistor ladder is an assembly of 1% toler ance metal-o xide
film resistors. The fiv e arms requiring the highest accuracy are
assembled with series and parallel combinations of 806,000Ω
resistors from the same manuf acturing lot.
A single 15V supply provides a positiv e b us f or the CA3160
f ollower amplifier and f eeds the CA3085 v oltage regulator. A
“scale-adjust” function is provided by the regulator output control,
set to a nominal 10V le vel in this system. The line-v oltage
regulation (appro ximately 0.2%) permits a 9-bit accuracy to be
maintained with variations of se v eral v olts in the supply. The
fle xibility aff orded by the CMOS b uilding b locks simplifies the
design of D A C systems tailored to particular needs.
NOTE:
6. “Digital-to-Analog Conversion Using the Harris CD4007A
COS/MOS lC”, Application Note AN6080.
FIGURE 4A.
FIGURE 4B. OUTPUT WAVEFORM WITH GROUND REFERENCE
SINE WAVE INPUT
FIGURE 4C. OUTPUT SIGNAL WITH INPUT SIGNAL RAMPING
FIGURE 4. SINGLE SUPPLY VOLTAGE FOLLOWER WITH
ASSOCIATED WAVEFORMS. (e.g., FOR USE IN
SINGLE SUPPLY D/A CONVERTER; SEE FIGURE 9
IN AN6080)
CA3160 6
7
3
4
2
+15V
0.01µF
10kΩ+
-
0.1µF
BW (-3dB) = 4MHz
SR = 10V/µs
15
2kΩ
OFFSET
ADJUST
Top Trace: Output
Bottom Trace: Input
CA3160, CA3160A
9
Error-Amplifier in Regulated Power Supplies
The CA3160 is an ideal choice for error-amplifier service in
regulated power supplies since it can function as an error-
amplifier when the regulated output voltage is required to
approach zero.
The circuit shown in Figure 6 uses a CA3160 as an error
amplifier in a continuously adjustable 1A power supply. One
of the key features of this circuit is its ability to regulate down
to the vicinity of 0V with only one DC power supply input.
An RC network, connected between the base of the output
drive transistor and the input voltage, prevents “turn-on
overshoot”, a condition typical of many operational
amplifier regulator circuits. As the amplifier becomes
operational, this RC network ceases to have any influence
on the regulator perfor mance.
Precision Voltage-Controlled Oscillator
The circuit diagram of a precision voltage-controlled oscillator is
shown in Figure 7. The oscillator operates with a tr ac king error
in the order of 0.02% and a temperature coefficient of
0.01%/oC. A multivibr ator (A1) gener ates pulses of constant
amplitude (V) and width (T2). Since the output (Terminal 6) of
A1 (a CA3130) can s wing within about 10mV of either supply-
rail, the output pulse amplitude (V) is essentially equal to V+.
The av er age output v oltage (EAVG = V T2/T1) is applied to the
non-inverting Input terminal of comparator A2via an integrating
network R3, C2. Comparator A2 oper ates to estab lish circuit
conditions such that EAVG = V1. This circuit condition is
accomplished by feeding an output signal from Terminal 6 of A2
through R4, D4 to the inv erting terminal (Terminal 2) of A1,
thereby adjusting the m ultivibrator interval, T3.
Voltmeter With High Input Resistance
The voltmeter circuit shown in Figure 8 illustrates an
application in which a number of the CA3160 characteristics
are exploited. Range-switch SW1 is ganged between input
and output circuitry to permit selection of the proper output
voltage for feedback to Terminal 2 via 10kΩ current-limiting
resistor. The circuit is powered by a single 8.4V mercury
battery. With zero input signal, the circuit consumes
somewhat less than 500µA plus the meter current required
to indicate a given voltage. Thus, at full scale input, the total
supply current rises to slightly more than 1500µA.
CA3085
1
2
6
3
0.001µF
47
6
13
8
1
5
12
CD4007A
“SWITCHES”
103
14
11
2
9
4
7
806K
1% 402K
1% 200K
1%
806K
1%
6
13
8
1 12
CD4007A
“SWITCHES”
103
100K
1%
(2)
806K
6
13
8
12
CD4007A
“SWITCHES”
103
806K
1% 806K
1% 1%
(4)
806K
1%
(8)
806K
1%
1
5
806K
1% 750K
1%
10V LOGIC INPUTS
PARALLELED
RESISTORS
+10.010V
LSB MSB
987 654 321
8+10.010V
22.1K
1%
1K
3.83K
1%
2µF
25V
+
-
+15V 62
VOLTAGE
REGULATOR
REGULATED
VOLTAGE
ADJUST
CA3160
3
42
0.1µF
+
-
1
5
6
2K
+15V
100K
VOLTAGE
FOLLOWER
7
OFFSET
NULL
OUTPUT
LOAD
10K
BIT REQUIRED
RATIO-MATCH
1 Standard
2±0.1%
3±0.2%
4±0.4%
5±0.8%
6 - 9 ±1% ABS.
FIGURE 5. 9-BIT DAC USING CMOS DIGITAL SWITCHES AND CA3160
806K
1%
5
CA3160, CA3160A
10
Function Generator
A function generator having a wide tuning range is shown in
Figure 9. The adjustment range, in excess of 1,000,000/1, is
accomplished by a single potentiometer. Three operational
amplifiers are utilized: a CA3160 as a voltage follower, a
CA3080 as a high speed comparator, and a second
CA3080A as a programmable current source. Three variable
capacitors C1, C2, and C3 shape the triangular signal
between 500kHz and 1MHz. Capacitors C4, C5, and the
trimmer potentiometer in series with C5 maintain essentially
constant (+10%) amplitude up to 1MHz.
5
4
1
6
7
8
+
-
CA3160
2
3
1
2
3
40V INPUT
+
2.4kΩ
1W
100µF
25V CA3086
+
-+
-
2.2kΩ
5µF
10 11 2 1
93
57
64
12 14
13
0.2µF
TURN
ON
DELAY
100kΩ1.5kΩ
1W
1kΩ
62kΩ
-
2N6385
POWER DARLINGTON SHORT-CIRCUIT CURRENT
LIMIT ADJUSTMENT
1Ω
10kΩ
1kΩ2N2102
1N914 56pF 43kΩ
10kΩ
-
+
OUTPUT
0V TO 35V
AT 1A
10kΩ
4.7kΩ
0.01µF
8.2kΩ
100µF
100kΩ50kΩ
2kΩ
-
Hum and Noise Output <250µVRMS; Regulation (No Load to Full Load) <0.005%; Input Regulation <0.01%/V
FIGURE 6. VOLTAGE REGULATOR CIRCUIT (0.1V TO 35V AT 1A)
1kΩ
2N2102
8
4
7
+
-
MULTI-
3
R5
VIBRATOR
CA3130
2
6
+
-
COMPARATOR
CA3160
3 4
1
27
6
+15V
100K
R6
100K C1
500pF
D1
D20.1
µF
R1
182K
100K
10K
fO
EAVG = V T2/T1
R3
1M
0.01µF
1M
R2
10K
VCO CONTROL VOLTAGE (VI)
(0V - 10V)
(SENSITIVITY = 1kHz/V)
C2
0.01µF
D1 - D5 = 1N914
R4
R7
100K
0.01µF
D5
T2T3
V
T1
+15V
+15V
D3
D4
FIGURE 7. VOLTAGE CONTROLLED OSCILLATOR
3K
5
CA3160, CA3160A
11
300V
100V
30V
10V
1V
300V
100V
30V
10V
3V
1V
300V
100V
30V
10V
3V
300V
100V
30V
10V
100MΩ
1.02
SW1A
INPUT
MΩ
CA3160
7
3
4
2
15
6
+
-
30V
10V
3V
1V
300mV
100V
300V
30mV
10mV
100mV
SW1B
SW1C SW1D
M
30V
10V
1V
100V
300V
3V
300mV
30mV
10mV
100mV
9kΩ
900Ω
100Ω
BATTERY
TEST
OFF ON
3 POSITION
SLIDE SWITCH
BATTERY
100kΩ
ZERO
ADJUST
10kΩ
9.1kΩ
1V CAL.
820Ω200Ω
2.7kΩ3V CAL.
500Ω
+9V
BATTERY
500
µF
0-1mA
+
-
0.001µF
22MΩ
9.9kΩ
FIGURE 8. HIGH INPUT RESISTANCE DC VOLTMETER
1kΩ
3
7
5
CA3080A
+
-4
2
63
CA3160
+
-
2
7
4
6 2
CA3080
+
-
3
7
6
5
20pF
8.2kΩ
+7.5V
VOLTAGE-CONTROLLED
CURRENT SOURCE
1kΩ
2MΩ-7.5V
4.7kΩ
-7.5V
SYMMETRY
+7.5V
10kΩ
MAX FREQ
SET
500Ω
FREQ
ADJUST
MIN FREQ.SET
-7.5V
EXTERNAL
SWEEPING INPUT
10-80pF
C2
100kΩ
+7.5V
0.9 - 7pF
C1
6.2kΩ
HIGH
FREQ.
SHAPE
4 - 60pF
C3
BUFFER
VOLTAGE FOLLOWER
+7.5V
0.1µF
CENTERING
100kΩ
430pF
10kΩ
2kΩ
C4
4 - 60pF
HIGH FREQ
LEVEL
ADJUST
6.8MΩ
-7.5V +7.5V
30kΩ
10kΩ
50kΩ
C5
15 - 115pF
0.1µF
-7.5V
THRESHOLD
DETECTOR
2-1N914
+7.5V
-7.5V
6.2kΩ500Ω
FIGURE 9A. 1,000,000/1 SINGLE CONTROL FUNCTION GENERATOR: 1Hz to 1MHz
CA3160, CA3160A
12
Staircase Generator
Figure 10 shows a staircase generator circuit utilizing three
CMOS operational amplifiers. Two CA3130s are used; one
as a multivibrator, the other as a hysteresis switch. The third
amplifier, a CA3160, is used as a linear staircase generator.
Picoammeter Circuit
Figure 11 is a current-to-voltage converter configuration
utilizing a CA3160 and CA3140 to provide a picoampere
meter for 13pA full scale meter deflection. By placing
Terminals 2 and 4 of the CA3160 at ground potential, the
CA3160 input is operated in the “guarded mode”. Under this
operating condition, even slight leakage resistance present
between Terminals 3 and 2 or between Terminals 3 and 4
would result in zero voltage across this leakage resistance,
thus substantially reducing the leakage current.
If the CA3160 is operated with the same voltage on input
Terminals 3 and 2 as on Terminal 4, a further reduction in the
NOTE: Asquarewave signalmodulatestheexternalsweepinginput
toproduce1Hz and 1MHz,showingthe 1,000,000/1 frequencyrange
of the Function Generator.
FIGURE 9B. TWO-TONE OUTPUT SIGNAL FROM THE
FUNCTION GENERATOR
NO TE: The bottom trace is the s w eeping signal and the top tr ace is
theactual generatoroutput. The center trace displaysthe1MHzsignal
via delayed oscilloscope triggering of the upper swept output signal.
FIGURE 9C. TRIPLE-TRACE OF THE FUNCTION GENERATOR
SWEEPING TO 1MHz
FIGURE 9. 1,000,000/1 SINGLE CONTROL FUNCTION GENERATOR: 1Hz to 1MHz
8
3
2
4
7
CA3130
+
-
62
3
4
7
CA3160
+
-6 3
2
4
7
CA3130
+
-8
6
+15V
100
kΩ1MΩ+15V
15 - 115pF
FREQ
ADJUST
MULTIVIBRATOR RETRACE INHIBIT
100
kΩ
100
kΩ
MULTIVIBRATOR
STEP HEIGHT
ADJUST
4 - 60pF
8.2kΩ
CHARGE
COMMUTATING
NETWORK
470pF
+15V
INTEGRATOR
STAIRCASE
OUTPUT
10kΩ
2kΩ
1.5
HYSTERESIS SWITCH
+15V
+15V
+15mV TO +10V 51kΩ
100kΩ
5.1kΩ1N914
MΩ
1N914
FIGURE 10A. STAIRCASE GENERATOR CIRCUIT
CA3160, CA3160A
13
input current to the less than one picoampere level can be
achieved as shown in Figure 23.
To further enhance the stability of this circuit, the CA3160
can be operated with its output (Terminal 6) near ground,
thus markedly reducing the dissipation by reducing the
supply current to the device.
The CA3140 stage serves as a X100 gain stage to provide
the required plus and minus output swing for the meter and
feedback network. A 100-to-1 voltage divider network
consisting of a 9.9kΩ resistor in series with a 100Ω resistor
sets the voltage at the 10GΩresistor (in series with Terminal
3) to ±30mV full-scale deflection. This 30mV signal results
from ±3V appearing at the top of the voltage divider network
which also drives the meter circuitry.
By utilizing a switching technique in the meter circuit and in
the 9.9kΩand 100Ωnetwork similar to that used in voltmeter
circuit shown in Figure 8, a current range of 3pA to 1nA full
scale can be handled with the single 10GΩ resistor.
STAIRCASE
OUTPUT
2V STEPS
COMPARATOR
OSCILLATOR
Top Trace: Staircase Output 2V Steps
Center Trace: Comparator
Bottom Trace: Oscillator
FIGURE 10B. STAIRCASE GENERATOR WAVEFORM
FIGURE 10. STAIRCASE GENERATOR CIRCUIT
4
1
7
CA3160
+
-6
10MΩ
+15V
100kΩ
10kΩ
5
2
4
6
7
CA3140
+
-
3
1MΩ
M
9.9kΩ5.6kΩ
500-0-500µA
-15V
560kΩ
9.1kΩ
500Ω
100Ω
+15V
10GΩ
10pF
0.1µF
2
0.1µF
3
-15V
FIGURE 11. CURRENT-TO-VOLTAGE CONVERTER TO PROVIDE A PICOAMMETER WITH ±3pA FULL SCALE DEFLECTION
4
1
7
CA3160
+
-
1MΩ
+15V
100kΩ
5
9.1kΩ
2
0.1µF
3
6
0.1µF
2
6
34
CA3080A
+
-7
5
2
34
CA3140
+
-7
6
+15V
0.1µF
39kΩ
2200pF
8.2Ω
1MΩ
100kΩ
27kΩ
STROBE INPUT
500µA
DROOP
ZERO
ADJUST
SAMPLE =
HOLD = 15V
0V
100kΩ
30pF
39kΩ
0.1µF
1N914
OFFSET
VOLTAGE
ADJUST
8.2kΩ
2kΩ
0.1µF
+15V
FIGURE 12A. SINGLE SUPPLY SAMPLE AND HOLD SYSTEM, INPUT 0V TO 10V
8
CA3160, CA3160A
14
Single Supply Sample-and-Hold System
Figure 12 shows a single supply sample-and-hold system
using a CA3160 to provide a high input impedance and an
input voltage range of 0V to 10V. The output from the input
buffer integrator network is coupled to a CA3080A. The
CA3080A functions as a strobeable current source for the
CA3140 output integrator and storage capacitor. The
CA3140 was chosen because of its low output impedance
and constant gain-bandwidth product. Pulse “droop” during
the hold interval can be reduced to zero by adjusting the
100kΩ bias-voltage potentiometer on the positive input of
the CA3140. This zero adjustment sets the CA3080A output
voltage at its zero current position. In this sample-and-hold
circuit it is essential that the amplifier bias current be
reduced to zero to minimize output signal current during the
hold mode. Even with 320mV at the amplifier bias circuit
terminal (5) at least 1100pA of output current will be
available.
Wien Bridge Oscillator
A simple, single supply Wien Bridge oscillator using a
CA3160 is shown in Figure 13. A pair of parallel-connected
1N914 diodes comprise the gain-setting network which
standardizes the output voltage at approximately 1.1V. The
500Ω potentiometer is adjusted so that the oscillator will
always star t and the oscillation will be maintained.
Increasing the amplitude of the voltage may lower the
threshold level for starting and for sustaining the oscillation,
but will introduce more distortion.
Operation with Output Stage Power Booster
The current sourcing and sinking capability of the CA3160
output stage is easily supplemented to provide po wer-boost
capability. In the circuit of Figure 14, three CMOS transistor-
pairs in a single CA3600 lC array are shown parallel-connected
with the output stage in the CA3160. In the Class A mode of
CA3600E shown, a typical de vice consumes 20mA of supply
current at 15V operation. This arrangement boosts the current-
handling capability of the CA3160 output stage by about 2.5X.
The amplifier circuit in Figure 14 employs feedback to
establish a closed-loop gain of 20dB. The typical large-
signal-bandwidth (-3dB) is 190kHz.
Top Trace: Sampled Output
Center Trace: Input Signal
Bottom Trace: Sampling Pulses
FIGURE 12B. SAMPLE AND HOLD WAVEFORM
Top Trace: Sampled Output
Center Trace: Input Signal
Bottom Trace: Sampling Pulses
FIGURE 12C. SAMPLE AND HOLD WAVEFORM
FIGURE 12. SINGLE SUPPLY SAMPLE AND HOLD SYSTEM, INPUT 0V TO 10V
SAMPLED
OUTPUT
INPUT
SIGNAL
SAMPLING
PULSES
SAMPLED
OUTPUT
INPUT 0V-
SAMPLING
PULSES
0V-
4
CA3160
+
-
7
6
0.01µF
2kΩ
f = 1
2π√(R1 || R2) C1 R3 C2
R1
100kΩ
R3
51kΩ+15V
R2
100kΩ
C1
10-80
pF
680Ω
500Ω
0.1
µF
C2
51pF OUTPUT
f = 100kHz
2% THD AT 1.1VP-P
2-1N914
3
2
FIGURE 13. SINGLE SUPPLY WEIN BRIDGE OSCILLATOR
CA3160, CA3160A
15
Typical Performance Curves
FIGURE 15. OPEN LOOP VOLTAGE GAIN AND PHASE SHIFT
vs FREQUENCY FIGURE 16. OPEN LOOP GAIN vs TEMPERATURE
8
CA3160
+
-6
1MΩ
26
3
7
13
3 10
7 4 9
85
1
2
14 11
12
0.01µF
1µF
680kΩ
2kΩ
INPUT
1µF
20kΩ
CA3600
A = 20dB
LARGE SIGNAL
BW (-3dB) = 190kHz QN1 QN2 QN3
QP1 QP2 QP3
4
+15V
500µF
50Ω
100mW
AT 10%
THD
-+
FIGURE 14. CMOS TRANSISTOR ARRAY (CA3600E) CONNECTED AS POWER BOOSTER IN THE OUTPUT STAGE OF THE CA3160
120
100
80
60
40
20
0
OPEN LOOP VOLTAGE GAIN (dB)
0
50
100
150
200
OPEN LOOP PHASE (DEGREES)
101102103104105106107108
FREQUENCY (Hz)
VS = ±7.5V
TA = 25oC
CL = 30pF
RL = 2kΩ
φ OL
150
140
130
120
110
100
90
80
-100 -50 0 50 100
OPEN LOOP VOLTAGE GAIN (dB)
TEMPERATURE (oC)
RL = 2kΩ
CA3160, CA3160A
16
FIGURE 17. VOLTAGE TRANSFER CHARACTERISTICS OF
CMOS OUTPUT STAGE FIGURE 18. QUIESCENT SUPPLY CURRENT vs SUPPLY
VOLTAGE
FIGURE 19. QUIESCENT SUPPLY CURRENT vs SUPPLY
VOLTAGE FIGURE 20. VOLTAGE ACROSS PMOS OUTPUT TRANSISTOR
(Q8) vs LOAD CURRENT
FIGURE 21. VOLTAGE ACROSS NMOS OUTPUT TRANSISTOR
(Q12) vs LOAD CURRENT FIGURE 22. EQUIVALENT NOISE VOLTAGE vs FREQUENCY
Typical Performance Curves
(Continued)
17.5
15
12.5
10
7.5
5
2.5
OUTPUT VOLTAGE [TERMS. 4 AND 6] (V)
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5
GATE VOLTAGE [TERMINALS 4 AND 8] (V)
V+ = 15V, V- = 0V
TA = 25oC
RL = 5kΩ
2kΩ
1kΩ
500Ω
0
15.0
12.5
10.0
7.5
5.0
2.5
0
QUIESCENT SUPPLY CURRENT (mA)
6 8 10 12 14 16 18
POSITIVE SUPPLY VOLTAGE (V)
TA = 25oC
RL = ∞
V- = 0
HIGH VO = V+
OR LOW VO = V-
BALANCED
VO = V+/2
14
12
10
8
6
4
2
0
QUIESCENT SUPPLY CURRENT (mA)
0 2 4 6 8 10 12 14 16 18
POSITIVE SUPPLY VOLTAGE (V)
VO = V+ / 2
V- = 0
TA = -55oC
25oC
125oC
50
10
1
0.1
0.01
0.001
VOLTAGE DROP ACROSS PMOS OUTPUT STAGE
TRANSISTOR (Q8) (V)
0.001 0.01 0.1 1 10 100
MAGNITUDE OF LOAD CURRENT (mA)
V- = 0V
TA = 25oCV+ = 15V
10V
5V
V- = 0V
TA = 25oCV+ = 15V
10V
5V
50
10
1
0.1
0.01
0.001
VOLTAGE DROP ACROSS NMOS OUTPUT STAGE
TRANSISTOR (Q12) (V)
0.001 0.01 0.1 1 10 100
MAGNITUDE OF LOAD CURRENT (mA)
1000
100
10
EN (nV/√Hz)
1101102103104105
FREQUENCY (Hz)
TA = 25oC
VS = ±7.5V
1
CA3160, CA3160A
17
FIGURE 23. INPUT CURRENT vs COMMON MODE VOLTAGE FIGURE 24. INPUT CURRENT vs TEMPERATURE
FIGURE 25. TYPICAL INCREMENTAL OFFSET VOLTAGE SHIFT vs OPERATING LIFE
Typical Performance Curves
(Continued)
10
7.5
5
2.5
0-101234567
INPUT CURRENT (pA)
INPUT VOLTAGE (V)
TA = 25oC
15V
TO
5V
V+
V-
0V
TO
-10V
CA3160
2
3
6
7
8
4
PA
VIN
4000
1000
100
10
1
-80 -60 -40 -20 0 20 40 60 80 100 120 140
VS = ±7.5V
TEMPERATURE (oC)
INPUT CURRENT (pA)
7
6
5
4
3
2
1
0
OFFSET VOLTAGE SHIFT (mV)
0500 1000 1500 2000 2500 3000 3500 4000
TIME (HOURS)
TA = 125oC FOR
METAL CAN PACKAGES
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 0V
OUTPUT VOLTAGE = V+ / 2
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 2V
OUTPUT STAGE TOGGLED
CA3160, CA3160A
