VNH2SP30-E Automotive fully integrated H-bridge motor driver Features Type RDS(on) Iout Vccmax VNH2SP30-E 19m max (per leg) 30A 41V 5V logic level compatible inputs Undervoltage and overvoltage shut-down Overvoltage clamp Thermal shut down Cross-conduction protection Linear current limiter Very low stand-by power consumption PWM operation up to 20 kHz Protection against loss of ground and loss of VCC Current sense output proportional to motor current Package: ECOPACK(R) MultiPowerSO-30TM The low side switches are vertical MOSFETs manufactured using STMicroelectronic's proprietary EHD (`STripFETTM') process. The three die are assembled in the MultiPowerSO-30 package on electrically isolated leadframes. This package, specifically designed for the harsh automotive environment offers improved thermal performance thanks to exposed die pads. Moreover, its fully symmetrical mechanical design allows superior manufacturability at board level. The input signals INA and INB can directly interface to the microcontroller to select the motor direction and the brake condition. The DIAGA/ENA or DIAGB/ENB, when connected to an external pull-up resistor, enable one leg of the bridge. They also provide a feedback digital diagnostic signal. The normal condition operation is explained in Table 12: Truth table in normal operating conditions on page 14. The motor current can be monitored with the CS pin by delivering a current proportional to its value. The speed of the motor can be controlled in all possible conditions by the PWM up to 20 kHz. In all cases, a low level state on the PWM pin will turn off both the LSA and LSB switches. When PWM rises to a high level, LSA or LSB turn on again depending on the input pin state. Description The VNH2SP30-E is a full bridge motor driver intended for a wide range of automotive applications. The device incorporates a dual monolithic high side driver and two low side switches. The high side driver switch is designed using STMicroelectronic's well known and proven proprietary VIPowerTM M0 technology which permits efficient integration on the same die of a true Power MOSFET with an intelligent signal/protection circuitry. Table 1. Device summary Order codes Package MultiPowerSO-30 October 2008 Tube Tape and Reel VNH2SP30-E VNH2SP30TR-E Rev 8 1/33 www.st.com 1 Contents VNH2SP30-E Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1 5 6 2/33 Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PowerSSO-30 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.1 Thermal calculation in clockwise and anti-clockwise operation in steadystate mode 26 4.1.2 Thermal resistances definition (values according to the PCB heatsink area) 26 4.1.3 Thermal calculation in transient mode . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1.4 Single pulse thermal impedance definition (values according to the PCB heatsink area) . . . . . . . . . . . . . . . . . . . . . 26 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1 ECOPACK(R) packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2 MultiPowerSO-30 package mechanical data . . . . . . . . . . . . . . . . . . . . . . 29 5.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 VNH2SP30-E List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Block description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin functions description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic inputs (INA, INB, ENA, ENB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Switching (VCC = 13V, RLOAD = 0.87W , unless otherwise specified) . . . . . . . . . . . . . . . . 10 Protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Current sense (9V < VCC < 16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Truth table in normal operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Truth table in fault conditions (detected on OUTA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Thermal calculation in clockwise and anti-clockwise operation in steady-state mode . . . . 26 Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 MultiPowerSO-30 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3/33 List of figures VNH2SP30-E List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. 4/33 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Definition of the delay times measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Definition of the low side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Definition of the high side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Definition of dynamic cross conduction current during a PWM operation. . . . . . . . . . . . . . 13 On state supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Off state supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 High level enable pin current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Delay time during change of operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Enable clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 High level enable voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Low level enable voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PWM high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PWM low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PWM high level current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Current limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 On state high side resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 On state low side resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Turn-On delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Turn-Off delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Output voltage rise time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Output voltage fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Typical application circuit for DC to 20 kHz PWM operation short circuit protection . . . . . 20 Behavior in fault condition (How a fault can be cleared). . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Half-bridge configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Multi-motors configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Waveforms in full bridge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Waveforms in full bridge operation (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 MultiPowerSO-30TM PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Chipset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Auto and mutual Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . 25 MultiPowerSO-30 HSD thermal impedance junction ambient single pulse . . . . . . . . . . . . 27 MultiPowerSO-30 LSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . 27 Thermal fitting model of an H-bridge in MultiPowerSO-30 . . . . . . . . . . . . . . . . . . . . . . . . . 28 MultiPowerSO-30 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 MultiPowerSO-30 suggested pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 MultiPowerSO-30 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 MultiPowerSO-30 tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 VNH2SP30-E 1 Block diagram and pin description Block diagram and pin description Figure 1. Block diagram VCC OVERTEMPERATURE A OV + UV OVERTEMPERATURE B CLAMP HSA HSA CLAMP HSB DRIVER HSA CURRENT LIMITATION A OUTA CURRENT LIMITATION B 1/K 1/K CLAMP LSA GNDA Table 2. OUTB CLAMP LSB DRIVER LSB DRIVER LSA LSA HSB DRIVER HSB LOGIC DIAGA/ENA INA CS PWM INB DIAGB/ENB LSB GNDB Block description Name Description Logic control Allows the turn-on and the turn-off of the high side and the low side switches according to the truth table Overvoltage + undervoltage Shuts down the device outside the range [5.5V..16V] for the battery voltage High side and low side clamp voltage Protects the high side and the low side switches from the high voltage on the battery line in all configurations for the motor High side and low side driver Drives the gate of the concerned switch to allow a proper RDS(on) for the leg of the bridge Linear current limiter Limits the motor current by reducing the high side switch gate-source voltage when short-circuit to ground occurs Overtemperature protection In case of short-circuit with the increase of the junction's temperature, shuts down the concerned high side to prevent its degradation and to protect the die Fault detection Signals an abnormal behavior of the switches in the half-bridge A or B by pulling low the concerned ENx/DIAGx pin 5/33 Block diagram and pin description Figure 2. VNH2SP30-E Configuration diagram (top view) OUTA Nc VCC Nc 1 OUTA Heat Slug3 INA ENA/DIAGA Nc PWM CS ENB/DIAGB INB Nc VCC Nc OUTB Table 3. GNDA OUTA Nc VCC VCC Heat Slug1 Nc OUTB OUTB Heat Slug2 15 16 Symbol GNDB GNDB GNDB Nc OUTB Function OUTA, Heat Slug3 Source of high side switch A / Drain of low side switch A 2, 4, 7, 12, 14, NC 17, 22, 24, 29 Not connected 3, 13, 23 VCC, Heat Slug1 Drain of high side switches and power supply voltage 6 ENA/DIAGA Status of high side and low side switches A; open drain output 5 INA Clockwise input 8 PWM PWM input 9 CS Output of current sense 11 INB Counter clockwise input 10 ENB/DIAGB Status of high side and low side switches B; open drain output 15, 16, 21 OUTB, Heat Slug2 Source of high side switch B / Drain of low side switch B 26, 27, 28 GNDA Source of low side switch A(1) 18, 19, 20 GNDB Source of low side switch B(1) 1. GNDA and GNDB must be externally connected together. 6/33 OUTA Nc GNDA GNDA Pin definitions and functions Pin No 1, 25, 30 30 VNH2SP30-E Block diagram and pin description Table 4. Pin functions description Name VCC Description Battery connection GNDA, GNDB Power grounds; must always be externally connected together OUTA, OUTB Power connections to the motor INA, INB Voltage controlled input pins with hysteresis, CMOS compatible. These two pins control the state of the bridge in normal operation according to the truth table (brake to VCC, brake to GND, clockwise and counterclockwise). PWM Voltage controlled input pin with hysteresis, CMOS compatible. Gates of low side FETs are modulated by the PWM signal during their ON phase allowing speed control of the motor. ENA/DIAGA, ENB/DIAGB Open drain bidirectional logic pins. These pins must be connected to an external pull up resistor. When externally pulled low, they disable half-bridge A or B. In case of fault detection (thermal shutdown of a high side FET or excessive ON state voltage drop across a low side FET), these pins are pulled low by the device (see truth table in fault condition). CS Analog current sense output. This output sources a current proportional to the motor current. The information can be read back as an analog voltage across an external resistor. 7/33 Electrical specifications 2 VNH2SP30-E Electrical specifications Figure 3. Current and voltage conventions IS VCC IINA VCC INA IINB INB IENA OUTB CS DIAGA/ENA IENB PWM VINB VOUTB GNDA GNDB GND VENB Vpw 8/33 VOUTA Ipw VENA 2.1 IOUTB ISENSE VSENSE DIAGB/ENB VINA IOUTA OUTA IGND Absolute maximum ratings Table 5. Absolute maximum ratings Symbol Parameter Value Unit V VCC Supply voltage +41 Imax Maximum output current (continuous) 30 IR Reverse output current (continuous) -30 IIN Input current (INA and INB pins) 10 IEN Enable input current (DIAGA/ENA and DIAGB/ENB pins) 10 Ipw PWM input current 10 VCS Current sense maximum voltage VESD Electrostatic discharge (R = 1.5k, C = 100pF) - CS pin - logic pins - output pins: OUTA, OUTB, VCC Tj Junction operating temperature Tc Case operating temperature -40 to 150 TSTG Storage temperature -55 to 150 A mA -3/+15 V 2 4 5 kV kV kV Internally limited C VNH2SP30-E 2.2 Electrical specifications Electrical characteristics VCC = 9V up to 16 V; -40C < TJ < 150C, unless otherwise specified. Table 6. Symbol VCC IS Power section Parameter Test conditions Operating supply voltage Supply current Min Typ Max Unit 5.5 16 V 30 60 A A mA On state: INA or INB = 5V, no PWM 10 mA Off state with all Fault Cleared & ENx=0 INA = INB = PWM = 0; Tj = 25C; VCC = 13V INA = INB = PWM = 0 Off state: INA = INB = PWM = 0 12 2 Static high side resistance IOUT = 15A; Tj = 25C 14 RONHS IOUT = 15A; Tj = -40 to 150C 28 IOUT = 15A; Tj = 25C 5 RONLS Static low side resistance IOUT = 15A; Tj = -40 to 150C 10 Vf High side freewheeling diode forward voltage High side off state output current (per channel) Tj = 25C; VOUTX = ENX = 0V; VCC = 13V 3 IL(off) Tj = 125C; VOUTX = ENX = 0V; VCC = 13V 5 IRM Dynamic crossconduction current IOUT = 15A (see Figure 7) Table 7. Symbol VIL m If = 15A 0.8 1.1 V A 0.7 A Logic inputs (INA, INB, ENA, ENB) Parameter Test conditions Min Typ Max Unit Input low level voltage 1.25 Normal operation (DIAGX/ENX pin acts as an input pin) VIH Input high level voltage VIHYST Input hysteresis voltage VICL Input clamp voltage IINL Input low current VIN = 1.25V IINH Input high current VIN = 3.25V 10 VDIAG Enable output low level voltage Fault operation (DIAGX/ENX pin acts as an output pin); IEN = 1mA 0.4 3.25 0.5 V IIN = 1mA 5.5 IIN = -1mA -1.0 -0.7 -0.3 6.3 7.5 1 A V 9/33 Electrical specifications Table 8. Symbol VNH2SP30-E PWM Parameter Vpwl PWM low level voltage Ipwl PWM pin current Vpwh PWM high level voltage Ipwh PWM pin current Vpwhhyst PWM hysteresis voltage Vpwcl PWM clamp voltage CINPWM PWM pin input capacitance Table 9. Symbol Test conditions Min Vpw = 1.25V Typ Max Unit 1.25 V 1 A 3.25 V Vpw = 3.25V 10 A V 0.5 Ipw = 1mA VCC + 0.3 VCC + 0.7 VCC + 1.0 Ipw = -1mA -6.0 -4.5 -3.0 VIN = 2.5V 25 pF Switching (VCC = 13V, RLOAD = 0.87 , unless otherwise specified) Parameter Test conditions Min Typ Unit 20 kHz f PWM frequency td(on) Turn-on delay time Input rise time < 1s (see Figure 6) 250 td(off) Turn-off delay time Input rise time < 1s (see Figure 6) 250 tr Rise time (see Figure 5) 1 1.6 tf Fall time (see Figure 5) 1.2 2.4 tDEL Delay time during change of operating mode (see Figure 4) 600 1800 trr High side free wheeling diode reverse recovery time (see Figure 7) toff(min)(1) PWM minimum off time 0 Max 300 110 s ns 9V < VCC < 16V; Tj = 25C; L = 250H; IOUT = 15A 6 s 1. To avoid false Short to Battery detection during PWM operation, the PWM signal must be low for a time longer than 6s. Table 10. Symbol Protection and diagnostic Parameter Test conditions Min Typ Undervoltage shut-down VUSD 10/33 Max Unit 5.5 Undervoltage reset 4.7 V VOV Overvoltage shut-down 16 19 22 ILIM High side current limitation 30 50 70 A VCLP Total clamp voltage (VCC to GND) IOUT = 15A 43 48 54 V TTSD Thermal shut-down temperature VIN = 3.25V 150 175 200 TTR Thermal reset temperature THYST Thermal hysteresis 135 7 C 15 VNH2SP30-E Electrical specifications Table 11. Current sense (9V < VCC < 16V) Symbol Parameter Test conditions Min Typ Max K1 IOUT/ISENSE IOUT = 30A; RSENSE = 1.5k; Tj = -40 to 150C 9665 11370 13075 K2 IOUT/ISENSE IOUT = 8A; RSENSE = 1.5k; Tj = -40 to 150C 9096 11370 13644 = 30A; RSENSE = 1.5k; I dK1 / K1(1) Analog sense current drift OUT Tj = -40 to 150C -8 +8 I > 8A; RSENSE = 1.5k; dK2 / K2(1) Analog sense current drift OUT Tj = -40 to 150C -10 +10 0 65 ISENSEO Analog sense leakage current IOUT = 0A; VSENSE = 0V; Tj = -40 to 150C Unit % A 1. Analog sense current drift is deviation of factor K for a given device over (-40C to 150C and 9V < VCC < 16V) with respect to its value measured at Tj = 25C, VCC = 13V. Figure 4. Definition of the delay times measurement VINA t VINB t PWM t ILOAD tDEL tDEL t 11/33 Electrical specifications Figure 5. VNH2SP30-E Definition of the low side switching times PWM t VOUTA, B 90% tf Figure 6. 80% 20% 10% tr t Definition of the high side switching times VINA tD(on) tD(off) t VOUTA 90% 10% t 12/33 VNH2SP30-E Figure 7. Electrical specifications Definition of dynamic cross conduction current during a PWM operation INA = 1, INB = 0 PWM t IMOTOR t VOUTB t ICC IRM t trr 13/33 Electrical specifications Table 12. INA INB VNH2SP30-E Truth table in normal operating conditions DIAGA/ENA DIAGB/ENB OUTA OUTB 1 H 1 CS High Imp. H 0 1 1 H 0 Brake to VCC Clockwise (CW) L 1 Operating mode ISENSE = IOUT/K Counterclockwise (CCW) L 0 Table 13. INA L High Imp. Brake to GND Truth table in fault conditions (detected on OUTA) INB DIAGA/ENA DIAGB/ENB OUTA OUTB 1 H 0 L 1 CS High Imp. 1 1 H 0 0 0 IOUTB/K L OPEN High Imp. X X 0 OPEN 1 H IOUTB/K L High Imp. 1 0 Fault Information Note: 14/33 Protection Action Notice that saturation detection on the low side power MOSFET is possible only if the impedance of the short-circuit from the output to the battery is less than 100m when the device is supplied with a battery voltage of 13.5V. VNH2SP30-E Electrical specifications Table 14. Electrical transient requirements ISO T/R - 7637/1 Test Level Test Level Test Level Test Level Test levels Test pulse I II III IV delays and impedance 1 -25V -50V -75V -100V 2ms, 10 2 +25V +50V +75V +100V 0.2ms, 10 3a -25V -50V -100V -150V 3b +25V +50V +75V +100V 4 -4V -5V -6V -7V 100ms, 0.01 5 +26.5V +46.5V +66.5V +86.5V 400ms, 2 0.1s, 50 ISO T/R - 7637/1 Test levels Test levels Test levels Test levels test pulse result I result II result III result IV C C C E E E 1 2 3a C 3b 4 5(1) 1. For load dump exceeding the above value a centralized suppressor must be adopted. Class Contents C All functions of the device are performed as designed after exposure to disturbance. E One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. 15/33 Electrical specifications VNH2SP30-E 2.3 Electrical characteristics curves Figure 8. On state supply current Figure 9. Is (mA) Off state supply current Is (A) 6 50 5.5 45 Vcc=13V INA or INB=5V 5 Vcc=13V 40 4.5 35 4 3.5 30 3 25 2.5 20 2 15 1.5 10 1 5 0.5 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (C) 50 75 100 125 150 175 Tc (C) Figure 10. High level input current Figure 11. Input clamp voltage Iinh (A) Vicl (V) 5 8 4.5 7.75 Vin=3.25V Iin =1mA 7.5 4 7.25 3.5 7 3 6.75 2.5 6.5 2 6.25 6 1.5 5.75 1 5.5 0.5 5.25 0 5 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (C) 50 75 100 125 150 175 150 175 Tc (C) Figure 12. Input high level voltage Figure 13. Input low level voltage Vih (V) Vil (V) 3 3 2.9 2.75 2.8 2.5 2.7 2.25 2.6 2.5 2 2.4 1.75 2.3 1.5 2.2 1.25 2.1 2 1 -50 -25 0 25 50 75 Tc (C) 16/33 100 125 150 175 -50 -25 0 25 50 75 Tc (C) 100 125 VNH2SP30-E Electrical specifications Figure 14. Input hysteresis voltage Figure 15. High level enable pin current Vihyst (V) Ienh (A) 2 8 1.75 7 Vcc=13V Ven=3.25V 1.5 6 1.25 5 1 4 0.75 3 0.5 2 0.25 1 0 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 Tc (C) Tc (C) Figure 16. Delay time during change of operation mode Figure 17. Enable clamp voltage tdel (s) Vencl (V) 1000 -0.2 900 -0.3 Ien=-1mA 800 -0.4 700 -0.5 600 500 -0.6 400 -0.7 300 -0.8 200 -0.9 100 0 -1 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (C) 50 75 100 125 150 175 Tc (C) Figure 18. High level enable voltage Figure 19. Low level enable voltage Venh (V) Venl (V) 3.6 3 3.4 2.8 Vcc=9V Vcc=9V 3.2 2.6 3 2.4 2.8 2.2 2.6 2 2.4 1.8 2.2 1.6 2 1.4 1.8 1.2 1.6 1 -50 -25 0 25 50 75 Tc (C) 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tc (C) 17/33 Electrical specifications VNH2SP30-E Figure 20. PWM high level voltage Figure 21. PWM low level voltage Vpwh (V) Vpwl (V) 5 2.6 4.5 2.4 Vcc=9V Vcc=9V 4 2.2 3.5 2 3 2.5 1.8 2 1.6 1.5 1.4 1 1.2 0.5 0 1 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (C) 50 75 100 125 150 175 Tc (C) Figure 22. PWM high level current Figure 23. Overvoltage shutdown Ipwh (A) Vov (V) 8 30 7 27.5 Vcc=9V Vpw=3.25V 6 25 5 22.5 4 20 3 17.5 2 15 1 12.5 0 10 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (C) 50 75 100 125 150 175 100 125 150 175 Tc (C) Figure 24. Undervoltage shutdown Figure 25. Current limitation Vusd(V) Ilim (A) 8 80 75 7 70 6 65 5 60 4 55 50 3 45 2 40 1 35 0 30 -50 -25 0 25 50 75 Tc (C) 18/33 100 125 150 175 -50 -25 0 25 50 75 Tc (C) VNH2SP30-E Electrical specifications Figure 26. On state high side resistance vs Tcase Figure 27. On state low side resistance vs Tcase Ronhs (mOhm) Ronls (mOhm) 40 9 8 35 Vcc=9V; 16V Iout=15A 30 Vcc=9V; 16V Iout=15A 7 6 25 5 20 4 15 3 10 2 5 1 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (C) 50 75 100 125 150 175 125 150 175 Tc (C) Figure 28. Turn-On delay time Figure 29. Turn-Off delay time td(on) (s) td(off) (s) 260 200 240 190 220 180 200 170 180 160 160 150 140 140 120 130 100 120 80 110 60 100 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (C) 50 75 100 Tc (C) Figure 30. Output voltage rise time Figure 31. Output voltage fall time tr (s) tf (s) 2 8 1.8 7 1.6 6 1.4 5 1.2 4 1 3 0.8 2 0.6 1 0.4 0.2 0 -50 -25 0 25 50 75 Tc (C) 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tc (C) 19/33 Application information 3 VNH2SP30-E Application information In normal operating conditions the DIAGX/ENX pin is considered as an input pin by the device. This pin must be externally pulled high. PWM pin usage: in all cases, a "0" on the PWM pin will turn off both LSA and LSB switches. When PWM rises back to "1", LSA or LSB turn on again depending on the input pin state. Figure 32. Typical application circuit for DC to 20 kHz PWM operation short circuit protection VCC Reg 5V +5V + 5V VCC 3.3K 3.3K DIAGB/ENB 1K 1K DIAGA/ENA 1K HSA HSB PWM C OUTA 1K OUTB INA INB LSA 10K 33nF 1K LSB CS C M 1.5K GNDB GNDA S 100K G b) N MOSFET D Note: The value of the blocking capacitor (C) depends on the application conditions and defines voltage and current ripple onto supply line at PWM operation. Stored energy of the motor inductance may fly back into the blocking capacitor, if the bridge driver goes into tri-state. This causes a hazardous overvoltage if the capacitor is not big enough. As basic orientation, 500F per 10A load current is recommended. In case of a fault condition the DIAGX/ENX pin is considered as an output pin by the device.The fault conditions are: overtemperature on one or both high sides short to battery condition on the output (saturation detection on the low side power MOSFET) Possible origins of fault conditions may be: 20/33 OUTA is shorted to ground overtemperature detection on high side A. OUTA is shorted to VCC low side power MOSFET saturation detection. VNH2SP30-E Application information When a fault condition is detected, the user can know which power element is in fault by monitoring the INA, INB, DIAGA/ENA and DIAGB/ENB pins. In any case, when a fault is detected, the faulty leg of the bridge is latched off. To turn on the respective output (OUTX) again, the input signal must rise from low to high level. Figure 33. Behavior in fault condition (How a fault can be cleared) INA INB DIAGA ENA DIAGB ENB Device Unlatched Device Latched Device Latched IoutA AE outB FAULTA (Internal Signal) FAULTB tDEL (Internal Signal) Normal Operation Note: OUT B shorted to VCC Fault Cleared tDEL Stby (*) Normal Operation OUTB shorted Fault Cleared to GND Normal Operation In case of the fault condition is not removed, the procedure for unlatching and sending the device in Stby mode is: - Clear the fault in the device (toggle : INA if ENA=0 or INB if ENB=0) - Pull low all inputs, PWM and Diag/EN pins within tDEL. If the Diag/En pins are already low, PWM=0, the fault can be cleared simply toggling the input. The device will enter in stby mode as soon as the fault is cleared. 3.1 Reverse battery protection Three possible solutions can be considered: 1. a Schottky diode D connected to VCC pin 2. an N-channel MOSFET connected to the GND pin (see Figure 32: Typical application circuit for DC to 20 kHz PWM operation short circuit protection on page 20) 3. a P-channel MOSFET connected to the VCC pin The device sustains no more than -30A in reverse battery conditions because of the two body diodes of the power MOSFETs. Additionally, in reverse battery condition the I/Os of VNH2SP30-E are pulled down to the VCC line (approximately -1.5V). A series resistor must 21/33 Application information VNH2SP30-E be inserted to limit the current sunk from the microcontroller I/Os. If IRmax is the maximum target reverse current through C I/Os, the series resistor is: Figure 34. Half-bridge configuration VCC INA INB DIAGA/ENA DIAGB/ENB PWM INA INB DIAGA/ENA DIAGB/ENB PWM OUTA GNDA Note: M OUTB GNDA GNDB OUTB OUTA GNDB The VNH2SP30-E can be used as a high power half-bridge driver achieving an On resistance per leg of 9.5m. Figure 35. Multi-motors configuration VCC INA INB DIAGA/ENA DIAGB/ENB PWM INA INB DIAGA/ENA DIAGB/ENB PWM OUTA OUTB GNDA GNDB M1 Note: 22/33 M2 OUTB OUTA GNDA GNDB M3 The VNH2SP30-E can easily be designed in multi-motors driving applications such as seat positioning systems where only one motor must be driven at a time. DIAGX/ENX pins allow to put unused half-bridges in high impedance. VNH2SP30-E Application information Figure 36. Waveforms in full bridge operation NORMAL OPERATION (DIAGA/ENA = 1, DIAGB/ENB = 1) LOAD CONNECTED BETWEEN OUTA, OUTB DIAGA/ENA DIAGB/ENB INA INB PWM OUTA OUTB IOUTA->OUTB CS (*) tDEL tDEL (*) CS BEHAVIOR DURING PWM MODE WILL DEPEND ON PWM FREQUENCY AND DUTY CYCLE. NORMAL OPERATION (DIAGA/ENA = 1, DIAGB/ENB = 0 and DIAGA/ENA = 0, DIAGB/ENB = 1) LOAD CONNECTED BETWEEN OUTA, OUTB DIAGA/ENA DIAGB/ENB INA INB PWM OUTA OUTB IOUTA->OUTB CS CURRENT LIMITATION/THERMAL SHUTDOWN or OUTA SHORTED TO GROUND INA INB ILIM IOUTA->OUTB TTSD TTR Tj > TTR Tj DIAGA/ENA DIAGB/ENB CS normal operation OUTA shorted to ground normal operation 23/33 Application information VNH2SP30-E Figure 37. Waveforms in full bridge operation (continued) OUTA shorted to VCC and undervoltage shutdown INA INB undefined OUTA OUTB undefined IOUTA->OUTB DIAGB/ENB DIAGA/ENA CS V < nominal normal operation 24/33 OUTA shorted to VCC normal operation undervoltage shutdown VNH2SP30-E Package and PCB thermal data 4 Package and PCB thermal data 4.1 PowerSSO-30 thermal data Figure 38. MultiPowerSO-30TM PC board Layout condition of Rth and Zth measurements (PCB FR4 area = 58mm x 58mm, PCB thickness = 2mm. Cu thickness = 35m, Copper areas: from minimum pad layout to 16cm2). Figure 39. Chipset configuration HIGH SIDE CHIP HSAB LOW SIDE CHIP A LOW SIDE CHIP B LSA LSB Figure 40. Auto and mutual Rthj-amb vs PCB copper area in open box free air condition 45 R thH S R thLS R thH SLS R thLSLS 40 35 30 25 20 15 C/W Note: 10 5 0 0 5 10 15 20 c m 2 o f C u a re a (re fe r to P C B la yo u t) 25/33 Package and PCB thermal data 4.1.1 Thermal calculation in clockwise and anti-clockwise operation in steady-state mode Table 15. Thermal calculation in clockwise and anti-clockwise operation in steadystate mode HSA HSB LSA LSB 4.1.2 VNH2SP30-E TjHSAB TjLSA TjLSB ON OFF OFF ON PdHSA x RthHS + PdLSB PdHSA x RthHSLS + x RthHSLS + Tamb PdLSB x RthLSLS + Tamb PdHSA x RthHSLS + PdLSB x RthLS + Tamb OFF ON PdHSB x RthHS + PdLSA PdHSB x RthHSLS + x RthHSLS + Tamb PdLSA x RthLS + Tamb PdHSB x RthHSLS + PdLSA x RthLSLS + Tamb ON OFF Thermal resistances definition (values according to the PCB heatsink area) RthHS = RthHSA = RthHSB = High Side Chip Thermal Resistance Junction to Ambient (HSA or HSB in ON state) RthLS = RthLSA = RthLSB = Low Side Chip Thermal Resistance Junction to Ambient RthHSLS = RthHSALSB = RthHSBLSA = Mutual Thermal Resistance Junction to Ambient between High Side and Low Side Chips RthLSLS = RthLSALSB = Mutual Thermal Resistance Junction to Ambient between Low Side Chips 4.1.3 Thermal calculation in transient mode(a) TjHSAB = ZthHS x PdHSAB + ZthHSLS x (PdLSA + PdLSB) + Tamb TjLSA = ZthHSLS x PdHSAB + ZthLS x PdLSA + ZthLSLS x PdLSB + Tamb TjLSB = ZthHSLS x PdHSAB + ZthLSLS x PdLSA + ZthLS x PdLSB + Tamb 4.1.4 Single pulse thermal impedance definition (values according to the PCB heatsink area) ZthHS = High Side Chip Thermal Impedance Junction to Ambient ZthLS = ZthLSA = ZthLSB = Low Side Chip Thermal Impedance Junction to Ambient ZthHSLS = ZthHSABLSA = ZthHSABLSB = Mutual Thermal Impedance Junction to Ambient between High Side and Low Side Chips ZthLSLS = ZthLSALSB = Mutual Thermal Impedance Junction to Ambient between Low Side Chips a. Calculation is valid in any dynamic operating condition. Pd values set by user. 26/33 VNH2SP30-E Package and PCB thermal data Equation 1: pulse calculation formula Z TH = R TH + Z THtp ( 1 - ) where = t p T Figure 41. MultiPowerSO-30 HSD thermal impedance junction ambient single pulse 100 Footprint 4 cm2 8 cm2 16 cm2 ZthHS Footprint 4 cm2 8 cm2 16 cm2 10 C/W ZthHSLS 1 0 .1 0 .0 0 1 0 .0 1 0 .1 t i m e ( se c ) 1 10 100 1000 Figure 42. MultiPowerSO-30 LSD thermal impedance junction ambient single pulse 100 Footprint 4 cm2 8 cm2 16 cm2 ZthLS Footprint 4 cm2 8 cm2 16 cm2 10 C/W ZthLSLS 1 0 .1 0 .0 0 1 0 .0 1 0 .1 t i m e ( se c ) 1 10 100 1000 27/33 Package and PCB thermal data VNH2SP30-E Figure 43. Thermal fitting model of an H-bridge in MultiPowerSO-30 Table 16. Thermal parameters(1) Area/island (cm2) Footprint R1 = R7 (C/W) 0.05 R2 = R8 (C/W) 0.3 R3 (C/W) 0.5 R4 (C/W) 1.3 R5 (C/W) 14 R6 (C/W) 44.7 R9 = R15 (C/W) 0.2 R10 = R16 (C/W) 0.4 R11 = R17 (C/W) 0.8 R12 = R18 (C/W) 1.5 R13 = R19 (C/W) 20 R14 = R20 (C/W) 46.9 R21 = R22 = R23 (C/W) 115 C1 = C7 (W.s/C) 0.005 C2 = C8 (W.s/C) 0.008 C3 = C11 = C17 (W.s/C) 0.01 C4 = C13 = C19 (W.s/C) 0.3 C5 (W.s/C) 0.6 C6 (W.s/C) 5 C9 = C15 (W.s/C) 0.003 C10 = C16 (W.s/C) 0.006 C12 = C18 (W.s/C) 0.075 C14 = C20 (W.s/C) 2.5 4 8 16 39.1 31.6 23.7 36.1 30.4 20.8 7 9 11 3.5 4.5 5.5 1. The blank space means that the value is the same as the previous one. 28/33 VNH2SP30-E Package and packing information 5 Package and packing information 5.1 ECOPACK(R) packages In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. ECOPACK(R) packages are lead-free. The category of Second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. 5.2 MultiPowerSO-30 package mechanical data Figure 44. MultiPowerSO-30 package outline 29/33 Package and packing information Table 17. VNH2SP30-E MultiPowerSO-30 mechanical data Millimeters Symbol Min Typ A 2.35 A2 1.85 2.25 A3 0 0.1 B 0.42 0.58 C 0.23 0.32 D 17.1 E 18.85 E1 15.9 e 17.2 17.3 19.15 16 16.1 1 F1 5.55 6.05 F2 4.6 5.1 F3 9.6 10.1 L 0.8 1.15 N S 10deg 0deg Figure 45. MultiPowerSO-30 suggested pad layout 30/33 Max 7deg VNH2SP30-E Package and packing information 5.3 Packing information Note: The devices can be packed in tube or tape and reel shipments (see the Device summary on page 1 for packaging quantities). Figure 46. MultiPowerSO-30 tube shipment (no suffix) Dimension A C B mm Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.13) 29 435 532 3.82 23.6 0.8 Figure 47. MultiPowerSO-30 tape and reel shipment (suffix "TR") Reel dimensions SO-28 tube shipment (no suffix) Dimension mm Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) D (min) G (+ 2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 32 100 38.4 Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Description Dimension mm Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.1) K (max) 32 4 24 1.5 2 14.2 2.2 End Start Top cover tape No components Components No components 500 mm min 500 mm min Empty components pockets User direction of feed 31/33 Revision history 6 VNH2SP30-E Revision history Table 18. 32/33 Document revision history Date Revision Description of changes Sep-2004 1 First issue Dec- 2004 2 Inserted toff(min) test condition modification and note Modified IRM figure number Feb-2005 3 Minor changes Apr-2005 4 Public release 01-Sep-2006 5 Document converted into new ST corporate template. Added table of contents, list of tables and list of figures Removed figure number from package outline on page 1 Changed Features on page 1 to add ECOPACK(R) package Added Section 1: Block diagram and pin description on page 5 Added Section 2.2: Electrical characteristics on page 9 Added "low" and "high" to parameters for IINL and IINH in Table 7 on page 9 Inserted note in Figure 32 on page 20 Added vertical limitation line to left side arrow of tD(off) to Figure 7 on page 13 Added Section 4.1: PowerSSO-30 thermal data on page 25 Added Section 5: Package and packing information on page 29 Added Section 5.3: Packing information on page 31 Updated disclaimer (last page) to include a mention about the use of ST products in automotive applications 15-May-2007 6 Document reformatted and converted into new ST template. 06-Feb-2008 7 Corrected Heat Slug numbers in Table 3: Pin definitions and functions. 02-Oct-2008 8 Added new infomation in Table 6: Power section Added Figure 33: Behavior in fault condition (How a fault can be cleared) VNH2SP30-E Please Read Carefully: Information in this document is provided solely in connection with ST products. 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