October 2008 Rev 8 1/33
1
VNH2SP30-E
Automotive fully integrated H-bridge motor driver
Features
■5V logic level compatible inputs
■Undervoltage and overvoltage shut-down
■Overvoltage clamp
■Thermal shut down
■Cross-conduction protection
■Linear current limiter
■Very low stand-by power consumption
■PWM operation up to 20 kHz
■Protection against loss of ground and loss of
VCC
■Current sense output proportional to motor
current
■Package: ECOPACK®
Description
The VNH2SP30-E is a full bridge motor driver
intended for a wide range of automotive
applications. The device incorporates a dual
monolithic high side driver and two low side
switches. The high side driver switch is designed
using STMicroelectronic’s well known and proven
proprietary VIPower™ M0 technology which
permits efficient integration on the same die of a
true Power MOSFET with an intelligent
signal/protection circuitry.
The low side switches are vertical MOSFETs
manufactured using STMicroelectronic’s
proprietary EHD (‘STripFET™’) process. The
three die are assembled in the MultiPowerSO-30
package on electrically isolated leadframes. This
package, specifically designed for the harsh
automotive environment offers improved thermal
performance thanks to exposed die pads.
Moreover, its fully symmetrical mechanical design
allows superior manufacturability at board level.
The input signals INA and INB can directly
interface to the microcontroller to select the motor
direction and the brake condition. The
DIAGA/ENA or DIAGB/ENB, when connected to an
external pull-up resistor, enable one leg of the
bridge. They also provide a feedback digital
diagnostic signal. The normal condition operation
is explained in Table 12: Truth table in normal
operating conditions on page 14. The motor
current can be monitored with the CS pin by
delivering a current proportional to its value. The
speed of the motor can be controlled in all
possible conditions by the PWM up to 20 kHz. In
all cases, a low level state on the PWM pin will
turn off both the LSA and LSB switches. When
PWM rises to a high level, LSA or LSB turn on
again depending on the input pin state.
Type RDS(on) Iout Vccmax
VNH2SP30-E 19mΩ max
(per leg) 30A 41V
MultiPowerSO-30™
Table 1. Device summary
Package
Order codes
Tube Tape and Reel
MultiPowerSO-30 VNH2SP30-E VNH2SP30TR-E
www.st.com
Contents VNH2SP30-E
2/33
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1 Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1 PowerSSO-30 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1.1 Thermal calculation in clockwise and anti-clockwise operation in steady-
state mode 26
4.1.2 Thermal resistances definition (values according to the PCB heatsink
area) 26
4.1.3 Thermal calculation in transient mode . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1.4 Single pulse thermal impedance definition
(values according to the PCB heatsink area) . . . . . . . . . . . . . . . . . . . . . 26
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2 MultiPowerSO-30 package mechanical data . . . . . . . . . . . . . . . . . . . . . . 29
5.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
VNH2SP30-E List of tables
3/33
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Block description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Pin functions description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Logic inputs (INA, INB, ENA, ENB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 9. Switching (VCC =13V, R
LOAD = 0.87W , unless otherwise specified) . . . . . . . . . . . . . . . . 10
Table 10. Protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 11. Current sense (9V < VCC < 16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 12. Truth table in normal operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 13. Truth table in fault conditions (detected on OUTA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 14. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 15. Thermal calculation in clockwise and anti-clockwise operation in steady-state mode . . . . 26
Table 16. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 17. MultiPowerSO-30 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
List of figures VNH2SP30-E
4/33
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Definition of the delay times measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Definition of the low side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Definition of the high side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Definition of dynamic cross conduction current during a PWM operation. . . . . . . . . . . . . . 13
Figure 8. On state supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. Off state supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12. Input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13. Input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 14. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 15. High level enable pin current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 16. Delay time during change of operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 17. Enable clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 18. High level enable voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 19. Low level enable voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 20. PWM high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 21. PWM low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 22. PWM high level current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 23. Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 24. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 25. Current limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 26. On state high side resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 27. On state low side resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 28. Turn-On delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 29. Turn-Off delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 30. Output voltage rise time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 31. Output voltage fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 32. Typical application circuit for DC to 20 kHz PWM operation short circuit protection . . . . . 20
Figure 33. Behavior in fault condition (How a fault can be cleared). . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 34. Half-bridge configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 35. Multi-motors configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 36. Waveforms in full bridge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 37. Waveforms in full bridge operation (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 38. MultiPowerSO-30™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 39. Chipset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 40. Auto and mutual Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . 25
Figure 41. MultiPowerSO-30 HSD thermal impedance junction ambient single pulse . . . . . . . . . . . . 27
Figure 42. MultiPowerSO-30 LSD thermal impedance junction ambient single pulse. . . . . . . . . . . . . 27
Figure 43. Thermal fitting model of an H-bridge in MultiPowerSO-30 . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 44. MultiPowerSO-30 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 45. MultiPowerSO-30 suggested pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 46. MultiPowerSO-30 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 47. MultiPowerSO-30 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
VNH2SP30-E Block diagram and pin description
5/33
1 Block diagram and pin description
Figure 1. Block diagram
Table 2. Block description
Name Description
Logic control Allows the turn-on and the turn-off of the high side and the low side switches
according to the truth table
Overvoltage +
undervoltage Shuts down the device outside the range [5.5V..16V] for the battery voltage
High side and low
side clamp voltage
Protects the high side and the low side switches from the high voltage on the
battery line in all configurations for the motor
High side and low
side driver
Drives the gate of the concerned switch to allow a proper RDS(on) for the leg of
the bridge
Linear current limiter Limits the motor current by reducing the high side switch gate-source voltage
when short-circuit to ground occurs
Overtemperature
protection
In case of short-circuit with the increase of the junction’s temperature, shuts
down the concerned high side to prevent its degradation and to protect the die
Fault detection Signals an abnormal behavior of the switches in the half-bridge A or B by
pulling low the concerned ENx/DIAGx pin
LOGIC
V
CC
OUT
A
DIAG
A
/EN
A
IN
B
IN
A
GND
A
CS DIAG
B
/EN
B
LS
A
CLAMP HS
A
LS
A
HS
A
OVERTEMPERATURE A OVERTEMPERATURE B
O
V
+ U
V
CURRENT
LIMITATION A
OUT
B
GND
B
LS
B
HS
B
CURRENT
LIMITATION B
DRIVER
HS
A
DRIVER
LS
B
DRIVER
HS
B
DRIVER
CLAMP HS
B
CLAMP LS
B
CLAMP LS
A
PWM
1/K
1/K
Block diagram and pin description VNH2SP30-E
6/33
Figure 2. Configuration diagram (top view)
Table 3. Pin definitions and functions
Pin No Symbol Function
1, 25, 30 OUTA, Heat Slug3 Source of high side switch A / Drain of low side switch A
2, 4, 7, 12, 14,
17, 22, 24, 29 NC Not connected
3, 13, 23 VCC, Heat Slug1 Drain of high side switches and power supply voltage
6EN
A/DIAGAStatus of high side and low side switches A; open drain output
5IN
AClockwise input
8 PWM PWM input
9 CS Output of current sense
11 INBCounter clockwise input
10 ENB/DIAGBStatus of high side and low side switches B; open drain output
15, 16, 21 OUTB, Heat Slug2 Source of high side switch B / Drain of low side switch B
26, 27, 28 GNDASource of low side switch A(1)
1. GNDA and GNDB must be externally connected together.
18, 19, 20 GNDBSource of low side switch B(1)
OUT
A
OUT
A
OUT
A
OUT
B
OUT
B
Nc
V
CC
Nc
IN
A
EN
A
/DIAG
A
Nc
PWM
CS
EN
B
/DIAG
B
IN
B
Nc
Nc
V
CC
OUT
B
Nc
Nc
GND
A
GND
A
GND
A
Nc
V
CC
Nc
GND
B
GND
B
GND
B
1
15 16
30
V
CC
Heat Slug1
OUT
B
Heat Slug2
OUT
A
Heat Slug3
VNH2SP30-E Block diagram and pin description
7/33
Table 4. Pin functions description
Name Description
VCC Battery connection
GNDA, GNDBPower grounds; must always be externally connected together
OUTA, OUTBPower connections to the motor
INA, INB
Voltage controlled input pins with hysteresis, CMOS compatible. These two pins
control the state of the bridge in normal operation according to the truth table (brake
to VCC, brake to GND, clockwise and counterclockwise).
PWM
Voltage controlled input pin with hysteresis, CMOS compatible. Gates of low side
FETs are modulated by the PWM signal during their ON phase allowing speed
control of the motor.
ENA/DIAGA,
ENB/DIAGB
Open drain bidirectional logic pins. These pins must be connected to an external pull
up resistor. When externally pulled low, they disable half-bridge A or B. In case of
fault detection (thermal shutdown of a high side FET or excessive ON state voltage
drop across a low side FET), these pins are pulled low by the device (see truth table
in fault condition).
CS
Analog current sense output. This output sources a current proportional to the motor
current. The information can be read back as an analog voltage across an external
resistor.
Electrical specifications VNH2SP30-E
8/33
2 Electrical specifications
Figure 3. Current and voltage conventions
2.1 Absolute maximum ratings
V
CC
IN
A
GND
B
I
S
I
OUTA
I
INA
V
INA
V
CC
V
OUTA
I
SENSE
V
OUTB
DIAG
A
/EN
A
I
ENA
I
GND
I
OUTB
IN
B
I
INB
DIAG
B
/EN
B
I
ENB
V
ENB
V
ENA
V
INB
V
SENSE
OUT
A
OUT
B
PWM
CS
I
pw
V
pw
GND
A
GND
Table 5. Absolute maximum ratings
Symbol Parameter Value Unit
VCC Supply voltage +41 V
Imax Maximum output current (continuous) 30 A
IR Reverse output current (continuous) -30
IIN Input current (INA and INB pins) ±10
mAIEN Enable input current (DIAGA/ENA and DIAGB/ENB pins) ±10
Ipw PWM input current ±10
VCS Current sense maximum voltage -3/+15 V
VESD
Electrostatic discharge (R = 1.5kΩ, C = 100pF)
–CS pin
– logic pins
– output pins: OUTA, OUTB, VCC
2
4
5
kV
kV
kV
TjJunction operating temperature Internally limited
°CTcCase operating temperature -40 to 150
TSTG Storage temperature -55 to 150
VNH2SP30-E Electrical specifications
9/33
2.2 Electrical characteristics
VCC = 9V up to 16 V; -40°C < TJ < 150°C, unless otherwise specified.
Table 6. Power section
Symbol Parameter Test conditions Min Typ Max Unit
VCC
Operating supply
voltage 5.5 16 V
ISSupply current
Off state with all Fault Cleared & ENx=0
INA=IN
B=PWM=0; T
j= 25°C; VCC =13V
INA=IN
B=PWM=0
Off state: INA=IN
B=PWM=0
12
2
30
60
µA
µA
mA
On state:
INA or INB=5V, no PWM 10 mA
RONHS
Static high side
resistance
IOUT = 15A; Tj= 25°C 14
mΩ
IOUT = 15A; Tj= -40 to 150°C 28
RONLS
Static low side
resistance
IOUT = 15A; Tj= 25°C 5
IOUT = 15A; Tj= -40 to 150°C 10
Vf
High side free-
wheeling diode
forward voltage
If= 15A 0.8 1.1 V
IL(off)
High side off state
output current
(per channel)
Tj=25°C; V
OUTX =EN
X=0V; V
CC =13V 3
µA
Tj= 125°C; VOUTX =EN
X=0V; V
CC =13V 5
IRM
Dynamic cross-
conduction current IOUT = 15A (see Figure 7)0.7A
Table 7. Logic inputs (INA, INB, ENA, ENB)
Symbol Parameter Test conditions Min Typ Max Unit
VIL Input low level voltage
Normal operation (DIAGX/ENX pin acts
as an input pin)
1.25
V
VIH Input high level voltage 3.25
VIHYST Input hysteresis voltage 0.5
VICL Input clamp voltage IIN =1mA 5.5 6.3 7.5
IIN = -1mA -1.0 -0.7 -0.3
IINL Input low current VIN =1.25V 1 µA
IINH Input high current VIN =3.25V 10
VDIAG
Enable output low level
voltage
Fault operation (DIAGX/ENX pin acts as
an output pin); IEN =1mA 0.4 V
Electrical specifications VNH2SP30-E
10/33
Table 8. PWM
Symbol Parameter Test conditions Min Typ Max Unit
Vpwl PWM low level voltage 1.25 V
Ipwl PWM pin current Vpw = 1.25V 1 µA
Vpwh PWM high level voltage 3.25 V
Ipwh PWM pin current Vpw = 3.25V 10 µA
Vpwhhyst PWM hysteresis voltage 0.5
V
Vpwcl PWM clamp voltage Ipw = 1mA VCC +0.3 V
CC +0.7 V
CC +1.0
Ipw = -1mA -6.0 -4.5 -3.0
CINPWM
PWM pin input
capacitance VIN =2.5V 25 pF
Table 9. Switching (VCC =13V, R
LOAD =0.87Ω , unless otherwise specified)
Symbol Parameter Test conditions Min Typ Max Unit
f PWM frequency 0 20 kHz
td(on) Turn-on delay time Input rise time < 1µs
(see Figure 6)250
µs
td(off) Turn-off delay time Input rise time < 1µs
(see Figure 6)250
trRise time (see Figure 5)11.6
tfFall time (see Figure 5)1.22.4
tDEL
Delay time during change
of operating mode (see Figure 4) 300 600 1800
trr
High side free wheeling
diode reverse recovery
time
(see Figure 7)110ns
toff(min)(1)
1. To avoid false Short to Battery detection during PWM operation, the PWM signal must be low for a time
longer than 6µs.
PWM minimum off time 9V < VCC <16V; T
j= 25°C;
L = 250µH; IOUT = 15A 6µs
Table 10. Protection and diagnostic
Symbol Parameter Test conditions Min Typ Max Unit
VUSD
Undervoltage shut-down 5.5
VUndervoltage reset 4.7
VOV Overvoltage shut-down 16 19 22
ILIM High side current limitation 30 50 70 A
VCLP Total clamp voltage (VCC to GND) IOUT = 15A 43 48 54 V
TTSD Thermal shut-down temperature VIN = 3.25V 150 175 200
°CTTR Thermal reset temperature 135
THYST Thermal hysteresis 7 15
VNH2SP30-E Electrical specifications
11/33
Figure 4. Definition of the delay times measurement
Table 11. Current sense (9V < VCC <16V)
Symbol Parameter Test conditions Min Typ Max Unit
K1IOUT/ISENSE
IOUT = 30A; RSENSE =1.5kΩ;
Tj= -40 to 150°C 9665 11370 13075
K2IOUT/ISENSE
IOUT =8A; R
SENSE =1.5kΩ;
Tj= -40 to 150°C 9096 11370 13644
dK1/K
1(1)
1. Analog sense current drift is deviation of factor K for a given device over (-40°C to 150°C and
9V < VCC < 16V) with respect to its value measured at Tj= 25°C, VCC =13V.
Analog sense current drift IOUT = 30A; RSENSE =1.5kΩ;
Tj= -40 to 150°C -8 +8
%
dK2/K
2(1) Analog sense current drift IOUT >8A; R
SENSE =1.5kΩ;
Tj= -40 to 150°C -10 +10
ISENSEO
Analog sense leakage
current
IOUT =0A; V
SENSE =0V;
Tj= -40 to 150°C 065µA
t
t
V
INB
V
INA
t
PWM
t
I
LOAD
t
DEL
t
DEL
Electrical specifications VNH2SP30-E
12/33
Figure 5. Definition of the low side switching times
Figure 6. Definition of the high side switching times
t
f
PWM
t
t
V
OUTA, B
20%
90% 80%
10%
t
r
t
t
V
OUTA
V
INA
90%
10%
t
D(on)
t
D(off)
VNH2SP30-E Electrical specifications
13/33
Figure 7. Definition of dynamic cross conduction current during a PWM operation
t
t
I
MOTOR
PWM
t
V
OUTB
t
I
CC
t
rr
I
RM
INA=1, IN
B=0
Electrical specifications VNH2SP30-E
14/33
Note: Notice that saturation detection on the low side power MOSFET is possible only if the
impedance of the short-circuit from the output to the battery is less than 100mΩ when the
device is supplied with a battery voltage of 13.5V.
Table 12. Truth table in normal operating conditions
INAINBDIAGA/ENADIAGB/ENBOUTAOUTBCS Operating mode
11
11
HH High Imp. Brake to VCC
0L
ISENSE =I
OUT/K Clockwise (CW)
01LH Counterclockwise (CCW)
0 L High Imp. Brake to GND
Table 13. Truth table in fault conditions (detected on OUTA)
INAINBDIAGA/ENADIAGB/ENBOUTAOUTBCS
11
0
1
OPEN
HHigh Imp.
0L
01HI
OUTB/K
0L
High Imp.
X
X 0 OPEN
11HI
OUTB/K
0 L High Imp.
Fault Information Protection Action
VNH2SP30-E Electrical specifications
15/33
Table 14. Electrical transient requirements
ISO T/R - 7637/1
Test pulse
Test Level
I
Test Level
II
Test Level
III
Test Level
IV
Test levels
delays and impedance
1 -25V -50V -75V -100V 2ms, 10Ω
2 +25V +50V +75V +100V 0.2ms, 10Ω
3a -25V -50V -100V -150V 0.1µs, 50Ω
3b +25V +50V +75V +100V
4 -4V -5V -6V -7V 100ms, 0.01Ω
5 +26.5V +46.5V +66.5V +86.5V 400ms, 2Ω
ISO T/R - 7637/1
test pulse
Test levels
result I
Test levels
result II
Test levels
result III
Test levels
result IV
1
CCCC
2
3a
3b
4
5(1)
1. For load dump exceeding the above value a centralized suppressor must be adopted.
EEE
Class Contents
CAll functions of the device are performed as designed after exposure to
disturbance.
E
One or more functions of the device are not performed as designed after
exposure to disturbance and cannot be returned to proper operation without
replacing the device.
Electrical specifications VNH2SP30-E
16/33
2.3 Electrical characteristics curves
Figure 8. On state supply current Figure 9. Off state supply current
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Is (mA)
Vcc=13V
INA or INB=5V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
5
10
15
20
25
30
35
40
45
50
Is (µA)
Vcc=13V
Figure 10. High level input current Figure 11. Input clamp voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Iinh (µA)
Vin=3.25V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
5
5.25
5.5
5.75
6
6.25
6.5
6.75
7
7.25
7.5
7.75
8
Vicl (V)
Iin =1mA
Figure 12. Input high level voltage Figure 13. Input low level voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
Vih (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
1
1.25
1.5
1.75
2
2.25
2.5
2.75
3
Vil (V)
VNH2SP30-E Electrical specifications
17/33
Figure 14. Input hysteresis voltage Figure 15. High level enable pin current
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
Vihyst (V)
Vcc=13V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
1
2
3
4
5
6
7
8
Ienh (µA)
Ven=3.25V
Figure 16. Delay time during change of
operation mode
Figure 17. Enable clamp voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
100
200
300
400
500
600
700
800
900
1000
tdel (µs)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
Vencl (V)
Ien=-1mA
Figure 18. High level enable voltage Figure 19. Low level enable voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Venh (V)
Vcc=9V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
Venl (V)
Vcc=9V
Electrical specifications VNH2SP30-E
18/33
Figure 20. PWM high level voltage Figure 21. PWM low level voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Vpwh (V)
Vcc=9V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
Vpwl (V)
Vcc=9V
Figure 22. PWM high level current Figure 23. Overvoltage shutdown
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
1
2
3
4
5
6
7
8
Ipwh (µA)
Vcc=9V
Vpw=3.25V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
10
12.5
15
17.5
20
22.5
25
27.5
30
Vov (V)
Figure 24. Undervoltage shutdown Figure 25. Current limitation
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
1
2
3
4
5
6
7
8
Vusd(V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
30
35
40
45
50
55
60
65
70
75
80
Ilim (A)
VNH2SP30-E Electrical specifications
19/33
Figure 26. On state high side resistance vs
Tcase
Figure 27. On state low side resistance vs
Tcase
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
5
10
15
20
25
30
35
40
Ronhs (mOhm)
Vcc=9V; 16V
Iout=15A
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
1
2
3
4
5
6
7
8
9
Ronls (mOhm)
Vcc=9V; 16V
Iout=15A
Figure 28. Turn-On delay time Figure 29. Turn-Off delay time
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
60
80
100
120
140
160
180
200
220
240
260
td(on) (µs)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
100
110
120
130
140
150
160
170
180
190
200
td(off) (µs)
Figure 30. Output voltage rise time Figure 31. Output voltage fall time
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
tr (µs)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
1
2
3
4
5
6
7
8
tf (µs)
Application information VNH2SP30-E
20/33
3 Application information
In normal operating conditions the DIAGX/ENX pin is considered as an input pin by the
device. This pin must be externally pulled high.
PWM pin usage: in all cases, a “0” on the PWM pin will turn off both LSA and LSB switches.
When PWM rises back to “1”, LSA or LSB turn on again depending on the input pin state.
Figure 32. Typical application circuit for DC to 20 kHz PWM operation short circuit
protection
Note: The value of the blocking capacitor (C) depends on the application conditions and defines voltage and current ripple onto supply
line at PWM operation. Stored energy of the motor inductance may fly back into the blocking capacitor, if the bridge driver goes into
tri-state. This causes a hazardous overvoltage if the capacitor is not big enough. As basic orientation, 500µF per 10A load current is
recommended.
In case of a fault condition the DIAGX/ENX pin is considered as an output pin by the
device.The fault conditions are:
●overtemperature on one or both high sides
●short to battery condition on the output (saturation detection on the low side power
MOSFET)
Possible origins of fault conditions may be:
●OUTA is shorted to ground → overtemperature detection on high side A.
●OUTA is shorted to VCC → low side power MOSFET saturation detection.
M
μC
Reg 5V + 5V
HSAHSB
LSALSB
VCC
DIAGA/ENA
CS
INA
PWM
OUTAOUTB
D
S
Gb) N MOSFET
3.3K
1K
1K
1K
10K
33nF 1.5K
VCC
100K
DIAGB/ENB
+5V
1K
3.3K
IN
B
1K
GNDAGNDB
C
VNH2SP30-E Application information
21/33
When a fault condition is detected, the user can know which power element is in fault by
monitoring the INA, INB, DIAGA/ENA and DIAGB/ENB pins.
In any case, when a fault is detected, the faulty leg of the bridge is latched off. To turn on the
respective output (OUTX) again, the input signal must rise from low to high level.
Note: In case of the fault condition is not removed, the procedure for unlatching and sending the
device in Stby mode is:
- Clear the fault in the device (toggle : INA if ENA=0 or INB if ENB=0)
- Pull low all inputs, PWM and Diag/EN pins within tDEL.
If the Diag/En pins are already low, PWM=0, the fault can be cleared simply toggling the
input. The device will enter in stby mode as soon as the fault is cleared.
3.1 Reverse battery protection
Three possible solutions can be considered:
1. a Schottky diode
D
connected to VCC pin
2. an N-channel MOSFET connected to the GND pin (see Figure 32: Typical application
circuit for DC to 20 kHz PWM operation short circuit protection on page 20)
3. a P-channel MOSFET connected to the VCC pin
The device sustains no more than -30A in reverse battery conditions because of the two
body diodes of the power MOSFETs. Additionally, in reverse battery condition the I/Os of
VNH2SP30-E are pulled down to the VCC line (approximately -1.5V). A series resistor must
Figure 33. Behavior in fault condition (How a fault can be cleared)
INA
INB
DIAGA
ENA
DIAGB
ENB
IoutAÆoutB
FAULTA
(Internal Signal)
FAULTB
(Internal Signal)
Normal
Operation OUTBshorted
to VCC
tDEL
Fault Cleared Stby (*) Normal
Operation OUTBshorted
to GND
tDEL
Fault Cleared Normal
Operation
Device Latched Device Latched Dev ice Unlatched
INA
INB
DIAGA
ENA
DIAGB
ENB
IoutAÆoutB
FAULTA
(Internal Signal)
FAULTB
(Internal Signal)
Normal
Operation OUTBshorted
to VCC
tDEL
Fault Cleared Stby (*) Normal
Operation OUTBshorted
to GND
tDEL
Fault Cleared Normal
Operation
Device Latched Device Latched Dev ice Unlatched
Application information VNH2SP30-E
22/33
be inserted to limit the current sunk from the microcontroller I/Os. If IRmax is the maximum
target reverse current through µC I/Os, the series resistor is:
Figure 34. Half-bridge configuration
Note: The VNH2SP30-E can be used as a high power half-bridge driver achieving an On
resistance per leg of 9.5mΩ.
Figure 35. Multi-motors configuration
Note: The VNH2SP30-E can easily be designed in multi-motors driving applications such as seat
positioning systems where only one motor must be driven at a time. DIAGX/ENX pins allow
to put unused half-bridges in high impedance.
M
OUT
A
OUT
A
OUT
B
OUT
B
V
CC
PWM
DIAG
A
/EN
A
IN
A
DIAG
B
/EN
B
IN
B
GND
B
GND
A
GND
B
GND
A
PWM
DIAG
A
/EN
A
IN
A
DIAG
B
/EN
B
IN
B
M
2
OUT
A
OUT
A
OUT
B
OUT
B
V
CC
PWM
DIAG
A
/EN
A
IN
A
DIAG
B
/EN
B
IN
B
GND
B
GND
A
GND
B
GND
A
PWM
DIAG
A
/EN
A
IN
A
DIAG
B
/EN
B
IN
B
M
1
M
3
VNH2SP30-E Application information
23/33
Figure 36. Waveforms in full bridge operation
NORMAL OPERATION (DIAGA/ENA=1, DIAG
B/ENB=1)
INA
INB
PWM
OUTA
OUTB
IOUTA->OUTB
DIAGA/ENA
DIAGB/ENB
DIAGB/ENB
INA
INB
PWM
OUTA
OUTB
DIAGA/ENA
NORMAL OPERATION (DIAGA/ENA=1, DIAG
B/ENB= 0 and DIAGA/ENA=0, DIAG
B/ENB=1)
normal operation OUTA shorted to ground normal operation
INA
INB
Tj
DIAGA/ENA
DIAGB/ENB
ILIM
TTSD
TTR
Tj > TTR
CURRENT LIMITATION/THERMAL SHUTDOWN or OUTA SHORTED TO GROUND
CS (*)
CS
CS
IOUTA->OUTB
IOUTA->OUTB
tDEL tDEL
LOAD CONNECTED BETWEEN OUTA, OUTB
LOAD CONNECTED BETWEEN OUTA, OUTB
(*) CS BEHAVIOR DURING PWM MODE WILL DEPEND ON PWM FREQUENCY AND DUTY CYCLE.
Application information VNH2SP30-E
24/33
Figure 37. Waveforms in full bridge operation (continued)
normal
operation OUT
A
shorted to V
CC
normal operation undervoltage shutdown
IN
A
IN
B
OUT
A
OUT
B
DIAG
B
/EN
B
DIAG
A
/EN
A
OUT
A
shorted to V
CC
and undervoltage shutdown
CS V < nominal
I
OUTA
->
OUTB
undefined
undefined
VNH2SP30-E Package and PCB thermal data
25/33
4 Package and PCB thermal data
4.1 PowerSSO-30 thermal data
Figure 38. MultiPowerSO-30™ PC board
Note: Layout condition of Rth and Zth measurements (PCB FR4 area = 58mm x 58mm, PCB
thickness = 2mm. Cu thickness = 35μm, Copper areas: from minimum pad layout to
16cm2).
Figure 39. Chipset configuration
Figure 40. Auto and mutual Rthj-amb vs PCB copper area in open box free air
condition
HIGH SIDE
CHIP
HSAB
LOW SIDE
CHIP A
LOW SIDE
CHIP B
LSALSB
0
5
10
15
20
25
30
35
40
45
0 5 10 15 20
cm2 of Cu area (refer to PCB layout)
°C/W
RthHS
RthLS
RthHSLS
RthLSLS
Package and PCB thermal data VNH2SP30-E
26/33
4.1.1 Thermal calculation in clockwise and anti-clockwise operation in
steady-state mode
4.1.2 Thermal resistances definition (values according to the PCB heatsink
area)
RthHS = RthHSA = RthHSB = High Side Chip Thermal Resistance Junction to Ambient (HSA or
HSB in ON state)
RthLS = RthLSA = RthLSB = Low Side Chip Thermal Resistance Junction to Ambient
RthHSLS = RthHSALSB = RthHSBLSA = Mutual Thermal Resistance Junction to Ambient
between High Side and Low Side Chips
RthLSLS = RthLSALSB = Mutual Thermal Resistance Junction to Ambient between Low Side
Chips
4.1.3 Thermal calculation in transient mode(a)
TjHSAB = ZthHS x PdHSAB + ZthHSLS x (PdLSA + PdLSB) + Tamb
TjLSA = ZthHSLS x PdHSAB + ZthLS x PdLSA + ZthLSLS x PdLSB + Tamb
TjLSB = ZthHSLS x PdHSAB + ZthLSLS x PdLSA + ZthLS x PdLSB + Tamb
4.1.4 Single pulse thermal impedance definition
(values according to the PCB heatsink area)
ZthHS = High Side Chip Thermal Impedance Junction to Ambient
ZthLS = ZthLSA = ZthLSB = Low Side Chip Thermal Impedance Junction to Ambient
ZthHSLS = ZthHSABLSA = ZthHSABLSB = Mutual Thermal Impedance Junction to Ambient
between High Side and Low Side Chips
ZthLSLS = ZthLSALSB = Mutual Thermal Impedance Junction to Ambient between Low Side
Chips
Table 15. Thermal calculation in clockwise and anti-clockwise operation in steady-
state mode
HSAHSBLSALSBTjHSAB TjLSA TjLSB
ON OFF OFF ON PdHSA x RthHS + PdLSB
x RthHSLS + Tamb
PdHSA x RthHSLS +
PdLSB x RthLSLS + Tamb
PdHSA x RthHSLS + PdLSB
x RthLS + Tamb
OFF ON ON OFF PdHSB x RthHS + PdLSA
x RthHSLS + Tamb
PdHSB x RthHSLS +
PdLSA x RthLS + Tamb
PdHSB x RthHSLS + PdLSA
x RthLSLS + Tamb
a. Calculation is valid in any dynamic operating condition. Pd values set by user.
VNH2SP30-E Package and PCB thermal data
27/33
Equation 1: pulse calculation formula
Figure 41. MultiPowerSO-30 HSD thermal impedance junction ambient single pulse
Figure 42. MultiPowerSO-30 LSD thermal impedance junction ambient single pulse
ZTHδRTH δZTHtp 1δ–()+Þ=
where δtpT⁄=
0.1
1
10
100
0.001 0.01 0.1 1 10 100 1000
ti me (sec)
°C/W
16 cm2
Footprint
8 cm2
4 cm2
16 cm2
Footprint
8 cm2
4 cm2
ZthHS
ZthHSLS
0.1
1
10
100
0.001 0.01 0.1 1 10 100 1000
tim e (sec )
°C/W
16 cm2
Footprint
8 cm2
4 cm2
16 cm2
Footprint
8 cm2
4 cm2
ZthLS
ZthLSLS
Package and PCB thermal data VNH2SP30-E
28/33
Figure 43. Thermal fitting model of an H-bridge in MultiPowerSO-30
Table 16. Thermal parameters(1)
1. The blank space means that the value is the same as the previous one.
Area/island (cm2)Footprint4 816
R1 = R7 (°C/W) 0.05
R2 = R8 (°C/W) 0.3
R3 (°C/W) 0.5
R4 (°C/W) 1.3
R5 (°C/W) 14
R6 (°C/W) 44.7 39.1 31.6 23.7
R9 = R15 (°C/W) 0.2
R10 = R16 (°C/W) 0.4
R11 = R17 (°C/W) 0.8
R12 = R18 (°C/W) 1.5
R13 = R19 (°C/W) 20
R14 = R20 (°C/W) 46.9 36.1 30.4 20.8
R21 = R22 = R23 (°C/W) 115
C1 = C7 (W.s/°C) 0.005
C2 = C8 (W.s/°C) 0.008
C3 = C11 = C17 (W.s/°C) 0.01
C4 = C13 = C19 (W.s/°C) 0.3
C5 (W.s/°C) 0.6
C6 (W.s/°C) 5 7 9 11
C9 = C15 (W.s/°C) 0.003
C10 = C16 (W.s/°C) 0.006
C12 = C18 (W.s/°C) 0.075
C14 = C20 (W.s/°C) 2.5 3.5 4.5 5.5
VNH2SP30-E Package and packing information
29/33
5 Package and packing information
5.1 ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. ECOPACK® packages are lead-free. The category of Second Level Interconnect
is marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner
box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com.
5.2 MultiPowerSO-30 package mechanical data
Figure 44. MultiPowerSO-30 package outline
Package and packing information VNH2SP30-E
30/33
Figure 45. MultiPowerSO-30 suggested pad layout
Table 17. MultiPowerSO-30 mechanical data
Symbol
Millimeters
Min Typ Max
A2.35
A2 1.85 2.25
A3 0 0.1
B 0.42 0.58
C 0.23 0.32
D 17.1 17.2 17.3
E 18.85 19.15
E1 15.9 16 16.1
e1
F1 5.55 6.05
F2 4.6 5.1
F3 9.6 10.1
L 0.8 1.15
N 10deg
S 0deg 7deg
VNH2SP30-E Package and packing information
31/33
5.3 Packing information
Note: The devices can be packed in tube or tape and reel shipments (see the Device summary on
page 1 for packaging quantities).
Figure 46. MultiPowerSO-30 tube shipment (no suffix)
Figure 47. MultiPowerSO-30 tape and reel shipment (suffix “TR”)
A
B
C
Dimension mm
Base Q.ty 29
Bulk Q.ty 435
Tube length (± 0.5) 532
A3.82
B23.6
C (± 0.13) 0.8
Reel dimensions
SO-28 tube shipment (no suffix)
Dimension mm
Base Q.ty 1000
Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
D (min) 20.2
G (+ 2 / -0) 32
N (min) 100
T (max) 38.4
Top
cover
tape
Start
No componentsNo components Components
500 mm min
500 mm min
Empty components pockets
User direction of feed
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Description Dimension mm
Tape width W 32
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 24
Hole Diameter D (± 0.1/-0) 1.5
Hole Diameter D1 (min) 2
Hole Position F (± 0.1) 14.2
Compartment Depth K (max) 2.2
End
Revision history VNH2SP30-E
32/33
6 Revision history
Table 18. Document revision history
Date Revision Description of changes
Sep-2004 1 First issue
Dec- 2004 2 Inserted toff(min) test condition modification and note
Modified IRM figure number
Feb-2005 3 Minor changes
Apr-2005 4 Public release
01-Sep-2006 5
Document converted into new ST corporate template.
Added table of contents, list of tables and list of figures
Removed figure number from package outline on page 1
Changed Features on page 1 to add ECOPACK® package
Added Section 1: Block diagram and pin description on page 5
Added Section 2.2: Electrical characteristics on page 9
Added “low” and “high” to parameters for IINL and IINH in Tabl e 7 o n
page 9
Inserted note in Figure 32 on page 20
Added vertical limitation line to left side arrow of
t
D(off)
to Figure 7 on
page 13
Added Section 4.1: PowerSSO-30 thermal data on page 25
Added Section 5: Package and packing information on page 29
Added Section 5.3: Packing information on page 31
Updated disclaimer (last page) to include a mention about the use of
ST products in automotive applications
15-May-2007 6 Document reformatted and converted into new ST template.
06-Feb-2008 7 Corrected Heat Slug numbers in Table 3: Pin definitions and
functions.
02-Oct-2008 8
Added new infomation in Table 6: Power section
Added Figure 33: Behavior in fault condition (How a fault can be
cleared)
VNH2SP30-E
33/33
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