ICS950812YGLFT - Integrated Circuit Systems, Inc.

Integrated

Circuit

Systems, Inc.

ICS950812

0542G—08/21/03

Block Diagram

Recommended Application:

CK-408 clock with Buffered/Unbuffered mode supporting

Almador, Brookdale, ODEM, and Montara-G chipsets with

PIII/P4 processor. Programmable for group to group skew.

Output Features:

• 3 Differential CPU Clock Pairs @ 3.3V

• 7 PCI (3.3V) @ 33.3MHz including 2 early PCI clocks

• 3 PCI_F (3.3V) @ 33.3MHz

• 1 USB (3.3V) @ 48MHz, 1 DOT (3.3V) @ 48MHz

• 1 REF (3.3V) @ 14.318MHz

• 5 3V66 (3.3V) @ 66.6MHz

• 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz

• 3 66MHz_OUT/3V66 (3.3V) @ 66.6MHz_IN or 66.6MHz

Features:

• Provides standard frequencies and additional 5%

and 10% over-clocked frequencies

• Supports spread spectrum modulation:

No spread, Center Spread (±0.35%, ±0.5%,

or ±0.75%), or Down Spread (-0.5%, -1.0%, or -1.5%)

• Offers adjustable PCI early clock via latch inputs

• Selectable 1X or 2X strength for REF via I2C interface

• Efficient power management scheme through PD#,

CPU_STOP# and PCI_STOP#.

• Uses external 14.318MHz crystal

• Stop clocks and functional control available through

I2C interface.

Key Specifications:

•CPU Output Jitter <150ps

• 3V66 Output Jitter <250ps

• 66MHz Output Jitter (Additive) (Buffered Mode) <100ps

• CPU Output Skew <100ps

Pin Configuration

Frequency Generator with 200MHz Differential CPU Clocks

Frequency Select

Note:

Almador board level designs MUST use pin 22,

66MHZ_OUT1, as the feedback connection from the

clock buffer path to the Almador (GMCH) chipset.

66MHz_OU

(

2:0

)

66MHz_IN PCICLK_F

3V66 (4:2) 3V66_5 P CICL K

FS2 FS1 FS0 MHz MHz MHz MHz MHz

0 0 0 66.66 66.66 66.66 66.66 33.33

0 0 1 100.00 66.66 66.66 66.66 33.33

0 1 0 200.00 66.66 66.66 66.66 33.33

0 1 1 133.33 66.66 66.66 66.66 33.33

1 0 0 66.66 66.66 66MHz_IN Input 66MHz_IN/2

1 0 1 100.00 66.66 66MHz_IN Input 66MHz_IN/2

1 1 0 200.00 66.66 66MHz_IN Input 66MHz_IN/2

1 1 1 133.33 66.66 66MHz_IN Input 66MHz_IN/2

CPUCLK 3V66Bit

PLL2

PLL1

Spread

Spectrum

3V66_5/66MHz_IN

3V66_3/66MHz_OUT1

3V66_(4,2)/66MHz_OUT(2,0)

48MHz_USB

48MHz_DOT

X2 XTAL

OSC

3V66

DIVDER

PD#

CPU_STOP#

PCI_STOP#

MULTSEL

SDATA

SCLK

FS (5:0)

I REF

Control

Logic

Config.

Reg.

REF

3V66_0

CPU

DIVDER

CPUCLKT (2:0)

CPUCLKC (2:0)

Stop

3V66_1/VCH_CLK

PCICLK (6:4, 2, 0)

PCI

DIVDER

PCICLK_F (2:0)

Stop

E_PCICLK(1,3)/PCICLK(1,3)

_PWRGD#

VDDREF 1 56 REF

X1 2 55 FS1

X2 3 54 FS0

GND 4 53 CPU_STOP#*

PCICLK_F0 5 52 CPUCLKT0

PCICLK_F1 651

CPUCLKC0

PCICLK_F2 7 50 VDDCPU

VDDPCI 8 49 CPUCLKT1

GND 9 48 CPUCLKC1

PCICLK0 10 47 GND

**E_PCICLK1/PCICLK1 11 46 VDDCPU

PCICLK2 12 45 CPUCLKT2

**E_PCICLK3/PCICLK3 13 44 CPUCLKC2

VDDPCI 14 43 MULTSEL*

GND 15 42 IREF

PCICLK4 16 41 GND

PCICLK5 17 40 FS2

PCICLK6 18 39 48MHz_USB/FS3**

VDD3V66 19 38 48MHz_DOT

GND 20 37 VDD48

66MHZ_OUT0/3V66_2 21 36 GND

66MHZ_OUT1/3V66_3 22 35 3V66_1/VCH_CLK/FS4**

66MHZ_OUT2/3V66_4 23 34 PCI_STOP#*

66MHZ_IN/3V66_5 24 33 3V66_0/FS5**

*PD# 25 32 VDD3V66

VDDA 26 31 GND

GND 27 30 SCLK

Vtt_PWRGD# 28 29 SDATA

56-P i n 300m i l S S OP

6. 10 mm. Bod y, 0.50 mm . p itch T S SOP

*These inputs have 120K internal pull-up resistors to VDD.

**Internal pull-down resistors to ground.

ICS950812

0542G—08/21/03

Pin Configuration

PIN # PIN NAME PIN TYPE DESCRIPTION

1 V DDREF PWR Re f , XTA L po we r supp ly, nom ina l 3.3V

2 X1 IN Crystal input, Nominal ly 14.318MHz.

3 X2 OUT Crystal output, Nominally 14 .318MHz

4 GND PWR Ground pin.

5 PCICLK_F0 OUT Free running PCI clock not affected by PCI_STOP# .

6 PCICLK_F1 OUT Free running PCI clock not affected by PCI_STOP# .

7 PCICLK_F2 OUT Free running PCI clock not affected by PCI_STOP# .

8 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V

9 GND PWR Ground pin.

10 PCICLK0 OUT PCI clock output.

11 **E_PCICLK1/PCICLK1 I/O Early/Normal PCI cl ock output lat ched at power up.

12 PCICLK2 OUT PCI clock output.

13 **E_PCICLK3/PCICLK3 I/O Early/Normal PCI cl ock output lat ched at power up.

14 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V

15 GND PWR Ground pin.

16 PCICLK4 OUT PCI clock output.

17 PCICLK5 OUT PCI clock output.

18 PCICLK6 OUT PCI clock output.

19 VDD3V66 PWR Power pin for the 3V66 clocks.

20 GND PWR Ground pin.

21 66MHZ_OUT0/3V66_2 OUT 3.3V 66.66MHz clock output selected via buffered or internal VCO.

22 66MHZ_OUT1/3V66_3 OUT 3.3V 66.66MHz clock output selected via buffered or internal VCO.

23 66MHZ_OUT2/3V66_4 OUT 3.3V 66.66MHz clock output selected via buffered or internal VCO.

24 66MHZ_IN/3V66_5 I/O 3.3V 66.66MHz clock from internal VCO, 66MHZ input to 66MHz output and

PCI.

25 *PD# IN Asynchronous active low input pin used to po wer down the device into a low

power state. The internal clocks are disabled and the VCO and the crystal

are stopped. The latency of the power down will not be greater than 1.8ms.

26 VDDA PWR 3.3 V power for the PLL core.

27 GND PWR Ground pin.

28 Vtt_PWRGD# IN This 3.3V LVTTL input is a level sensitive strobe used to determine when

latch inputs are vali d and are ready to be sampled. This is an active low

input.

ICS950812

0542G—08/21/03

Pin Configuration (Continued)

PIN # PIN NAME PIN T YPE DESCRIPTION

29 SDATA I/O Data pin for I2C ci rcuitry 5V t olerant

30 SCLK IN Clock pin of I2C circuitry 5V tolerant

31 GND PWR Ground pin.

32 VDD3V66 PWR Power pin for the 3V66 clocks.

33 3V66_0/FS5** I/O F requency select latch input pin / 3.3V 66.66MHz clock output.

34 PCI_STOP#* IN Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input

low

35 3V66_1/VCH_CLK/FS4** I/O Frequenc y select latch input pin / 3.3V 66.66MHz clock output / 48MHz

VCH clock output.

36 GND PWR Ground pin.

37 VDD48 PWR Power pin for the 48MHz output.3.3V

38 48MHz_DOT OUT 48MHz clock output.

39 48MHz_USB/FS3** I/O Fr equency select latch input pin / 3.3V 48MHz clock output.

40 FS2 IN Fre quency select pin.

41 GND PWR Ground pin.

42 IREF OUT Th is pin estab lishes the re ference curre nt for the differential current-mod e

outp ut pairs. This pin requir es a fixed precision r esistor tied to ground in

order to estab lish the appropriate current. 475 ohms is the standard va lue.

43 MULTSEL* IN 3.3V LVTTL input for selection the current m ultiplier for CPU outputs

44 CPUCLKC2 OUT Comp limentary clock of differential pair CPU output s. These are cu rren t

mode outputs. External resis tors are requir ed for voltage bias.

45 CPUCLKT2 OUT True clock of differ e ntial pair CPU outputs. T hese are current mode

outp uts. External resistors are required for voltag e bias.

46 VDDCPU PWR Supply for CPU cloc ks, 3.3V nominal

47 GND PWR Ground pin.

48 CPUCLKC1 OUT Comp limentary clock of differential pair CPU output s. These are cu rren t

mode outputs. External resis tors are requir ed for voltage bias.

49 CPUCLKT1 OUT True clock of differ e ntial pair CPU outputs. T hese are current mode

outp uts. External resistors are required for voltag e bias.

50 VDDCPU PWR Supply for CPU cloc ks, 3.3V nominal

51 CPUCLKC0 OUT Comp limentary clock of differential pair CPU output s. These are cu rren t

mode outputs. External resis tors are requir ed for voltage bias.

52 CPUCLKT0 OUT True clock of differ e ntial pair CPU outputs. T hese are current mode

outp uts. External resistors are required for voltag e bias.

53 CPU_STOP#* IN Stops all CPUCLK besi des the free runni ng cl ocks

54 FS0 IN Fre quency select pin.

55 FS1 IN Fre quency select pin.

56 REF OUT 14.3 18 MHz referen ce clock.

ICS950812

0542G—08/21/03

Frequency Select Table 2

Fr equency Sel ec t Table 1 66MHz_OU

T (2:0 ) 66MHz_IN

2FS

1FS

03V66 (4:2) 3V66 _5

0 0 0 66.66 66.66 66.66 66.66 33.33 14.318 48.008

0 0 1 100.00 66.66 66.66 66.66 33.33 14.318 48.008

0 1 0 200.00 66.66 66.66 66.66 33.33 14.318 48.008

0 1 1 133.33 66.66 66.66 66.66 33.33 14.318 48.008

1 0 0 66.66 66.66 66MHz_IN Input 66MHz_IN/2 14.318 48.008

1 0 1 100.00 66.66 66MHz_IN Input 66MHz_IN/2 14.318 48.008

1 1 0 200.00 66.66 66MHz_IN Input 66MHz_IN/2 14.318 48.008

1 1 1 133.33 66.66 66MHz_IN Input 66MHz_IN/2 14.318 48.008

0 0 0 70.00 70.00 70.00 70.00 35.00 14.318 48.008

0 0 1 105.00 70.00 70.00 70.00 35.00 14.318 48.008

0 1 0 Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate

0 1 1 140.00 70.00 70.00 70.00 35.00 14.318 48.008

1 0 0 70.00 70.00 66MHz_IN Input 66MHz_IN/2 14.318 48.008

1 0 1 105.00 70.00 66MHz_IN Input 66MHz_IN/2 14.318 48.008

1 1 0 Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate

1 1 1 140.00 70.00 66MHz_IN Input 66MHz_IN/2 14.318 48.008 5% Overclocking

0 0 0 73.32 73.32 73.32 73.32 36.66 14.318 48.008

0 0 1 110.00 73.32 73.32 73.32 36.66 14.318 48.008

0 1 0 Test/2 Test/4 Test/4 Test/4 Test/8 Test Test/2 Test

0 1 1 146.60 73.32 73.32 73.32 36.66 14.318 48.008

1 0 0 73.32 73.32 66MHz_IN Input 66MHz_IN/2 14.318 48.008

1 0 1 110.00 73.32 66MHz_IN Input 66MHz_IN/2 14.318 48.008

1 1 0 Test/2 Test/4 Test/4 Test/4 Test/8 Test Test/2 Test

1 1 1 146.60 73.32 66MHz_IN Input 66MHz_IN/2 14.318 48.008 10% Overclocking

10% Overclocking

Standard Clocking

5% Overclocking

110

(See table 2)

111

(See table 2)

REF MHz USB/DOT

MHz Clocking Mode

Fre q Sel CPU MHz 3 V66 MHz

FS(5:3) PCI MHz

From

000

101

(See table 2)

5FS

4FS

000

001

010

011

100

101

110

111 +/-0.35%, Center Spread

0 to -1.5%, Down Spread

+/-0.5%, Center Spread

+/-0.75%, Center Spread

+/-0.35%, Center Spread

10% Overclocking

Cloc king Mode

No Spread (default)

or +/-0.4%

0 to -0.5%, Down Spread

0 to -1.0%, Down SpreadStandard Clocking

Standard Clocking

CPU, 3V66, 66MHz_OUT,

66MHz_IN, PCI

5% Overclocking

Fre q Sel

Standard Clocking

Note: To enable spread, Byte 0 Bit 7 must be set to 1.

ICS950812

0542G—08/21/03

Maximum Allowed Current

Host Sw i ng Select Func t i ons

MULTSEL

PCI Select Func t i ons

Note:

* A pprox i m ate v al ues

Max 3.3V suppl y consum pt i on

Max di scret e cap l oads,

V dd = 3.465V

All s t atic in

ut s = Vdd or GND

40mA

280mA

Condition

P owerdown Mode

(P D# = 0 )

Active Full

B oard Target

Trace/Term Z Ref erenc e R,

Iref = VDD/3*Rr

Rr = 221 1%,

I ref = 5. 00m A

Rr = 475 1%,

I ref = 2. 32m A

50 ohms

Output

Current

I oh = 4 * I RE F

I oh = 6 * I RE F

1. 0V @ 50 ohm

0. 7V @ 50 ohm

Voh @ Z

E _P CI CL K1 (11) E _P CI CL K3 (13) E_PCICLK(3,1)*

E _P CI CLK1 = 10K ohm resi st or.

0 0 0ns

0 1 0.5ns

1.0ns

1 1 1.5ns

E _P CI CLK3 = 10K ohm resi st or.

0 = No resistor

1 = 10Kohm pul l -up t o VD

ICS950812

0542G—08/21/03

P in # Name 0 1 PWD

Bit 7 - Spread Enabled Spread Spectrum Control RW OFF ON 0

Bit 6 - CPUCLKT(2:0) Power down mode output level

0= CPU driven in power down

1= undriven RW HIGH LOW 0

Bit 5 35 3V66_1/VCH_CLK/FS4** VCH/66.66 Select RW 66 .66 48.0 0 0

Bit 4 53 CPU_S TOP#* Refl ects value of pin R Stop Active X

Bit 3 34 PCI_STOP#* Refl ects value of pin at power up.

Also can be set. RW Stop Active X

Bit 2 39 FS3 Frequen cy S election RW - - X

Bit 1 55 FS1 Frequen cy S election R - - X

Bit 0 54 FS0 Frequen cy S election R - - X

Note: For PCI_STOP# function, refer to table 3.

Type Bit Control

Control Function

Affected PinBYTE

P in # Name 0 1 PWD

Bit 7 43 MULTSEL* Refl ects value of pin R - - x

Bit 6 - CPUCLKT(2:0) CPU_Stop mode output level

0= CPU driven when stopped

1 = undriven RW HIGH LOW 0

Bit 5 45, 44 CPUCLKT2 , CPUCLKC 2

(see note) Al low control of outp ut with

assertion of CPU_S TOP#. RW Not

Freerun Freerun 0

Bit 4 49, 48 CPUCLKT1 , CPUCLKC 1

(see note) Al low control of outp ut with

assertion of CPU_S TOP#. RW Not

Freerun Freerun 0

Bit 3 52, 51 CPUCLKT0 , CPUCLKC 0

(see note) Al low control of outp ut with

assertion of CPU_S TOP#. RW Not

Freerun Freerun 0

Bit 2 45, 44 CPUCLKT2, CPUCLKC2 Output control RW Di sable Enable 1

Bit 1 49, 48 CPUCLKT1, CPUCLKC1 Output control RW Di sable Enable 1

Bit 0 52, 51 CPUCLKT0, CPUCLKC0 Output control RW Di sable Enable 1

Note:

Type Bit Control

Control Function

Affected PinBYTE

CPUCLK(2:0) can be turned on/off by CPU_STOP#. Refer to table 4.

P in # Name 0 1 PWD

Bit 7 56 REF 1X or 2X Strength control RW 1X 2X 0

Bit 6 18 PCICLK 6 Output control RW Disable Enabl e 1

Bit 5 17 PCICLK 5 Output control RW Disable Enabl e 1

Bit 4 16 PCICLK 4 Output control RW Disable Enabl e 1

Bit 3 13 ** E_PCICLK3/PCICLK3 Output control RW Disable Enabl e 1

Bit 2 12 PCICLK 2 Output control RW Disable Enabl e 1

Bit 1 11 ** E_PCICLK1/PCICLK1 Output control RW Disable Enabl e 1

Bit 0 10 PCICLK 0 Output control RW Disable Enabl e 1

Note:

BYTE

2Control Function Bit Control

PCICLK(6:0) can be turned on/of f by PCI_STOP# . Refer to table 3.

Affected Pin Type

P in # Name 0 1 PWD

Bit 7 38 48MHz_DOT Output control RW Disable Enabl e 1

Bit 6 39 48MHz_USB /FS3* * Output control RW Disable Enabl e 1

Bit 5 7 PCICLK_F2 (see note) Allow control of output with

assertion of PCI_STOP #. RW Freerun Not

Freerun 0

Bit 4 6 PCICLK_F1 (see note) Allow control of output with

assertion of PCI_STOP #. RW Freerun Not

Freerun 0

Bit 3 5 PCICLK_F0 (see note) Allow control of output with

assertion of PCI_STOP #. RW Freerun Not

Freerun 0

Bit 2 7 P CICLK_ F2 Output control RW Disable Enabl e 1

Bit 1 6 P CICLK_ F1 Output control RW Disable Enabl e 1

Bit 0 5 P CICLK_ F0 Output control RW Disable Enabl e 1

Note: PCICLK_F(2:0) can be turned on/off by P CI_STOP#. Refer to table 5.

BYTE

3Control Function

Affected Pin Bit Control

Type

ICS950812

0542G—08/21/03

P in # Name 0 1 PWD

Bit 7 35 FS4 Frequen cy S election RW Disable Enable X

Bit 6 33 FS5 Frequen cy S election RW Disable Enable X

Bit 5 33 3V66_0/FS5* * Output control RW Disable Enabl e 1

Bit 4 35 3V66_1 /V CH_CLK/FS4** Output control RW Di sable Enabl e 1

Bit 3 24 66MHZ_IN/3V 66_5 Output control RW Di sable Enable 1

Bit 2 23 66MHZ_OUT2/3V66_4 Output control RW Disabl e Enable 1

Bit 1 22 66MHZ_OUT1/3V66_3 Output control RW Disabl e Enable 1

Bit 0 21 66MHZ_OUT0/3V66_2 Output control RW Disabl e Enable 1

TypeControl Function

Affected PinBYTE

4Bit Control

P in # Name 0 1 PWD

Bit 7 X - Unused - - - 0

Bit 6 X - Reserved X - - 0

Bit 5 X 3V66 (5:2)/66MHZ_OUT(2:0)

(See table 6) Allow control of output with

assertion of CPU_STOP#. X Freerun Not

Freerun 0

Bit 4 X 3V66(1:0) (See tabl e 7) Allow control of output with

assertion of CPU_STOP#. X Freerun Not

Freerun 0

Bit 3 RW - - 0

Bit 2 RW - - 0

Bit 1 RW - - 0

Bit 0 RW - - 0

Note:

Control Function

00 = Medium (default), 01 = Low,

11,10 =High

Type

38 48MHz_DOT Slew Control

Affected PinBYTE

Functions in Byte 5 of CK408 were intended as a test and debug byte only.

00 = Medium (default), 01 = Low,

11,10 =High

Bit Control

48MHz_USB Slew Control39

P in # Name 0 1 PWD

Bit 7 X Revision ID Bit 3 R - - X

Bit 6 X Revision ID Bit 2 R - - X

Bit 5 X Revision ID Bit 1 R - - X

Bit 4 X Revision ID Bit 0 R - - X

Bit 3 X Vendor ID Bit 3 (Reserved) R - - 0

Bit 2 X Vendor ID Bit 2 (Reserved) R - - 0

Bit 1 X Vendor ID Bit 1 (Reserved) R - - 0

Bit 0 X Vendor ID Bit 0 (Reserved) R - - 1

Revisi on ID Value Based on

Device Revision

Control Function Type Bit ControlAffected PinBYTE

P in # Name 0 1 PWD

Bit 7 X - Unused R - - 0

Bit 6 X - Unused R - - 0

Bit 5 X - Unused R - - 0

Bit 4 X - Unused R - - 0

Bit 3 X - Unused R - - 0

Bit 2 X - Unused R - - 0

Bit 1 X - Unused R - - 0

Bit 0 X - Unused R - - 0

TypeControl Function Bit ControlAffected PinBYTE

P in # Name 0 1 PWD

Bit 7 X - (Reserved) X - - 0

Bit 6 X - (Reserved) X - - 0

Bit 5 X - (Reserved) X - - 0

Bit 4 X - (Reserved) X - - 0

Bit 3 X - R - - 1

Bit 2 X - R - - 1

Bit 1 X - R - - 1

Bit 0 X - R - - 1

Note: Byte 8 is for ICS test only. Do not write as system damage may occur. Bit(3:0) contain the readback Byte count.

Bit ControlAffected Pin Control Function

Readback Byte Count

Type

BYTE

ICS950812

0542G—08/21/03

P in # Name 0 1 PWD

Bit 7 RW - - 0

Bit 6 RW - - 0

Bit 5 RW - - 0

Bit 4 RW - - 0

Bit 3 RW - - 0

Bit 2 RW - - 0

Bit 1 RW - - 0

Bit 0 RW - - 0

Bit Control

00 (default), 11 = Medium

01 = Low, 10 =High

00 (default), 11 = Medium

10 = Low, 01 =High

00 (default), 11 = Medium

10 = Low, 01 =High

00 = High(default), 01 = Low,

11,10 = Medium

V CHCLK Slew Control

Type

BYTE

9Affected Pin Control Function

7, 6, 5 PCICLK_ F (2:0) Slew Contol

13, 12,

11, 10 PCICLK (3:0) Slew Contol

18, 17, 16,

13 , 12 , 11, 10 PCICLK (6:0) Slew Contol

P in # Name 0 1 PWD

Bit 7 X - M/N Enable (Enable access to

Byte 11 - 14) RW HW/B0 Byte

(11-14) 0

Bit 6 X - Unused - - - 0

Bit 5 RW - - 0

Bit 4 RW - - 0

Bit 3 RW - - 0

Bit 2 RW - - 0

Bit 1 X - Unused - - - 0

Bit 0 X - Unused - - - 0

Bit Control

Control Function Type

BYTE

10 Affected Pin

24, 23,

22, 21 3V 66(5:2)/66MHZ_OUT(2:0)

Skew Approx 250ps per bit (Ref to P CI)

33, 35 3V66(1:0) Skew Approx 250ps per bit (Ref to PCI)

P in # Name 0 1 PWD

Bit 7 X - VCO Divider Bit8 RW - - X

Bit 6 X - REF Divider Bit6 RW - - X

Bit 5 X - REF Divider Bit5 RW - - X

Bit 4 X - REF Divider Bit4 RW - - X

Bit 3 X - REF Divider Bit3 RW - - X

Bit 2 X - REF Divider Bit2 RW - - X

Bit 1 X - REF Divider Bit1 RW - - X

Bit 0 X - REF Divider Bit0 RW - - X

Note: The decimal representation of these 7 bits (Byte 11 bit[6:0]) + 2 is equal to the REF divider val ue.

BYTE

11 Affected Pin Control Function Type Bit Control

P in # Name 0 1 PWD

Bit 7 X - VCO Divider Bit7 RW - - X

Bit 6 X - VCO Divider Bit6 RW - - X

Bit 5 X - VCO Divider Bit5 RW - - X

Bit 4 X - VCO Divider Bit4 RW - - X

Bit 3 X - VCO Divider Bit3 RW - - X

Bit 2 X - VCO Divider Bit2 RW - - X

Bit 1 X - VCO Divider Bit1 RW - - X

Bit 0 X - VCO Divider Bit0 RW - - X

Note: The decimal representation of these 9 bits (Byte 12 bit[7:0]) and Byte 11 bit [7]) + 8 is equal to the VCO divide r value.

Bit ControlBYTE

12 Affected Pin Control Function Type

Note: See table 8 for Byte 11-14 default information

ICS950812

0542G—08/21/03

P in # Name 0 1 PWD

Bit 7 X - Spread Spectrum Bit7 RW - - X

Bit 6 X - Spread Spectrum Bit6 RW - - X

Bit 5 X - Spread Spectrum Bit5 RW - - X

Bit 4 X - Spread Spectrum Bit4 RW - - X

Bit 3 X - Spread Spectrum Bit3 RW - - X

Bit 2 X - Spread Spectrum Bit2 RW - - X

Bit 1 X - Spread Spectrum Bit1 RW - - X

Bit 0 X - Spread Spectrum Bit0 RW - - X

Affected Pin

Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread

percentage may cause system failure.

BYTE

13 Control Function Type Bit Control

P in # Name 0 1 PWD

B it 7 X - (Reserved) RW - - X

B it 6 X - (Reserved) RW - - X

Bit 5 X - S pread Spectrum Bi t13 RW - - X

Bit 4 X - S pread Spectrum Bi t12 RW - - X

Bit 3 X - S pread Spectrum Bi t11 RW - - X

Bit 2 X - S pread Spectrum Bi t10 RW - - X

Bit 1 X - Spread Spectrum Bit9 RW - - X

Bit 0 X - Spread Spectrum Bit8 RW - - X

BYTE

14 Affected Pin Control Function

Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread

percentage may cause system failure.

Bit Control

Type

Note: See table 8 for Byte 11-14 default information

Spread Spectrum Enable Procedure

Step 1: Power-up ---- Latched inputs, FS(5:0), set frequency per Hardware default on board. SS is off.

BIOS program set IIC Byte0, bit7 to 1, SS will be enable Spread. Note that Byte 10,

bit 7 is default to 0. This allows all setup to be controlled by the Frequency Select

Tables, 1 and 2.

Step 3: To set up Linear programming and SS% adjust using Byte 11 through 14, the BIOS must set

Byte 10, bit 7 to a 1. This will enable access to Byte 11 and 12, M/N linear programming

and Byte 13 and 14, Spread Spectrum % adjust.

Step 2: After power up, SS% can be changed to the fixed selections shown in Frequency Table 2. This

is achieved by Writing to Byte 4, bit 6/7 (FS5:4) and/or Byte 0 (FS3), The data written

to these bytes will overwrite the existing contents and switch to the desired selection.

ICS950812

0542G—08/21/03

Tabl e 3

PCI _STOP# I2C Contro l Table- By te 0, Bi t 3

No t e: When t his B yt e 0, B i t 3 i s low (0), al l P CI clock s are s t opped.

Tabl e 4

CPUCLKT/C ( 2 : 0 ) O utputs I 2C Contr ol Table

Note: Individual CPUCLK out put s are c ont roll ed by B yt e 1, B i t 3, 4, and 5.

Tabl e 5

PCICLK_F (2:0) Outputs I2C Cont r o l Table

Note: Individual P CI CLK out put s are c ont roll ed by B y te 3, B i t 3, 4, and 5.

Tabl e 6

3V66 (5: 2)/ 66M Hz_O UT(2: 0)/ 66M Hz_I N I 2C Contr ol Table

Note: Activating Byte 5, Bit 5 will allow CPU_STOP# to control stop of pins 21, 22, 23, and 24.

CPU_STOP#

(Pin 53) Byte 5

Bi t 5 3V 6 6 (5:2) (Driven )

66MHZ_OUT(2:0)/66M HZ_IN (Buffered)

10 1`1

Byt e 0, Bit 3 R ea d Bit

(Internal Statu s)

PCI_STOP#

(Pin 34)

CPU_STOP#

(

Pin 53

)

Byte 1

Bit 3 , 4 , 5

Byte 0 Bi t 3

Write Bi t

CP UCLKT / C (2:0 ) Ou tp uts

00 Stop

0 1 Running

1 0 Running

1 1 Running

PCI_STOP#

(

Pin 34

)

Byte 3

Bit 3

5 PCICLK (2 :0) Outp uts

00 Stop

0 1 Running

1 0 Running

1 1 Running

Running

01 Running

Stopped

ICS950812

0542G—08/21/03

FS5FS4FS3FS1FS0 Freq Center

Down 11 12 13 14 11 12 13 14

000000 66.66 Center 0.4 0% 8D 9B 02 18 100 01 10 1 10011 01 1 000 00 010 000 11 00 0

100001 99.99 Center 0.4 0% 8D 9B 02 18 100 01 10 1 10011 01 1 000 00 010 000 11 00 0

200010 199.98 Center 0.40% 8 D 9B 02 18 100 01101 100 1101 1 00000 010 000 11000

300011 133.32 Center 0.40% 8 D 9B 02 18 100 01101 100 1101 1 00000 010 000 11000

400100 66.50 Down -0.48% 8D 9A E F 17 10001101 10011010 11101111 00010111

500101 99.75 Down -0.48% 8D 9A E F 17 10001101 10011010 11101111 00010111

600110 199.50 Down -0. 48% 8D 9A E F 17 10001101 10011010 11101111 00010111

700111 133.00 Down -0. 48% 8D 9A E F 17 10001101 10011010 11101111 00010111

801000 66.34 Down -0.98% 8D 99 E7 17 10001101 10011001 11100111 00010111

901001 99.51 Down -0.98% 8D 99 E7 17 10001101 10011001 11100111 00010111

1001010 199.02 Down -0.98% 8D 99 E7 17 10001101 10011001 11100111 00010111

1101011 132.68 Down -0.98% 8D 99 E7 17 10001101 10011001 11100111 00010111

1201100 66.16 Down -1. 52% 90 EB DD 17 10010000 11101011 11011101 00010111

1301101 99.23 Down -1. 52% 90 EB DD 17 10010000 11101011 11011101 00010111

1401110 198.47 Down -1.52% 90 EB DD 17 10010000 11101011 11011101 00010111

1501111 132.31 Down -1.52% 90 EB DD 17 10010000 11101011 11011101 00010111

1610000 66.66 Cente r 0.5 1% 8D 9B 05 18 100 01 10 1 10011 01 1 000 00 10 1 00011 00 0

1710001 99.99 Cente r 0.5 1% 8D 9B 05 18 100 01 10 1 10011 01 1 000 00 10 1 00011 00 0

1810010 199.98 Cent e r 0. 5 1% 8 D 9 B 05 18 1 0001 101 100 11011 000 0010 1 00011 000

1910011 133.32 Cent e r 0. 5 1% 8 D 9 B 05 18 1 0001 101 100 11011 000 0010 1 00011 000

2010100 66.66 Cente r 0.7 4% 8D 9B 0 B 18 1 00 01 10 1 10011 01 1 000 01 011 000 11 00 0

2110101 99.99 Cente r 0.7 4% 8D 9B 0 B 18 1 00 01 10 1 10011 01 1 000 01 011 000 11 00 0

2210110 199.98 Cent e r 0. 7 4% 8 D 9 B 0B 18 1 0001 101 100 1101 1 0000101 1 00011 000

2310111 133.32 Cent e r 0. 7 4% 8 D 9 B 0B 18 1 0001 101 100 1101 1 0000101 1 00011 000

2411000 70.00 Cente r 0.3 5% 8D B0 35 19 1 00 0110 1 101 10 00 0 00110 10 1 000 11 001

2511001 105.00 Cent e r 0. 3 5% 8 D B0 35 19 100 01101 101 1000 0 00110 101 000 11001

2611010 210.00 Cent e r 0. 3 5% 8 D B0 35 19 100 01101 101 1000 0 00110 101 000 11001

2711011 140.00 Cent e r 0. 3 5% 8 D B0 35 19 100 01101 101 1000 0 00110 101 000 11001

2811100 73.33 Cente r 0.3 4% 89 4A 68 1A 1 00 0100 1 010 01 01 0 01101 00 0 000 11 01 0

2911101 109.99 Cent e r 0. 3 4% 8 9 4A 68 1A 100 01001 010 0101 0 01101 000 00011 010

3011110 219.98 Cent e r 0. 3 4% 8 9 4A 68 1A 100 01001 010 0101 0 01101 000 00011 010

3111111 146.65 Cent e r 0. 3 4% 8 9 4A 68 1A 100 01001 010 0101 0 01101 000 00011 010

I2C read back values in Hex. Bytes I2C read bac k values i n binary .

SpreadCPUADDRESS

Table 8: Byte 11-14 Defaults

Tabl e 7

3V66 (0:1) I2C Cont r ol Tabl e

Note: Activating Byte 5, Bit 4 will allow CPU_STOP# to control stop of pins 33 and 35.

CPU_STOP#

(Pin 53) Byte 5

Bi t 4 3V 6 6 (1:0)

0 0 Running

1 1 Running

0 1 Stopped

1 0 Running

ICS950812

0542G—08/21/03

Absolute Maximum Ratings

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V

Ambient Operating Temperature . . . . . . . . . . 0°C to +90°C

Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Stresses above those listed under

Absolute Maximum Ratings

may cause permanent damage to the device. These ratings

are stress specifications only and functional operation of the device at these or any other conditions above those listed

in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

Elect r i cal Character i st i cs - I nput/Supply / Comm on O ut put Param et ers

TA = 0 - 90°C; S upply V o ltage V DD = 3. 3 V + /-5%

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

I nput High Voltage VIH 2VDD+0.

I nput Low V ol t age V IL VSS-

0.3 0.8 V

IIH VIN = VDD; Inputs with no pull-down

resistors 5.75 mA

IIH VIN = VDD; Inputs with pull-down

resistors 200 µA

IIL1 VIN = 0 V ; I nput s wi t h no pull -up

resistors -5.75 mA

IIL2 VIN = 0 V ; I nput s wi t h pul l-up

resistors -200 µA

IDD3.3OP CL = F ull l oad; Sel ec t @ 100 MHz 233 280 m A

IDD3.3OP CL = F ul l l oad; Select @ 133 M Hz 234 280 m A

IDD3.3PD I RE F =5 mA 20 52 mA

IDD3.3PDHIz 0.289 0.5 mA

I nput Frequenc y F iVDD = 3.3 V 14. 32 MHz

P i n I nduct ance L

in 7nH

CIN Logic Inputs 5 pF

COUT O ut put pi n capac i t ance 6 pF

CINX X 1 & X 2 pins 27 30 45 pF

Cl k Stabil i za ti on1,2 TSTAB From P owerUp or deas sert i on of

P owerDown t o 1st cl ock. 12.1 ms

tPZH,tPZL Out put enable del ay (al l out put s) 1 12 ns

tPHZ,tPLZ Output di sabl e delay (al l output s) 1 12 ns

1Guarant eed by design, not 100% test ed i n produc t i on.

2S ee t i m i ng diagrams for buf f ered and un-buf fered ti m i ng requirements .

Delay1

I nput Capaci t ance1

I nput High Current

I nput Low Current

Operat ing S uppl y Current

P owerdown Current

ICS950812

0542G—08/21/03

Electrical Characteristics - CPU (1V Select) 100MHz

TA = 0 - 90°C; V DD= 3. 3V + /-5% ; CL = 10-20 pF (unless otherwis e speci f i ed)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Current S ource Out put

Impedance Zo1 VO = Vx2500 Ω

A v erage Peri od T PERIOD F i g. 5 10. 00 10. 01 10.20 ns

Output High Vol t age V OH3 0.92 1.45

Output Low V ol t age VOL3 -0.2 0.35

Ri se T i me t r3 VOL = 0. 41V , V OH = 0. 86V (Fi g. 6) 175 390 540 ps

Fall Ti me t f3 VOH = 0.86V V OL = 0.41V (Fi g.6) 175 305 540 ps

Dut y Cyc le dt3 Fig. 5 45 51 55 %

Skew tsk3 VT = 50% 10 100 ps

Jitter, Cycle to cycle t

c-c

c1VT = 50% 40 175 ps

1Guarant eed by des i gn, not 100% tested i n produc t i on.

2 IOWT c an be varied and i s sel ectabl e t hru t he M ULTSEL pi n.

VM eas ured f rom S i ngl e E nded Wavef orm

El ectr i cal Charact eri st i cs - CPU ( 0.7V Select ) 100MHz

TA = 0 - 90°C; V DD= 3.3V + / -5%; (unl ess otherwi s e speci f i ed )

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Current S ourc e Output

Impedance Zo1 VO = Vx3000 Ω

A verage Pe ri od TPERIOD F ig. 1 10. 00 10. 0 1 10. 20 ns

Volta

e Hi

hVHi

h 660 720 850

V ol t a ge Low VLow -150 1 5 150

M ax Vol t a ge Vovs 750 1150

Min Volt a

e Vuds -450 -2

Crossin

Volta

e (abs) V cross(abs) Fi

. 3 2 50 319 550 m V

Cros si ng V ol tage (var) d-V cross Vari at i on of c r os si ng over al l edges (F i g. 4) 12 14 0 m V

Ri se T im e t rVOL = 0.17 5V, VOH = 0. 5 25V (F ig . 3) 175 310 810 ps

Fall Time tfVOH = 0.525V VOL = 0.175V (Fi g. 3) 1 75 300 81 0 ps

Rise T i m e V aria t i on d-t r10 125 ps

Fall Time Variat ion d-t f10 125 ps

Duty Cycl e dt3 M easurem en t f rom di f ferenti al wav efrom (F i g 1) 45 51 55 %

Skew tsk3 VT = 50% 16 10 0 ps

Jitter, Cycle to cycle tjcyc-cyc1VT = 50% (Fi g. 1) 48 175 ps

1Guaranteed by desi gn, not 100% t e s ted i n producti on.

2 IOWT c a n be v ari ed and is sel ectabl e t h ru t he M ULTSE L pin .

S tatist i cal m easurem ent on si ngl e ended si gn al

us ing os c illos c ope math funct ion.

M easurem ent on si ngl e ended si gnal usi ng

absol ute val ue. mV

ICS950812

0542G—08/21/03

El ect r ical Chara ct er i s t i c s - PCI CLK Buf f er ed M ode

TA = 0 - 90°C; VDD = 3.3V +/-5%; CL = 10-30 pF (unless otherwise speci fi ed)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Im pedance RDSP11VO = VDD*(0.5) 12 33 65 Ω

Output Hi gh V ol tage VOH1IOH = -1 mA 2.05 V

Output Low Vol t age VOL1IOL = 1 m A 0. 65 V

Output Hi gh Current IOH1VOH@MIN = 1.0V, VOH@MAX = 3. 135V -33 -28 mA

Output Low Current IOL1VOL @MI N = 1. 95V , V OL @MAX = 0. 4V 26 38 m A

Rise T i me t r11VOL = 0.4 V, V OH = 2.4 V (Fi g. 7) 0. 5 1.4 2. 3 ns

Fall Time t f11VOH = 2. 4 V, V OL = 0. 4 V (F ig. 7) 0. 5 1. 2 2. 3 ns

Duty Cyc le dt11VT = 1.5 V 45 52 55 %

Skew tsk11VT = 1.5 V 35 500 ps

Jitter,cycle to cyc tjcyc-cyc1VT = 1. 5 V (A ddi ti ve) (F i g. 8) 60 120 ps

1Guarant eed by desi gn, not 100% tested i n product i on.

Elect r i cal Char acter i st i cs - CPU (0. 7V Select ) 133. 33M Hz

TA = 0 - 90°C; V DD= 3. 3V + /-5% ; (unless otherwi se s pecifi ed)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Current Source Output

Impedance Zo1 VO = Vx3000 Ω

A v e rage P eri od TPERIO

Fig. 1 7.50 7.51 7.65 ns

V oltage High VHigh 660 718 850

V olt ag e Low VLo w -150 17 1 50

Max V olta

e Vovs 730 1150

M in V ol t age V uds -450 7

Crossi ng Voltag e (abs) V cross(ab s) Fi g . 3 250 34 0 550 m V

Cros sing V ol t age (v ar) d-Vcros s Variat i on of c ros si ng ov er all edges (Fi g. 4) 15 140 m V

Ri se T im e trVOL = 0.175V, V OH = 0.525V (F i g . 3) 175 31 0 810 p s

Fall Time t fVOH = 0. 525V V OL = 0.175V (Fi g. 3) 175 315 810 ps

Ri se T ime Varia ti o n d- tr5125ps

Fall Time Variation d-tf5125ps

Duty Cyc le dt3 M eas urement from diff erenti al wavef rom (Fig 1) 45 51 55 %

Skew tsk3 V

= 50% 14 100 ps

Jitter, Cy cle to cyc le tjcyc-cyc1VT = 50% (Fig. 1) 75 175 ps

1Guarant eed by des i gn, not 100% t est ed in producti on.

2 IOW

c an be v aried and is select abl e t hru the M ULTS E L pin.

S t ati st i cal m eas urement on si ngle ended s i gnal

usi ng o sci l l oscope math functi o n. mV

M e asurem e nt on singl e ende d si gna l using

absolute value. mV

ICS950812

0542G—08/21/03

Elect r i cal Character i st i cs- 3V66 - Buf f ered Mode: 3V66 [ 1:0] 66M Hz_OUT [ 2:0]

TA = 0 - 90°C; V DD= 3. 3V +/-5% ; CL = 10-30 pF (unless ot herwise spec i fied)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Out put I m pedanc e RDSP11VO = VDD*(0.5) 12 33 65 Ω

Outp ut Hi gh V o l tag e VOH1IOH = -1 mA 2. 05 V

Out put Low V ol t age VOL1IOL = 1 m A 0. 65 V

Out put High Current IOH1V OH@MIN = 1. 0 V , V OH@MAX = 3. 135 V -33 -28 m A

Out put Low Current IOL1VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 26 38 mA

Ri se T ime tr11VOL = 0. 4 V , V OH = 2.4 V (Fi g. 7) 0. 5 1.6 2.3 ns

Fall Time tf11VOH = 2.4 V, VOL = 0. 4 V (Fi g. 7) 0. 5 1 2. 3 ns

Duty Cy cle dt11VT = 1.5 V (F ig. 8) 45 52 55 %

Skew tsk11VT = 1. 5 V 3V 66 [ 1:0] 10 250 ps

Jitter tjcyc-cyc1VT = 1.5 V 3V66 [1:0] (Additive) (Fig. 8) 83 120 ps

Skew tsk11VT = 1. 5 V 66M Hz _OUT [2: 0] 169 250 ps

Jitter tjcyc-cyc1VT = 1.5V 66MHz _OUT [2:0]

(F i g. 8) 83 290 ps

1Guarant eed by design, not 100% test ed i n produc t i on.

Elect r i cal Charact eri st i cs - PCI CLK Un-Buff er ed Mode

TA = 0 - 90°C; V DD= 3. 3V + /-5% ; CL = 10-30 pF (unl es s otherwi s e specifi ed)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Out put Im pedanc e RDSP11VO = VDD*(0.5) 12 33 65 Ω

A verage Peri od T PERIOD F ig. 8 30. 00 30. 01 ns

Output High V ol t age VOH1IOH = -1 mA 2.05 V

Output Low Voltage VOL1IOL = 1 m A 0. 65 V

Out put High Current IOH1VOH@MIN = 1.0V , VOH@MAX = 3. 135V -33 -28 m A

Out put Low Current IOL1VOL @ MIN = 1. 95 V , V OL @MAX = 0.4 V 26 38 m A

Ri se T im e tr11VOL = 0.4 V , VOH = 2 .4 V (F i g . 7) 0. 5 1.4 2.3 ns

Fall Time tf11VOH = 2. 4 V, V OL = 0 .4 V (F i g . 7) 0. 5 1 . 2 2.3 ns

Duty Cycle dt11VT = 1. 5 V (F ig. 8) 45 50 55 %

Skew tsk11VT = 1. 5 V 65 500 ps

Jitter,cy cle to cyc tjcyc-cyc1VT = 1. 5 V (Fi g. 8) 101 290 ps

1Guarant eed by des i gn, not 100% t ested in product i on.

ICS950812

0542G—08/21/03

Elect r i cal Charact eri st i cs - VCH, 48MHz DOT, 48MHz, USB

TA = 0 - 90°C; V DD= 3. 3V +/ -5% ; CL = 10-20 pF (unles s otherwi s e specifi ed)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Out put F requenc y F O1 Fig. 8 48 MHz

Output I m pedanc e RDSP11VO = VDD*(0.5) 20 48 70 Ω

Out put High V ol t age VOH1IOH = -1 m A 2.05 V

Output Low Vol t age VOL1IOL = 1 m A 0. 5 V

Output High Current IOH1V OH@MIN = 1. 0 V, V OH@MAX = 3. 135 V -29 -20 mA

Output Low Current IOL1VOL @MIN = 1. 95 V, V OL @MAX = 0.4 V 25 27 mA

48DO T Ri se T ime tr11VOL = 0.4 V, VOH = 2.4 V (F ig. 7) 0.5 0.7 1.15 ns

48DOT Fall Ti me tf11VOH = 2. 4 V, VOL = 0. 4 V (Fi g. 7) 0. 5 0.8 1. 15 ns

VCH 48 USB Rise Time tr11VOL = 0.4 V, VOH = 2.4 V (Fi g. 7) 1 1. 2 2. 3 ns

VCH 48 USB Fall Time tf11VOH = 2. 4 V, V OL = 0. 4 V (Fi g. 7) 1 1. 4 2. 3 ns

48 DO T Duty Cycle dt11VT = 1. 5 V (Fi g. 8) 45 53 55 %

V CH 4 8 USB Duty Cycle dt11VT = 1. 5 V (Fi g. 8) 45 53 55 %

48 DOT Jitter t

c-c

c1VT = 1. 5 V (Fi g. 8) 183 410 ps

USB to DOT Ske w tsk11VT = 1. 5 V (0 OR 180 degrees ) 0. 43 1 ns

VCH Jitter tjcyc-cyc1VT = 1. 5 V (Fi g. 8) 157 410 ps

1Guarant eed by des i gn, not 100% t ested in product i on.

Elect r i cal Charact eristics - 3V66 - Un-Buff ered M ode: 3V66 [5: 0]

TA = 0 - 90°C; V DD= 3. 3V +/ -5% ; CL = 10-30 pF (unles s otherwi se speci f i ed)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Out put I m pedanc e RDSP11VO = VDD*(0.5) 12 33 65 Ω

A verage P eriod TPERIOD F i g. 8 15. 00 15.01 15.30 ns

Outp ut Hi gh V o l tag e VOH1IOH = -1 mA 2.05 V

Out put Low Vol t age VOL1IOL = 1 m A 0. 65 V

Out put High Current IOH1V OH@MIN = 1.0 V, V OH@MAX = 3. 135 V -33 -28 m A

Output Low Current IOL1VOL @MI N = 1. 95 V, V OL @MAX = 0.4 V 26 38 m A

Ri se Ti me tr11VOL = 0.4 V , VOH = 2 .4 V (F i g . 7) 0.5 1.6 2. 3 ns

Fall Time tf11VOH = 2.4 V , VOL = 0 .4 V (F i g . 7) 0.5 1.2 2.3 ns

Duty Cy cle dt11VT = 1.5 V (Fi g. 8) 45 48 55 %

Skew tsk11VT = 1.5 V 40 250 ps

Jitter tjcyc-cyc1VT = 1.5 V (Fi g. 8) 133 290 ps

1Guarant eed by des i gn, not 100% t ested in product i on.

ICS950812

0542G—08/21/03

Elect r i cal Charact eri st i cs - REF ( 2X select )

TA = 0 - 90°C; VDD=3. 3V + /-5% ; CL = 20-40 pF (unl es s ot herwise spec i fi ed)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Frequency F O1 F i g. 8 14. 32 M Hz

Out put Im pedanc e RDSP11VO = VDD*(0.5) Ω

Output High V ol t age VOH1IOH = -1 mA V

Output Low Voltage VOL1IOL = 1 mA V

Out put High Current IOH1V OH@MIN = 1. 0 V, V OH@MAX = 3.135 V mA

Output Low Current IOL1VOL @MIN = 1. 95 V , V OL @MAX = 0.4 V mA

Rise T i m e tr11VOL = 0.4 V, VOH = 2. 4 V (Fig. 7) 1 1. 1 2. 3 ns

Fall Time tf11VOH = 2.4 V, VOL = 0. 4 V (Fi g. 7) 1 0. 9 2. 3 ns

Duty Cyc le dt11VT = 1.5 V 45 53 55 %

Jitter tjcyc-cyc1VT = 1.5 V (F i g . 8) 180 12 00 p s

1Guarant eed by des i gn, not 100% test ed i n produc t i on.

Elect r i cal Charact eri st i cs - REF (1X sel ect )

TA = 0 - 90°C; V DD= 3. 3V +/-5% ; CL = 10-20 pF (unless ot herwise spec i fied)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Out put F requenc y FO1 F ig. 8 14. 32 M Hz

Output I m pedanc e RDSP11VO = VDD*(0.5) 20 48 70 Ω

Out put High V ol t age VOH1IOH = -1 m A 2.05 V

Output Low Vol tage VOL1IOL = 1 mA 0. 45 V

Output High Current IOH1V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -29 -25 m A

Out put Low Current IOL1VOL @MIN = 1.95 V , V OL @MAX = 0.4 V 25 27 mA

Rise T i m e tr11VOL = 0.4 V, VOH = 2.4 V (Fi g. 7) 1 1.1 2. 3 ns

Fall Time tf11VOH = 2.4 V , VOL = 0.4 V (Fi g. 7) 1 1.4 2. 3 ns

Duty Cyc le dt11VT = 1.5 V 45 53 55 %

Jitter tjcyc-cyc1VT = 1. 5 V (Fi g. 8) 180 1200 ps

1Guarant eed by design, not 100% tes ted i n product i on.

ICS950812

0542G—08/21/03

0.000 V

PERIOD

High Duty Cycle % Low Duty Cycle %

+0.35V

CPUCLK#

0.0V

-0.35V

CPUCLK T

RISE

FALL

Figure 1 - Differential (CPUCLK - CPUCLK#) Measurement Points (Tperiod, Duty Cycle, Jitter)

Figure 2 - 0.7V Differential TRise and TFall Measurement Points

ICS950812

0542G—08/21/03

Figure 3 - 0.7V Single Ended Measurement Points for TRise, TFall

= 0.525

CROSS

= 0.175V

CPUCLK#

CPUCLK

FALL

(CPUCLK#)

RISE

(CPUCLK)

Figure 4 - 0.7V VCross Range Measurement Clarification

VCROSS(REL) max

VCROSS(REL) min Total VCROSS Variation

(140mV max)

ICS950812

0542G—08/21/03

Figure 5 - 1.0V Single Ended VCross, VOH and VOL Measurement Points

Figure 6 - 1.0V Single Ended Measurement Points for TRise, TFall

CROSS

Max 0.76V

Max 1.45V

CPUCLK#

CPUCLK

Min 0.92V

CROSS

Min 0.51V

Max 0.35V

Min -0.20V

= 0.86V

CROSS

= 0.41V

CPUCLK#

CPUCLK

FALL

(CPUCLK#)

RISE

(CPUCLK)

ICS950812

0542G—08/21/03

Figure 7 - Measurement Points for TRise, TFall with Lumped Load

1.5V

2.4V

0.4V

Figure 8 - Measurement Points for TPeriod, Duty Cycle and Jitter

1.5V

PERIOD

High Duty Cycle % Low Duty Cycle %

ICS950812

0542G—08/21/03

General I2C serial interface information

How to Write:

•Controller (host) sends a start bit.

• Controller (host) sends the write address D2 (H)

• ICS clock will

acknowledge

• Controller (host) sends the begining byte location = N

• ICS clock will

acknowledge

• Controller (host) sends the data byte count = X

• ICS clock will

acknowledge

• Controller (host) star ts sending

Byte N through

Byte N + X -1

(see Note 2)

• ICS clock will

acknowledge

each byte

one at a time

• Controller (host) sends a Stop bit

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the write address D2 (H)

• ICS clock will

acknowledge

• Controller (host) sends the begining byte

location = N

• ICS clock will

acknowledge

• Controller (host) will send a separate start bit.

• Controller (host) sends the read address D3 (H)

• ICS clock will

acknowledge

• ICS clock will send the data byte count = X

• ICS clock sends

Byte N + X -1

• ICS clock sends

Byte 0 through byte X (if X

(H)

was written to byte 8)

• Controller (host) will need to acknowledge each

byte

• Controllor (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

ICS (Slave/Receiver)

WR ACK

ACK

PstoP bit

X Byte

Index Bloc k Write Operati on

Slave Address D2(H)

Beginning Byte = N

WRite

starT bit

Controller (Host)

Byte N + X - 1

Data Byte Count = X

Beginning Byte N

T starT bit

WR WRite

RT Repeat starT

RD ReaD

Beginning Byte N

Byte N + X - 1

N Not acknowledge

PstoP bit

Slave Address D3(H)

Index Block Read Operation

Slave Address D2(H)

Beginning Byte = N ACK

ACK

Data Byte Count = X

ACK

ICS (Slave/Receiver)

Controller (Host)

X Byte

ACK

ICS950812

0542G—08/21/03

All 3V66 clocks are to be in phase with each other. All 66MHz_OUT clocks are to be in phase with each other. There is

NO phase relationship between the 3V66 clocks and the 66MHz_OUT and PCI clocks. In the case where 3V66_1 is

configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1_VCH and other 3V66 clocks.

The PCI group should lag 3V66 by the standard skew described below as Tpci.

The 66MHz_IN to 66MHz_OUT delay is shown in the figure below and is specified to be within a min and max propagation

value.

Buffered Mode - 3V66[0:1], 66MHz_IN, 66MHz_OUT[0:2] and PCI Phase Relationship

G r o up t o Gr oup Sk ews at Com m on Tr ans it ion Edg es: Buf fer e d M o de

GROUP SYMBOL CONDITIONS MIN TYP MAX UNITS

66MHz_I N 66MHz _O UT1,2 Tpd P ropogat i on delay from

66MHz_IN to 66MHz _OUT (2:0) 2.5 2.9 4.5 ns

66MHz _OUT to PCI1,2 Tpci 66M Hz _O UT (2: 0) leads 33 M Hz

PCICLK 1.5 3.5 ns

1Guarant eed by design, not 100% test ed i n produc t i on.

2500ps T oleranc e

E_PCICLK t o PCICLK Ske w s

GROUP SYMBOL CONDITIONS MIN TYP MAX UNITS

TE_PCI-PCI1 E _PCI CLK1 (pin 11)=0

E _PCI CLK3 (pin 13)= 1 0.3 0.5 0.7 ns

TE_PCI-PCI2 E _PCI CLK1 (pin 11)=1

E _PCI CLK3 (pin 13)= 0 0.8 1.0 1.2 ns

TE_PCI-PCI3 E _PCI CLK1 (pin 11)=1

E _PCI CLK3 (pin 13)= 1 1.3 1.5 1.7 ns

1Guarant eed by design, not 100% test ed i n produc t i on.

E_PCICLK to PCICLK1

66MHz_IN

66MHz_OUT

3V66

Tpd

Tpci

No Relationship

E_PCICLK (3,1) Tepci

PCICLK_F (2:0) PCICLK (6:0)

ICS950812

0542G—08/21/03

All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there

is no defined phase relationship between 3V66_1_VCH and other 3V66 clocks. The PCI group should lag 3V66 by the

standard skew described below as Tpci.

Un-Buffered Mode 3V66 & PCI Phase Relationship

G r o up t o Gr oup Sk ews at Com m on Tr ans i ti o n Edges : Unbuffe r ed Mode

GROUP SYMBOL CONDITIONS MIN TYP MAX UNITS

3V 66 t o P CI 1,2 S3V66-PCI 3V 66 (5: 0) leads 33M Hz P CI 1.5 2. 55 3. 5 ns

1Guarent eed by design, not 100% test ed i n produc t i on.

2500ps T oleranc e

E_PCICLK t o PCICLK Ske w s

GROUP SYMBOL CONDITIONS MIN TYP MAX UNITS

TE_PCI-PCI1 E _PCI CLK1 (pin 11)=0

E _PCI CLK3 (pin 13)= 1 0.3 0.5 0.7 ns

TE_PCI-PCI2 E _PCI CLK1 (pin 11)=1

E _PCI CLK3 (pin 13)= 0 0.8 1.0 1.2 ns

TE_PCI-PCI3 E _PCI CLK1 (pin 11)=1

E _PCI CLK3 (pin 13)= 1 1.3 1.5 1.7 ns

1Guarant eed by design, not 100% test ed i n produc t i on.

E_PCICLK to PCICLK1

3V66 (1:0)

3V66 (4:2)

3V66_5

E_PCICLK (3,1)

PCICLK_F (2:0) PCICLK (6:0) Tpci

Tepci

ICS950812

0542G—08/21/03

The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch

low in their ne xt high to low tr ansition. The PCI_ST OP# setup time tsu is 10 ns, f or transitions to be recognized b y the next

rising edge.

PCI_STOP#

PCI_F[2:0] 33MHz

PCI[6:0] 33MHz

tsu

Asser tion of PCI_STOP# Waveforms

PCI_STOP# - Assertion (transition from logic "1" to logic "0")

CPU_STOP# - Assertion (transition from logic "1" to logic "0")

Assertion of CPU_STOP# Waveforms

CPU_STOP# Functionality

#POTS_UPCTUPCCUPC

1lamroNlamroN

0tluM*feritaolF

The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via

assertion of CPU_ST OP# are to be stopped after their next transition. When the I2C Bit 6 of Byte 1 is programmed to '0'

the final state of the stopped CPU signals is CPU = High and CPU# = Low. There is to be no change to the output drive

current v alues. The CPU will be driv en high with a current v alue equal to (Mult 0 'select') x (Iref), the CPU# signal will not

be driven . When the I2C Bit 6 of Byte 1 is programmed to '1' then final state of the stopped CPU signals is Low , both CPU

and CPU# outputs will not be driven.

CPU_STOP#

CPUCLKT

CPUCLKC

ICS950812

0542G—08/21/03

PD# Functionality

#DPTKLCUPCCKLCUPC66V3TUO_zHM66 F_KLCICP KLCICP KLCICP TOD/BSU zHM84

1lamroNlamroNzHM66NI_zHM66

2/NI_zHM662/NI_zHM66

zHM84

0tluM*feritaolFwoLwoLwoLwoLwoL

CPU_STOP# - De-assertion (transition from logic "0" to logic "1")

De-assertion of CPU_STOP# Waveforms

All CPU outputs that were stopped are to resume normal operation in a glitch free manner . The maximum latency from the

de-asser tion to active outputs is to be defined to be between 2 - 6 CPU clock periods (2 clocks are shown). If the I2C

Bit 6 of Byte 1 is programmed to "1" then the stopped CPU outputs will be driven High within 10 nS of CPU_Stop# de-

assertion.

When PWRDWN# is sampled low by two consecutive rising edges of CPU clock, then all clock outputs except CPU clocks

must be held lo w on their ne xt high to low transitions . When the I2C Bit 6 of Byte 0 is programmed to '0' CPU clocks m ust

be held with the CPU clock pin driven high with a value of 2 x Iref, and CPU# undriven. If Bit 6 of Byte 0 is '1' then both

CPU and CPU# are undriven. Note the example below shows CPU = 133 MHz and Bit 6 of Byte 0 = '0', this diagram and

description is applicable for all valid CPU frequencies 66, 100, 133, 200 MHz.

Due to the state if the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than

one clock cycle to complete.

PD# - Assertion (transition from logic "1" to logic "0")

Power Down Assertion of Waveforms

0ns

PD#

CPUCLKT 100MHz

CPUCLKC 100MHz

3V66MHz

66MHz_IN

66MHz_OUT

PCICLK 33MHz

USB 48MHz

REF 14.318MHz

25ns 50ns

CPU_STOP#

CPUCLKT(2:0)

*CPUCLKT(2:0)TS

CPUCLKC(2:0)

Tdrive_CPU_STOP# <10ns @ 200mV

*Signal TS is CPUCLKT in Tri-State mode

ICS950812

0542G—08/21/03

Power Down De-Assertion Mode

The power-up latency needs to be less than 1.8mS. this is the time from the de-asseration of the powerdown of the ramping

of the pow er supply until the time that stable clocks are output from the cloc k chip . If the I2C Bit 6 of Byte 0 is programmed

to "1" then the stopped CPU outputs will be driven high within 3 nS of PD# de-asseration.

Test Configuration Diagrams

CPU 1.0V Configuration test load board termination

TLA

TLB

REF

=221 Ohms

MULTSEL Pin must be Low

Rs=33 Ohms

Rp=63.4 Ohms

1% Rp=63.4 Ohms

Rdif=475 Ohms

2pF

5% 2pF

CPUCLKT test

point

CPUCLKC test

point

LK408

CPU 0.7V Configuration test load board termination

TLA

TLB

MULTSEL Pin must be High

Rs=33 Ohms

Rp=49.9 Ohms

1% Rp=49.9 Ohms

Rset=475 Ohms

1% 2pF

5% 2pF

CPUCLKT tes

point

CPUCLKC test

point

LK408

ICS950812

0542G—08/21/03

INDEX

AREA

INDEX

AREA

1 2

h x 45°

E1 E



SEATING

PLANE

SEATING

PLANE

-C-

- C -

.10 (.004) C

300 mil SSOP Package

MIN MAX MIN MAX

A 2.41 2.80 .095 .110

A1 0.20 0.40 .008 .016

b 0.20 0.34 .008 .0135

c 0.13 0.25 .005 .010

E 10.03 10.68 .395 .420

E1 7.40 7.60 .291 .299

h 0.38 0.64 .015 .025

L 0.50 1.02 .020 .040

α0° 8° 0° 8°

MIN MAX MIN MAX

56 18.31 18.55 .720 .730

10-0034

SYMBOL I n Mi llim eters In Inch es

COMMO N DIM ENSIO N S COMMO N DIMENSIO NS

SEE VARIATIONS SEE VARIATIONS

0.635 BASIC 0.025 B ASIC

Reference Doc.: JEDEC Publication 95, M O-118

VARIATIONS

SEE VARIATIONS SEE VARIATIONS

ND mm. D (inch)

Ordering Information

ICS950812yFLFT

Example:

Designation for tape and reel packaging

Lead Free (optional)

Package Type

F = SSOP

Revision Designator (will not correlate with datasheet revision)

Device T ype (consists of 3 or 4 digit n umber s)

Prefix

ICS, AV = Standard Device

ICS XXXX y F LF T

ICS950812

0542G—08/21/03

Ordering Information

ICS950812yGLFT

INDEX

AREA

INDEX

AREA

1 2

E1 E



SEATING

PLANE

SEATING

PLANE

-C-

- C -

aaa

6.10 mm. Body, 0.50 mm. pitch TSSOP

(240 mil) (20 mil)

MIN MAX MIN MAX

A--1.20--.047

A1 0.05 0.15 .002 .006

A2 0.80 1.05 .032 .041

b 0.17 0.27 .007 .011

c 0.09 0.20 .0035 .008

E1 6.00 6.20 .236 .244

L 0.45 0.75 .018 .030

α0° 8° 0° 8°

aaa -- 0.10 -- .004

VARIATIONS

MIN MAX MIN MAX

56 13.90 14.10 .547 .555

10-0039

ND m m . D (i nch)

Reference Doc.: JEDEC Publication 95, M O-153

0. 50 B A S IC 0. 020 B A SIC

SEE VARIATIONS SEE VARIATIONS

8. 10 B A S IC 0. 319 B A SIC

SYMBOL In Millimeters In Inches

COMMO N D IM ENSION S COMMO N DIM ENSIO NS

Example:

Designation for tape and reel packaging

Lead Free (optional)

Packag e Ty pe

G = TSSOP

Revision Designator (will not correlate with datasheet revision)

Device T ype (consists of 3 or 4 digit n umber s)

Prefix

ICS, AV = Standard Device

ICS XXXX y G LF T