1
FEATURES DESCRIPTION
APPLICATIONS
FM Tuner
ABB
Codec
(MP3)
TPA2051D3
MonoClass-D
plus
DirectPathTM
8 Dual-Mode
Speaker
Stereo
HeadphoneJack
Mono+
Mono-
Left
(SE)
Right
(SE)
Left
(SE)
Right
(SE)
Bypass+
Bypass-
TPA2051D3
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..................................................................................................................................................... SLOS641A – JUNE 2009 – REVISED OCTOBER 2009
2.9 W/Channel Mono Class-D Audio Subsystem with DirectPath™ Headphone Amplifier &SpeakerGuard™
23
•Mono Class-D Amp: 730 mW into 8 Ωfrom 3.6
The TPA2051D3 is an audio subsystem with a monoV Supply (1% THD)
Class-D power amplifier, a stereo DirectPathheadphone amplifier, and bypass switches. The•Class-D Bypass Switches
DirectPath headphone amplifier eliminates the need•DirectPath™ Stereo Headphone Amplifier
for external dc-blocking output capacitors. The built-in– No Output Capacitors Required
charge pump creates a negative supply voltage forthe headphone amplifier, allowing a 0 V dc bias at the•SpeakerGuard™ Automatic Gain Control
output. The DirectPath headphone amplifier drives(AGC)
25 mW into 16 Ωspeakers from a 4.2 V supply.•One Differential Mono and Two Stereo
The subsystem includes three inputs: A differentialSingle-Ended Inputs
mono input and two stereo single-ended (SE) inputs.•3:1 Input MUX with Mode Control
The stereo inputs are also configurable as differential•32-Step Volume Control for Both Input
mono inputs. Each input channel has an independentChannels
volume control. Seven operating modes provideinput-to-output combinations and shutdown control.•Independent Volume Controls for All Inputs
Operating mode and volume levels are controlled•Independent Shutdown for Headphone and
over a 1.8 V compatible I
2
C interface.Class-D Amplifiers
The TPA2051D3 uses SpeakerGuard
TM
technology to•I
2
C™ Interface
prevent output clipping distortion and excessive•Short-Circuit and Thermal-Overload Protection
power to the speaker and headphones.•Operates from 2.5 V to 5.5 V
The Class-D amplifier includes a bypass mode. This•25-Ball 2,16 mm × 2,11 mm, 0,4 mm pitch
allows the baseband IC (BB) to directly drive the 8 ΩWCSP
speaker. This is useful for dual-mode speaker phonesin voice – only mode.
The Class-D amplifier uses 4.9 mA and the•Smart Phones / Cellular Phones
DirectPath amplifier uses 4.1 mA of typical quiescent•Portable Media Players
current. Total supply current reduces to less than•Portable Gaming
1µA in shutdown.•Multimedia Platforms
The TPA2051D3 is available in a 25-bump 2,16 mm× 2,11 mm, 0,4 mm pitch WCSP with less than0.8 mm height.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2DirectPath, SpeakerGuard are trademarks of Texas Instruments.3I2C is a trademark of NXP B.V. Corporation, Netherlands.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
FUNCTIONAL BLOCK DIAGRAM
+
–
BiasControl
andPop
Suppression
MONO-
Mux
+
Mode
Control
+
SpeakerGuard™
AGC
PVDD
1 Fm
INL1
HPL
HPR
-60 dBto +18 dB
VolumeControl
SDA
-60 dBto +18 dB
VolumeControl
SCL
MONO+
Charge
Pump
2.2 Fm
CPP
CPN
HPVSS PGND
HPVDD
HPVSS
HPVDD
HPVSS
Voice- Mode
Bypass
Voice - Mode
Bypass
INR1
EN
Gain
Select:
0 dB
to
-12 dB
1.5 dB/
step
PVDD
PGND
PWM H-
Bridge
VREF
I2CInterface
INL2 -60 dBto +18 dB
VolumeControl
INR2
DVDD
Gain
Select:
+12 dB
+6 dB
OUT-
OUT+
BYPASS+
BYPASS-
HPVDD
AGND
AVDD
1 Fm
1 Fm2.2 Fm
TPA2051D3
SLOS641A – JUNE 2009 – REVISED OCTOBER 2009 .....................................................................................................................................................
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
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DEVICE PINOUT
D1 D2 D3 D4
C1 C2 C3 C4
B1 B2 B3 B4
AVDD
MONO–
MONO+
BYPASS+
SDA
INL2
SCL
DVDD
EN
INL1
A1 A3 A4
OUT+ PVDD PGND OUT–
A2
BYPASS–
D5
C5
B5
CPP
HPL
A5
CPN
HPVDD HPVSS
E1 E2 E3 E4
INR2 INR1 VREF
E5
AGND HPR
TPA2051D3
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..................................................................................................................................................... SLOS641A – JUNE 2009 – REVISED OCTOBER 2009
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TPA2051D3
SLOS641A – JUNE 2009 – REVISED OCTOBER 2009 .....................................................................................................................................................
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PIN FUNCTIONS
PIN INPUT/ OUTPUT/
POWER
DESCRIPTIONBALLNAME
(I/O/P)WCSP
OUT+ A1 O Speaker positive output; connect to + terminal of loudspeakerPVDD A2 P Supply for Class-D amplifier. Connect to voltage supplyPGND A3 P Ground for Class-D amplifier; connect to GND directly or to the groundplaneOUT – A4 O Speaker negative output; connect to – terminal of loudspeakerCPN A5 P Charge pump flying capacitor negative terminal. Connect negative side ofcapacitor between CPP and CPNAVDD B1 P Connect to voltage supplyBYPASS+ B2 I Bypass Mode positive inputBYPASS – B3 I Bypass Mode negative inputDVDD B4 P Connect to I2C bus supply voltageCPP B5 P Charge pump flying capacitor positive terminal. Connect positive side ofcapacitor between CPP and CPNMONO – C1 I Mono negative differential inputSDA C2 I/O I
2
C data inputSCL C3 I I
2
C clock inputEN C4 I Master shutdownHPL C5 O Headphone left channel outputMONO+ D1 I Mono positive differential inputINL2 D2 I Input channel 2 left inputINL1 D3 I Input channel 1 left inputHPVDD D4 O Headphone reference voltage. Connect to 2.2 µF capacitor to groundHPVSS D5 P Negative supply generated by the charge pump. Connect a 2.2 µF cap toground to reduce voltage rippleINR2 E1 I Input channel 2 right inputINR1 E2 I Input channel 1 right inputVREF E3 I Reference voltage. Connect to 1 µF capacitor to groundAGND E4 P Connect to ground planeHPR E5 O Headphone right channel output
ORDERING INFORMATION
T
A
PACKAGED DEVICES
(1)
PART NUMBER
(2)
SYMBOL
TPA2051D3YFFR TPA2051– 40 ° C to 85 ° C 25-ball WSCP
TPA2051D3YFFT TPA2051
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIWeb site at www.ti.com .(2) The YFF package is only available taped and reeled. The suffix “ R ” indicates a reel of 3000, the suffix “ T ” indicates a reel of 250.
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
TPA2051D3
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..................................................................................................................................................... SLOS641A – JUNE 2009 – REVISED OCTOBER 2009
over operating free-air temperature range, T
A
= 25 ° C (unless otherwise noted)
VALUE / UNIT
Supply voltage, AVDD, PVDD – 0.3 V to 6.0 VI
2
C Supply Voltage DVDD – 0.3 to 3.6 VV
I
Input Voltage – 0.3 V to AVDD + 0.3 VOutput Continuous total power dissipation See Dissipation Rating TableT
A
Operating free-air temperature range – 40 ° C to 85 ° CT
J
Operating junction temperature range – 40 ° C to 150 ° CT
stg
Storage temperature range – 65 ° C to 85 ° C
T
A
< 25 ° C OPERATING FACTOR T
A
= 70 ° C T
A
= 85 ° CPACKAGE
POWER RATING ABOVE T
A
= 25 ° C POWER RATING POWER RATING
YFF (WCSP) 845 mW 6.757 mW/ ° C 540 mW 440 mW
MIN MAX UNIT
Supply voltage, AVDD, PVDD 2.5 5.5 VI2C supply voltage, DVDD 1.7 3.3 VV
IH
High-level input voltage SDA, SCL, EN, DVDD = 1.8 V 1.3 VSDA, SCL, EN, DVDD = 3.3 V 3.0 VV
IL
Low-level input voltage SDA, SCL, EN, DVDD = 1.8 V 0.3 VSDA, SCL, EN, DVDD = 3.3 V 0.3 VT
A
Operating free-air temperature – 40 85 ° C
over operating free-air temperature range, T
A
= 25 ° C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power supply rejection ratio (Class-D amplifier) AVDD = PVDD = 2.5 V to 5.5 V, Single-ended 60 75 dBmodesPower supply rejection ratio (headphone AVDD = PVDD = 2.5 V to 5.5 V, Single-ended 75 85 dBamplifiers) modesHigh-level input current (SDA, SCL, EN) 1 µALow-level input current (SDA, SCL, EN) 1 µAAVDD = PVDD = 2.5 V, Class-D and headphone 6.3 7.5 mAamplifiers active, no loadAVDD = PVDD = 3.6 V, Class-D and headphone 7.1 8.5 mAamplifiers active, no loadAVDD = PVDD = 3.6 V, headphone active, 4.1 5.25 mASupply current
Class-D deactivated, no loadAVDD = PVDD = 3.6 V, Class-D active, 4.9 6.0 mAheadphone deactivated, no loadAVDD = PVDD = 2.5 V to 5.5 V, Full shutdown 0.2 1 µAmode
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TIMING REQUIREMENTS
SCL
SDA
tw(H) tw(L)
tsu1 th1
SCL
SDA
th2 t(buf)
tsu2 tsu3
StartCondition StopCondition
TPA2051D3
SLOS641A – JUNE 2009 – REVISED OCTOBER 2009 .....................................................................................................................................................
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For I
2
C Interface Signals and voltage power up sequence, over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
SCL
Frequency, SCL No wait states 400 kHzt
W(H)
Pulse duration, SCL high 0.6 µst
W(L)
Pulse duration, SCL low 1.3 µst
su1
Setup time, SDA to SCL 100 nst
h1
Hold time, SCL to SDA 10 nst
(buf)
Bus free time between stop and start condition 1.3 µst
su2
Setup time, SCL to start condition 0.6 µst
h2
Hold time, start condition to SCL 0.6 µst
su3
Setup time, SCL to stop condition 0.6 µst
pws
Power up delay time, AVDD and PVDD to DVDD 100 µspower up sequencet
ens
Enable pin wait time 1000 µst
SWS
SWS enable wait time 250 µst
EN
Spk_Enable, HPL_Enable, HPR_Enable wait time 250 µs
Figure 1. SCL and SDA Timing
Figure 2. Start and Stop Conditions Timing
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EN
DVDD
PVDD
AVDD
tpws
tens
Other Write
or ttSWS EN
SDA
SWS or EN Write
TPA2051D3
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..................................................................................................................................................... SLOS641A – JUNE 2009 – REVISED OCTOBER 2009
Figure 3. Supply Voltage Timing
Figure 4. I
2
C SWS and Enable Register Timing
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OPERATING CHARACTERISTICS
TPA2051D3
SLOS641A – JUNE 2009 – REVISED OCTOBER 2009 .....................................................................................................................................................
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V
DD
= 3.6 V, T
A
= 25 ° C, Input gain = 0 dB, Class-D gain = +6 dB, Headphone gain = 0 dB, R
SPEAKER
= 8 Ω, R
HEADPHONES
=16 Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CLASS-D POWER AMPLIFIER
THD = 1%, AVDD = PVDD = 4.2 V, 1000f = 1 kHzTHD = 1%, AVDD = PVDD = 3.6 V, 730f = 1 kHzP
O
Speaker output power mWTHD = 10%, AVDD = PVDD = 3.6 V, 900f = 1 kHzTHD = 10%, AVDD = PVDD = 5.0 V, 2900f = 1 kHz, R
SPEAKER
= 4 Ω
SNR Signal-to-noise ratio P
O
= 600 mW 97 dBE
n
Noise output voltage A-weighted 21 µV
RMS
P
O
= 400 mW, f = 1 kHz 0.06%Total harmonic distortion plusTHD+N
noise
(1)
P
O
= 1 W , AVDD = PVDD = 5.0 V, f = 1 kHz 0.04%200 mV
pp
ripple, f = 217 Hz 77 dBAC PSRR AC-Power supply rejection ratio
200 mV
pp
ripple, f = 10 kHz 68 dBThreshold 150 ° CThermal shutdown
Hysteresis 15 ° COutput impedance in shutdown 2 k Ω
HEADPHONE AMPLIFIER
P
O
Headphone output power
(2)
THD = 1%, AVDD = PVDD = 3.0 V, 25 mWf = 1 kHz, in-phaseV
OS
Output Offset Voltage Volume at 0 dB ± 0.6 mVOutput impedance in shutdown 25 Ω
SNR Signal-to-noise ratio P
O
= 20 mW 97 dBE
n
Noise output voltage A-weighted 7.5 µV
RMS
P
O
= 20 mW, f = 1 kHz 0.02%Total harmonic distortion plusTHD+N
noise
(1)
P
O
= 20 mW into 32 Ω, f = 1 kHz 0.01%200 mV
pp
ripple, f = 217 Hz 95 dBAC PSRR AC-Power supply rejection ratio
200 mV
pp
ripple, f = 10 kHz 84 dBf
OSC
Charge pump switching frequency 1200 kHz
ΔA
V
Gain matching Between Left and Right channels 0.1 dBHBM Electrostatic discharge HPLEFT and HPRIGHT ± 8 kV
BYPASS MODE
R
ON
Bypass switch on impedance AVDD = PVDD = 3 V, VDIFF = 2 V
P-P
, 1.1 4.5 ΩVCM = AVDD/2, Temp = 25 ° CTHD Total harmonic distortion V
DIFF
= 2 V
P-P
, f = 1 kHz, R
SERIES
= 10 Ω0.02%Off attenuation 80 dB
INPUT SECTION
R
IN
Input impedance (per input pin) Volume Control gain = 18 dB 4.0 5.0 k Ω
V
IN_MAX
Maximum differential input signal Volume Control gain = – 66 dB 5.2 V
P – Pswing
Volume Control gain = 0 dB 2.6Volume Control gain = 18 dB 0.22Gain matching 0.1 dBCrosstalk GAIN = 0 dB, f = 1 kHz 60 dBStart-up time from shutdown 8 ms
(1) A-weighted
(2) Per output channel
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TYPICAL CHARACTERISTICS
f − Frequency − Hz
THD+N − Total Harmonic Distortion + Noise − %
20 100 1k 10k 20k
0.001
0.01
0.1
1
10 VDD = 2.5 V, PO = 150 mW
VDD = 3.6 V, PO = 400 mW
VDD = 5.0 V, PO = 800 mW
Mono Input Mode
RL = 8 Ω + 33 µH
Total Gain = 6 dB
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
1m 10m 100m 1 2
0.01
0.1
1
10
100 VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
Mono Input Mode
RL = 8 Ω + 33 µH
Total Gain = 6 dB
f − Frequency − Hz
THD+N − Total Harmonic Distortion + Noise − %
20 100 1k 10k 20k
0.001
0.01
0.1
1
10 VDD = 2.5 V, PO = 5 mW
VDD = 3.6 V, PO = 10 mW
VDD = 5.0 V, PO = 20 mW
Stereo SE Input 1 Mode
RL = 16 Ω
Total Gain = 0 dB
Out of Phase
f − Frequency − Hz
THD+N − Total Harmonic Distortion + Noise − %
20 100 1k 10k 20k
0.001
0.01
0.1
1
10 VDD = 2.5 V, PO = 5 mW
VDD = 3.6 V, PO = 10 mW
VDD = 5.0 V, PO = 20 mW
Stereo SE Input 1 Mode
RL = 32 Ω
Total Gain = 0 dB
Out of Phase
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
100u 1m 10m 50m
0.01
0.1
1
10
100 VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
Stereo SE Input 1 Mode
RL = 16 Ω
Total Gain = 0 dB
In−Phase
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
100u 1m 10m 50m
0.01
0.1
1
10
100 VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
Stereo SE Input 1 Mode
RL = 16 Ω
Total Gain = 0 dB
Out of Phase
TPA2051D3
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..................................................................................................................................................... SLOS641A – JUNE 2009 – REVISED OCTOBER 2009
AVDD = PVDD = 3.6 V, C
I
= C
VREF
= C
F
= 1 µF, C
HPVDD
= C
HPVSS
= 2.2 µF, T
A
= 25 ° C, unless otherwise specified
TOTAL HARMONIC DISTORTION + NOISE (SP) TOTAL HARMONIC DISTORTION + NOISE (SP)vs vsFREQUENCY OUTPUT POWER
Figure 5. Figure 6.
TOTAL HARMONIC DISTORTION + NOISE (HP) TOTAL HARMONIC DISTORTION + NOISE (HP)vs vsFREQUENCY FREQUENCY
Figure 7. Figure 8.
TOTAL HARMONIC DISTORTION + NOISE (HP) TOTAL HARMONIC DISTORTION + NOISE (HP)vs vsOUTPUT POWER OUTPUT POWER
Figure 9. Figure 10.
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PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
100u 1m 10m 50m
0.01
0.1
1
10
100 VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
Stereo SE Input 1 Mode
RL = 32 Ω
Total Gain = 0 dB
In−Phase
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
100u 1m 10m 50m
0.01
0.1
1
10
100 VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
Stereo SE Input 1 Mode
RL = 32 Ω
Total Gain = 0 dB
Out of Phase
f − Frequency − Hz
PSRR − Power Supply Rejection Ratio − dB
20 100 1k 10k 20k
−100
−80
−60
−40
−20
0VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
RL = 8 Ω + 33 µH
Mono Input Mode
Input Level = 0.2 Vpp
Total Gain = 0 dB
f − Frequency − Hz
PSRR − Power Supply Rejection Ratio − dB
20 100 1k 10k 20k
−100
−80
−60
−40
−20
0VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
RL = 32 Ω
Stereo SE Input 1 Mode
Input Level = 0.2 Vpp
Total Gain = 0 dB
PO − Total Output Power − W
IDD − Supply Current − A
1u 10u 100u 1m 10m 40m
1m
10m
100m
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
Stereo SE Input 1 Mode
RL = 16 Ω
Total Gain = 0 dB
Out of Phase
PO − Total Output Power − W
IDD − Supply Current − A
1u 10u 100u 1m 10m 40m
1m
10m
100m
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
Stereo SE Input 1 Mode
RL = 32 Ω
Total Gain = 0 dB
Out of Phase
TPA2051D3
SLOS641A – JUNE 2009 – REVISED OCTOBER 2009 .....................................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)AVDD = PVDD = 3.6 V, C
I
= C
VREF
= C
F
= 1 µF, C
HPVDD
= C
HPVSS
= 2.2 µF, T
A
= 25 ° C, unless otherwise specified
TOTAL HARMONIC DISTORTION + NOISE (HP) TOTAL HARMONIC DISTORTION + NOISE (HP)vs vsOUTPUT POWER OUTPUT POWER
Figure 11. Figure 12.
POWER SUPPLY REJECTION RATIO (SP) POWER SUPPLY REJECTION RATIO (HP)vs vsFREQUENCY FREQUENCY
Figure 13. Figure 14.
SUPPLY CURRENT (HP) SUPPLY CURRENT (HP)vs vsTOTAL OUTPUT POWER TOTAL OUTPUT POWER
Figure 15. Figure 16.
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PO − Total Output Power − W
PD − Total Power Dissipation − W
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
0
20m
40m
60m
80m
100m
120m
140m
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
Mono Input Mode
RL = 8 Ω + 33 µH
Total Gain = 6 dB
PO − Total Output Power − W
IDD − Supply Current − A
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
0
50m
100m
150m
200m
250m
300m
350m
400m
450m
500m
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
Mono Input Mode
RL = 8 Ω + 33 µH
Total Gain = 6 dB
PO − Output Power − W
η − Efficiency − %
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
0
10
20
30
40
50
60
70
80
90
100
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
Mono Input Mode
RL = 8 Ω + 33 µH
Total Gain = 6 dB
VDD − Supply Voltage − V
PO − Output Power − W
2.5 3.0 3.5 4.0 4.5 5.0 5.5
0.0
0.4
0.8
1.2
1.6
2.0
2.4
THD + N = 10%
THD + N = 1%
Mono Input Mode
RL = 8 Ω + 33 µH
Total Gain = 6 dB
VDD − Supply Voltage − V
PO − Output Power Per Channel − W
2.5 3.0 3.5 4.0 4.5 5.0 5.5
0
10m
20m
30m
40m
50m
THD + N = 10%
THD + N = 1%
Stereo SE Input 1 Mode
RL = 16 Ω
Total Gain = 0 dB
Out of Phase
VDD − Supply Voltage − V
PO − Output Power Per Channel − W
2.5 3.0 3.5 4.0 4.5 5.0 5.5
0
10m
20m
30m
40m
50m
THD + N = 10%
THD + N = 1%
Stereo SE Input 1 Mode
RL = 32 Ω
Total Gain = 0 dB
Out of Phase
TPA2051D3
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..................................................................................................................................................... SLOS641A – JUNE 2009 – REVISED OCTOBER 2009
TYPICAL CHARACTERISTICS (continued)AVDD = PVDD = 3.6 V, C
I
= C
VREF
= C
F
= 1 µF, C
HPVDD
= C
HPVSS
= 2.2 µF, T
A
= 25 ° C, unless otherwise specified
TOTAL POWER DISSIPATION (SP) SUPPLY CURRENT (SP)vs vsTOTAL OUTPUT POWER TOTAL OUTPUT POWER
Figure 17. Figure 18.
EFFICIENCY (SP) OUTPUT POWER (SP)vs vsOUTPUT POWER SUPPLY VOLTAGE
Figure 19. Figure 20.
OUTPUT POWER PER CHANNEL (HP) OUTPUT POWER PER CHANNEL (HP)vs vsSUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 21. Figure 22.
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f − Frequency − Hz
Crosstalk − dB
20 100 1k 10k 20k
−160
−140
−120
−100
−80
−60
−40
−20
0Mono Input Mode
Speaker RL = 8 Ω + 33 µH
Headphone RL = 32 Ω
PO = 250 mW
f − Frequency − Hz
CMRR − Common−Mode Rejection Ratio − dB
20 100 1k 10k 20k
−100
−80
−60
−40
−20
0RL = 8 Ω + 33 µH
VDD = 3.6 V
Input Level = 0.2 Vpp
Total Gain = 6 dB
Volume Control Gain − dB
Differential Input Impedance − Ω
−66 −60 −54 −48 −42 −36 −30 −24 −18 −12 −6 0 6 12 18
10k
20k
30k
40k
50k
60k
70k
80k
90k
100k VDD = 3.6 V
Volume Control Gain − dB
Single−Ended Input Impedance − Ω
−66 −60 −54 −48 −42 −36 −30 −24 −18 −12 −6 0 6 12 18
5k
10k
15k
20k
25k
30k
35k
40k
45k
50k VDD = 3.6 V
VDD − Supply Voltage − V
IDD − Supply Current − mA
2.5 3.0 3.5 4.0 4.5 5.0 5.5
0
5
10
15
20
25 SPKR Enabled Only
HP Enabled Only
SPKR and HP Enabled
SPKR RL = 8 Ω + 33 µH
HP RL = 32 Ω
SPKR Total Gain = 6 dB
HP Total Gain = 0 dB
Input Level − dBV
Output Level − dBV
−20 −15 −10 −5 0 5
−6
−4
−2
0
2
4
6
8
10
12
Limiter = 1.3 V
Limiter = 1.65 V
Limiter = 2.1 V
Limiter = 2.6 V
Mono Input Mode
RL = 8 Ω + 33 µH
VDD = 5 V
Total Gain = 16 dB
TPA2051D3
SLOS641A – JUNE 2009 – REVISED OCTOBER 2009 .....................................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)AVDD = PVDD = 3.6 V, C
I
= C
VREF
= C
F
= 1 µF, C
HPVDD
= C
HPVSS
= 2.2 µF, T
A
= 25 ° C, unless otherwise specified
SPEAKER TO HEADPHONE CROSSTALK COMMON-MODE REJECTION RATIO (SP)vs vsFREQUENCY FREQUENCY
Figure 23. Figure 24.
DIFFERENTIAL INPUT IMPEDANCE SINGLE-ENDED INPUT IMPEDANCEvs vsVOLUME CONTROL GAIN VOLUME CONTROL GAIN
Figure 25. Figure 26.
SUPPLY CURRENT SPEAKER LIMITER OUTPUT LEVELvs vsSUPPLY VOLTAGE INPUT LEVEL
Figure 27. Figure 28.
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t − Time − s
V − Voltage − V
0 2m 4m 6m 8m 10m 12m 14m 16m 18m 20m
−1.5
−1.0
−0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5 Speaker Output
SDA
Startup Time = 7.8 ms
t − Time − s
V − Voltage − V
0 1m 2m 3m 4m 5m
−1.5
−1.0
−0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5 Speaker Output
SDA
t − Time − s
V − Voltage − V
0 2m 4m 6m 8m 10m 12m 14m 16m 18m 20m
−1.0
−0.5
0.0
0.5
1.0
1.5
2.0 HP Output
SDA
Startup Time = 7.4 ms
t − Time − s
V − Voltage − V
0 1m 2m 3m 4m 5m
−1.0
−0.5
0.0
0.5
1.0
1.5
2.0 HP Output
SDA
TPA2051D3
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..................................................................................................................................................... SLOS641A – JUNE 2009 – REVISED OCTOBER 2009
TYPICAL CHARACTERISTICS (continued)AVDD = PVDD = 3.6 V, C
I
= C
VREF
= C
F
= 1 µF, C
HPVDD
= C
HPVSS
= 2.2 µF, T
A
= 25 ° C, unless otherwise specified
SPEAKER OUTPUT - STARTUP SPEAKER OUTPUT - SHUTDOWNvs vsTIME TIME
Figure 29. Figure 30.
HEADPHONE OUTPUT - STARTUP HEADPHONE OUTPUT - SHUTDOWNvs vsTIME TIME
Figure 31. Figure 32.
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APPLICATION CIRCUIT
GENERAL I
2
C OPERATION
Register(N)
8-BitDatafor 8-BitDatafor
Register(N+1)
TPA2051D3
SLOS641A – JUNE 2009 – REVISED OCTOBER 2009 .....................................................................................................................................................
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Figure 33. Typical Apps Configuration with Differential Input Signals
The I
2
C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in asystem. The bus transfers data serially one bit at a time. The address and data 8-bit bytes are transferred mostsignificant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving devicewith an acknowledge bit. Each transfer operation begins with the master device driving a start condition on thebus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the dataterminal (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition onSDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit transitions bust occur withinthe low time of the clock period. Figure 34 shows a typical sequence. The master generates the 7-bit slaveaddress and the read/write (R/W) bit to open communication with another device and then waits for anacknowledge condition. The TPA2051D3 holds SDA low during the acknowledge clock period to indicateacknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device isaddressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signalsvia a bidirectional bus using a wired-AND connection.
The TPA2051D3 operates as an I
2
C slave. The I
2
C voltage can not exceed the TPA2051D3 supply voltage,AVDD.
An external pull-up resistor must be used for the SDA and SCL signals to set the logic high level for the bus.When the bus level is 3.3 V, use pull-up resistors between 660 Ωand 1.2 k Ω.
Figure 34. Typical I
2
C Sequence
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SINGLE-AND MULTIPLE-BYTE TRANSFERS
SINGLE-BYTE WRITE
A6 A5 A4 A3 A2 A1 A0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
I2CDevice Addressand
Read/WriteBit
Register DataByte
MULTIPLE-BYTE WRITE AND INCREMENTAL MULTIPLE-BYTE WRITE
Register
SINGLE-BYTE READ
TPA2051D3
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..................................................................................................................................................... SLOS641A – JUNE 2009 – REVISED OCTOBER 2009
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the lastword transfers, the master generates a stop condition to release the bus. A generic data transfer sequence isshown in Figure 34 .
The serial control interface supports both single-byte and multi-byte read/write operations for all registers.
During multiple-byte read operations, the TPA2051D3 responds with data, a byte at a time, starting at theregister assigned, as long as the master device continues to respond with acknowledges.
The TPA2051D3 supports sequential I
2
C addressing. For write transactions, if a register is issued followed bydata for that register and all the remaining registers that follow, a sequential I
2
C write transaction has takenplace. For I
2
C sequential write transactions, the register issued then serves as the starting point, and the amountof data subsequently transmitted, before a stop or start is transmitted, determines to how many registers arewritten.
As shown in Figure 35 , a single-byte data write transfer begins with the master device transmitting a startcondition followed by the I
2
C device address and the read/write bit. The read/write bit determines the direction ofthe data transfer. For a write data transfer, the read/write bit must be set to 0. After receiving the correct I
2
Cdevice address and the read/write bit, the TPA2051D3 responds with an acknowledge bit. Next, the mastertransmits the register byte corresponding to the TPA2051D3 internal memory address being accessed. Afterreceiving the register byte, the TPA2051D3 again responds with an acknowledge bit. Finally, the master devicetransmits a stop condition to complete the single-byte data write transfer.
Figure 35. Single-Byte Write Transfer
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytesare transmitted by the master device to the TPA2051D3 as shown in Figure 36 . After receiving each data byte,the TPA2051D3 responds with an acknowledge bit.
Figure 36. Multiple-Byte Write Transfer
As shown in Figure 37 , a single-byte data read transfer begins with the master device transmitting a startcondition followed by the I
2
C device address and the read/write bit. For the data read transfer, both a writefollowed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memoryaddress to be read. As a result, the read/write bit is set to a 0.
After receiving the TPA2051D3 address and the read/write bit, the TPA2051D3 responds with an acknowledge
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A6 A5 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A5 A0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
I2CDevice Addressand
Read/WriteBit
Register DataByte
D7 D6 D1 D0 ACK
I2CDevice Addressand
Read/WriteBit
Not
Acknowledge
R/WA1 A1
RepeatStart
Condition
MULTIPLE-BYTE READ
A6 A0 ACK
Acknowledge
I2CDevice Addressand
Read/WriteBit
R/WA6 A0 R/W ACK A0 ACK D7 D0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
LastDataByte
ACK
FirstDataByte
RepeatStart
Condition Not
Acknowledge
I2CDevice Addressand
Read/WriteBit
Register OtherDataBytes
A7 A6 A5 D7 D0 ACK
Acknowledge
D7 D0
REGISTER MAPS
TPA2051D3
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bit. The master then sends the internal memory address byte, after which the TPA2051D3 issues anacknowledge bit. The master device transmits another start condition followed by the TPA2051D3 address andthe read/write bit again. This time, the read/write bit is set to 1, indicating a read transfer. Next, the TPA2051D3transmits the data byte from the memory address being read. After receiving the data byte, the master devicetransmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer.
Figure 37. Single-Byte Read Transfer
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytesare transmitted by the TPA2051D3 to the master device as shown in Figure 38 . With the exception of the lastdata byte, the master device responds with an acknowledge bit after receiving each data byte.
Figure 38. Multiple-Byte Read Transfer
REGISTER BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
0 Version[3] Version[2] Version[1] Version[0] Reserved Reserved Spk_Fault Thermal1 LIM_SEL LIM_EN Reserved SWS HPL_Enable HPR_Enable Spk_Enable VM_Bypass2 ATK_time[4] ATK_time[3] ATK_time[2] ATK_time[1] ATK_time[0] LIMSPK[2] LIMSPK[1] LIMSPK[0]3 REL_time[4] REL_time[3] REL_time[2] REL_time[1] REL_time[0] LIMHP[2] LIMHP[1] LIMHP[0]4 Mode[2] Mode[1] Mode[0] MON_Vol[4] MON_Vol[3] MON_Vol[2] MON_Vol[1] MON_Vol[0]5 SPK_Gain HP_0dB Reserved ST1_Vol[4] ST1_Vol[3] ST1_Vol[2] ST1_Vol[1] ST1_Vol[0]6 HP_Gain[2] HP_Gain[1] HP_Gain[0] ST2_Vol[4] ST2_Vol[3] ST2_Vol[2] ST2_Vol[1] ST2_Vol[0]
Bits labeled “ Reserved ” are reserved for future enhancements. They may not be written to as it may change thefunction of the device. If read, these bits may assume any value.
The TPA2051D3 I2C address is 0xE0 (binary 11100000) for writing and 0xE1 (binary 11100001) for reading.Refer to the General I2C Operation section for more details
Fault Register (Address: 0)
BIT 76543210
Function Version[3] Version[2] Version[1] Version[0] Reserved Reserved Spk_Fault ThermalReset Value 0 0 0 0 0 0 0 0
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..................................................................................................................................................... SLOS641A – JUNE 2009 – REVISED OCTOBER 2009
Version[3:0] Read-only bits that indicate the silicon revision.Spk_Fault Logic high indicates an output over-current event has occurred on the Class-D channel output.This bit is clear-on-write.Thermal Logic high indicates thermal shutdown activated. Bit automatically clears when the thermalcondition lowers past the hysteresis threshold.Reserved These bits are reserved for future enhancements. If read these bits may assume any value.
Amplifier Control Register (Address: 1)
BIT 76543210
Function LIM_SEL LIM_EN Reserved SWS HPL_Enable HPR_Enable Spk_Enable VM_BypassReset Value 1 0 0 0 0 0 0 1
LIM_SEL Selects which limiter register value is used. Set to logic high for LIMSPK[2:0]. Set to logic lowfor LIMHP[2:0]. Default is 1 (speaker limiter selected).LIM_EN AGC limiter function enable. Set to logic high to enable the limiter function.SWS Software Shutdown Mode. Set to logic high to deactivate the amplifier.HPL_Enable Headphone left channel enable. Set to logic low to deactivate left channel.HPR_Enable Headphone right channel enable. Set to logic low to deactivate right channel.Spk_Enable Class-D power amplifier enable. Set to logic low to deactivate speaker Class-D power amplifier.VM_Bypass Speaker bypass mode. Set to logic low to deactivate speaker bypass. Setting VM_Bypass to 1forces SPK_Enable to 0 and bypasses the volume control. The headphone amplifiers can stillbe enabled/disabled and the volume control for inputs 1 and 2 are still active.Reserved These bits are reserved for future enhancements. If read these bits may assume any value.
Attack Time and Speaker Limiter Control Register (Address: 2)
BIT 76543210
Function ATK_time[4] ATK_time[3] ATK_time[2] ATK_time[1] ATK_time[0] LIMSPK[2] LIMSPK[1] LIMSPK[0]Reset Value 0 0 1 0 0 1 0 1
ATK_time [4:0] Five bit attack time (gain decrease) control for the AGC. 00000 sets to the lowest attacktime. Default setting on power up is 00100 (6.4 ms / step)LIMSPK[2:0] Three-bit limiter level control for the speaker amplifier. 000 sets to the lowest limiter level.Default setting on power-up is 101 (4.2 Vpeak)
Release Time and Headphone Limiter Level Control Register (Address: 3)
BIT 76543210
Function REL_time[4] REL_time[3] REL_time[2] REL_time[1] REL_time[0] LIMHP[2] LIMHP[1] LIMHP[0]Reset Value 0 1 0 1 0 1 1 1
REL _time [4:0] Five bit release time (gain increase) control for the AGC. 00000 sets to the lowest releasetime. Default setting on power up is 01010 (451 ms / step)LIMHP [2:0] Three-bit limiter level control for the headphone amplifier. 000 sets to the lowest limiter level.Default setting on power-up is 111 (highest setting)
Mode / Mono Input Volume Control Register (Address: 4)
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BIT 76543210
Function Mode[2] Mode[1] Mode[0] MON_Vol[4] MON_Vol[3] MON_Vol[2] MON_Vol[1] MON_Vol[0]Reset Value 0 0 0 0 1 1 0 1
Mode[2:0] Sets mux output mode. Refer to Modes of Operation section for details. Default mode is 000(Mono Input selected) on power-up.MON_Vol[4:0] Five-bit volume control for Mono input mode (mode 0). 11111 sets device to its highest channelgain; 00000 sets device to its lowest channel gain. Default setting on power-up is 01101 (0 dB).
Stereo Input 1 / Output Gain Control Register (Address: 5)
BIT 76543210
Function SPK_Gain HP_0dB Reserved ST1_Vol[4] ST1_Vol[3] ST1_Vol[2] ST1_Vol[1] ST1_Vol[0]Reset Value 0 0 0 0 1 1 0 1
SPK_Gain Class-D speaker amplifier gain. Set to logic high for 12 dB Class-D gain. Set to logic low for6 dB Class-D gain.HP_0dB Set bit to 1 to set HP amp gain to 0 dB regardless of HP_Gain[2:0] setting. The default is 0.Reserved These bits are reserved for future enhancements. Do not write to these bits as writing to thesebits may change device function. If read these bits may assume any value.ST1_Vol[4:0] Five-bit volume control for Stereo Input 1 (modes 1, 3, 5, and 6): INL1 and INR1. 11111 setsdevice to its highest gain; 00000 sets device to its lowest gain. Default setting on power-up is01101 (0 dB).
Stereo Input 2 / Headphone Gain Control Register (Addresses: 6)
BIT 76543210
Function HP_Gain[2] HP_Gain1] HP_Gain[0] ST2_Vol[4] ST2_Vol[3] ST2_Vol[2] ST2_Vol[1] ST2_Vol[0]Reset Value 0 0 0 0 1 1 0 1
HP_Gain [2:0] Headphone gain select. Sets the gain of the headphone output amplifiers according to Table 2 .The default is 000.ST2_Vol[4:0] Five-bit volume control for Stereo Input 2 (modes 2 and 4): INL2 and INR2. 11111 sets deviceto its highest gain; 00000 sets device to its lowest gain. Default setting on power-up is 01101(0 dB).
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MODES OF OPERATION
Mux Output Mode
Voice-Mode Bypass
POWER – UP SEQUENCE AND TIMING
TPA2051D3
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..................................................................................................................................................... SLOS641A – JUNE 2009 – REVISED OCTOBER 2009
The TPA2051D3 supports numerous modes of operation. "Stereo 1" refers to the INL1 and INR1 input pair;"Stereo 2" refers to the INL2 and INR2 input pair. The "Mono Diff 1" input refers to the differential input at INL1 -INR1 and "Mono Diff 2" refers to the differential input at INL2 - INR2, which are typically connected to thedifferential output of the baseband IC. "Mono" refers to the Mono+ – Mono – differential input.
Use the following sequence to prevent pop when changing modes:•Change Mode[2:0] bits to 111 (Mute)•Change to desired new Mode[2:0]
The input mux selects which device input is directed to both the Class-D and headphone amplifiers. Muxsumming and output are after the channel volume controls, as shown in the Simplified Functional Diagram onpage 2. Control the mux through the Mode[2:0] bits in Mux Output Control (Register 2, Bits 0 – 2) according tothe table below.
HEADPHONE OUTPUTMODE BYTE:
MUX MODE SPEAKER OUTPUTMODE[2:0]
LEFT RIGHT
0 [000] Mono Input Mono+ – Mono – Mono+ – Mono – Mono+ – Mono –1 [001] Mono Diff Input 1 L1 – R1 L1 – R 1 L1 – R 12 [010] Mono Diff Input 2 L 2 – R 2 L 2 – R 2 L 2 – R 23 [011] Stereo SE Input 1 L1 + R 1 L1 R14 [100] Stereo SE Input 2 L2 + R2 L2 R25 [101] Mono Diff Input 1 + 2 (L1 – R1) + (L2 – R2) (L1 – R1) + (L2 – R2) (L1 – R1) + (L2 – R2)6 [110] Mono SE Input 1 + 2 (L1 – R1) + (L2 – R2) (L1 – R1) (L2 – R2)7 [111] MUTE MUTE MUTE MUTE
Enable Voice-Mode Bypass mode by setting VM_Bypass (Register 1, Bit 0) to logic high. This deactivates theClass-D amplifier regardless of Spk_Enable bit status, and enables the bypass mode around the Class-D amp,connecting BYPASS+ to OUT+ and BYPASS – to OUT – . This allows the baseband IC to drive the dual-modeloudspeaker directly without using the Class-D amplifier, saving power and reducing noise for low-powervoice-only phone modes.
The TPA2051D3 startup sequence is shown in Figure 3 . It is important to minimize the time delay betweenpowering up AVDD/PVDD and powering up DVDD in order to minimize potential spikes in the supply current.
It is important to observe the minimum delay time between powering up DVDD and enabling the TPA2051D3(changing EN pin from LOW to HIGH) in order to prevent spikes in the supply current.
After changing SWS from logic HIGH (amplifier disabled) to logic LOW (amplifier enabled) wait 250 µsec, beforethe next I
2
C write (refer to Figure 4 ).
After changing Spk_Enable, HPL_Enable, or HPR_Enable from logic LOW (amplifier disabled) to logic HIGH(amplifier enabled) wait 250 µsec, before the next I
2
C write (refer to Figure 4 ).
When enabling the Class-D amplifier (Spk_Enable from LOW to HIGH) and/or the headphone amplifiers(HPL_Enable or HPR_Enable from LOW to HIGH) for the first time after changing EN from LOW to HIGH followthis sequence:
•Set Mode[2:0] to 111•Change VM_Bypass to 0 and Spk_Enable (and/or HPx_Enable) to 1•Change to desired Mode[2:0]
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OPERATION WITH DELAYED DVDD SUPPLY
TPA2051D3 8Ω Dual-Mode
Speaker
Stereo
HeadphoneJack
SCL
SDA
PVDD/AVDD
DVDD
EN
BBIC
SCL
SDA
GPIO(EN)
DVDD
SHUTDOWN CONTROL AND POWER MANAGEMENT
Charge Pump Enable
Class-D Output Amplifier
TPA2051D3
SLOS641A – JUNE 2009 – REVISED OCTOBER 2009 .....................................................................................................................................................
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In case the DVDD supply can not be available within t
pws
(refer to Figure 3 ) use the supply of TPA2051D3 (AVDDor PVDD) to power up DVDD. Refer to Figure 39 for an application diagram. The TPA2051D3 DVDD supplymust be less than or equal to SDA/SCL V
IH
. SDA/SCL V
IH
can be higher than DVDD but must be lower thanPVDD.
Figure 39. Operation With Delayed DVDD Supply
Power management for the TPA2051D3 is divided into four sections: Class-D power amplifier, headphone leftamplifier, headphone right amplifier, and bypass mode. Each section has its own enable bit in the AmplifierControl byte (Register 1). Set Register 1, Bits 3 through 0 to logic low to turn off the amplifier via softwarecontrol.
The software shutdown mode can also be achieved by changing the SWS to logic high (Register 1, Bit 4). Thiswill turn off all sections of the amplifier and also the reference and bias circuitry, regardless of the settings onRegister 1, Bits 3 through 1.
For lowest current consumption in shutdown mode change the EN pin to logic low or change SWS to logic HIGH.This will turn off all sections of the amplifier including reference, and bias.
All register contents are maintained provided the supply voltage is not powered down. On supply power-down, allinformation programmed into the registers by the user is lost, returning all registers back to their default stateonce power is reapplied.
The charge pump generates a negative voltage supply for the headphone amplifiers. This allows a 0 V bias onthe amplifier outputs, eliminating the need for an output coupling capacitor. The charge pump will automaticallyactivate if either the HPL_Enable or HPR_Enable bits are set to logic high.
The input to the Class-D amplifier is always a mono sum (L + R) of the mux output, regardless of mux mode. Setthe Spk_Enable bit (Register 1, Bit 1) to logic high to enable the Class-D power amplifier. The Class-D amplifierdraws 4.9 mA of typical supply current when active and less than 1 µA when deactivated.
The gain of the Class-D amplifier can be selected between +6 dB and +12 dB. Set register 5 bit 7 to logic low toselect a gain of +6 dB and to logic high to select a gain of +12 dB.
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DirectPath Headphone Amplifier
Voice Bypass Mode
HEADPHONE AMPLIFIER GAIN
VOLUME CONTROL
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..................................................................................................................................................... SLOS641A – JUNE 2009 – REVISED OCTOBER 2009
Table 1. Class-D Amplifier Gain Levels
CLASS-D GAIN NOMINAL GAINREGISTER BYTE:SPK_GAIN
0 +6 dB1 +12 dB
Set the HPL_Enable bit (Register 1, Bit 3) to logic high to enable the headphone left output and the HPR_Enablebit (Register 1, Bit 2) to logic high to enable the headphone right output. The headphone amplifier draws 4.1 mAof typical supply current with both left and right outputs active and less than 1 µA when deactivated.
Set the VM_Bypass bit (Register 1, Bit 0) to logic high to the bypass mode from BYPASS+ and BYPASS – to thespeaker pins (OUT+ and OUT-pins). This will automatically disable the Class-D speaker amplifier.
The Headphone amplifier gain can be differentiated from the default volume control gain. Register 6, bits 7 to 5and register 5 bit 6 can be used to attenuate the gain on the headphone amplifier. This function is useful todifferentiate the channel gain of the speaker amplifier from the channel gain of the headphone amplifier. So forthe same input signal different output voltage levels for the speaker and the headphone amplifier can beselected. The following table shows the gain values. This feature is required since the headphone does notrequire the same output voltage level as the speaker amplifier.
Table 2. Headphone Amplifier Gain Levels
HEADPHONE GAIN HEADPHONE GAINREGISTER BYTE: NOMINAL GAIN REGISTER BYTE: NOMINAL GAINHP_0dB, HP_GAIN[2:0] HP_0DB, HP_GAIN[2:0]
0000 -12 dB 0101 -4.5 dB0001 -10.5 dB 0110 -3 dB0010 -9 dB 0111 -1.5 dB0011 -7.5 dB 1xxx 0 dB0100 -6 dB
The TPA2051D3 has three independent volume controls: One for the mono input configurations (Mode 0), onefor the STEREO1 input pair (INL1 and INR1, when in Mode 1, 3, 5, and 6), and one for the STEREO2 input pair(INL2 and INR2, when in Mode 2 and 4). Each have 5-bit (32-step) resolution and are audio tapered; gain stepchanges become smaller at higher gain settings. All volume controls range from – 66 dB to +18 dB.
The Class-D speaker amplifier gain can be selected between 6 dB and 12 dB on top of the volume control. Thusthe total gain for the speaker channel (volume control plus Class-D amplifier) range is from – 60 dB to +30 dB.
The headphone amplifiers have a secondary volume control (see Headphone Amplifier Gain section) besides themain volume control. The secondary volume control ranges from – 12 dB to 0 dB in 1.5 dB steps. Thus the totalgain for the headphone channel (volume control plus headphone amplifier) range is from – 78 dB to +18 dB.
The Mono Input volume control byte is located in Register 4, Bits 4 to 0. The Stereo Input 1 volume control byteis located at Register 5, Bits 4 to 0, and the Stereo Input 2 volume control byte is at Register 6, Bits 4 to 0. Gainmatching between the left and right channels for STEREO1 and STEREO2 is presented in the operatingcharacteristics table.
The input impedance to the TPA2051D3 changes as gain changes. See the Operating Characteristics section forspecifications. Values listed in Table 3 are nominal values.
When the SpeakerGuard
TM
(Automatic Gain Control) is enabled the volume changes at a rate dictated by theattack time (volume decrease) and the release time (volume increase).
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AUDIO TAPER GAIN VALUES
AUTOMATIC GAIN CONTROL
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For MONO, STEREO1, and STEREO2 inputs.
Table 3. Volume Control Gain Table
VOLUME CONTROL NOMINAL GAIN VOLUME CONTROL NOMINAL GAINREGISTER BYTE: VOL[4:0] REGISTER BYTE: VOL[4:0]
00000 – 66 dB 10000 +3 dB00001 – 54 dB 10001 +4 dB00010 – 42 dB 10010 +5 dB00011 – 36 dB 10011 +6 dB00100 – 30 dB 10100 +7 dB00101 – 24 dB 10101 +8 dB00110 – 18 dB 10110 +9 dB00111 – 12 dB 10111 +10 dB01000 – 9 dB 11000 +11 dB01001 – 6 dB 11001 +12 dB01010 – 4.5 dB 11010 +13 dB01011 – 3 dB 11011 +14 dB01100 – 1.5 dB 11100 +15 dB01101 0 dB 11101 +16 dB01110 +1 dB 11110 +17 dB01111 +2 dB 11111 +18 dB
The automatic gain control (AGC) is a limiter function only (SpeakerGuard
TM
). It works by automatically adjustingamplifier gain based on the audio signal level. This prevents speaker damage from audio that is too loud. TheAGC function can also be used to improve audio loudness without increasing the peak power delivered to thespeaker.
If the audio signal is higher than the limiter level, the gain will decrease until the audio signal is just below thelimiter setting. The gain decrease rate (attack time) is set via I
2
C interface.
If the audio signal is below the limiter level and the gain is below the fixed gain, the gain will increase. The gainincrease rate (release time) is set via I
2
C interface.
There are two register settings for the limiter level. The first one is for the speaker amplifier, and the second oneis for the headphone amplifier. If the speaker and headphone amplifiers are enabled at the same time, the limiterlevel setting for the speaker amplifier takes precedence in setting the gain. If only the HP amplifier is enabled,then the channel with the highest signal level dictates the AGC gain.
Table 4 shows the selectable limiter levels for the Class-D amplifier when SPK_Gain (Register 5, bit 7) is LOW(6 dB).
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Product Folder Link(s): TPA2051D3
GAIN
OUTPUT
SIGNAL
INPUT
SIGNAL
LIMITER
LEVEL
Attack Time Release Time
GainStep
TPA2051D3
www.ti.com
..................................................................................................................................................... SLOS641A – JUNE 2009 – REVISED OCTOBER 2009
Figure 40. SpeakerGuard
TM
Operation
Table 4. Speaker Output Limiter Levels
SPEAKER LIMITER REGISTER DIFFERENTIAL OUTPUT PEAKBYTE: LIMSPK [2:0] VOLTAGE
000 2.6 V001 3.0 V010 3.3 V011 3.6 V100 3.9 V101 4.2 V110 4.8 V111 5.2 V
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 23
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TPA2051D3
SLOS641A – JUNE 2009 – REVISED OCTOBER 2009 .....................................................................................................................................................
www.ti.com
The headphone amplifier limiter settings depend on the setting of the HP_gain bits. Table 5 shows limiter valuesfor different headphone amplifier gains.
Table 5. Typical Headphone Output Limiter Levels
HEADPHONE LIMITER HEADPHONE OUTPUT HEADPHONE OUTPUT HEADPHONE OUTPUTREGISTER BYTE: PEAK VOLTAGE PEAK VOLTAGE PEAK VOLTAGELIMHP [2:0] (HP_GAIN = 0dB) (HP_GAIN = -6dB) (HP_GAIN = -12dB)
000 0.65 V 0.325 V 0.163 V001 0.75 V 0.375 V 0.188 V010 0.83 V 0.415 V 0.208 V011 0.90 V 0.45 V 0.225 V100 0.97 V 0.485 V 0.244 V101 1.05 V 0.525 V 0.263 V110 1.2 V 0.60 V 0.300 V111 1.3 V 0.65 V 0.325 V
The attack and release time can be selected via I2C interface. Table 6 gives the possible selections for theattack time.
Table 6. Attack Time Selection
ATTACK TIME ATTACK TIME ATTACK TIME ATTACK TIMEREGISTER BYTE: (MS/STEP) REGISTER BYTE: (MS/STEP)ATK_TIME[4:0] ATK_TIME[4:0]
00000 1.28 10000 21.7600001 2.56 10001 23.0400010 3.84 10010 24.3200011 5.12 10011 25.600100 6.4 10100 26.8800101 7.68 10101 28.1600110 8.96 10110 29.4400111 10.24 10111 30.7201000 11.52 11000 3201001 12.8 11001 33.2801010 14.08 11010 34.5601011 15.36 11011 35.8401100 16.64 11100 37.1201101 17.92 11101 38.401110 19.2 11110 39.6801111 20.48 11111 40.96
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Product Folder Link(s): TPA2051D3
DECOUPLING CAPACITOR
INPUT CAPACITORS
C
I I
1
=(2 R C )
¦´ ´p
(1)
TPA2051D3
www.ti.com
..................................................................................................................................................... SLOS641A – JUNE 2009 – REVISED OCTOBER 2009
Table 7 gives the possible selections for the release time.
Table 7. Release Time Selection
RELEASE TIME RELEASE TIME RELEASE TIME RELEASE TIMEREGISTER BYTE: (MS/STEP) REGISTER BYTE: (MS/STEP)REL_TIME[4:0] REL_TIME[4:0]
00000 41 10000 69700001 82 10001 73800010 123 10010 77900011 164 10011 82000100 205 10100 86100101 246 10101 90200110 287 10110 94300111 328 10111 98401000 369 11000 102501001 410 11001 106601010 451 11010 110701011 492 11011 114801100 533 11100 118901101 574 11101 123001110 615 11110 127101111 656 11111 1312
The TPA2051D3 is a high-performance Class-D audio amplifier that requires adequate power supply decouplingto ensure the efficiency is high and total harmonic distortion (THD) is low. For higher frequency transients,spikes, or digital hash on the line a good low equivalent-series-resistance (ESR) ceramic capacitor, typically1µF, placed as close as possible to the device PVDD lead works best. Placing this decoupling capacitor close tothe TPA2051D3 is important for the efficiency of the Class-D amplifier, because any resistance or inductance inthe trace between the device and the capacitor can cause a loss in efficiency. For filtering lower-frequency noisesignals, a 4.7 µF or greater capacitor placed near the audio power amplifier would also help, but it is not requiredin most applications because of the high PSRR of this device.
The TPA2051D3 does not require input coupling capacitors if the design uses a differential source that is biasedwithin the common mode input range. If the input signal is not biased within the recommended common-modeinput range, if high pass filtering is needed, or if using a single-ended source, input coupling capacitors arerequired.
The input capacitors and input resistors form a high-pass filter with the corner frequency, ƒ
C
, determined inEquation 1 .
The value of the input capacitor is important to consider as it directly affects the bass (low frequency)performance of the circuit. Speakers in wireless phones cannot usually respond well to low frequencies, so thecorner frequency can be set to block low frequencies in this application. Not using input capacitors can increaseoutput offset.
Equation 2 is used to solve for the input coupling capacitance. If the corner frequency is within the audio band,the capacitors should have a tolerance of ± 10% or better, because any mismatch in capacitance causes animpedance mismatch at the corner frequency and below.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): TPA2051D3
I
I C
1
C = (2 R )´ ´ ¦p
(2)
BOARD LAYOUT
TPA2051D3
SLOS641A – JUNE 2009 – REVISED OCTOBER 2009 .....................................................................................................................................................
www.ti.com
If the corner frequency is within the audio band, the capacitors should have a tolerance of ± 10% or better,because any mismatch in capacitance causes an impedance mismatch at the corner frequency and below.
In making the pad size for the WCSP balls, it is recommended that the layout use nonsolder mask defined(NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and theopening size is defined by the copper pad width. Figure 41 and Table 8 shows the appropriate diameters for aWCSP layout. The TPA2051D3 evaluation module (EVM) layout is shown in the next section as a layoutexample.
Figure 41. Land Pattern Dimensions
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COMPONENT LOCATION
Trace Width
EFFICIENCY AND THERMAL INFORMATION
JA
1 1
θ = = = 148 C/W
Derating Factor 0.0068
°
(3)
o
A J JA Dmax
T MAX T MAX θ P 150 148(0.2) 120 C= - = - =
(4)
OPERATION WITH DACS AND CODECS
TPA2051D3
www.ti.com
..................................................................................................................................................... SLOS641A – JUNE 2009 – REVISED OCTOBER 2009
Table 8. Land Pattern Dimensions
(1) (2) (3) (4)
SOLDER PAD SOLDER MASK
(5)
COPPER STENCIL
(6) (7)
STENCILCOPPER PADDEFINITIONS OPENING THICKNESS OPENING THICKNESS
Nonsolder mask 230 µm 310 µm 275 µm x 275 µm Sq.1 oz max (32 µm) 100 µm thickdefined (NSMD) (+0.0, – 25 µm) (+0.0, – 25 µm) (rounded corners)
(1) Circuit traces from NSMD defined PWB lands should be 75 µm to 100 µm wide in the exposed area inside the solder mask opening.Wider trace widths reduce device stand off and impact reliability.(2) Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the range of theintended application.(3) Recommend solder paste is Type 3 or Type 4.(4) For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 mm to avoid a reduction in thermal fatigue performance.(5) Solder mask thickness should be less than 20 µm on top of the copper circuit pattern(6) Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically etched stencils results ininferior solder paste volume control.(7) Trace routing away from WCSP device should be balanced in X and Y directions to avoid unintentional component movement due tosolder wetting forces.
Place all the external components very close to the TPA2051D3. Placing the decoupling capacitor, Cs, close tothe TPA2051D3 is important for the efficiency of the Class-D amplifier. Any resistance or inductance in the tracebetween the device and the capacitor can cause a loss in efficiency.
Recommended trace width at the solder balls is 75- µm to 100- µm to prevent solder wicking onto wider PCBtraces.
For high current pins (PVDD, PGND, and audio output pins) of the TPA2051D3, use 100- µm trace widths at thesolder balls and at least 500- µm PCB traces to ensure proper performance and output power for the device.
For the remaining signals of the TPA2051D3, use 75- µm to 100- µm trace widths at the solder balls. The audioinput pins (INR ± and INL ± ) must run side-by-side to maximize common-mode noise cancellation.
The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factorfor the packages are shown in the dissipation rating table. Converting this to θ
JA
for the WCSP package:
Given θ
JA
of 148 ° C/W, the maximum allowable junction temperature of 150 ° C, and the internal dissipation of0.2 W for 2 W, 8 Ωload, 5 V supply, the maximum ambient temperature can be calculated with Equation 4 .
Equation 4 shows that the calculated maximum ambient temperature is 120 ° C at maximum power dissipationwith a 5 V supply and 8 Ωa load. The TPA2051D3 is designed with thermal protection that turns the device offwhen the junction temperature surpasses 150 ° C to prevent damage to the IC.
In using Class-D amplifiers with CODECs and DACs, sometimes there is an increase in the output noise floorfrom the audio amplifier. This occurs when mixing of the output frequencies of the CODEC/DAC mix with theswitching frequencies of the audio amplifier input stage. The noise increase can be solved by placing a low-passfilter between the CODEC/DAC and audio amplifier. This filters off the high frequencies that cause the problemand allow proper performance. See Figure 42 for the application diagram.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): TPA2051D3
FM Tuner
ABB
Codec
(MP3)
TPA2051D3
MonoClass-D
plus
DirectPathTM
8 Dual-Mode
Speaker
Stereo
HeadphoneJack
Mono+
Mono-
Left
(SE)
Right
(SE)
Left
(SE)
Right
(SE)
Bypass+
Bypass-
FILTER FREE OPERATION AND FERRITE BEAD FILTERS
Package Dimensions
TPA2051D3
SLOS641A – JUNE 2009 – REVISED OCTOBER 2009 .....................................................................................................................................................
www.ti.com
Figure 42. Example of Low Pass Input Filter Application
A ferrite bead filter can often be used if the design is failing radiated emissions without an LC filter and thefrequency sensitive circuit is greater than 1 MHz. This filter functions well for circuits that just have to pass FCCand CE because FCC and CE only test radiated emissions greater than 30 MHz. When choosing a ferrite bead,choose one with high impedance at high frequencies, and very low impedance at low frequencies. In addition,select a ferrite bead with adequate current rating to prevent distortion of the output signal.
Use an LC output filter if there are low frequency ( < 1 MHz) EMI sensitive circuits and/or there are long leadsfrom amplifier to speaker.
Figure 43 shows typical ferrite bead output filters.
Figure 43. Typical Ferrite Bead Filter (Chip bead example: TDK: MPZ1608S221A)
D E
Max = 2190m Max = 2130mMin = 2136m Min = 2076m
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Product Folder Link(s): TPA2051D3
TPA2051D3
www.ti.com
..................................................................................................................................................... SLOS641A – JUNE 2009 – REVISED OCTOBER 2009
REVISION HISTORY
Changes from Original (June 2009) to Revision A ......................................................................................................... Page
•Changed R
ON
max value from 2.7 to 4.5 ............................................................................................................................... 8
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Link(s): TPA2051D3
PACKAGE OPTION ADDENDUM
www.ti.com 2-Apr-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPA2051D3YFFR ACTIVE DSBGA YFF 25 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
TPA2051D3YFFT ACTIVE DSBGA YFF 25 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPA2051D3YFFR DSBGA YFF 25 3000 180.0 8.4 2.2 2.35 0.8 4.0 8.0 Q1
TPA2051D3YFFT DSBGA YFF 25 250 180.0 8.4 2.2 2.35 0.8 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 22-Sep-2011
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPA2051D3YFFR DSBGA YFF 25 3000 210.0 185.0 35.0
TPA2051D3YFFT DSBGA YFF 25 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 22-Sep-2011
Pack Materials-Page 2
D: Max =
E: Max =
2.19 mm, Min =
2.136 mm, Min =
2.13 mm
2.076 mm
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